Patch "irqchip/gic-v3: Configure all interrupts as non-secure Group-1" has been added to the 4.5-stable tree

Patch "irqchip/gic-v3: Configure all interrupts as non-secure Group-1" has been added to the 4.5-stable tree

[gregkh]

This is a note to let you know that I've just added the patch titled

    irqchip/gic-v3: Configure all interrupts as non-secure Group-1

to the 4.5-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     irqchip-gic-v3-configure-all-interrupts-as-non-secure-group-1.patch
and it can be found in the queue-4.5 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.


>From 7c9b973061b03af62734f613f6abec46c0dd4a88 Mon Sep 17 00:00:00 2001
From: Marc Zyngier <marc.zyngier@arm.com>
Date: Fri, 6 May 2016 19:41:56 +0100
Subject: irqchip/gic-v3: Configure all interrupts as non-secure Group-1

From: Marc Zyngier <marc.zyngier@arm.com>

commit 7c9b973061b03af62734f613f6abec46c0dd4a88 upstream.

The GICv3 driver wrongly assumes that it runs on the non-secure
side of a secure-enabled system, while it could be on a system
with a single security state, or a GICv3 with GICD_CTLR.DS set.

Either way, it is important to configure this properly, or
interrupts will simply not be delivered on this HW.

Reported-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

---
 drivers/irqchip/irq-gic-v3.c |   12 ++++++++++++
 1 file changed, 12 insertions(+)

--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -387,6 +387,15 @@ static void __init gic_dist_init(void)
 	writel_relaxed(0, base + GICD_CTLR);
 	gic_dist_wait_for_rwp();
 
+	/*
+	 * Configure SPIs as non-secure Group-1. This will only matter
+	 * if the GIC only has a single security state. This will not
+	 * do the right thing if the kernel is running in secure mode,
+	 * but that's not the intended use case anyway.
+	 */
+	for (i = 32; i < gic_data.irq_nr; i += 32)
+		writel_relaxed(~0, base + GICD_IGROUPR + i / 8);
+
 	gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp);
 
 	/* Enable distributor with ARE, Group1 */
@@ -501,6 +510,9 @@ static void gic_cpu_init(void)
 
 	rbase = gic_data_rdist_sgi_base();
 
+	/* Configure SGIs/PPIs as non-secure Group-1 */
+	writel_relaxed(~0, rbase + GICR_IGROUPR0);
+
 	gic_cpu_config(rbase, gic_redist_wait_for_rwp);
 
 	/* Give LPIs a spin */


Patches currently in stable-queue which might be from marc.zyngier@arm.com are

queue-4.5/irqchip-gic-ensure-ordering-between-read-of-intack-and-shared-data.patch
queue-4.5/arm-arm64-kvm-enforce-break-before-make-on-stage-2-page-tables.patch
queue-4.5/irqchip-gic-v3-configure-all-interrupts-as-non-secure-group-1.patch
queue-4.5/kvm-arm64-fix-ec-field-in-inject_abt64.patch