* [PATCH V4 1/2] mtd: rawnand: qcom: avoid write to unavailable register [not found] <1591948596-15899-1-git-send-email-sivaprak@codeaurora.org> @ 2020-06-12 7:56 ` Sivaprakash Murugesan 0 siblings, 0 replies; 4+ messages in thread From: Sivaprakash Murugesan @ 2020-06-12 7:56 UTC (permalink / raw) To: sivaprak; +Cc: stable SFLASHC_BURST_CFG is only available on older ipq nand platforms, this register has been removed when the NAND controller is moved as part of qpic controller. Avoid writing this register on devices which are based on qpic NAND controller. Fixes: dce84760 (mtd: nand: qcom: Support for IPQ8074 QPIC NAND controller) Cc: stable@vger.kernel.org Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> --- drivers/mtd/nand/raw/qcom_nandc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index f1daf33..78b5f21 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -459,11 +459,13 @@ struct qcom_nand_host { * among different NAND controllers. * @ecc_modes - ecc mode for NAND * @is_bam - whether NAND controller is using BAM + * @is_qpic - whether NAND CTRL is part of qpic IP * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset */ struct qcom_nandc_props { u32 ecc_modes; bool is_bam; + bool is_qpic; u32 dev_cmd_reg_start; }; @@ -2774,7 +2776,8 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc) u32 nand_ctrl; /* kill onenand */ - nandc_write(nandc, SFLASHC_BURST_CFG, 0); + if (!nandc->props->is_qpic) + nandc_write(nandc, SFLASHC_BURST_CFG, 0); nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD), NAND_DEV_CMD_VLD_VAL); @@ -3035,12 +3038,14 @@ static const struct qcom_nandc_props ipq806x_nandc_props = { static const struct qcom_nandc_props ipq4019_nandc_props = { .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT), .is_bam = true, + .is_qpic = true, .dev_cmd_reg_start = 0x0, }; static const struct qcom_nandc_props ipq8074_nandc_props = { .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT), .is_bam = true, + .is_qpic = true, .dev_cmd_reg_start = 0x7000, }; -- 2.7.4 ^ permalink raw reply related [flat|nested] 4+ messages in thread
[parent not found: <1591948696-16015-1-git-send-email-sivaprak@codeaurora.org>]
* [PATCH V4 1/2] mtd: rawnand: qcom: avoid write to unavailable register [not found] <1591948696-16015-1-git-send-email-sivaprak@codeaurora.org> @ 2020-06-12 7:58 ` Sivaprakash Murugesan 2020-06-15 8:49 ` Miquel Raynal 2020-06-15 8:59 ` Miquel Raynal 0 siblings, 2 replies; 4+ messages in thread From: Sivaprakash Murugesan @ 2020-06-12 7:58 UTC (permalink / raw) To: miquel.raynal, richard, vigneshr, peter.ujfalusi, sivaprak, boris.brezillon, linux-mtd, linux-kernel Cc: stable SFLASHC_BURST_CFG is only available on older ipq nand platforms, this register has been removed when the NAND controller is moved as part of qpic controller. Avoid writing this register on devices which are based on qpic NAND controller. Fixes: dce84760 (mtd: nand: qcom: Support for IPQ8074 QPIC NAND controller) Cc: stable@vger.kernel.org Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> --- drivers/mtd/nand/raw/qcom_nandc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index f1daf33..78b5f21 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -459,11 +459,13 @@ struct qcom_nand_host { * among different NAND controllers. * @ecc_modes - ecc mode for NAND * @is_bam - whether NAND controller is using BAM + * @is_qpic - whether NAND CTRL is part of qpic IP * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset */ struct qcom_nandc_props { u32 ecc_modes; bool is_bam; + bool is_qpic; u32 dev_cmd_reg_start; }; @@ -2774,7 +2776,8 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc) u32 nand_ctrl; /* kill onenand */ - nandc_write(nandc, SFLASHC_BURST_CFG, 0); + if (!nandc->props->is_qpic) + nandc_write(nandc, SFLASHC_BURST_CFG, 0); nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD), NAND_DEV_CMD_VLD_VAL); @@ -3035,12 +3038,14 @@ static const struct qcom_nandc_props ipq806x_nandc_props = { static const struct qcom_nandc_props ipq4019_nandc_props = { .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT), .is_bam = true, + .is_qpic = true, .dev_cmd_reg_start = 0x0, }; static const struct qcom_nandc_props ipq8074_nandc_props = { .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT), .is_bam = true, + .is_qpic = true, .dev_cmd_reg_start = 0x7000, }; -- 2.7.4 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH V4 1/2] mtd: rawnand: qcom: avoid write to unavailable register 2020-06-12 7:58 ` Sivaprakash Murugesan @ 2020-06-15 8:49 ` Miquel Raynal 2020-06-15 8:59 ` Miquel Raynal 1 sibling, 0 replies; 4+ messages in thread From: Miquel Raynal @ 2020-06-15 8:49 UTC (permalink / raw) To: Sivaprakash Murugesan Cc: richard, vigneshr, peter.ujfalusi, boris.brezillon, linux-mtd, linux-kernel, stable Hi Sivaprakash, Sivaprakash Murugesan <sivaprak@codeaurora.org> wrote on Fri, 12 Jun 2020 13:28:15 +0530: > SFLASHC_BURST_CFG is only available on older ipq nand platforms, this > register has been removed when the NAND controller is moved as part of qpic > controller. > > Avoid writing this register on devices which are based on qpic NAND > controller. > > Fixes: dce84760 (mtd: nand: qcom: Support for IPQ8074 QPIC NAND controller) The Fixes line is not properly formed: the number of digest digits must be 12 and the title should be enclosed with "". I will fix when applying. Thanks, Miquèl ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH V4 1/2] mtd: rawnand: qcom: avoid write to unavailable register 2020-06-12 7:58 ` Sivaprakash Murugesan 2020-06-15 8:49 ` Miquel Raynal @ 2020-06-15 8:59 ` Miquel Raynal 1 sibling, 0 replies; 4+ messages in thread From: Miquel Raynal @ 2020-06-15 8:59 UTC (permalink / raw) To: Sivaprakash Murugesan, miquel.raynal, richard, vigneshr, peter.ujfalusi, boris.brezillon, linux-mtd, linux-kernel Cc: stable On Fri, 2020-06-12 at 07:58:15 UTC, Sivaprakash Murugesan wrote: > SFLASHC_BURST_CFG is only available on older ipq nand platforms, this > register has been removed when the NAND controller is moved as part of qpic > controller. > > Avoid writing this register on devices which are based on qpic NAND > controller. > > Fixes: dce84760 (mtd: nand: qcom: Support for IPQ8074 QPIC NAND controller) > Cc: stable@vger.kernel.org > Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks. Miquel ^ permalink raw reply [flat|nested] 4+ messages in thread
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2020-06-12 7:56 ` [PATCH V4 1/2] mtd: rawnand: qcom: avoid write to unavailable register Sivaprakash Murugesan
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2020-06-15 8:49 ` Miquel Raynal
2020-06-15 8:59 ` Miquel Raynal
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