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From: Sasha Levin <sashal@kernel.org>
To: Yan Zhao <yan.y.zhao@intel.com>
Cc: zhenyuw@linux.intel.com, stable@vger.kernel.org
Subject: Re: [PATCH for 4.14] drm/i915/gvt: do not let pin count of shadow mm go negative
Date: Mon, 8 Apr 2019 10:25:21 -0400	[thread overview]
Message-ID: <20190408142521.GD4689@sasha-vm> (raw)
In-Reply-To: <20190408051247.3697-1-yan.y.zhao@intel.com>

On Mon, Apr 08, 2019 at 01:12:47AM -0400, Yan Zhao wrote:
>shadow mm's pin count got increased in workload preparation phase, which
>is after workload scanning.
>it will get decreased in complete_current_workload() anyway after
>workload completion.
>Sometimes, if a workload meets a scanning error, its shadow mm pin count
>will not get increased but will get decreased in the end.
>This patch lets shadow mm's pin count not go below 0.
>
>v2: add fixes tag and cc stable kernel (zhenyu wang)
>Fixes: 2707e4446688 ("drm/i915/gvt: vGPU graphics memory virtualization")
>Cc: zhenyuw@linux.intel.com
>Cc: stable@vger.kernel.org #4.14+
>Signed-off-by: Yan Zhao <yan.y.zhao@intel.com>
>---
>upstream commit id: 663a50ceac75c2208d2ad95365bc8382fd42f44d
>---
> drivers/gpu/drm/i915/gvt/gtt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
>index dadacbe558ab..1a1f7eb46d1e 100644
>--- a/drivers/gpu/drm/i915/gvt/gtt.c
>+++ b/drivers/gpu/drm/i915/gvt/gtt.c
>@@ -1629,7 +1629,7 @@ void intel_vgpu_unpin_mm(struct intel_vgpu_mm *mm)
> 	if (WARN_ON(mm->type != INTEL_GVT_MM_PPGTT))
> 		return;
>
>-	atomic_dec(&mm->pincount);
>+	atomic_dec_if_positive(&mm->pincount);
> }
>
> /**

Queued for 4.14 (which missing s-o-b from upstream), thanks.

--
Thanks,
Sasha

      reply	other threads:[~2019-04-08 14:25 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-08  5:12 [PATCH for 4.14] drm/i915/gvt: do not let pin count of shadow mm go negative Yan Zhao
2019-04-08 14:25 ` Sasha Levin [this message]

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