* [PATCH 5.4 1/2] arm64: Add AMPERE1 to the Spectre-BHB affected list
@ 2023-08-01 9:37 ovidiu.panait
2023-08-01 9:37 ` [PATCH 5.4 2/2] arm64: Fix bit-shifting UB in the MIDR_CPU_MODEL() macro ovidiu.panait
2023-08-04 10:24 ` [PATCH 5.4 1/2] arm64: Add AMPERE1 to the Spectre-BHB affected list Greg KH
0 siblings, 2 replies; 3+ messages in thread
From: ovidiu.panait @ 2023-08-01 9:37 UTC (permalink / raw)
To: stable; +Cc: D Scott Phillips, James Morse, Catalin Marinas, Ovidiu Panait
From: D Scott Phillips <scott@os.amperecomputing.com>
commit 0e5d5ae837c8ce04d2ddb874ec5f920118bd9d31 upstream.
Per AmpereOne erratum AC03_CPU_12, "Branch history may allow control of
speculative execution across software contexts," the AMPERE1 core needs the
bhb clearing loop to mitigate Spectre-BHB, with a loop iteration count of
11.
Signed-off-by: D Scott Phillips <scott@os.amperecomputing.com>
Link: https://lore.kernel.org/r/20221011022140.432370-1-scott@os.amperecomputing.com
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
---
arch/arm64/include/asm/cputype.h | 4 ++++
arch/arm64/kernel/cpu_errata.c | 6 ++++++
2 files changed, 10 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index f0165df489a3..08241810cfea 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -59,6 +59,7 @@
#define ARM_CPU_IMP_NVIDIA 0x4E
#define ARM_CPU_IMP_FUJITSU 0x46
#define ARM_CPU_IMP_HISI 0x48
+#define ARM_CPU_IMP_AMPERE 0xC0
#define ARM_CPU_PART_AEM_V8 0xD0F
#define ARM_CPU_PART_FOUNDATION 0xD00
@@ -101,6 +102,8 @@
#define HISI_CPU_PART_TSV110 0xD01
+#define AMPERE_CPU_PART_AMPERE1 0xAC3
+
#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
@@ -131,6 +134,7 @@
#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
+#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index b18f307a3c59..342cba2ae982 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -1145,6 +1145,10 @@ u8 spectre_bhb_loop_affected(int scope)
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
{},
};
+ static const struct midr_range spectre_bhb_k11_list[] = {
+ MIDR_ALL_VERSIONS(MIDR_AMPERE1),
+ {},
+ };
static const struct midr_range spectre_bhb_k8_list[] = {
MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
@@ -1155,6 +1159,8 @@ u8 spectre_bhb_loop_affected(int scope)
k = 32;
else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k24_list))
k = 24;
+ else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k11_list))
+ k = 11;
else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k8_list))
k = 8;
--
2.39.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* [PATCH 5.4 2/2] arm64: Fix bit-shifting UB in the MIDR_CPU_MODEL() macro
2023-08-01 9:37 [PATCH 5.4 1/2] arm64: Add AMPERE1 to the Spectre-BHB affected list ovidiu.panait
@ 2023-08-01 9:37 ` ovidiu.panait
2023-08-04 10:24 ` [PATCH 5.4 1/2] arm64: Add AMPERE1 to the Spectre-BHB affected list Greg KH
1 sibling, 0 replies; 3+ messages in thread
From: ovidiu.panait @ 2023-08-01 9:37 UTC (permalink / raw)
To: stable; +Cc: D Scott Phillips, Geert Uytterhoeven, Catalin Marinas,
Ovidiu Panait
From: D Scott Phillips <scott@os.amperecomputing.com>
commit 8ec8490a1950efeccb00967698cf7cb2fcd25ca7 upstream.
CONFIG_UBSAN_SHIFT with gcc-5 complains that the shifting of
ARM_CPU_IMP_AMPERE (0xC0) into bits [31:24] by MIDR_CPU_MODEL() is
undefined behavior. Well, sort of, it actually spells the error as:
arch/arm64/kernel/proton-pack.c: In function 'spectre_bhb_loop_affected':
arch/arm64/include/asm/cputype.h:44:2: error: initializer element is not constant
(((imp) << MIDR_IMPLEMENTOR_SHIFT) | \
^
This isn't an issue for other Implementor codes, as all the other codes
have zero in the top bit and so are representable as a signed int.
Cast the implementor code to unsigned in MIDR_CPU_MODEL to remove the
undefined behavior.
Fixes: 0e5d5ae837c8 ("arm64: Add AMPERE1 to the Spectre-BHB affected list")
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: D Scott Phillips <scott@os.amperecomputing.com>
Link: https://lore.kernel.org/r/20221102160106.1096948-1-scott@os.amperecomputing.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
---
arch/arm64/include/asm/cputype.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 08241810cfea..892fc0ceccb8 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -41,7 +41,7 @@
(((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
#define MIDR_CPU_MODEL(imp, partnum) \
- (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \
+ ((_AT(u32, imp) << MIDR_IMPLEMENTOR_SHIFT) | \
(0xf << MIDR_ARCHITECTURE_SHIFT) | \
((partnum) << MIDR_PARTNUM_SHIFT))
--
2.39.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH 5.4 1/2] arm64: Add AMPERE1 to the Spectre-BHB affected list
2023-08-01 9:37 [PATCH 5.4 1/2] arm64: Add AMPERE1 to the Spectre-BHB affected list ovidiu.panait
2023-08-01 9:37 ` [PATCH 5.4 2/2] arm64: Fix bit-shifting UB in the MIDR_CPU_MODEL() macro ovidiu.panait
@ 2023-08-04 10:24 ` Greg KH
1 sibling, 0 replies; 3+ messages in thread
From: Greg KH @ 2023-08-04 10:24 UTC (permalink / raw)
To: ovidiu.panait; +Cc: stable, D Scott Phillips, James Morse, Catalin Marinas
On Tue, Aug 01, 2023 at 12:37:35PM +0300, ovidiu.panait@windriver.com wrote:
> From: D Scott Phillips <scott@os.amperecomputing.com>
>
> commit 0e5d5ae837c8ce04d2ddb874ec5f920118bd9d31 upstream.
>
> Per AmpereOne erratum AC03_CPU_12, "Branch history may allow control of
> speculative execution across software contexts," the AMPERE1 core needs the
> bhb clearing loop to mitigate Spectre-BHB, with a loop iteration count of
> 11.
>
> Signed-off-by: D Scott Phillips <scott@os.amperecomputing.com>
> Link: https://lore.kernel.org/r/20221011022140.432370-1-scott@os.amperecomputing.com
> Reviewed-by: James Morse <james.morse@arm.com>
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
> ---
> arch/arm64/include/asm/cputype.h | 4 ++++
> arch/arm64/kernel/cpu_errata.c | 6 ++++++
> 2 files changed, 10 insertions(+)
>
> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> index f0165df489a3..08241810cfea 100644
> --- a/arch/arm64/include/asm/cputype.h
> +++ b/arch/arm64/include/asm/cputype.h
> @@ -59,6 +59,7 @@
> #define ARM_CPU_IMP_NVIDIA 0x4E
> #define ARM_CPU_IMP_FUJITSU 0x46
> #define ARM_CPU_IMP_HISI 0x48
> +#define ARM_CPU_IMP_AMPERE 0xC0
>
> #define ARM_CPU_PART_AEM_V8 0xD0F
> #define ARM_CPU_PART_FOUNDATION 0xD00
> @@ -101,6 +102,8 @@
>
> #define HISI_CPU_PART_TSV110 0xD01
>
> +#define AMPERE_CPU_PART_AMPERE1 0xAC3
> +
> #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
> #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
> #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
> @@ -131,6 +134,7 @@
> #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
> #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
> #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
> +#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
>
> /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
> #define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index b18f307a3c59..342cba2ae982 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -1145,6 +1145,10 @@ u8 spectre_bhb_loop_affected(int scope)
> MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
> {},
> };
> + static const struct midr_range spectre_bhb_k11_list[] = {
> + MIDR_ALL_VERSIONS(MIDR_AMPERE1),
> + {},
> + };
> static const struct midr_range spectre_bhb_k8_list[] = {
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
> @@ -1155,6 +1159,8 @@ u8 spectre_bhb_loop_affected(int scope)
> k = 32;
> else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k24_list))
> k = 24;
> + else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k11_list))
> + k = 11;
> else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k8_list))
> k = 8;
>
> --
> 2.39.1
>
Both now queued up, thanks.
greg k-h
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-08-01 9:37 [PATCH 5.4 1/2] arm64: Add AMPERE1 to the Spectre-BHB affected list ovidiu.panait
2023-08-01 9:37 ` [PATCH 5.4 2/2] arm64: Fix bit-shifting UB in the MIDR_CPU_MODEL() macro ovidiu.panait
2023-08-04 10:24 ` [PATCH 5.4 1/2] arm64: Add AMPERE1 to the Spectre-BHB affected list Greg KH
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