* [PATCH -fixes v2 1/4] riscv: Fix enabling cbo.zero when running in M-mode [not found] <20240213033744.4069020-1-samuel.holland@sifive.com> @ 2024-02-13 3:37 ` Samuel Holland 2024-02-13 3:37 ` [PATCH -fixes v2 3/4] riscv: Add ISA extension parsing for Sm and Ss Samuel Holland 2024-02-13 3:37 ` [PATCH -fixes v2 4/4] riscv: Save/restore envcfg CSR during CPU suspend Samuel Holland 2 siblings, 0 replies; 15+ messages in thread From: Samuel Holland @ 2024-02-13 3:37 UTC (permalink / raw) To: Palmer Dabbelt Cc: Andrew Jones, linux-riscv, linux-kernel, Stefan O'Rear, Samuel Holland, stable When the kernel is running in M-mode, the CBZE bit must be set in the menvcfg CSR, not in senvcfg. Cc: <stable@vger.kernel.org> Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode") Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> --- (no changes since v1) arch/riscv/include/asm/csr.h | 2 ++ arch/riscv/kernel/cpufeature.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 510014051f5d..2468c55933cd 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -424,6 +424,7 @@ # define CSR_STATUS CSR_MSTATUS # define CSR_IE CSR_MIE # define CSR_TVEC CSR_MTVEC +# define CSR_ENVCFG CSR_MENVCFG # define CSR_SCRATCH CSR_MSCRATCH # define CSR_EPC CSR_MEPC # define CSR_CAUSE CSR_MCAUSE @@ -448,6 +449,7 @@ # define CSR_STATUS CSR_SSTATUS # define CSR_IE CSR_SIE # define CSR_TVEC CSR_STVEC +# define CSR_ENVCFG CSR_SENVCFG # define CSR_SCRATCH CSR_SSCRATCH # define CSR_EPC CSR_SEPC # define CSR_CAUSE CSR_SCAUSE diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 89920f84d0a3..c5b13f7dd482 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -950,7 +950,7 @@ arch_initcall(check_unaligned_access_all_cpus); void riscv_user_isa_enable(void) { if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ)) - csr_set(CSR_SENVCFG, ENVCFG_CBZE); + csr_set(CSR_ENVCFG, ENVCFG_CBZE); } #ifdef CONFIG_RISCV_ALTERNATIVE -- 2.43.0 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH -fixes v2 3/4] riscv: Add ISA extension parsing for Sm and Ss [not found] <20240213033744.4069020-1-samuel.holland@sifive.com> 2024-02-13 3:37 ` [PATCH -fixes v2 1/4] riscv: Fix enabling cbo.zero when running in M-mode Samuel Holland @ 2024-02-13 3:37 ` Samuel Holland 2024-02-13 15:14 ` Andrew Jones 2024-02-13 18:07 ` Conor Dooley 2024-02-13 3:37 ` [PATCH -fixes v2 4/4] riscv: Save/restore envcfg CSR during CPU suspend Samuel Holland 2 siblings, 2 replies; 15+ messages in thread From: Samuel Holland @ 2024-02-13 3:37 UTC (permalink / raw) To: Palmer Dabbelt Cc: Andrew Jones, linux-riscv, linux-kernel, Stefan O'Rear, Samuel Holland, stable Previously, all extension version numbers were ignored. However, the version number is important for these two extensions. The simplest way to implement this is to use a separate bitmap bit for each supported version, with each successive version implying all of the previous ones. This allows alternatives and riscv_has_extension_[un]likely() to work naturally. To avoid duplicate extensions in /proc/cpuinfo, the new successor_id field allows hiding all but the newest implemented version of an extension. Cc: <stable@vger.kernel.org> # v6.7+ Signed-off-by: Samuel Holland <samuel.holland@sifive.com> --- Changes in v2: - New patch for v2 arch/riscv/include/asm/cpufeature.h | 1 + arch/riscv/include/asm/hwcap.h | 8 ++++++ arch/riscv/kernel/cpu.c | 5 ++++ arch/riscv/kernel/cpufeature.c | 42 +++++++++++++++++++++++++---- 4 files changed, 51 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 0bd11862b760..ac71384e7bc4 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -61,6 +61,7 @@ struct riscv_isa_ext_data { const char *property; const unsigned int *subset_ext_ids; const unsigned int subset_ext_size; + const unsigned int successor_id; }; extern const struct riscv_isa_ext_data riscv_isa_ext[]; diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 5340f818746b..5b51aa1db15b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -80,13 +80,21 @@ #define RISCV_ISA_EXT_ZFA 71 #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 +#define RISCV_ISA_EXT_SM1p11 74 +#define RISCV_ISA_EXT_SM1p12 75 +#define RISCV_ISA_EXT_SS1p11 76 +#define RISCV_ISA_EXT_SS1p12 77 #define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX #ifdef CONFIG_RISCV_M_MODE +#define RISCV_ISA_EXT_Sx1p11 RISCV_ISA_EXT_SM1p11 +#define RISCV_ISA_EXT_Sx1p12 RISCV_ISA_EXT_SM1p12 #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA #else +#define RISCV_ISA_EXT_Sx1p11 RISCV_ISA_EXT_SS1p11 +#define RISCV_ISA_EXT_Sx1p12 RISCV_ISA_EXT_SS1p12 #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA #endif diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index d11d6320fb0d..2e6b90ed0d51 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -215,6 +215,11 @@ static void print_isa(struct seq_file *f, const unsigned long *isa_bitmap) if (!__riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].id)) continue; + /* Only show the newest implemented version of an extension */ + if (riscv_isa_ext[i].successor_id != RISCV_ISA_EXT_INVALID && + __riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].successor_id)) + continue; + /* Only multi-letter extensions are split by underscores */ if (strnlen(riscv_isa_ext[i].name, 2) != 1) seq_puts(f, "_"); diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c5b13f7dd482..8e10b50120e9 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -113,23 +113,29 @@ static bool riscv_isa_extension_check(int id) return true; } -#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size) { \ +#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size, _successor) { \ .name = #_name, \ .property = #_name, \ .id = _id, \ .subset_ext_ids = _subset_exts, \ - .subset_ext_size = _subset_exts_size \ + .subset_ext_size = _subset_exts_size, \ + .successor_id = _successor, \ } -#define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0) +#define __RISCV_ISA_EXT_DATA(_name, _id) \ + _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, RISCV_ISA_EXT_INVALID) /* Used to declare pure "lasso" extension (Zk for instance) */ #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ - _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, ARRAY_SIZE(_bundled_exts)) + _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, \ + _bundled_exts, ARRAY_SIZE(_bundled_exts), RISCV_ISA_EXT_INVALID) /* Used to declare extensions that are a superset of other extensions (Zvbb for instance) */ #define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \ - _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts)) + _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), RISCV_ISA_EXT_INVALID) + +#define __RISCV_ISA_EXT_VERSION(_name, _id, _preds, _preds_size, _successor) \ + _RISCV_ISA_EXT_DATA(_name, _id, _preds, _preds_size, _successor) static const unsigned int riscv_zk_bundled_exts[] = { RISCV_ISA_EXT_ZBKB, @@ -201,6 +207,16 @@ static const unsigned int riscv_zvbb_exts[] = { RISCV_ISA_EXT_ZVKB }; +static const unsigned int riscv_sm_ext_versions[] = { + RISCV_ISA_EXT_SM1p11, + RISCV_ISA_EXT_SM1p12, +}; + +static const unsigned int riscv_ss_ext_versions[] = { + RISCV_ISA_EXT_SS1p11, + RISCV_ISA_EXT_SS1p12, +}; + /* * The canonical order of ISA extension names in the ISA string is defined in * chapter 27 of the unprivileged specification. @@ -299,8 +315,16 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH), __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), + __RISCV_ISA_EXT_VERSION(sm1p11, RISCV_ISA_EXT_SM1p11, riscv_sm_ext_versions, 0, + RISCV_ISA_EXT_SM1p12), + __RISCV_ISA_EXT_VERSION(sm1p12, RISCV_ISA_EXT_SM1p12, riscv_sm_ext_versions, 1, + RISCV_ISA_EXT_INVALID), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), + __RISCV_ISA_EXT_VERSION(ss1p11, RISCV_ISA_EXT_SS1p11, riscv_ss_ext_versions, 0, + RISCV_ISA_EXT_SS1p12), + __RISCV_ISA_EXT_VERSION(ss1p12, RISCV_ISA_EXT_SS1p12, riscv_ss_ext_versions, 1, + RISCV_ISA_EXT_INVALID), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), @@ -414,6 +438,14 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc ; ++ext_end; + + /* + * As a special case for the Sm and Ss extensions, where the version + * number is important, include it in the extension name. + */ + if (ext_end - ext == 2 && tolower(ext[0]) == 's' && + (tolower(ext[1]) == 'm' || tolower(ext[1]) == 's')) + ext_end = isa; break; default: /* -- 2.43.0 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH -fixes v2 3/4] riscv: Add ISA extension parsing for Sm and Ss 2024-02-13 3:37 ` [PATCH -fixes v2 3/4] riscv: Add ISA extension parsing for Sm and Ss Samuel Holland @ 2024-02-13 15:14 ` Andrew Jones 2024-02-13 17:52 ` Stefan O'Rear 2024-02-13 18:07 ` Conor Dooley 1 sibling, 1 reply; 15+ messages in thread From: Andrew Jones @ 2024-02-13 15:14 UTC (permalink / raw) To: Samuel Holland Cc: Palmer Dabbelt, linux-riscv, linux-kernel, Stefan O'Rear, stable On Mon, Feb 12, 2024 at 07:37:34PM -0800, Samuel Holland wrote: > Previously, all extension version numbers were ignored. However, the > version number is important for these two extensions. The simplest way > to implement this is to use a separate bitmap bit for each supported > version, with each successive version implying all of the previous ones. > This allows alternatives and riscv_has_extension_[un]likely() to work > naturally. > > To avoid duplicate extensions in /proc/cpuinfo, the new successor_id > field allows hiding all but the newest implemented version of an > extension. > > Cc: <stable@vger.kernel.org> # v6.7+ > Signed-off-by: Samuel Holland <samuel.holland@sifive.com> > --- > > Changes in v2: > - New patch for v2 > > arch/riscv/include/asm/cpufeature.h | 1 + > arch/riscv/include/asm/hwcap.h | 8 ++++++ > arch/riscv/kernel/cpu.c | 5 ++++ > arch/riscv/kernel/cpufeature.c | 42 +++++++++++++++++++++++++---- > 4 files changed, 51 insertions(+), 5 deletions(-) > > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h > index 0bd11862b760..ac71384e7bc4 100644 > --- a/arch/riscv/include/asm/cpufeature.h > +++ b/arch/riscv/include/asm/cpufeature.h > @@ -61,6 +61,7 @@ struct riscv_isa_ext_data { > const char *property; > const unsigned int *subset_ext_ids; > const unsigned int subset_ext_size; > + const unsigned int successor_id; > }; > > extern const struct riscv_isa_ext_data riscv_isa_ext[]; > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 5340f818746b..5b51aa1db15b 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -80,13 +80,21 @@ > #define RISCV_ISA_EXT_ZFA 71 > #define RISCV_ISA_EXT_ZTSO 72 > #define RISCV_ISA_EXT_ZACAS 73 > +#define RISCV_ISA_EXT_SM1p11 74 > +#define RISCV_ISA_EXT_SM1p12 75 > +#define RISCV_ISA_EXT_SS1p11 76 > +#define RISCV_ISA_EXT_SS1p12 77 > > #define RISCV_ISA_EXT_MAX 128 > #define RISCV_ISA_EXT_INVALID U32_MAX > > #ifdef CONFIG_RISCV_M_MODE > +#define RISCV_ISA_EXT_Sx1p11 RISCV_ISA_EXT_SM1p11 > +#define RISCV_ISA_EXT_Sx1p12 RISCV_ISA_EXT_SM1p12 > #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA > #else > +#define RISCV_ISA_EXT_Sx1p11 RISCV_ISA_EXT_SS1p11 > +#define RISCV_ISA_EXT_Sx1p12 RISCV_ISA_EXT_SS1p12 > #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA > #endif > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index d11d6320fb0d..2e6b90ed0d51 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -215,6 +215,11 @@ static void print_isa(struct seq_file *f, const unsigned long *isa_bitmap) > if (!__riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].id)) > continue; > > + /* Only show the newest implemented version of an extension */ > + if (riscv_isa_ext[i].successor_id != RISCV_ISA_EXT_INVALID && > + __riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].successor_id)) > + continue; I'm not sure we need this. Expanding Ss1p12 to 'Ss1p11 Ss1p12' and then outputting both in the ISA string doesn't seem harmful to me. Also, using a successor field instead of supersedes field may make this logic easy, but it'll require updating old code (changing RISCV_ISA_EXT_INVALID to the new version extension ID) when new versions are added. A supersedes field wouldn't require old code updates and would match the profiles spec which have explicit 'Ss1p12 supersedes Ss1p11.' type sentences. > + > /* Only multi-letter extensions are split by underscores */ > if (strnlen(riscv_isa_ext[i].name, 2) != 1) > seq_puts(f, "_"); > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index c5b13f7dd482..8e10b50120e9 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -113,23 +113,29 @@ static bool riscv_isa_extension_check(int id) > return true; > } > > -#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size) { \ > +#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size, _successor) { \ > .name = #_name, \ > .property = #_name, \ > .id = _id, \ > .subset_ext_ids = _subset_exts, \ > - .subset_ext_size = _subset_exts_size \ > + .subset_ext_size = _subset_exts_size, \ > + .successor_id = _successor, \ > } > > -#define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0) > +#define __RISCV_ISA_EXT_DATA(_name, _id) \ > + _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, RISCV_ISA_EXT_INVALID) > > /* Used to declare pure "lasso" extension (Zk for instance) */ > #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ > - _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, ARRAY_SIZE(_bundled_exts)) > + _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, \ > + _bundled_exts, ARRAY_SIZE(_bundled_exts), RISCV_ISA_EXT_INVALID) > > /* Used to declare extensions that are a superset of other extensions (Zvbb for instance) */ > #define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \ > - _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts)) > + _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), RISCV_ISA_EXT_INVALID) > + > +#define __RISCV_ISA_EXT_VERSION(_name, _id, _preds, _preds_size, _successor) \ > + _RISCV_ISA_EXT_DATA(_name, _id, _preds, _preds_size, _successor) > > static const unsigned int riscv_zk_bundled_exts[] = { > RISCV_ISA_EXT_ZBKB, > @@ -201,6 +207,16 @@ static const unsigned int riscv_zvbb_exts[] = { > RISCV_ISA_EXT_ZVKB > }; > > +static const unsigned int riscv_sm_ext_versions[] = { > + RISCV_ISA_EXT_SM1p11, > + RISCV_ISA_EXT_SM1p12, > +}; > + > +static const unsigned int riscv_ss_ext_versions[] = { > + RISCV_ISA_EXT_SS1p11, > + RISCV_ISA_EXT_SS1p12, > +}; > + > /* > * The canonical order of ISA extension names in the ISA string is defined in > * chapter 27 of the unprivileged specification. > @@ -299,8 +315,16 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH), > __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), > __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), > + __RISCV_ISA_EXT_VERSION(sm1p11, RISCV_ISA_EXT_SM1p11, riscv_sm_ext_versions, 0, > + RISCV_ISA_EXT_SM1p12), > + __RISCV_ISA_EXT_VERSION(sm1p12, RISCV_ISA_EXT_SM1p12, riscv_sm_ext_versions, 1, > + RISCV_ISA_EXT_INVALID), > __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), > __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), > + __RISCV_ISA_EXT_VERSION(ss1p11, RISCV_ISA_EXT_SS1p11, riscv_ss_ext_versions, 0, > + RISCV_ISA_EXT_SS1p12), > + __RISCV_ISA_EXT_VERSION(ss1p12, RISCV_ISA_EXT_SS1p12, riscv_ss_ext_versions, 1, > + RISCV_ISA_EXT_INVALID), > __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), > @@ -414,6 +438,14 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc > ; > > ++ext_end; > + > + /* > + * As a special case for the Sm and Ss extensions, where the version > + * number is important, include it in the extension name. > + */ > + if (ext_end - ext == 2 && tolower(ext[0]) == 's' && > + (tolower(ext[1]) == 'm' || tolower(ext[1]) == 's')) > + ext_end = isa; > break; > default: > /* > -- > 2.43.0 > Thanks, drew ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH -fixes v2 3/4] riscv: Add ISA extension parsing for Sm and Ss 2024-02-13 15:14 ` Andrew Jones @ 2024-02-13 17:52 ` Stefan O'Rear 2024-02-13 18:18 ` Samuel Holland 0 siblings, 1 reply; 15+ messages in thread From: Stefan O'Rear @ 2024-02-13 17:52 UTC (permalink / raw) To: Andrew Jones, Samuel Holland Cc: Palmer Dabbelt, linux-riscv, linux-kernel, stable On Tue, Feb 13, 2024, at 10:14 AM, Andrew Jones wrote: > On Mon, Feb 12, 2024 at 07:37:34PM -0800, Samuel Holland wrote: >> Previously, all extension version numbers were ignored. However, the >> version number is important for these two extensions. The simplest way >> to implement this is to use a separate bitmap bit for each supported >> version, with each successive version implying all of the previous ones. >> This allows alternatives and riscv_has_extension_[un]likely() to work >> naturally. >> >> To avoid duplicate extensions in /proc/cpuinfo, the new successor_id >> field allows hiding all but the newest implemented version of an >> extension. >> >> Cc: <stable@vger.kernel.org> # v6.7+ >> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> >> --- >> >> Changes in v2: >> - New patch for v2 >> >> arch/riscv/include/asm/cpufeature.h | 1 + >> arch/riscv/include/asm/hwcap.h | 8 ++++++ >> arch/riscv/kernel/cpu.c | 5 ++++ >> arch/riscv/kernel/cpufeature.c | 42 +++++++++++++++++++++++++---- >> 4 files changed, 51 insertions(+), 5 deletions(-) >> >> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h >> index 0bd11862b760..ac71384e7bc4 100644 >> --- a/arch/riscv/include/asm/cpufeature.h >> +++ b/arch/riscv/include/asm/cpufeature.h >> @@ -61,6 +61,7 @@ struct riscv_isa_ext_data { >> const char *property; >> const unsigned int *subset_ext_ids; >> const unsigned int subset_ext_size; >> + const unsigned int successor_id; >> }; >> >> extern const struct riscv_isa_ext_data riscv_isa_ext[]; >> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h >> index 5340f818746b..5b51aa1db15b 100644 >> --- a/arch/riscv/include/asm/hwcap.h >> +++ b/arch/riscv/include/asm/hwcap.h >> @@ -80,13 +80,21 @@ >> #define RISCV_ISA_EXT_ZFA 71 >> #define RISCV_ISA_EXT_ZTSO 72 >> #define RISCV_ISA_EXT_ZACAS 73 >> +#define RISCV_ISA_EXT_SM1p11 74 >> +#define RISCV_ISA_EXT_SM1p12 75 >> +#define RISCV_ISA_EXT_SS1p11 76 >> +#define RISCV_ISA_EXT_SS1p12 77 >> >> #define RISCV_ISA_EXT_MAX 128 >> #define RISCV_ISA_EXT_INVALID U32_MAX >> >> #ifdef CONFIG_RISCV_M_MODE >> +#define RISCV_ISA_EXT_Sx1p11 RISCV_ISA_EXT_SM1p11 >> +#define RISCV_ISA_EXT_Sx1p12 RISCV_ISA_EXT_SM1p12 >> #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA >> #else >> +#define RISCV_ISA_EXT_Sx1p11 RISCV_ISA_EXT_SS1p11 >> +#define RISCV_ISA_EXT_Sx1p12 RISCV_ISA_EXT_SS1p12 >> #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA >> #endif >> >> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c >> index d11d6320fb0d..2e6b90ed0d51 100644 >> --- a/arch/riscv/kernel/cpu.c >> +++ b/arch/riscv/kernel/cpu.c >> @@ -215,6 +215,11 @@ static void print_isa(struct seq_file *f, const unsigned long *isa_bitmap) >> if (!__riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].id)) >> continue; >> >> + /* Only show the newest implemented version of an extension */ >> + if (riscv_isa_ext[i].successor_id != RISCV_ISA_EXT_INVALID && >> + __riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].successor_id)) >> + continue; > > I'm not sure we need this. Expanding Ss1p12 to 'Ss1p11 Ss1p12' and then > outputting both in the ISA string doesn't seem harmful to me. Also, using > a successor field instead of supersedes field may make this logic easy, > but it'll require updating old code (changing RISCV_ISA_EXT_INVALID to the > new version extension ID) when new versions are added. A supersedes field > wouldn't require old code updates and would match the profiles spec which > have explicit 'Ss1p12 supersedes Ss1p11.' type sentences. Seconding - suppressing implied extensions in /proc/cpuinfo will require anything that parses /proc/cpuinfo to know about extension implication in order to generate the complete list. >> + >> /* Only multi-letter extensions are split by underscores */ >> if (strnlen(riscv_isa_ext[i].name, 2) != 1) >> seq_puts(f, "_"); >> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c >> index c5b13f7dd482..8e10b50120e9 100644 >> --- a/arch/riscv/kernel/cpufeature.c >> +++ b/arch/riscv/kernel/cpufeature.c >> @@ -113,23 +113,29 @@ static bool riscv_isa_extension_check(int id) >> return true; >> } >> >> -#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size) { \ >> +#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size, _successor) { \ >> .name = #_name, \ >> .property = #_name, \ >> .id = _id, \ >> .subset_ext_ids = _subset_exts, \ >> - .subset_ext_size = _subset_exts_size \ >> + .subset_ext_size = _subset_exts_size, \ >> + .successor_id = _successor, \ >> } >> >> -#define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0) >> +#define __RISCV_ISA_EXT_DATA(_name, _id) \ >> + _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, RISCV_ISA_EXT_INVALID) >> >> /* Used to declare pure "lasso" extension (Zk for instance) */ >> #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ >> - _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, ARRAY_SIZE(_bundled_exts)) >> + _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, \ >> + _bundled_exts, ARRAY_SIZE(_bundled_exts), RISCV_ISA_EXT_INVALID) >> >> /* Used to declare extensions that are a superset of other extensions (Zvbb for instance) */ >> #define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \ >> - _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts)) >> + _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), RISCV_ISA_EXT_INVALID) >> + >> +#define __RISCV_ISA_EXT_VERSION(_name, _id, _preds, _preds_size, _successor) \ >> + _RISCV_ISA_EXT_DATA(_name, _id, _preds, _preds_size, _successor) >> >> static const unsigned int riscv_zk_bundled_exts[] = { >> RISCV_ISA_EXT_ZBKB, >> @@ -201,6 +207,16 @@ static const unsigned int riscv_zvbb_exts[] = { >> RISCV_ISA_EXT_ZVKB >> }; >> >> +static const unsigned int riscv_sm_ext_versions[] = { >> + RISCV_ISA_EXT_SM1p11, >> + RISCV_ISA_EXT_SM1p12, >> +}; >> + >> +static const unsigned int riscv_ss_ext_versions[] = { >> + RISCV_ISA_EXT_SS1p11, >> + RISCV_ISA_EXT_SS1p12, >> +}; >> + >> /* >> * The canonical order of ISA extension names in the ISA string is defined in >> * chapter 27 of the unprivileged specification. >> @@ -299,8 +315,16 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { >> __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH), >> __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), >> __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), >> + __RISCV_ISA_EXT_VERSION(sm1p11, RISCV_ISA_EXT_SM1p11, riscv_sm_ext_versions, 0, >> + RISCV_ISA_EXT_SM1p12), >> + __RISCV_ISA_EXT_VERSION(sm1p12, RISCV_ISA_EXT_SM1p12, riscv_sm_ext_versions, 1, >> + RISCV_ISA_EXT_INVALID), >> __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), >> __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), >> + __RISCV_ISA_EXT_VERSION(ss1p11, RISCV_ISA_EXT_SS1p11, riscv_ss_ext_versions, 0, >> + RISCV_ISA_EXT_SS1p12), >> + __RISCV_ISA_EXT_VERSION(ss1p12, RISCV_ISA_EXT_SS1p12, riscv_ss_ext_versions, 1, >> + RISCV_ISA_EXT_INVALID), >> __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), >> __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), >> __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), >> @@ -414,6 +438,14 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc >> ; >> >> ++ext_end; >> + >> + /* >> + * As a special case for the Sm and Ss extensions, where the version >> + * number is important, include it in the extension name. >> + */ >> + if (ext_end - ext == 2 && tolower(ext[0]) == 's' && >> + (tolower(ext[1]) == 'm' || tolower(ext[1]) == 's')) >> + ext_end = isa; Per the strategy in [1] we treat every ratified version of every extension as a unique extension; the unique aspect here is that more than one version of Sm/Ss is defined. [1]: https://lore.kernel.org/linux-riscv/20230608-sitting-bath-31eddc03c5a5@spud/ -s >> break; >> default: >> /* >> -- >> 2.43.0 >> > > Thanks, > drew > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH -fixes v2 3/4] riscv: Add ISA extension parsing for Sm and Ss 2024-02-13 17:52 ` Stefan O'Rear @ 2024-02-13 18:18 ` Samuel Holland 0 siblings, 0 replies; 15+ messages in thread From: Samuel Holland @ 2024-02-13 18:18 UTC (permalink / raw) To: Stefan O'Rear, Andrew Jones Cc: Palmer Dabbelt, linux-riscv, linux-kernel, stable On 2024-02-13 11:52 AM, Stefan O'Rear wrote: > On Tue, Feb 13, 2024, at 10:14 AM, Andrew Jones wrote: >> On Mon, Feb 12, 2024 at 07:37:34PM -0800, Samuel Holland wrote: >>> Previously, all extension version numbers were ignored. However, the >>> version number is important for these two extensions. The simplest way >>> to implement this is to use a separate bitmap bit for each supported >>> version, with each successive version implying all of the previous ones. >>> This allows alternatives and riscv_has_extension_[un]likely() to work >>> naturally. >>> >>> To avoid duplicate extensions in /proc/cpuinfo, the new successor_id >>> field allows hiding all but the newest implemented version of an >>> extension. >>> >>> Cc: <stable@vger.kernel.org> # v6.7+ >>> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> >>> --- >>> >>> Changes in v2: >>> - New patch for v2 >>> >>> arch/riscv/include/asm/cpufeature.h | 1 + >>> arch/riscv/include/asm/hwcap.h | 8 ++++++ >>> arch/riscv/kernel/cpu.c | 5 ++++ >>> arch/riscv/kernel/cpufeature.c | 42 +++++++++++++++++++++++++---- >>> 4 files changed, 51 insertions(+), 5 deletions(-) >>> >>> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h >>> index 0bd11862b760..ac71384e7bc4 100644 >>> --- a/arch/riscv/include/asm/cpufeature.h >>> +++ b/arch/riscv/include/asm/cpufeature.h >>> @@ -61,6 +61,7 @@ struct riscv_isa_ext_data { >>> const char *property; >>> const unsigned int *subset_ext_ids; >>> const unsigned int subset_ext_size; >>> + const unsigned int successor_id; >>> }; >>> >>> extern const struct riscv_isa_ext_data riscv_isa_ext[]; >>> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h >>> index 5340f818746b..5b51aa1db15b 100644 >>> --- a/arch/riscv/include/asm/hwcap.h >>> +++ b/arch/riscv/include/asm/hwcap.h >>> @@ -80,13 +80,21 @@ >>> #define RISCV_ISA_EXT_ZFA 71 >>> #define RISCV_ISA_EXT_ZTSO 72 >>> #define RISCV_ISA_EXT_ZACAS 73 >>> +#define RISCV_ISA_EXT_SM1p11 74 >>> +#define RISCV_ISA_EXT_SM1p12 75 >>> +#define RISCV_ISA_EXT_SS1p11 76 >>> +#define RISCV_ISA_EXT_SS1p12 77 >>> >>> #define RISCV_ISA_EXT_MAX 128 >>> #define RISCV_ISA_EXT_INVALID U32_MAX >>> >>> #ifdef CONFIG_RISCV_M_MODE >>> +#define RISCV_ISA_EXT_Sx1p11 RISCV_ISA_EXT_SM1p11 >>> +#define RISCV_ISA_EXT_Sx1p12 RISCV_ISA_EXT_SM1p12 >>> #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA >>> #else >>> +#define RISCV_ISA_EXT_Sx1p11 RISCV_ISA_EXT_SS1p11 >>> +#define RISCV_ISA_EXT_Sx1p12 RISCV_ISA_EXT_SS1p12 >>> #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA >>> #endif >>> >>> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c >>> index d11d6320fb0d..2e6b90ed0d51 100644 >>> --- a/arch/riscv/kernel/cpu.c >>> +++ b/arch/riscv/kernel/cpu.c >>> @@ -215,6 +215,11 @@ static void print_isa(struct seq_file *f, const unsigned long *isa_bitmap) >>> if (!__riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].id)) >>> continue; >>> >>> + /* Only show the newest implemented version of an extension */ >>> + if (riscv_isa_ext[i].successor_id != RISCV_ISA_EXT_INVALID && >>> + __riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].successor_id)) >>> + continue; >> >> I'm not sure we need this. Expanding Ss1p12 to 'Ss1p11 Ss1p12' and then >> outputting both in the ISA string doesn't seem harmful to me. Also, using I was thinking that parsers would be confused by seeing the same extension multiple times, but I have no problem with it if folks disagree. >> a successor field instead of supersedes field may make this logic easy, >> but it'll require updating old code (changing RISCV_ISA_EXT_INVALID to the >> new version extension ID) when new versions are added. A supersedes field >> wouldn't require old code updates and would match the profiles spec which >> have explicit 'Ss1p12 supersedes Ss1p11.' type sentences. > > Seconding - suppressing implied extensions in /proc/cpuinfo will require anything > that parses /proc/cpuinfo to know about extension implication in order to > generate the complete list. Well, from an ISA string perspective (i.e. what's shown in /proc/cpuinfo), only including the latest version _does_ give you the complete list, because Ss1p11 and Ss1p12 aren't different extensions. I'm only expanding them to different flags inside the kernel so we can avoid storing the version number as an integer and doing numeric comparisons at each usage site. So /proc/cpuinfo parsers wouldn't need to know about implication, since that's a kernel implementation detail. They just need to know how to parse the version number from an ISA string. And I would expect them to be able to do that anyway. There would only be backward-compatibility concerns if parsers are doing a string match on the whole "ss1p12", which I would consider wrong to start with. Regards, Samuel ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH -fixes v2 3/4] riscv: Add ISA extension parsing for Sm and Ss 2024-02-13 3:37 ` [PATCH -fixes v2 3/4] riscv: Add ISA extension parsing for Sm and Ss Samuel Holland 2024-02-13 15:14 ` Andrew Jones @ 2024-02-13 18:07 ` Conor Dooley 2024-02-13 20:22 ` Samuel Holland 1 sibling, 1 reply; 15+ messages in thread From: Conor Dooley @ 2024-02-13 18:07 UTC (permalink / raw) To: Samuel Holland Cc: Palmer Dabbelt, Andrew Jones, linux-riscv, linux-kernel, Stefan O'Rear, stable [-- Attachment #1: Type: text/plain, Size: 8043 bytes --] On Mon, Feb 12, 2024 at 07:37:34PM -0800, Samuel Holland wrote: > Previously, all extension version numbers were ignored. However, the > version number is important for these two extensions. The simplest way > to implement this is to use a separate bitmap bit for each supported > version, with each successive version implying all of the previous ones. > This allows alternatives and riscv_has_extension_[un]likely() to work > naturally. > > To avoid duplicate extensions in /proc/cpuinfo, the new successor_id > field allows hiding all but the newest implemented version of an > extension. > > Cc: <stable@vger.kernel.org> # v6.7+ > Signed-off-by: Samuel Holland <samuel.holland@sifive.com> > --- > > Changes in v2: > - New patch for v2 > > arch/riscv/include/asm/cpufeature.h | 1 + > arch/riscv/include/asm/hwcap.h | 8 ++++++ > arch/riscv/kernel/cpu.c | 5 ++++ > arch/riscv/kernel/cpufeature.c | 42 +++++++++++++++++++++++++---- > 4 files changed, 51 insertions(+), 5 deletions(-) > > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h > index 0bd11862b760..ac71384e7bc4 100644 > --- a/arch/riscv/include/asm/cpufeature.h > +++ b/arch/riscv/include/asm/cpufeature.h > @@ -61,6 +61,7 @@ struct riscv_isa_ext_data { > const char *property; > const unsigned int *subset_ext_ids; > const unsigned int subset_ext_size; > + const unsigned int successor_id; > }; > > extern const struct riscv_isa_ext_data riscv_isa_ext[]; > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 5340f818746b..5b51aa1db15b 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -80,13 +80,21 @@ > #define RISCV_ISA_EXT_ZFA 71 > #define RISCV_ISA_EXT_ZTSO 72 > #define RISCV_ISA_EXT_ZACAS 73 > +#define RISCV_ISA_EXT_SM1p11 74 > +#define RISCV_ISA_EXT_SM1p12 75 > +#define RISCV_ISA_EXT_SS1p11 76 > +#define RISCV_ISA_EXT_SS1p12 77 > > #define RISCV_ISA_EXT_MAX 128 > #define RISCV_ISA_EXT_INVALID U32_MAX > > #ifdef CONFIG_RISCV_M_MODE > +#define RISCV_ISA_EXT_Sx1p11 RISCV_ISA_EXT_SM1p11 > +#define RISCV_ISA_EXT_Sx1p12 RISCV_ISA_EXT_SM1p12 > #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA > #else > +#define RISCV_ISA_EXT_Sx1p11 RISCV_ISA_EXT_SS1p11 > +#define RISCV_ISA_EXT_Sx1p12 RISCV_ISA_EXT_SS1p12 > #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA > #endif > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index d11d6320fb0d..2e6b90ed0d51 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -215,6 +215,11 @@ static void print_isa(struct seq_file *f, const unsigned long *isa_bitmap) > if (!__riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].id)) > continue; > > + /* Only show the newest implemented version of an extension */ > + if (riscv_isa_ext[i].successor_id != RISCV_ISA_EXT_INVALID && > + __riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].successor_id)) > + continue; > + > /* Only multi-letter extensions are split by underscores */ > if (strnlen(riscv_isa_ext[i].name, 2) != 1) > seq_puts(f, "_"); > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index c5b13f7dd482..8e10b50120e9 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -113,23 +113,29 @@ static bool riscv_isa_extension_check(int id) > return true; > } > > -#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size) { \ > +#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size, _successor) { \ > .name = #_name, \ > .property = #_name, \ > .id = _id, \ > .subset_ext_ids = _subset_exts, \ > - .subset_ext_size = _subset_exts_size \ > + .subset_ext_size = _subset_exts_size, \ > + .successor_id = _successor, \ > } > > -#define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0) > +#define __RISCV_ISA_EXT_DATA(_name, _id) \ > + _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, RISCV_ISA_EXT_INVALID) > > /* Used to declare pure "lasso" extension (Zk for instance) */ > #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ > - _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, ARRAY_SIZE(_bundled_exts)) > + _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, \ > + _bundled_exts, ARRAY_SIZE(_bundled_exts), RISCV_ISA_EXT_INVALID) > > /* Used to declare extensions that are a superset of other extensions (Zvbb for instance) */ > #define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \ > - _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts)) > + _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), RISCV_ISA_EXT_INVALID) > + > +#define __RISCV_ISA_EXT_VERSION(_name, _id, _preds, _preds_size, _successor) \ > + _RISCV_ISA_EXT_DATA(_name, _id, _preds, _preds_size, _successor) > > static const unsigned int riscv_zk_bundled_exts[] = { > RISCV_ISA_EXT_ZBKB, > @@ -201,6 +207,16 @@ static const unsigned int riscv_zvbb_exts[] = { > RISCV_ISA_EXT_ZVKB > }; > > +static const unsigned int riscv_sm_ext_versions[] = { > + RISCV_ISA_EXT_SM1p11, > + RISCV_ISA_EXT_SM1p12, > +}; > + > +static const unsigned int riscv_ss_ext_versions[] = { > + RISCV_ISA_EXT_SS1p11, > + RISCV_ISA_EXT_SS1p12, > +}; > + > /* > * The canonical order of ISA extension names in the ISA string is defined in > * chapter 27 of the unprivileged specification. > @@ -299,8 +315,16 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH), > __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), > __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), > + __RISCV_ISA_EXT_VERSION(sm1p11, RISCV_ISA_EXT_SM1p11, riscv_sm_ext_versions, 0, > + RISCV_ISA_EXT_SM1p12), > + __RISCV_ISA_EXT_VERSION(sm1p12, RISCV_ISA_EXT_SM1p12, riscv_sm_ext_versions, 1, > + RISCV_ISA_EXT_INVALID), > __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), > __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), > + __RISCV_ISA_EXT_VERSION(ss1p11, RISCV_ISA_EXT_SS1p11, riscv_ss_ext_versions, 0, > + RISCV_ISA_EXT_SS1p12), > + __RISCV_ISA_EXT_VERSION(ss1p12, RISCV_ISA_EXT_SS1p12, riscv_ss_ext_versions, 1, > + RISCV_ISA_EXT_INVALID), > __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), > @@ -414,6 +438,14 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc > ; > > ++ext_end; > + > + /* > + * As a special case for the Sm and Ss extensions, where the version > + * number is important, include it in the extension name. > + */ > + if (ext_end - ext == 2 && tolower(ext[0]) == 's' && > + (tolower(ext[1]) == 'm' || tolower(ext[1]) == 's')) > + ext_end = isa; > break; > default: > /* Hmm, looking at all of this (especially this hack to the "old" parser), I feel more like these should be promoted to a property of their own. The "old" parser was designed to handle numbers, and here when you're interested in the values behind the numbers (which is a first iirc), you don't make any use of that. I don't really want to see a world where we have every single iteration of smNpM under the sun in the property, because there's a fair bit of churn in the isa. Granted, this applies to all the various, the difference for me is the level of churn. Or maybe we can still with the properties you have, but instead of treating them like any other extension, handle these separately, focusing on the numbering, so that only having the exact version supported by a cpu is possible. I'm still pretty undecided, I'd like to think about this a little bit, but I think we can do better here. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH -fixes v2 3/4] riscv: Add ISA extension parsing for Sm and Ss 2024-02-13 18:07 ` Conor Dooley @ 2024-02-13 20:22 ` Samuel Holland 2024-02-13 20:43 ` Stefan O'Rear 0 siblings, 1 reply; 15+ messages in thread From: Samuel Holland @ 2024-02-13 20:22 UTC (permalink / raw) To: Conor Dooley Cc: Palmer Dabbelt, Andrew Jones, linux-riscv, linux-kernel, Stefan O'Rear, stable On 2024-02-13 12:07 PM, Conor Dooley wrote: > On Mon, Feb 12, 2024 at 07:37:34PM -0800, Samuel Holland wrote: >> Previously, all extension version numbers were ignored. However, the >> version number is important for these two extensions. The simplest way >> to implement this is to use a separate bitmap bit for each supported >> version, with each successive version implying all of the previous ones. >> This allows alternatives and riscv_has_extension_[un]likely() to work >> naturally. >> >> To avoid duplicate extensions in /proc/cpuinfo, the new successor_id >> field allows hiding all but the newest implemented version of an >> extension. >> >> Cc: <stable@vger.kernel.org> # v6.7+ >> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> >> --- >> >> Changes in v2: >> - New patch for v2 >> >> arch/riscv/include/asm/cpufeature.h | 1 + >> arch/riscv/include/asm/hwcap.h | 8 ++++++ >> arch/riscv/kernel/cpu.c | 5 ++++ >> arch/riscv/kernel/cpufeature.c | 42 +++++++++++++++++++++++++---- >> 4 files changed, 51 insertions(+), 5 deletions(-) >> >> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h >> index 0bd11862b760..ac71384e7bc4 100644 >> --- a/arch/riscv/include/asm/cpufeature.h >> +++ b/arch/riscv/include/asm/cpufeature.h >> @@ -61,6 +61,7 @@ struct riscv_isa_ext_data { >> const char *property; >> const unsigned int *subset_ext_ids; >> const unsigned int subset_ext_size; >> + const unsigned int successor_id; >> }; >> >> extern const struct riscv_isa_ext_data riscv_isa_ext[]; >> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h >> index 5340f818746b..5b51aa1db15b 100644 >> --- a/arch/riscv/include/asm/hwcap.h >> +++ b/arch/riscv/include/asm/hwcap.h >> @@ -80,13 +80,21 @@ >> #define RISCV_ISA_EXT_ZFA 71 >> #define RISCV_ISA_EXT_ZTSO 72 >> #define RISCV_ISA_EXT_ZACAS 73 >> +#define RISCV_ISA_EXT_SM1p11 74 >> +#define RISCV_ISA_EXT_SM1p12 75 >> +#define RISCV_ISA_EXT_SS1p11 76 >> +#define RISCV_ISA_EXT_SS1p12 77 >> >> #define RISCV_ISA_EXT_MAX 128 >> #define RISCV_ISA_EXT_INVALID U32_MAX >> >> #ifdef CONFIG_RISCV_M_MODE >> +#define RISCV_ISA_EXT_Sx1p11 RISCV_ISA_EXT_SM1p11 >> +#define RISCV_ISA_EXT_Sx1p12 RISCV_ISA_EXT_SM1p12 >> #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA >> #else >> +#define RISCV_ISA_EXT_Sx1p11 RISCV_ISA_EXT_SS1p11 >> +#define RISCV_ISA_EXT_Sx1p12 RISCV_ISA_EXT_SS1p12 >> #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA >> #endif >> >> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c >> index d11d6320fb0d..2e6b90ed0d51 100644 >> --- a/arch/riscv/kernel/cpu.c >> +++ b/arch/riscv/kernel/cpu.c >> @@ -215,6 +215,11 @@ static void print_isa(struct seq_file *f, const unsigned long *isa_bitmap) >> if (!__riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].id)) >> continue; >> >> + /* Only show the newest implemented version of an extension */ >> + if (riscv_isa_ext[i].successor_id != RISCV_ISA_EXT_INVALID && >> + __riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].successor_id)) >> + continue; >> + >> /* Only multi-letter extensions are split by underscores */ >> if (strnlen(riscv_isa_ext[i].name, 2) != 1) >> seq_puts(f, "_"); >> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c >> index c5b13f7dd482..8e10b50120e9 100644 >> --- a/arch/riscv/kernel/cpufeature.c >> +++ b/arch/riscv/kernel/cpufeature.c >> @@ -113,23 +113,29 @@ static bool riscv_isa_extension_check(int id) >> return true; >> } >> >> -#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size) { \ >> +#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size, _successor) { \ >> .name = #_name, \ >> .property = #_name, \ >> .id = _id, \ >> .subset_ext_ids = _subset_exts, \ >> - .subset_ext_size = _subset_exts_size \ >> + .subset_ext_size = _subset_exts_size, \ >> + .successor_id = _successor, \ >> } >> >> -#define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0) >> +#define __RISCV_ISA_EXT_DATA(_name, _id) \ >> + _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, RISCV_ISA_EXT_INVALID) >> >> /* Used to declare pure "lasso" extension (Zk for instance) */ >> #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ >> - _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, ARRAY_SIZE(_bundled_exts)) >> + _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, \ >> + _bundled_exts, ARRAY_SIZE(_bundled_exts), RISCV_ISA_EXT_INVALID) >> >> /* Used to declare extensions that are a superset of other extensions (Zvbb for instance) */ >> #define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \ >> - _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts)) >> + _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), RISCV_ISA_EXT_INVALID) >> + >> +#define __RISCV_ISA_EXT_VERSION(_name, _id, _preds, _preds_size, _successor) \ >> + _RISCV_ISA_EXT_DATA(_name, _id, _preds, _preds_size, _successor) >> >> static const unsigned int riscv_zk_bundled_exts[] = { >> RISCV_ISA_EXT_ZBKB, >> @@ -201,6 +207,16 @@ static const unsigned int riscv_zvbb_exts[] = { >> RISCV_ISA_EXT_ZVKB >> }; >> >> +static const unsigned int riscv_sm_ext_versions[] = { >> + RISCV_ISA_EXT_SM1p11, >> + RISCV_ISA_EXT_SM1p12, >> +}; >> + >> +static const unsigned int riscv_ss_ext_versions[] = { >> + RISCV_ISA_EXT_SS1p11, >> + RISCV_ISA_EXT_SS1p12, >> +}; >> + >> /* >> * The canonical order of ISA extension names in the ISA string is defined in >> * chapter 27 of the unprivileged specification. >> @@ -299,8 +315,16 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { >> __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH), >> __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), >> __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), >> + __RISCV_ISA_EXT_VERSION(sm1p11, RISCV_ISA_EXT_SM1p11, riscv_sm_ext_versions, 0, >> + RISCV_ISA_EXT_SM1p12), >> + __RISCV_ISA_EXT_VERSION(sm1p12, RISCV_ISA_EXT_SM1p12, riscv_sm_ext_versions, 1, >> + RISCV_ISA_EXT_INVALID), >> __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), >> __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), >> + __RISCV_ISA_EXT_VERSION(ss1p11, RISCV_ISA_EXT_SS1p11, riscv_ss_ext_versions, 0, >> + RISCV_ISA_EXT_SS1p12), >> + __RISCV_ISA_EXT_VERSION(ss1p12, RISCV_ISA_EXT_SS1p12, riscv_ss_ext_versions, 1, >> + RISCV_ISA_EXT_INVALID), >> __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), >> __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), >> __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), >> @@ -414,6 +438,14 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc >> ; >> >> ++ext_end; >> + >> + /* >> + * As a special case for the Sm and Ss extensions, where the version >> + * number is important, include it in the extension name. >> + */ >> + if (ext_end - ext == 2 && tolower(ext[0]) == 's' && >> + (tolower(ext[1]) == 'm' || tolower(ext[1]) == 's')) >> + ext_end = isa; >> break; >> default: >> /* > > > Hmm, looking at all of this (especially this hack to the "old" parser), > I feel more like these should be promoted to a property of their own. > The "old" parser was designed to handle numbers, and here when you're > interested in the values behind the numbers (which is a first iirc), you > don't make any use of that. I don't really want to see a world where I had a version of this code that parsed the numbers and stored them as integers in `struct riscv_isainfo`. It didn't work with of_property_match_string() as used for riscv,isa-extensions, since that function expects the extension name to be the full string. Either we would need to change the code to parse a version number out of each string in the riscv,isa-extensions list (and make the binding a bunch of regexes), or we need a separate "extension" entry (and DT binding entry) for each supported version. I chose the second option, and as a consequence I didn't actually need to parse the integer value in the ISA string code path either. > we have every single iteration of smNpM under the sun in the property, > because there's a fair bit of churn in the isa. Granted, this applies to > all the various, the difference for me is the level of churn. Indeed. In fact, one thought I had while looking at this code is that we should be ignoring any extension in the ISA string with a version < 1.0 or >= 2.0, since those won't be compatible with what we expect. > Or maybe we can still with the properties you have, but instead of > treating them like any other extension, handle these separately, > focusing on the numbering, so that only having the exact version > supported by a cpu is possible. Maybe I'm misunderstanding what you're saying here, but it is already the case that the DT for a CPU would only contain the exact version of the privileged ISA supported by that CPU. With this implementation, the fact that the integer version gets expanded to a series of flags is supposed to be invisible in the DT and to userspace. I realize I don't quite succeed there: putting "ss1p13" in the ISA string should work, but does not. > I'm still pretty undecided, I'd like to think about this a little bit, > but I think we can do better here. Sure, no problem. I'm happy to implement whatever we agree on. Though one consideration I had is that this is all in support of fixing a bug in v6.7, so I wanted the changes to be backportable. I suppose the easy way out for backporting is to check for RISCV_ISA_EXT_ZICBOZ for now, and then solve the larger problem once there is some other user of the envcfg CSR (or another Ss1p12 feature). Regards, Samuel ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH -fixes v2 3/4] riscv: Add ISA extension parsing for Sm and Ss 2024-02-13 20:22 ` Samuel Holland @ 2024-02-13 20:43 ` Stefan O'Rear 2024-02-13 23:15 ` Conor Dooley 0 siblings, 1 reply; 15+ messages in thread From: Stefan O'Rear @ 2024-02-13 20:43 UTC (permalink / raw) To: Samuel Holland, Conor Dooley Cc: Palmer Dabbelt, Andrew Jones, linux-riscv, linux-kernel, stable On Tue, Feb 13, 2024, at 3:22 PM, Samuel Holland wrote: > On 2024-02-13 12:07 PM, Conor Dooley wrote: >> On Mon, Feb 12, 2024 at 07:37:34PM -0800, Samuel Holland wrote: >>> Previously, all extension version numbers were ignored. However, the >>> version number is important for these two extensions. The simplest way >>> to implement this is to use a separate bitmap bit for each supported >>> version, with each successive version implying all of the previous ones. >>> This allows alternatives and riscv_has_extension_[un]likely() to work >>> naturally. >>> >>> To avoid duplicate extensions in /proc/cpuinfo, the new successor_id >>> field allows hiding all but the newest implemented version of an >>> extension. >>> >>> Cc: <stable@vger.kernel.org> # v6.7+ >>> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> >>> --- >>> >>> Changes in v2: >>> - New patch for v2 >>> >>> arch/riscv/include/asm/cpufeature.h | 1 + >>> arch/riscv/include/asm/hwcap.h | 8 ++++++ >>> arch/riscv/kernel/cpu.c | 5 ++++ >>> arch/riscv/kernel/cpufeature.c | 42 +++++++++++++++++++++++++---- >>> 4 files changed, 51 insertions(+), 5 deletions(-) >>> >>> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h >>> index 0bd11862b760..ac71384e7bc4 100644 >>> --- a/arch/riscv/include/asm/cpufeature.h >>> +++ b/arch/riscv/include/asm/cpufeature.h >>> @@ -61,6 +61,7 @@ struct riscv_isa_ext_data { >>> const char *property; >>> const unsigned int *subset_ext_ids; >>> const unsigned int subset_ext_size; >>> + const unsigned int successor_id; >>> }; >>> >>> extern const struct riscv_isa_ext_data riscv_isa_ext[]; >>> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h >>> index 5340f818746b..5b51aa1db15b 100644 >>> --- a/arch/riscv/include/asm/hwcap.h >>> +++ b/arch/riscv/include/asm/hwcap.h >>> @@ -80,13 +80,21 @@ >>> #define RISCV_ISA_EXT_ZFA 71 >>> #define RISCV_ISA_EXT_ZTSO 72 >>> #define RISCV_ISA_EXT_ZACAS 73 >>> +#define RISCV_ISA_EXT_SM1p11 74 >>> +#define RISCV_ISA_EXT_SM1p12 75 >>> +#define RISCV_ISA_EXT_SS1p11 76 >>> +#define RISCV_ISA_EXT_SS1p12 77 >>> >>> #define RISCV_ISA_EXT_MAX 128 >>> #define RISCV_ISA_EXT_INVALID U32_MAX >>> >>> #ifdef CONFIG_RISCV_M_MODE >>> +#define RISCV_ISA_EXT_Sx1p11 RISCV_ISA_EXT_SM1p11 >>> +#define RISCV_ISA_EXT_Sx1p12 RISCV_ISA_EXT_SM1p12 >>> #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA >>> #else >>> +#define RISCV_ISA_EXT_Sx1p11 RISCV_ISA_EXT_SS1p11 >>> +#define RISCV_ISA_EXT_Sx1p12 RISCV_ISA_EXT_SS1p12 >>> #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA >>> #endif >>> >>> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c >>> index d11d6320fb0d..2e6b90ed0d51 100644 >>> --- a/arch/riscv/kernel/cpu.c >>> +++ b/arch/riscv/kernel/cpu.c >>> @@ -215,6 +215,11 @@ static void print_isa(struct seq_file *f, const unsigned long *isa_bitmap) >>> if (!__riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].id)) >>> continue; >>> >>> + /* Only show the newest implemented version of an extension */ >>> + if (riscv_isa_ext[i].successor_id != RISCV_ISA_EXT_INVALID && >>> + __riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].successor_id)) >>> + continue; >>> + >>> /* Only multi-letter extensions are split by underscores */ >>> if (strnlen(riscv_isa_ext[i].name, 2) != 1) >>> seq_puts(f, "_"); >>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c >>> index c5b13f7dd482..8e10b50120e9 100644 >>> --- a/arch/riscv/kernel/cpufeature.c >>> +++ b/arch/riscv/kernel/cpufeature.c >>> @@ -113,23 +113,29 @@ static bool riscv_isa_extension_check(int id) >>> return true; >>> } >>> >>> -#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size) { \ >>> +#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size, _successor) { \ >>> .name = #_name, \ >>> .property = #_name, \ >>> .id = _id, \ >>> .subset_ext_ids = _subset_exts, \ >>> - .subset_ext_size = _subset_exts_size \ >>> + .subset_ext_size = _subset_exts_size, \ >>> + .successor_id = _successor, \ >>> } >>> >>> -#define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0) >>> +#define __RISCV_ISA_EXT_DATA(_name, _id) \ >>> + _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, RISCV_ISA_EXT_INVALID) >>> >>> /* Used to declare pure "lasso" extension (Zk for instance) */ >>> #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ >>> - _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, ARRAY_SIZE(_bundled_exts)) >>> + _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, \ >>> + _bundled_exts, ARRAY_SIZE(_bundled_exts), RISCV_ISA_EXT_INVALID) >>> >>> /* Used to declare extensions that are a superset of other extensions (Zvbb for instance) */ >>> #define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \ >>> - _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts)) >>> + _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), RISCV_ISA_EXT_INVALID) >>> + >>> +#define __RISCV_ISA_EXT_VERSION(_name, _id, _preds, _preds_size, _successor) \ >>> + _RISCV_ISA_EXT_DATA(_name, _id, _preds, _preds_size, _successor) >>> >>> static const unsigned int riscv_zk_bundled_exts[] = { >>> RISCV_ISA_EXT_ZBKB, >>> @@ -201,6 +207,16 @@ static const unsigned int riscv_zvbb_exts[] = { >>> RISCV_ISA_EXT_ZVKB >>> }; >>> >>> +static const unsigned int riscv_sm_ext_versions[] = { >>> + RISCV_ISA_EXT_SM1p11, >>> + RISCV_ISA_EXT_SM1p12, >>> +}; >>> + >>> +static const unsigned int riscv_ss_ext_versions[] = { >>> + RISCV_ISA_EXT_SS1p11, >>> + RISCV_ISA_EXT_SS1p12, >>> +}; >>> + >>> /* >>> * The canonical order of ISA extension names in the ISA string is defined in >>> * chapter 27 of the unprivileged specification. >>> @@ -299,8 +315,16 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { >>> __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH), >>> __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), >>> __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), >>> + __RISCV_ISA_EXT_VERSION(sm1p11, RISCV_ISA_EXT_SM1p11, riscv_sm_ext_versions, 0, >>> + RISCV_ISA_EXT_SM1p12), >>> + __RISCV_ISA_EXT_VERSION(sm1p12, RISCV_ISA_EXT_SM1p12, riscv_sm_ext_versions, 1, >>> + RISCV_ISA_EXT_INVALID), >>> __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), >>> __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), >>> + __RISCV_ISA_EXT_VERSION(ss1p11, RISCV_ISA_EXT_SS1p11, riscv_ss_ext_versions, 0, >>> + RISCV_ISA_EXT_SS1p12), >>> + __RISCV_ISA_EXT_VERSION(ss1p12, RISCV_ISA_EXT_SS1p12, riscv_ss_ext_versions, 1, >>> + RISCV_ISA_EXT_INVALID), >>> __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), >>> __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), >>> __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), >>> @@ -414,6 +438,14 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc >>> ; >>> >>> ++ext_end; >>> + >>> + /* >>> + * As a special case for the Sm and Ss extensions, where the version >>> + * number is important, include it in the extension name. >>> + */ >>> + if (ext_end - ext == 2 && tolower(ext[0]) == 's' && >>> + (tolower(ext[1]) == 'm' || tolower(ext[1]) == 's')) >>> + ext_end = isa; >>> break; >>> default: >>> /* >> >> >> Hmm, looking at all of this (especially this hack to the "old" parser), >> I feel more like these should be promoted to a property of their own. >> The "old" parser was designed to handle numbers, and here when you're >> interested in the values behind the numbers (which is a first iirc), you >> don't make any use of that. I don't really want to see a world where > > I had a version of this code that parsed the numbers and stored them as integers > in `struct riscv_isainfo`. It didn't work with of_property_match_string() as > used for riscv,isa-extensions, since that function expects the extension name to > be the full string. Either we would need to change the code to parse a version > number out of each string in the riscv,isa-extensions list (and make the binding > a bunch of regexes), or we need a separate "extension" entry (and DT binding > entry) for each supported version. Version numbers aren't real, there's no compatibility promise that we can consistently rely on so we treat riscv,isa-extensions as simply containing alphanumeric extensions. This was an intentional part of simplifying riscv,isa into riscv,isa-extensions. > I chose the second option, and as a consequence I didn't actually need to parse > the integer value in the ISA string code path either. > >> we have every single iteration of smNpM under the sun in the property, >> because there's a fair bit of churn in the isa. Granted, this applies to >> all the various, the difference for me is the level of churn. > > Indeed. In fact, one thought I had while looking at this code is that we should > be ignoring any extension in the ISA string with a version < 1.0 or >= 2.0, > since those won't be compatible with what we expect. I might go further and say that we should only accept specific exact versions of extensions other than Ss/Sm. This could be revisited after the recent "semver for ISA extensions" policy is tested at least once under real-world conditions. Right now we have two ratified versions of Ss/Sm, soon to be three, and one ratified version of all other extensions. I hardly think this is an excessive amount of churn. >> Or maybe we can still with the properties you have, but instead of >> treating them like any other extension, handle these separately, >> focusing on the numbering, so that only having the exact version >> supported by a cpu is possible. > > Maybe I'm misunderstanding what you're saying here, but it is already the case > that the DT for a CPU would only contain the exact version of the privileged ISA > supported by that CPU. If privileged spec versions are boolean extensions, then you would say "ss1p11", "ss1p12", "ss1p13" as separate/simultaneous extensions. This is needed in order to allow simple support checks as described in the riscv,isa-extensions cover letter. > With this implementation, the fact that the integer version gets expanded to a > series of flags is supposed to be invisible in the DT and to userspace. I > realize I don't quite succeed there: putting "ss1p13" in the ISA string should > work, but does not. > >> I'm still pretty undecided, I'd like to think about this a little bit, >> but I think we can do better here. > > Sure, no problem. I'm happy to implement whatever we agree on. Though one > consideration I had is that this is all in support of fixing a bug in v6.7, so I > wanted the changes to be backportable. > > I suppose the easy way out for backporting is to check for RISCV_ISA_EXT_ZICBOZ > for now, and then solve the larger problem once there is some other user of the > envcfg CSR (or another Ss1p12 feature). I support that course of action. -s > Regards, > Samuel > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH -fixes v2 3/4] riscv: Add ISA extension parsing for Sm and Ss 2024-02-13 20:43 ` Stefan O'Rear @ 2024-02-13 23:15 ` Conor Dooley 2024-02-18 15:00 ` Samuel Holland 0 siblings, 1 reply; 15+ messages in thread From: Conor Dooley @ 2024-02-13 23:15 UTC (permalink / raw) To: Stefan O'Rear Cc: Samuel Holland, Palmer Dabbelt, Andrew Jones, linux-riscv, linux-kernel, stable [-- Attachment #1: Type: text/plain, Size: 13086 bytes --] On Tue, Feb 13, 2024 at 03:43:27PM -0500, Stefan O'Rear wrote: > On Tue, Feb 13, 2024, at 3:22 PM, Samuel Holland wrote: > > On 2024-02-13 12:07 PM, Conor Dooley wrote: > >> On Mon, Feb 12, 2024 at 07:37:34PM -0800, Samuel Holland wrote: > >>> Previously, all extension version numbers were ignored. However, the > >>> version number is important for these two extensions. The simplest way > >>> to implement this is to use a separate bitmap bit for each supported > >>> version, with each successive version implying all of the previous ones. > >>> This allows alternatives and riscv_has_extension_[un]likely() to work > >>> naturally. > >>> > >>> To avoid duplicate extensions in /proc/cpuinfo, the new successor_id > >>> field allows hiding all but the newest implemented version of an > >>> extension. > >>> > >>> Cc: <stable@vger.kernel.org> # v6.7+ > >>> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> > >>> --- > >>> > >>> Changes in v2: > >>> - New patch for v2 > >>> > >>> arch/riscv/include/asm/cpufeature.h | 1 + > >>> arch/riscv/include/asm/hwcap.h | 8 ++++++ > >>> arch/riscv/kernel/cpu.c | 5 ++++ > >>> arch/riscv/kernel/cpufeature.c | 42 +++++++++++++++++++++++++---- > >>> 4 files changed, 51 insertions(+), 5 deletions(-) > >>> > >>> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h > >>> index 0bd11862b760..ac71384e7bc4 100644 > >>> --- a/arch/riscv/include/asm/cpufeature.h > >>> +++ b/arch/riscv/include/asm/cpufeature.h > >>> @@ -61,6 +61,7 @@ struct riscv_isa_ext_data { > >>> const char *property; > >>> const unsigned int *subset_ext_ids; > >>> const unsigned int subset_ext_size; > >>> + const unsigned int successor_id; > >>> }; > >>> > >>> extern const struct riscv_isa_ext_data riscv_isa_ext[]; > >>> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > >>> index 5340f818746b..5b51aa1db15b 100644 > >>> --- a/arch/riscv/include/asm/hwcap.h > >>> +++ b/arch/riscv/include/asm/hwcap.h > >>> @@ -80,13 +80,21 @@ > >>> #define RISCV_ISA_EXT_ZFA 71 > >>> #define RISCV_ISA_EXT_ZTSO 72 > >>> #define RISCV_ISA_EXT_ZACAS 73 > >>> +#define RISCV_ISA_EXT_SM1p11 74 > >>> +#define RISCV_ISA_EXT_SM1p12 75 > >>> +#define RISCV_ISA_EXT_SS1p11 76 > >>> +#define RISCV_ISA_EXT_SS1p12 77 > >>> > >>> #define RISCV_ISA_EXT_MAX 128 > >>> #define RISCV_ISA_EXT_INVALID U32_MAX > >>> > >>> #ifdef CONFIG_RISCV_M_MODE > >>> +#define RISCV_ISA_EXT_Sx1p11 RISCV_ISA_EXT_SM1p11 > >>> +#define RISCV_ISA_EXT_Sx1p12 RISCV_ISA_EXT_SM1p12 > >>> #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA > >>> #else > >>> +#define RISCV_ISA_EXT_Sx1p11 RISCV_ISA_EXT_SS1p11 > >>> +#define RISCV_ISA_EXT_Sx1p12 RISCV_ISA_EXT_SS1p12 > >>> #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA > >>> #endif > >>> > >>> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > >>> index d11d6320fb0d..2e6b90ed0d51 100644 > >>> --- a/arch/riscv/kernel/cpu.c > >>> +++ b/arch/riscv/kernel/cpu.c > >>> @@ -215,6 +215,11 @@ static void print_isa(struct seq_file *f, const unsigned long *isa_bitmap) > >>> if (!__riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].id)) > >>> continue; > >>> > >>> + /* Only show the newest implemented version of an extension */ > >>> + if (riscv_isa_ext[i].successor_id != RISCV_ISA_EXT_INVALID && > >>> + __riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].successor_id)) > >>> + continue; > >>> + > >>> /* Only multi-letter extensions are split by underscores */ > >>> if (strnlen(riscv_isa_ext[i].name, 2) != 1) > >>> seq_puts(f, "_"); > >>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > >>> index c5b13f7dd482..8e10b50120e9 100644 > >>> --- a/arch/riscv/kernel/cpufeature.c > >>> +++ b/arch/riscv/kernel/cpufeature.c > >>> @@ -113,23 +113,29 @@ static bool riscv_isa_extension_check(int id) > >>> return true; > >>> } > >>> > >>> -#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size) { \ > >>> +#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size, _successor) { \ > >>> .name = #_name, \ > >>> .property = #_name, \ > >>> .id = _id, \ > >>> .subset_ext_ids = _subset_exts, \ > >>> - .subset_ext_size = _subset_exts_size \ > >>> + .subset_ext_size = _subset_exts_size, \ > >>> + .successor_id = _successor, \ > >>> } > >>> > >>> -#define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0) > >>> +#define __RISCV_ISA_EXT_DATA(_name, _id) \ > >>> + _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, RISCV_ISA_EXT_INVALID) > >>> > >>> /* Used to declare pure "lasso" extension (Zk for instance) */ > >>> #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ > >>> - _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, ARRAY_SIZE(_bundled_exts)) > >>> + _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, \ > >>> + _bundled_exts, ARRAY_SIZE(_bundled_exts), RISCV_ISA_EXT_INVALID) > >>> > >>> /* Used to declare extensions that are a superset of other extensions (Zvbb for instance) */ > >>> #define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \ > >>> - _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts)) > >>> + _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), RISCV_ISA_EXT_INVALID) > >>> + > >>> +#define __RISCV_ISA_EXT_VERSION(_name, _id, _preds, _preds_size, _successor) \ > >>> + _RISCV_ISA_EXT_DATA(_name, _id, _preds, _preds_size, _successor) > >>> > >>> static const unsigned int riscv_zk_bundled_exts[] = { > >>> RISCV_ISA_EXT_ZBKB, > >>> @@ -201,6 +207,16 @@ static const unsigned int riscv_zvbb_exts[] = { > >>> RISCV_ISA_EXT_ZVKB > >>> }; > >>> > >>> +static const unsigned int riscv_sm_ext_versions[] = { > >>> + RISCV_ISA_EXT_SM1p11, > >>> + RISCV_ISA_EXT_SM1p12, > >>> +}; > >>> + > >>> +static const unsigned int riscv_ss_ext_versions[] = { > >>> + RISCV_ISA_EXT_SS1p11, > >>> + RISCV_ISA_EXT_SS1p12, > >>> +}; > >>> + > >>> /* > >>> * The canonical order of ISA extension names in the ISA string is defined in > >>> * chapter 27 of the unprivileged specification. > >>> @@ -299,8 +315,16 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > >>> __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH), > >>> __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), > >>> __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), > >>> + __RISCV_ISA_EXT_VERSION(sm1p11, RISCV_ISA_EXT_SM1p11, riscv_sm_ext_versions, 0, > >>> + RISCV_ISA_EXT_SM1p12), > >>> + __RISCV_ISA_EXT_VERSION(sm1p12, RISCV_ISA_EXT_SM1p12, riscv_sm_ext_versions, 1, > >>> + RISCV_ISA_EXT_INVALID), > >>> __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), > >>> __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), > >>> + __RISCV_ISA_EXT_VERSION(ss1p11, RISCV_ISA_EXT_SS1p11, riscv_ss_ext_versions, 0, > >>> + RISCV_ISA_EXT_SS1p12), > >>> + __RISCV_ISA_EXT_VERSION(ss1p12, RISCV_ISA_EXT_SS1p12, riscv_ss_ext_versions, 1, > >>> + RISCV_ISA_EXT_INVALID), > >>> __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), > >>> __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > >>> __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), > >>> @@ -414,6 +438,14 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc > >>> ; > >>> > >>> ++ext_end; > >>> + > >>> + /* > >>> + * As a special case for the Sm and Ss extensions, where the version > >>> + * number is important, include it in the extension name. > >>> + */ > >>> + if (ext_end - ext == 2 && tolower(ext[0]) == 's' && > >>> + (tolower(ext[1]) == 'm' || tolower(ext[1]) == 's')) > >>> + ext_end = isa; > >>> break; > >>> default: > >>> /* > >> > >> > >> Hmm, looking at all of this (especially this hack to the "old" parser), > >> I feel more like these should be promoted to a property of their own. > >> The "old" parser was designed to handle numbers, and here when you're > >> interested in the values behind the numbers (which is a first iirc), you > >> don't make any use of that. I don't really want to see a world where > > > > I had a version of this code that parsed the numbers and stored them as integers > > in `struct riscv_isainfo`. It didn't work with of_property_match_string() as > > used for riscv,isa-extensions, since that function expects the extension name to > > be the full string. I don't think I actually want what I am about to say, but it's not as if we are forced to parse it in that way for all properties. It's handy AF to be able to reuse reuse that function, and that was part of my goal originally with the property, but we are not locked into using of_property_match_string() if there's some specific property where that's getting in our way. That's kinda an aside though.. > > Either we would need to change the code to parse a version > > number out of each string in the riscv,isa-extensions list (and make the binding > > a bunch of regexes), or we need a separate "extension" entry (and DT binding > > entry) for each supported version. > > Version numbers aren't real, there's no compatibility promise that we can > consistently rely on so we treat riscv,isa-extensions as simply containing > alphanumeric extensions. This was an intentional part of simplifying riscv,isa > into riscv,isa-extensions. You seem to recall my motivations better than I do! > > I chose the second option, and as a consequence I didn't actually need to parse > > the integer value in the ISA string code path either. > > > >> we have every single iteration of smNpM under the sun in the property, > >> because there's a fair bit of churn in the isa. Granted, this applies to > >> all the various, the difference for me is the level of churn. > > > > Indeed. In fact, one thought I had while looking at this code is that we should > > be ignoring any extension in the ISA string with a version < 1.0 or >= 2.0, > > since those won't be compatible with what we expect. > > I might go further and say that we should only accept specific exact versions of > extensions other than Ss/Sm. This is what we do, right? Every property is supposed to match to exactly the frozen or ratified spec, so they do have exactly one version at present. The property descriptions should contain that information. > This could be revisited after the recent "semver > for ISA extensions" policy is tested at least once under real-world conditions. > > Right now we have two ratified versions of Ss/Sm, soon to be three, and one > ratified version of all other extensions. I hardly think this is an excessive > amount of churn. Yeah, maybe it's fine. I'm just overthinking it and there isn't a problem. > >> Or maybe we can still with the properties you have, but instead of > >> treating them like any other extension, handle these separately, > >> focusing on the numbering, so that only having the exact version > >> supported by a cpu is possible. > > > > Maybe I'm misunderstanding what you're saying here, but it is already the case > > that the DT for a CPU would only contain the exact version of the privileged ISA > > supported by that CPU. > > If privileged spec versions are boolean extensions, then you would say "ss1p11", > "ss1p12", "ss1p13" as separate/simultaneous extensions. > This is needed in order > to allow simple support checks as described in the riscv,isa-extensions cover > letter. Yes, it is explicitly a goal of riscv,isa-extensions that you can look for a specific extension in the list if that is all you care about. If you go and drop ss1p11 because you support ss1p12 it defeats that. I don't know off the top of my head how to enforce ss1p12 requiring ss1p11 in json schema, but I do have an idea of where to start... > > With this implementation, the fact that the integer version gets expanded to a > > series of flags is supposed to be invisible in the DT and to userspace. I > > realize I don't quite succeed there: putting "ss1p13" in the ISA string should > > work, but does not. > > > >> I'm still pretty undecided, I'd like to think about this a little bit, > >> but I think we can do better here. > > > > Sure, no problem. I'm happy to implement whatever we agree on. Though one > > consideration I had is that this is all in support of fixing a bug in v6.7, so I > > wanted the changes to be backportable. > > > > I suppose the easy way out for backporting is to check for RISCV_ISA_EXT_ZICBOZ > > for now, and then solve the larger problem once there is some other user of the > > envcfg CSR (or another Ss1p12 feature). > > I support that course of action. I saw another mail suggesting that Zicbom implied Ss1p12, I think that should be reasonable position to take for now. Cheers, Conor. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH -fixes v2 3/4] riscv: Add ISA extension parsing for Sm and Ss 2024-02-13 23:15 ` Conor Dooley @ 2024-02-18 15:00 ` Samuel Holland 2024-02-18 17:02 ` Conor Dooley 0 siblings, 1 reply; 15+ messages in thread From: Samuel Holland @ 2024-02-18 15:00 UTC (permalink / raw) To: Conor Dooley, Stefan O'Rear Cc: Palmer Dabbelt, Andrew Jones, linux-riscv, linux-kernel, stable Hi Conor, Stefan, Thanks for the discussion! On 2024-02-13 5:15 PM, Conor Dooley wrote: > On Tue, Feb 13, 2024 at 03:43:27PM -0500, Stefan O'Rear wrote: >> On Tue, Feb 13, 2024, at 3:22 PM, Samuel Holland wrote: >>> On 2024-02-13 12:07 PM, Conor Dooley wrote: >>>> On Mon, Feb 12, 2024 at 07:37:34PM -0800, Samuel Holland wrote: >>>>> Previously, all extension version numbers were ignored. However, the >>>>> version number is important for these two extensions. The simplest way >>>>> to implement this is to use a separate bitmap bit for each supported >>>>> version, with each successive version implying all of the previous ones. >>>>> This allows alternatives and riscv_has_extension_[un]likely() to work >>>>> naturally. >>>>> >>>>> To avoid duplicate extensions in /proc/cpuinfo, the new successor_id >>>>> field allows hiding all but the newest implemented version of an >>>>> extension. >>>>> >>>>> Cc: <stable@vger.kernel.org> # v6.7+ >>>>> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> >>>>> --- >>>>> >>>>> Changes in v2: >>>>> - New patch for v2 >>>>> >>>>> arch/riscv/include/asm/cpufeature.h | 1 + >>>>> arch/riscv/include/asm/hwcap.h | 8 ++++++ >>>>> arch/riscv/kernel/cpu.c | 5 ++++ >>>>> arch/riscv/kernel/cpufeature.c | 42 +++++++++++++++++++++++++---- >>>>> 4 files changed, 51 insertions(+), 5 deletions(-) >>>>> >>>>> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h >>>>> index 0bd11862b760..ac71384e7bc4 100644 >>>>> --- a/arch/riscv/include/asm/cpufeature.h >>>>> +++ b/arch/riscv/include/asm/cpufeature.h >>>>> @@ -61,6 +61,7 @@ struct riscv_isa_ext_data { >>>>> const char *property; >>>>> const unsigned int *subset_ext_ids; >>>>> const unsigned int subset_ext_size; >>>>> + const unsigned int successor_id; >>>>> }; >>>>> >>>>> extern const struct riscv_isa_ext_data riscv_isa_ext[]; >>>>> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h >>>>> index 5340f818746b..5b51aa1db15b 100644 >>>>> --- a/arch/riscv/include/asm/hwcap.h >>>>> +++ b/arch/riscv/include/asm/hwcap.h >>>>> @@ -80,13 +80,21 @@ >>>>> #define RISCV_ISA_EXT_ZFA 71 >>>>> #define RISCV_ISA_EXT_ZTSO 72 >>>>> #define RISCV_ISA_EXT_ZACAS 73 >>>>> +#define RISCV_ISA_EXT_SM1p11 74 >>>>> +#define RISCV_ISA_EXT_SM1p12 75 >>>>> +#define RISCV_ISA_EXT_SS1p11 76 >>>>> +#define RISCV_ISA_EXT_SS1p12 77 >>>>> >>>>> #define RISCV_ISA_EXT_MAX 128 >>>>> #define RISCV_ISA_EXT_INVALID U32_MAX >>>>> >>>>> #ifdef CONFIG_RISCV_M_MODE >>>>> +#define RISCV_ISA_EXT_Sx1p11 RISCV_ISA_EXT_SM1p11 >>>>> +#define RISCV_ISA_EXT_Sx1p12 RISCV_ISA_EXT_SM1p12 >>>>> #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA >>>>> #else >>>>> +#define RISCV_ISA_EXT_Sx1p11 RISCV_ISA_EXT_SS1p11 >>>>> +#define RISCV_ISA_EXT_Sx1p12 RISCV_ISA_EXT_SS1p12 >>>>> #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA >>>>> #endif >>>>> >>>>> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c >>>>> index d11d6320fb0d..2e6b90ed0d51 100644 >>>>> --- a/arch/riscv/kernel/cpu.c >>>>> +++ b/arch/riscv/kernel/cpu.c >>>>> @@ -215,6 +215,11 @@ static void print_isa(struct seq_file *f, const unsigned long *isa_bitmap) >>>>> if (!__riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].id)) >>>>> continue; >>>>> >>>>> + /* Only show the newest implemented version of an extension */ >>>>> + if (riscv_isa_ext[i].successor_id != RISCV_ISA_EXT_INVALID && >>>>> + __riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].successor_id)) >>>>> + continue; >>>>> + >>>>> /* Only multi-letter extensions are split by underscores */ >>>>> if (strnlen(riscv_isa_ext[i].name, 2) != 1) >>>>> seq_puts(f, "_"); >>>>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c >>>>> index c5b13f7dd482..8e10b50120e9 100644 >>>>> --- a/arch/riscv/kernel/cpufeature.c >>>>> +++ b/arch/riscv/kernel/cpufeature.c >>>>> @@ -113,23 +113,29 @@ static bool riscv_isa_extension_check(int id) >>>>> return true; >>>>> } >>>>> >>>>> -#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size) { \ >>>>> +#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size, _successor) { \ >>>>> .name = #_name, \ >>>>> .property = #_name, \ >>>>> .id = _id, \ >>>>> .subset_ext_ids = _subset_exts, \ >>>>> - .subset_ext_size = _subset_exts_size \ >>>>> + .subset_ext_size = _subset_exts_size, \ >>>>> + .successor_id = _successor, \ >>>>> } >>>>> >>>>> -#define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0) >>>>> +#define __RISCV_ISA_EXT_DATA(_name, _id) \ >>>>> + _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, RISCV_ISA_EXT_INVALID) >>>>> >>>>> /* Used to declare pure "lasso" extension (Zk for instance) */ >>>>> #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ >>>>> - _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, ARRAY_SIZE(_bundled_exts)) >>>>> + _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, \ >>>>> + _bundled_exts, ARRAY_SIZE(_bundled_exts), RISCV_ISA_EXT_INVALID) >>>>> >>>>> /* Used to declare extensions that are a superset of other extensions (Zvbb for instance) */ >>>>> #define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \ >>>>> - _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts)) >>>>> + _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), RISCV_ISA_EXT_INVALID) >>>>> + >>>>> +#define __RISCV_ISA_EXT_VERSION(_name, _id, _preds, _preds_size, _successor) \ >>>>> + _RISCV_ISA_EXT_DATA(_name, _id, _preds, _preds_size, _successor) >>>>> >>>>> static const unsigned int riscv_zk_bundled_exts[] = { >>>>> RISCV_ISA_EXT_ZBKB, >>>>> @@ -201,6 +207,16 @@ static const unsigned int riscv_zvbb_exts[] = { >>>>> RISCV_ISA_EXT_ZVKB >>>>> }; >>>>> >>>>> +static const unsigned int riscv_sm_ext_versions[] = { >>>>> + RISCV_ISA_EXT_SM1p11, >>>>> + RISCV_ISA_EXT_SM1p12, >>>>> +}; >>>>> + >>>>> +static const unsigned int riscv_ss_ext_versions[] = { >>>>> + RISCV_ISA_EXT_SS1p11, >>>>> + RISCV_ISA_EXT_SS1p12, >>>>> +}; >>>>> + >>>>> /* >>>>> * The canonical order of ISA extension names in the ISA string is defined in >>>>> * chapter 27 of the unprivileged specification. >>>>> @@ -299,8 +315,16 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { >>>>> __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH), >>>>> __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), >>>>> __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), >>>>> + __RISCV_ISA_EXT_VERSION(sm1p11, RISCV_ISA_EXT_SM1p11, riscv_sm_ext_versions, 0, >>>>> + RISCV_ISA_EXT_SM1p12), >>>>> + __RISCV_ISA_EXT_VERSION(sm1p12, RISCV_ISA_EXT_SM1p12, riscv_sm_ext_versions, 1, >>>>> + RISCV_ISA_EXT_INVALID), >>>>> __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), >>>>> __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), >>>>> + __RISCV_ISA_EXT_VERSION(ss1p11, RISCV_ISA_EXT_SS1p11, riscv_ss_ext_versions, 0, >>>>> + RISCV_ISA_EXT_SS1p12), >>>>> + __RISCV_ISA_EXT_VERSION(ss1p12, RISCV_ISA_EXT_SS1p12, riscv_ss_ext_versions, 1, >>>>> + RISCV_ISA_EXT_INVALID), >>>>> __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), >>>>> __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), >>>>> __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), >>>>> @@ -414,6 +438,14 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc >>>>> ; >>>>> >>>>> ++ext_end; >>>>> + >>>>> + /* >>>>> + * As a special case for the Sm and Ss extensions, where the version >>>>> + * number is important, include it in the extension name. >>>>> + */ >>>>> + if (ext_end - ext == 2 && tolower(ext[0]) == 's' && >>>>> + (tolower(ext[1]) == 'm' || tolower(ext[1]) == 's')) >>>>> + ext_end = isa; >>>>> break; >>>>> default: >>>>> /* >>>> >>>> >>>> Hmm, looking at all of this (especially this hack to the "old" parser), >>>> I feel more like these should be promoted to a property of their own. >>>> The "old" parser was designed to handle numbers, and here when you're >>>> interested in the values behind the numbers (which is a first iirc), you >>>> don't make any use of that. I don't really want to see a world where >>> >>> I had a version of this code that parsed the numbers and stored them as integers >>> in `struct riscv_isainfo`. It didn't work with of_property_match_string() as >>> used for riscv,isa-extensions, since that function expects the extension name to >>> be the full string. > > I don't think I actually want what I am about to say, but it's not as if we > are forced to parse it in that way for all properties. It's handy AF to be > able to reuse reuse that function, and that was part of my goal originally > with the property, but we are not locked into using > of_property_match_string() if there's some specific property where that's > getting in our way. That's kinda an aside though.. > >>> Either we would need to change the code to parse a version >>> number out of each string in the riscv,isa-extensions list (and make the binding >>> a bunch of regexes), or we need a separate "extension" entry (and DT binding >>> entry) for each supported version. >> >> Version numbers aren't real, there's no compatibility promise that we can >> consistently rely on so we treat riscv,isa-extensions as simply containing >> alphanumeric extensions. This was an intentional part of simplifying riscv,isa >> into riscv,isa-extensions. > > You seem to recall my motivations better than I do! > >>> I chose the second option, and as a consequence I didn't actually need to parse >>> the integer value in the ISA string code path either. >>> >>>> we have every single iteration of smNpM under the sun in the property, >>>> because there's a fair bit of churn in the isa. Granted, this applies to >>>> all the various, the difference for me is the level of churn. >>> >>> Indeed. In fact, one thought I had while looking at this code is that we should >>> be ignoring any extension in the ISA string with a version < 1.0 or >= 2.0, >>> since those won't be compatible with what we expect. >> >> I might go further and say that we should only accept specific exact versions of >> extensions other than Ss/Sm. > > This is what we do, right? Every property is supposed to match to > exactly the frozen or ratified spec, so they do have exactly one version > at present. The property descriptions should contain that information. > >> This could be revisited after the recent "semver >> for ISA extensions" policy is tested at least once under real-world conditions. >> >> Right now we have two ratified versions of Ss/Sm, soon to be three, and one My understanding (from hwprobe.rst and various ML comments) is that Linux assumes Ss1p10. That's why I started counting with Ss1p11. It looks like Ss1p10 was never ratified, but that doesn't prevent us from referencing it in the binding, if needed. Should we start enumerating extensions at Ss1p11 or something else? >> ratified version of all other extensions. I hardly think this is an excessive >> amount of churn. > > Yeah, maybe it's fine. I'm just overthinking it and there isn't a > problem. My interpretation of this and the above comments is that we do actually want to enumerate every supported "version" of the privileged ISA in the binding, and parse them as entirely independent extensions that just happen to have similar-looking names. Is that correct? >>>> Or maybe we can still with the properties you have, but instead of >>>> treating them like any other extension, handle these separately, >>>> focusing on the numbering, so that only having the exact version >>>> supported by a cpu is possible. >>> >>> Maybe I'm misunderstanding what you're saying here, but it is already the case >>> that the DT for a CPU would only contain the exact version of the privileged ISA >>> supported by that CPU. >> >> If privileged spec versions are boolean extensions, then you would say "ss1p11", >> "ss1p12", "ss1p13" as separate/simultaneous extensions. > >> This is needed in order >> to allow simple support checks as described in the riscv,isa-extensions cover >> letter. > > Yes, it is explicitly a goal of riscv,isa-extensions that you can look > for a specific extension in the list if that is all you care about. If > you go and drop ss1p11 because you support ss1p12 it defeats that. Okay, that makes sense, but that is not how the parsing code works right now, which is probably what led me down the wrong path. :) To have the intended semantics, we cannot parse _anything_ in riscv,isa-extensions as a "bundled" or "superset" extension. Because to accomplish your goal, each extension in the bundle must be listed explicitly, in case the consumer only cares about that one extension. So it sounds like riscv_fill_hwcap_from_ext_list() needs to ignore subset_ext_size/subset_ext_ids. > I don't know off the top of my head how to enforce ss1p12 requiring ss1p11 > in json schema, but I do have an idea of where to start... Yeah, this is different from normal "dependencies:" because it is a string list. I think we need to add dependencies in the binding for the bundled extensions as well, and maybe even between extensions like "d" and "f". >>> With this implementation, the fact that the integer version gets expanded to a >>> series of flags is supposed to be invisible in the DT and to userspace. I >>> realize I don't quite succeed there: putting "ss1p13" in the ISA string should >>> work, but does not. >>> >>>> I'm still pretty undecided, I'd like to think about this a little bit, >>>> but I think we can do better here. >>> >>> Sure, no problem. I'm happy to implement whatever we agree on. Though one >>> consideration I had is that this is all in support of fixing a bug in v6.7, so I >>> wanted the changes to be backportable. >>> >>> I suppose the easy way out for backporting is to check for RISCV_ISA_EXT_ZICBOZ >>> for now, and then solve the larger problem once there is some other user of the >>> envcfg CSR (or another Ss1p12 feature). >> >> I support that course of action. > > I saw another mail suggesting that Zicbom implied Ss1p12, I think that > should be reasonable position to take for now. Like I mentioned in my other email, I don't think Zicboz is sufficient to imply Ss1p12. So I'd prefer to either stay with checking Zicboz (like v3 does); or add a bit for specifically the existence of the the envcfg CSR, that doesn't map to anything in the ISA string (i.e. is not listed in riscv_isa_ext). Of course, if we start ignoring subset_ext_ids, I'll have to reconsider how to actually implement that. Regards, Samuel ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH -fixes v2 3/4] riscv: Add ISA extension parsing for Sm and Ss 2024-02-18 15:00 ` Samuel Holland @ 2024-02-18 17:02 ` Conor Dooley 0 siblings, 0 replies; 15+ messages in thread From: Conor Dooley @ 2024-02-18 17:02 UTC (permalink / raw) To: Samuel Holland Cc: Stefan O'Rear, Palmer Dabbelt, Andrew Jones, linux-riscv, linux-kernel, stable [-- Attachment #1: Type: text/plain, Size: 3300 bytes --] On Sun, Feb 18, 2024 at 09:00:14AM -0600, Samuel Holland wrote: > >>>> Or maybe we can still with the properties you have, but instead of > >>>> treating them like any other extension, handle these separately, > >>>> focusing on the numbering, so that only having the exact version > >>>> supported by a cpu is possible. > >>> > >>> Maybe I'm misunderstanding what you're saying here, but it is already the case > >>> that the DT for a CPU would only contain the exact version of the privileged ISA > >>> supported by that CPU. > >> > >> If privileged spec versions are boolean extensions, then you would say "ss1p11", > >> "ss1p12", "ss1p13" as separate/simultaneous extensions. > > > >> This is needed in order > >> to allow simple support checks as described in the riscv,isa-extensions cover > >> letter. > > > > Yes, it is explicitly a goal of riscv,isa-extensions that you can look > > for a specific extension in the list if that is all you care about. If > > you go and drop ss1p11 because you support ss1p12 it defeats that. > > Okay, that makes sense, but that is not how the parsing code works right now, > which is probably what led me down the wrong path. :) > > To have the intended semantics, we cannot parse _anything_ in > riscv,isa-extensions as a "bundled" or "superset" extension. That's not true I don't think. You can parse as a "bundle" but... > Because to > accomplish your goal, each extension in the bundle must be listed explicitly, in > case the consumer only cares about that one extension. ...as you note here, the extensions also have to be listed explicitly so that they can be detected in isolation if that is all that a consumer does. > So it sounds like > riscv_fill_hwcap_from_ext_list() needs to ignore subset_ext_size/subset_ext_ids. Do you mean this: if (ext->subset_ext_size) { for (int j = 0; j < ext->subset_ext_size; j++) { if (riscv_isa_extension_check(ext->subset_ext_ids[i])) set_bit(ext->subset_ext_ids[j], isainfo->isa); } } I think that is fine? If you find the "superset" you can enable the individual elements. The problem would just be if someone put only the superset in a DT (or ACPI tables) and the software looked for the individual element only, but IIRC the kernel currently checks both the superset and individual elements. It would be possible to check a bundle and then skip looking for the individual elements if the bundle was already found if the parsing is wont to be sped up. I think all we need to do is enforce that all individual elements are present on a schema validation level (I have no clue what we can do for ACPI) and no change is required in the kernel. Am I misunderstanding what you think is the problem here? > > I don't know off the top of my head how to enforce ss1p12 requiring ss1p11 > > in json schema, but I do have an idea of where to start... > > Yeah, this is different from normal "dependencies:" because it is a string list. I think it is actually doable, just will look sorta clunky. I meant to go and do it this weekend, but I've been rather sick unfortunately. Something similar is definitely doable for compatibles, so either it'll "just work" or I may have to extend the validation tooling. Cheers, Conor. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH -fixes v2 4/4] riscv: Save/restore envcfg CSR during CPU suspend [not found] <20240213033744.4069020-1-samuel.holland@sifive.com> 2024-02-13 3:37 ` [PATCH -fixes v2 1/4] riscv: Fix enabling cbo.zero when running in M-mode Samuel Holland 2024-02-13 3:37 ` [PATCH -fixes v2 3/4] riscv: Add ISA extension parsing for Sm and Ss Samuel Holland @ 2024-02-13 3:37 ` Samuel Holland 2024-02-13 14:49 ` Andrew Jones 2 siblings, 1 reply; 15+ messages in thread From: Samuel Holland @ 2024-02-13 3:37 UTC (permalink / raw) To: Palmer Dabbelt Cc: Andrew Jones, linux-riscv, linux-kernel, Stefan O'Rear, Samuel Holland, stable The value of the [ms]envcfg CSR is lost when entering a nonretentive idle state, so the CSR must be rewritten when resuming the CPU. Cc: <stable@vger.kernel.org> # v6.7+ Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode") Signed-off-by: Samuel Holland <samuel.holland@sifive.com> --- Changes in v2: - Check for privileged ISA v1.12 instead of the specific CSR - Use riscv_has_extension_likely() instead of new ALTERNATIVE()s arch/riscv/include/asm/suspend.h | 1 + arch/riscv/kernel/suspend.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h index 02f87867389a..491296a335d0 100644 --- a/arch/riscv/include/asm/suspend.h +++ b/arch/riscv/include/asm/suspend.h @@ -14,6 +14,7 @@ struct suspend_context { struct pt_regs regs; /* Saved and restored by high-level functions */ unsigned long scratch; + unsigned long envcfg; unsigned long tvec; unsigned long ie; #ifdef CONFIG_MMU diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c index 239509367e42..be03615486ed 100644 --- a/arch/riscv/kernel/suspend.c +++ b/arch/riscv/kernel/suspend.c @@ -15,6 +15,8 @@ void suspend_save_csrs(struct suspend_context *context) { context->scratch = csr_read(CSR_SCRATCH); + if (riscv_has_extension_likely(RISCV_ISA_EXT_Sx1p12)) + context->envcfg = csr_read(CSR_ENVCFG); context->tvec = csr_read(CSR_TVEC); context->ie = csr_read(CSR_IE); @@ -36,6 +38,8 @@ void suspend_save_csrs(struct suspend_context *context) void suspend_restore_csrs(struct suspend_context *context) { csr_write(CSR_SCRATCH, context->scratch); + if (riscv_has_extension_likely(RISCV_ISA_EXT_Sx1p12)) + csr_write(CSR_ENVCFG, context->envcfg); csr_write(CSR_TVEC, context->tvec); csr_write(CSR_IE, context->ie); -- 2.43.0 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH -fixes v2 4/4] riscv: Save/restore envcfg CSR during CPU suspend 2024-02-13 3:37 ` [PATCH -fixes v2 4/4] riscv: Save/restore envcfg CSR during CPU suspend Samuel Holland @ 2024-02-13 14:49 ` Andrew Jones 2024-02-13 17:53 ` Stefan O'Rear 0 siblings, 1 reply; 15+ messages in thread From: Andrew Jones @ 2024-02-13 14:49 UTC (permalink / raw) To: Samuel Holland Cc: Palmer Dabbelt, linux-riscv, linux-kernel, Stefan O'Rear, stable On Mon, Feb 12, 2024 at 07:37:35PM -0800, Samuel Holland wrote: > The value of the [ms]envcfg CSR is lost when entering a nonretentive > idle state, so the CSR must be rewritten when resuming the CPU. > > Cc: <stable@vger.kernel.org> # v6.7+ > Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode") > Signed-off-by: Samuel Holland <samuel.holland@sifive.com> > --- > > Changes in v2: > - Check for privileged ISA v1.12 instead of the specific CSR > - Use riscv_has_extension_likely() instead of new ALTERNATIVE()s > > arch/riscv/include/asm/suspend.h | 1 + > arch/riscv/kernel/suspend.c | 4 ++++ > 2 files changed, 5 insertions(+) > > diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h > index 02f87867389a..491296a335d0 100644 > --- a/arch/riscv/include/asm/suspend.h > +++ b/arch/riscv/include/asm/suspend.h > @@ -14,6 +14,7 @@ struct suspend_context { > struct pt_regs regs; > /* Saved and restored by high-level functions */ > unsigned long scratch; > + unsigned long envcfg; > unsigned long tvec; > unsigned long ie; > #ifdef CONFIG_MMU > diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c > index 239509367e42..be03615486ed 100644 > --- a/arch/riscv/kernel/suspend.c > +++ b/arch/riscv/kernel/suspend.c > @@ -15,6 +15,8 @@ > void suspend_save_csrs(struct suspend_context *context) > { > context->scratch = csr_read(CSR_SCRATCH); > + if (riscv_has_extension_likely(RISCV_ISA_EXT_Sx1p12)) > + context->envcfg = csr_read(CSR_ENVCFG); > context->tvec = csr_read(CSR_TVEC); > context->ie = csr_read(CSR_IE); > > @@ -36,6 +38,8 @@ void suspend_save_csrs(struct suspend_context *context) > void suspend_restore_csrs(struct suspend_context *context) > { > csr_write(CSR_SCRATCH, context->scratch); > + if (riscv_has_extension_likely(RISCV_ISA_EXT_Sx1p12)) > + csr_write(CSR_ENVCFG, context->envcfg); > csr_write(CSR_TVEC, context->tvec); > csr_write(CSR_IE, context->ie); > > -- > 2.43.0 > We're still exposing Zicboz to userspace in hwprobe when only RISCV_ISA_EXT_ZICBOZ is present, which will be the case for anything that either doesn't implement 1.12, but does implement Zicboz, or maybe does implement 1.12, but hasn't started putting Ss1p12 in its ISA string yet (e.g. QEMU). We should either stop exposing Zicboz to userspace in those cases (since it won't work) or rethink how we want to determine whether or not we have envcfg CSRs. Thanks, drew ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH -fixes v2 4/4] riscv: Save/restore envcfg CSR during CPU suspend 2024-02-13 14:49 ` Andrew Jones @ 2024-02-13 17:53 ` Stefan O'Rear 2024-02-18 14:09 ` Samuel Holland 0 siblings, 1 reply; 15+ messages in thread From: Stefan O'Rear @ 2024-02-13 17:53 UTC (permalink / raw) To: Andrew Jones, Samuel Holland Cc: Palmer Dabbelt, linux-riscv, linux-kernel, stable On Tue, Feb 13, 2024, at 9:49 AM, Andrew Jones wrote: > On Mon, Feb 12, 2024 at 07:37:35PM -0800, Samuel Holland wrote: >> The value of the [ms]envcfg CSR is lost when entering a nonretentive >> idle state, so the CSR must be rewritten when resuming the CPU. >> >> Cc: <stable@vger.kernel.org> # v6.7+ >> Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode") >> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> >> --- >> >> Changes in v2: >> - Check for privileged ISA v1.12 instead of the specific CSR >> - Use riscv_has_extension_likely() instead of new ALTERNATIVE()s >> >> arch/riscv/include/asm/suspend.h | 1 + >> arch/riscv/kernel/suspend.c | 4 ++++ >> 2 files changed, 5 insertions(+) >> >> diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h >> index 02f87867389a..491296a335d0 100644 >> --- a/arch/riscv/include/asm/suspend.h >> +++ b/arch/riscv/include/asm/suspend.h >> @@ -14,6 +14,7 @@ struct suspend_context { >> struct pt_regs regs; >> /* Saved and restored by high-level functions */ >> unsigned long scratch; >> + unsigned long envcfg; >> unsigned long tvec; >> unsigned long ie; >> #ifdef CONFIG_MMU >> diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c >> index 239509367e42..be03615486ed 100644 >> --- a/arch/riscv/kernel/suspend.c >> +++ b/arch/riscv/kernel/suspend.c >> @@ -15,6 +15,8 @@ >> void suspend_save_csrs(struct suspend_context *context) >> { >> context->scratch = csr_read(CSR_SCRATCH); >> + if (riscv_has_extension_likely(RISCV_ISA_EXT_Sx1p12)) >> + context->envcfg = csr_read(CSR_ENVCFG); >> context->tvec = csr_read(CSR_TVEC); >> context->ie = csr_read(CSR_IE); >> >> @@ -36,6 +38,8 @@ void suspend_save_csrs(struct suspend_context *context) >> void suspend_restore_csrs(struct suspend_context *context) >> { >> csr_write(CSR_SCRATCH, context->scratch); >> + if (riscv_has_extension_likely(RISCV_ISA_EXT_Sx1p12)) >> + csr_write(CSR_ENVCFG, context->envcfg); >> csr_write(CSR_TVEC, context->tvec); >> csr_write(CSR_IE, context->ie); >> >> -- >> 2.43.0 >> > > We're still exposing Zicboz to userspace in hwprobe when only > RISCV_ISA_EXT_ZICBOZ is present, which will be the case for anything that > either doesn't implement 1.12, but does implement Zicboz, or maybe does > implement 1.12, but hasn't started putting Ss1p12 in its ISA string yet > (e.g. QEMU). We should either stop exposing Zicboz to userspace in those > cases (since it won't work) or rethink how we want to determine whether > or not we have envcfg CSRs. opensbi treats the existence of menvcfg as sufficient evidence to prove that the hart supports 1.12. I wouldn't object to having Zicboz imply Ss1p12/Sm1p12. -s > Thanks, > drew > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH -fixes v2 4/4] riscv: Save/restore envcfg CSR during CPU suspend 2024-02-13 17:53 ` Stefan O'Rear @ 2024-02-18 14:09 ` Samuel Holland 0 siblings, 0 replies; 15+ messages in thread From: Samuel Holland @ 2024-02-18 14:09 UTC (permalink / raw) To: Stefan O'Rear Cc: Palmer Dabbelt, linux-riscv, linux-kernel, stable, Andrew Jones On 2024-02-13 11:53 AM, Stefan O'Rear wrote: > On Tue, Feb 13, 2024, at 9:49 AM, Andrew Jones wrote: >> On Mon, Feb 12, 2024 at 07:37:35PM -0800, Samuel Holland wrote: >>> The value of the [ms]envcfg CSR is lost when entering a nonretentive >>> idle state, so the CSR must be rewritten when resuming the CPU. >>> >>> Cc: <stable@vger.kernel.org> # v6.7+ >>> Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode") >>> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> >>> --- >>> >>> Changes in v2: >>> - Check for privileged ISA v1.12 instead of the specific CSR >>> - Use riscv_has_extension_likely() instead of new ALTERNATIVE()s >>> >>> arch/riscv/include/asm/suspend.h | 1 + >>> arch/riscv/kernel/suspend.c | 4 ++++ >>> 2 files changed, 5 insertions(+) >>> >>> diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h >>> index 02f87867389a..491296a335d0 100644 >>> --- a/arch/riscv/include/asm/suspend.h >>> +++ b/arch/riscv/include/asm/suspend.h >>> @@ -14,6 +14,7 @@ struct suspend_context { >>> struct pt_regs regs; >>> /* Saved and restored by high-level functions */ >>> unsigned long scratch; >>> + unsigned long envcfg; >>> unsigned long tvec; >>> unsigned long ie; >>> #ifdef CONFIG_MMU >>> diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c >>> index 239509367e42..be03615486ed 100644 >>> --- a/arch/riscv/kernel/suspend.c >>> +++ b/arch/riscv/kernel/suspend.c >>> @@ -15,6 +15,8 @@ >>> void suspend_save_csrs(struct suspend_context *context) >>> { >>> context->scratch = csr_read(CSR_SCRATCH); >>> + if (riscv_has_extension_likely(RISCV_ISA_EXT_Sx1p12)) >>> + context->envcfg = csr_read(CSR_ENVCFG); >>> context->tvec = csr_read(CSR_TVEC); >>> context->ie = csr_read(CSR_IE); >>> >>> @@ -36,6 +38,8 @@ void suspend_save_csrs(struct suspend_context *context) >>> void suspend_restore_csrs(struct suspend_context *context) >>> { >>> csr_write(CSR_SCRATCH, context->scratch); >>> + if (riscv_has_extension_likely(RISCV_ISA_EXT_Sx1p12)) >>> + csr_write(CSR_ENVCFG, context->envcfg); >>> csr_write(CSR_TVEC, context->tvec); >>> csr_write(CSR_IE, context->ie); >>> >>> -- >>> 2.43.0 >>> >> >> We're still exposing Zicboz to userspace in hwprobe when only >> RISCV_ISA_EXT_ZICBOZ is present, which will be the case for anything that >> either doesn't implement 1.12, but does implement Zicboz, or maybe does >> implement 1.12, but hasn't started putting Ss1p12 in its ISA string yet >> (e.g. QEMU). We should either stop exposing Zicboz to userspace in those >> cases (since it won't work) or rethink how we want to determine whether >> or not we have envcfg CSRs. > > opensbi treats the existence of menvcfg as sufficient evidence to prove that > the hart supports 1.12. I wouldn't object to having Zicboz imply Ss1p12/Sm1p12. Zicboz implies menvcfg, yes, but I don't think menvcfg is sufficient to imply S[ms]1p12. It's entirely possible for hardware to implement menvcfg but none of the other S[ms]1p12 features. Or it may attempt to implement S[ms]1p12, but have some bug that prevents it from being compliant, and therefore prevents declaring support in the devicetree/ISA string. What I think might work best is to have a cpufeature flag for "has the envcfg CSR" that doesn't map to anything in the devicetree/ISA string. Then Zicboz can imply envcfg, and Ss1p12 can imply envcfg, but we avoid any possible false implications going the other direction. Regards, Samuel ^ permalink raw reply [flat|nested] 15+ messages in thread
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[not found] <20240213033744.4069020-1-samuel.holland@sifive.com>
2024-02-13 3:37 ` [PATCH -fixes v2 1/4] riscv: Fix enabling cbo.zero when running in M-mode Samuel Holland
2024-02-13 3:37 ` [PATCH -fixes v2 3/4] riscv: Add ISA extension parsing for Sm and Ss Samuel Holland
2024-02-13 15:14 ` Andrew Jones
2024-02-13 17:52 ` Stefan O'Rear
2024-02-13 18:18 ` Samuel Holland
2024-02-13 18:07 ` Conor Dooley
2024-02-13 20:22 ` Samuel Holland
2024-02-13 20:43 ` Stefan O'Rear
2024-02-13 23:15 ` Conor Dooley
2024-02-18 15:00 ` Samuel Holland
2024-02-18 17:02 ` Conor Dooley
2024-02-13 3:37 ` [PATCH -fixes v2 4/4] riscv: Save/restore envcfg CSR during CPU suspend Samuel Holland
2024-02-13 14:49 ` Andrew Jones
2024-02-13 17:53 ` Stefan O'Rear
2024-02-18 14:09 ` Samuel Holland
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