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From: Sasha Levin <sashal@kernel.org>
To: stable@vger.kernel.org
Cc: jianqi.ren.cn@windriver.com, Sasha Levin <sashal@kernel.org>
Subject: Re: [PATCH 6.1.y] spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer
Date: Mon, 12 May 2025 17:52:40 -0400	[thread overview]
Message-ID: <20250512163207-282f1e7f1aec7163@stable.kernel.org> (raw)
In-Reply-To: <20250512015227.3326695-1-jianqi.ren.cn@windriver.com>

[ Sasha's backport helper bot ]

Hi,

✅ All tests passed successfully. No issues detected.
No action required from the submitter.

The upstream commit SHA1 provided is correct: 9cf71eb0faef4bff01df4264841b8465382d7927

WARNING: Author mismatch between patch and upstream commit:
Backport author: <jianqi.ren.cn@windriver.com>
Commit author: Steve Wilkins<steve.wilkins@raymarine.com>

Status in newer kernel trees:
6.14.y | Present (exact SHA1)
6.12.y | Present (exact SHA1)
6.6.y | Present (different SHA1: 3feda3677e8b)

Note: The patch differs from the upstream commit:
---
1:  9cf71eb0faef4 ! 1:  e2b7a4dc57e1d spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer
    @@ Metadata
      ## Commit message ##
         spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer
     
    +    [ Upstream commit 9cf71eb0faef4bff01df4264841b8465382d7927 ]
    +
         While transmitting with rx_len == 0, the RX FIFO is not going to be
         emptied in the interrupt handler. A subsequent transfer could then
         read crap from the previous transfer out of the RX FIFO into the
    @@ Commit message
         Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
         Link: https://patch.msgid.link/20240715-flammable-provoke-459226d08e70@wendy
         Signed-off-by: Mark Brown <broonie@kernel.org>
    +    [Minor conflict resolved due to code context change.]
    +    Signed-off-by: Jianqi Ren <jianqi.ren.cn@windriver.com>
    +    Signed-off-by: He Zhe <zhe.he@windriver.com>
     
      ## drivers/spi/spi-microchip-core.c ##
     @@
    @@ drivers/spi/spi-microchip-core.c: static int mchp_corespi_transfer_one(struct sp
      
     +	mchp_corespi_write(spi, REG_COMMAND, COMMAND_RXFIFORST | COMMAND_TXFIFORST);
     +
    - 	mchp_corespi_write(spi, REG_SLAVE_SELECT, spi->pending_slave_select);
    - 
      	while (spi->tx_len)
    + 		mchp_corespi_write_fifo(spi);
    + 
---

Results of testing on various branches:

| Branch                    | Patch Apply | Build Test |
|---------------------------|-------------|------------|
| stable/linux-6.1.y        |  Success    |  Success   |

  reply	other threads:[~2025-05-12 21:52 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-12  1:52 [PATCH 6.1.y] spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer jianqi.ren.cn
2025-05-12 21:52 ` Sasha Levin [this message]
2025-10-09 12:35   ` Nobuhiro Iwamatsu
2025-10-09 13:09     ` Greg Kroah-Hartman

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