* [PATCH 6.12.y 2/5] drm/xe/reg_sr: Do sanity check for MCR vs non-MCR
2026-08-01 12:07 ` [PATCH 6.12.y 1/5] drm/xe/mcr: Extract reg_in_steering_type_ranges() Sasha Levin
@ 2026-08-01 12:07 ` Sasha Levin
2026-08-01 12:07 ` [PATCH 6.12.y 3/5] drm/xe/rtp: Drop rule matching cases from rtp_to_sr_cases and rtp_cases Sasha Levin
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Sasha Levin @ 2026-08-01 12:07 UTC (permalink / raw)
To: stable; +Cc: Gustavo Sousa, Matt Roper, Sasha Levin
From: Gustavo Sousa <gustavo.sousa@intel.com>
[ Upstream commit 058da4a2b164e477b02ca0562f01a9eb9e621cdd ]
The type struct xe_reg_mcr exists to ensure that the correct API is used
when handling MCR registers. However, for the register save/restore
functionality, the RTP processing always cast the register to a struct
xe_reg and then apply_one_mmio() selects the MMIO API based on the "mcr"
field of the register instance.
This allows the developer to commit mistakes like passing a MCR register
for an RTP action for a GT where the respective register is not MCR; and
vice-versa.
To capture such scenarios, do a sanity check in xe_reg_sr_add() that,
upon an inconsistency:
- "fixes" the register type by favoring what we have in our MCR range
tables instead of what the developer selected for the save/restore
entry;
- raises a notice-level message to inform about the inconsistency.
Note: As a collateral of this change, we need to include MCR
initialization in xe_wa_test.c, otherwise a bunch of test cases end up
failing because xe_gt_mcr_check_reg() will always return false, meaning
that will incorrectly say that a MCR register is not MCR.
v2:
- Downgrade messages to notice level so as not to block CI execution
when inconsistencies are found. (Matt)
- Add missing EXPORT_SYMBOL_IF_KUNIT() calls. (Gustavo)
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20260514-rtp-mcr-check-v3-7-30dd47855fee@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Stable-dep-of: 4fe2844b0f0c ("drm/xe/rtp: Generalize whitelist_apply_to_hwe")
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/gpu/drm/xe/tests/xe_rtp_test.c | 71 +++++++++++++++++++++++---
drivers/gpu/drm/xe/tests/xe_wa_test.c | 10 +++-
drivers/gpu/drm/xe/xe_gt_mcr.c | 52 ++++++++++++++-----
drivers/gpu/drm/xe/xe_gt_mcr.h | 2 +
drivers/gpu/drm/xe/xe_reg_sr.c | 36 +++++++++++++
5 files changed, 151 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/xe/tests/xe_rtp_test.c b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
index 36a3b5420fef..28b21815e5ab 100644
--- a/drivers/gpu/drm/xe/tests/xe_rtp_test.c
+++ b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
@@ -9,24 +9,30 @@
#include <drm/drm_drv.h>
#include <drm/drm_kunit_helpers.h>
+#include <kunit/static_stub.h>
#include <kunit/test.h>
#include "regs/xe_gt_regs.h"
#include "regs/xe_reg_defs.h"
#include "xe_device.h"
#include "xe_device_types.h"
+#include "xe_gt_mcr.h"
#include "xe_kunit_helpers.h"
#include "xe_pci_test.h"
#include "xe_reg_sr.h"
#include "xe_rtp.h"
-#define REGULAR_REG1 XE_REG(1)
-#define REGULAR_REG2 XE_REG(2)
-#define REGULAR_REG3 XE_REG(3)
-#define MCR_REG1 XE_REG_MCR(1)
-#define MCR_REG2 XE_REG_MCR(2)
-#define MCR_REG3 XE_REG_MCR(3)
-#define MASKED_REG1 XE_REG(1, XE_REG_OPTION_MASKED)
+#define REGULAR_REG1 XE_REG(1)
+#define REGULAR_REG2 XE_REG(2)
+#define REGULAR_REG3 XE_REG(3)
+#define REGULAR_REG4 XE_REG(4)
+#define BAD_REGULAR_REG5 XE_REG(5)
+#define MCR_REG1 XE_REG_MCR(1)
+#define MCR_REG2 XE_REG_MCR(2)
+#define MCR_REG3 XE_REG_MCR(3)
+#define BAD_MCR_REG4 XE_REG_MCR(4)
+#define MCR_REG5 XE_REG_MCR(5)
+#define MASKED_REG1 XE_REG(1, XE_REG_OPTION_MASKED)
#undef XE_REG_MCR
#define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
@@ -48,6 +54,23 @@ struct rtp_test_case {
const struct xe_rtp_entry *entries;
};
+static bool fake_xe_gt_mcr_check_reg(struct xe_gt *gt, struct xe_reg reg)
+{
+ /*
+ * All supported platforms in this imaginary setup will always have REG4
+ * as a non-MCR register and REG5 as MCR, meaning that BAD_MCR_REG4 and
+ * BAD_REGULAR_REG5 represent programming errors to be captured by our
+ * tests.
+ */
+ if (reg.raw == BAD_REGULAR_REG5.raw)
+ return true;
+
+ if (reg.raw == BAD_MCR_REG4.raw)
+ return false;
+
+ return reg.mcr;
+}
+
static bool match_yes(const struct xe_gt *gt, const struct xe_hw_engine *hwe)
{
return true;
@@ -302,6 +325,38 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
{}
},
},
+ {
+ .name = "bad-mcr-reg-forced-to-regular",
+ .expected_reg = REGULAR_REG4,
+ .expected_set_bits = REG_BIT(0),
+ .expected_clr_bits = REG_BIT(0),
+ .expected_active = BIT(0),
+ .expected_count_sr_entries = 1,
+ .expected_sr_errors = 1,
+ .entries = (const struct xe_rtp_entry_sr[]) {
+ { XE_RTP_NAME("bad-mcr-regular-reg"),
+ XE_RTP_RULES(FUNC(match_yes)),
+ XE_RTP_ACTIONS(SET(BAD_MCR_REG4, REG_BIT(0)))
+ },
+ {}
+ },
+ },
+ {
+ .name = "bad-regular-reg-forced-to-mcr",
+ .expected_reg = MCR_REG5,
+ .expected_set_bits = REG_BIT(0),
+ .expected_clr_bits = REG_BIT(0),
+ .expected_active = BIT(0),
+ .expected_count_sr_entries = 1,
+ .expected_sr_errors = 1,
+ .entries = (const struct xe_rtp_entry_sr[]) {
+ { XE_RTP_NAME("bad-regular-reg"),
+ XE_RTP_RULES(FUNC(match_yes)),
+ XE_RTP_ACTIONS(SET(BAD_REGULAR_REG5, REG_BIT(0)))
+ },
+ {}
+ },
+ },
};
static void xe_rtp_process_to_sr_tests(struct kunit *test)
@@ -520,6 +575,8 @@ static int xe_rtp_test_init(struct kunit *test)
xe->drm.dev = dev;
test->priv = xe;
+ kunit_activate_static_stub(test, xe_gt_mcr_check_reg, fake_xe_gt_mcr_check_reg);
+
return 0;
}
diff --git a/drivers/gpu/drm/xe/tests/xe_wa_test.c b/drivers/gpu/drm/xe/tests/xe_wa_test.c
index c96d1fe34151..9e260549e2e9 100644
--- a/drivers/gpu/drm/xe/tests/xe_wa_test.c
+++ b/drivers/gpu/drm/xe/tests/xe_wa_test.c
@@ -9,6 +9,8 @@
#include <kunit/test.h>
#include "xe_device.h"
+#include "xe_gt.h"
+#include "xe_gt_mcr.h"
#include "xe_kunit_helpers.h"
#include "xe_pci_test.h"
#include "xe_reg_sr.h"
@@ -95,8 +97,10 @@ static int xe_wa_test_init(struct kunit *test)
.graphics_step = param->step.graphics,
.media_step = param->step.media,
};
- struct xe_device *xe;
struct device *dev;
+ struct xe_device *xe;
+ struct xe_gt *gt;
+ int id;
int ret;
dev = drm_kunit_helper_alloc_device(test);
@@ -109,6 +113,10 @@ static int xe_wa_test_init(struct kunit *test)
ret = xe_pci_fake_device_init(xe);
KUNIT_ASSERT_EQ(test, ret, 0);
+ /* Needed for sanitize_mcr(). */
+ for_each_gt(gt, xe, id)
+ xe_gt_mcr_init_early(gt);
+
if (!param->graphics_verx100)
xe->info.step = param->step;
diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
index 6295cd639f5c..d7159f4796d4 100644
--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
@@ -3,6 +3,9 @@
* Copyright © 2022 Intel Corporation
*/
+#include <kunit/static_stub.h>
+#include <kunit/visibility.h>
+
#include "xe_gt_mcr.h"
#include "regs/xe_gt_regs.h"
@@ -413,25 +416,17 @@ static const struct {
*
* Perform early software only initialization of the MCR lock to allow
* the synchronization on accessing the STEER_SEMAPHORE register and
- * use the xe_gt_mcr_multicast_write() function.
+ * use the xe_gt_mcr_multicast_write() function, and select the MCR
+ * ranges applicable to this GT.
*/
void xe_gt_mcr_init_early(struct xe_gt *gt)
{
+ struct xe_device *xe = gt_to_xe(gt);
+
BUILD_BUG_ON(IMPLICIT_STEERING + 1 != NUM_STEERING_TYPES);
BUILD_BUG_ON(ARRAY_SIZE(xe_steering_types) != NUM_STEERING_TYPES);
spin_lock_init(>->mcr_lock);
-}
-
-/**
- * xe_gt_mcr_init - Normal initialization of the MCR support
- * @gt: GT structure
- *
- * Perform normal initialization of the MCR for all usages.
- */
-void xe_gt_mcr_init(struct xe_gt *gt)
-{
- struct xe_device *xe = gt_to_xe(gt);
if (IS_SRIOV_VF(xe))
return;
@@ -468,6 +463,19 @@ void xe_gt_mcr_init(struct xe_gt *gt)
gt->steering[DSS].ranges = xelp_dss_steering_table;
}
}
+}
+EXPORT_SYMBOL_IF_KUNIT(xe_gt_mcr_init_early);
+
+/**
+ * xe_gt_mcr_init - Normal initialization of the MCR support
+ * @gt: GT structure
+ *
+ * Perform normal initialization of the MCR for all usages.
+ */
+void xe_gt_mcr_init(struct xe_gt *gt)
+{
+ if (IS_SRIOV_VF(gt_to_xe(gt)))
+ return;
/* Select non-terminated steering target for each type */
for (int i = 0; i < NUM_STEERING_TYPES; i++)
@@ -519,6 +527,26 @@ static bool reg_in_steering_type_ranges(struct xe_gt *gt,
return false;
}
+/*
+ * xe_gt_mcr_check_reg - check if a register is recognized by this GT as MCR
+ * @gt: GT structure
+ * @reg: The register to check
+ *
+ * Returns true if the register offset falls within one of the MMIO ranges
+ * classified as MCR for the GT.
+ */
+bool xe_gt_mcr_check_reg(struct xe_gt *gt, struct xe_reg reg)
+{
+ KUNIT_STATIC_STUB_REDIRECT(xe_gt_mcr_check_reg, gt, reg);
+
+ for (int type = 0; type <= IMPLICIT_STEERING; type++)
+ if (reg_in_steering_type_ranges(gt, reg, type))
+ return true;
+
+ return false;
+}
+EXPORT_SYMBOL_IF_KUNIT(xe_gt_mcr_check_reg);
+
/*
* xe_gt_mcr_get_nonterminated_steering - find group/instance values that
* will steer a register to a non-terminated instance
diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.h b/drivers/gpu/drm/xe/xe_gt_mcr.h
index 8d119a0d5493..fa6b856674c2 100644
--- a/drivers/gpu/drm/xe/xe_gt_mcr.h
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.h
@@ -26,6 +26,8 @@ void xe_gt_mcr_unicast_write(struct xe_gt *gt, struct xe_reg_mcr mcr_reg,
void xe_gt_mcr_multicast_write(struct xe_gt *gt, struct xe_reg_mcr mcr_reg,
u32 value);
+bool xe_gt_mcr_check_reg(struct xe_gt *gt, struct xe_reg reg);
+
void xe_gt_mcr_steering_dump(struct xe_gt *gt, struct drm_printer *p);
void xe_gt_mcr_get_dss_steering(struct xe_gt *gt, unsigned int dss, u16 *group, u16 *instance);
diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c
index ae9e6df2f4e1..6f18b5fb4537 100644
--- a/drivers/gpu/drm/xe/xe_reg_sr.c
+++ b/drivers/gpu/drm/xe/xe_reg_sr.c
@@ -72,14 +72,49 @@ static void reg_sr_inc_error(struct xe_reg_sr *sr)
#endif
}
+static struct xe_reg sanitize_mcr(struct xe_reg_sr *sr,
+ const struct xe_reg_sr_entry *e,
+ struct xe_gt *gt)
+{
+ struct xe_reg reg = e->reg;
+ bool is_mcr;
+
+ /*
+ * We need the gt structure to check MCR ranges.
+ */
+ if (!gt)
+ return reg;
+
+ is_mcr = xe_gt_mcr_check_reg(gt, reg);
+
+ if (is_mcr && !reg.mcr) {
+ reg.mcr = 1;
+ xe_gt_notice(gt, "xe_reg_sr_entry using non-MCR register for address 0x%x, forcing MCR\n",
+ reg.addr);
+ reg_sr_inc_error(sr);
+ }
+
+ if (!is_mcr && reg.mcr) {
+ reg.mcr = 0;
+ xe_gt_notice(gt, "xe_reg_sr_entry using MCR register for address 0x%x, forcing non-MCR\n",
+ reg.addr);
+ reg_sr_inc_error(sr);
+ }
+
+ return reg;
+}
+
int xe_reg_sr_add(struct xe_reg_sr *sr,
const struct xe_reg_sr_entry *e,
struct xe_gt *gt)
{
unsigned long idx = e->reg.addr;
struct xe_reg_sr_entry *pentry = xa_load(&sr->xa, idx);
+ struct xe_reg reg;
int ret;
+ reg = sanitize_mcr(sr, e, gt);
+
if (pentry) {
if (!compatible_entries(pentry, e)) {
ret = -EINVAL;
@@ -100,6 +135,7 @@ int xe_reg_sr_add(struct xe_reg_sr *sr,
}
*pentry = *e;
+ pentry->reg = reg;
ret = xa_err(xa_store(&sr->xa, idx, pentry, GFP_KERNEL));
if (ret)
goto fail_free;
--
2.53.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 6.12.y 3/5] drm/xe/rtp: Drop rule matching cases from rtp_to_sr_cases and rtp_cases
2026-08-01 12:07 ` [PATCH 6.12.y 1/5] drm/xe/mcr: Extract reg_in_steering_type_ranges() Sasha Levin
2026-08-01 12:07 ` [PATCH 6.12.y 2/5] drm/xe/reg_sr: Do sanity check for MCR vs non-MCR Sasha Levin
@ 2026-08-01 12:07 ` Sasha Levin
2026-08-01 12:07 ` [PATCH 6.12.y 4/5] drm/xe/rtp: Add struct types for RTP tables Sasha Levin
2026-08-01 12:07 ` [PATCH 6.12.y 5/5] drm/xe/rtp: Maintain OA whitelists separately Sasha Levin
3 siblings, 0 replies; 7+ messages in thread
From: Sasha Levin @ 2026-08-01 12:07 UTC (permalink / raw)
To: stable; +Cc: Gustavo Sousa, Matt Roper, Sasha Levin
From: Gustavo Sousa <gustavo.sousa@intel.com>
[ Upstream commit ff7746336b2325087aa7958d40f327bcc50185f8 ]
The kunit test cases for the RTP framework are currently separated into
three groups:
(1) rtp_rules_cases:
Those to verify rule matching logic.
(2) rtp_to_sr_cases:
Those to verify generation of save/restore tables from RTP tables.
(3) rtp_cases
Those to verify processing of RTP tables without save/restore action
associated, which are used for OOB workarounds.
Today we have some cases in (2) and (3) that are actually meant to
verify rule matching logic. Now that we have (1), let's cleanup (2)
and (3) so that they become focused on their main objectives.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20260522-rtp-rule-parser-v3-2-0c51039899f4@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Stable-dep-of: 4fe2844b0f0c ("drm/xe/rtp: Generalize whitelist_apply_to_hwe")
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/gpu/drm/xe/tests/xe_rtp_test.c | 122 ++-----------------------
1 file changed, 6 insertions(+), 116 deletions(-)
diff --git a/drivers/gpu/drm/xe/tests/xe_rtp_test.c b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
index 28b21815e5ab..e0972d42f96c 100644
--- a/drivers/gpu/drm/xe/tests/xe_rtp_test.c
+++ b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
@@ -122,80 +122,6 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
{}
},
},
- {
- .name = "match-or",
- .expected_reg = REGULAR_REG1,
- .expected_set_bits = REG_BIT(0) | REG_BIT(1) | REG_BIT(2),
- .expected_clr_bits = REG_BIT(0) | REG_BIT(1) | REG_BIT(2),
- .expected_active = BIT(0) | BIT(1) | BIT(2),
- .expected_count_sr_entries = 1,
- .entries = (const struct xe_rtp_entry_sr[]) {
- { XE_RTP_NAME("first"),
- XE_RTP_RULES(FUNC(match_yes), OR, FUNC(match_no)),
- XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
- },
- { XE_RTP_NAME("middle"),
- XE_RTP_RULES(FUNC(match_no), FUNC(match_no), OR,
- FUNC(match_yes), OR,
- FUNC(match_no)),
- XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
- },
- { XE_RTP_NAME("last"),
- XE_RTP_RULES(FUNC(match_no), OR, FUNC(match_yes)),
- XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(2)))
- },
- { XE_RTP_NAME("no-match"),
- XE_RTP_RULES(FUNC(match_no), OR, FUNC(match_no)),
- XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(3)))
- },
- {}
- },
- },
- {
- .name = "match-or-xfail",
- .expected_reg = REGULAR_REG1,
- .expected_count_sr_entries = 0,
- .entries = (const struct xe_rtp_entry_sr[]) {
- { XE_RTP_NAME("leading-or"),
- XE_RTP_RULES(OR, FUNC(match_yes)),
- XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
- },
- { XE_RTP_NAME("trailing-or"),
- /*
- * First condition is match_no, otherwise the failure
- * wouldn't really trigger as RTP stops processing as
- * soon as it has a matching set of rules
- */
- XE_RTP_RULES(FUNC(match_no), OR),
- XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
- },
- { XE_RTP_NAME("no-or-or-yes"),
- XE_RTP_RULES(FUNC(match_no), OR, OR, FUNC(match_yes)),
- XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(2)))
- },
- {}
- },
- },
- {
- .name = "no-match-no-add-multiple-rules",
- .expected_reg = REGULAR_REG1,
- .expected_set_bits = REG_BIT(0),
- .expected_clr_bits = REG_BIT(0),
- .expected_active = BIT(0),
- .expected_count_sr_entries = 1,
- /* Don't coalesce second entry due to one of the rules */
- .entries = (const struct xe_rtp_entry_sr[]) {
- { XE_RTP_NAME("basic-1"),
- XE_RTP_RULES(FUNC(match_yes)),
- XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
- },
- { XE_RTP_NAME("basic-2"),
- XE_RTP_RULES(FUNC(match_yes), FUNC(match_no)),
- XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
- },
- {}
- },
- },
{
.name = "two-regs-two-entries",
.expected_reg = REGULAR_REG1,
@@ -455,33 +381,15 @@ static const struct rtp_test_case rtp_cases[] = {
},
},
{
- .name = "inactive-1st_or_active-inactive",
+ .name = "inactive-active-inactive",
.expected_active = BIT(1),
.entries = (const struct xe_rtp_entry[]) {
{ XE_RTP_NAME("r1"),
XE_RTP_RULES(FUNC(match_no)),
},
- { XE_RTP_NAME("r2_or_conditions"),
- XE_RTP_RULES(FUNC(match_yes), OR,
- FUNC(match_no), OR,
- FUNC(match_no)) },
- { XE_RTP_NAME("r3"),
- XE_RTP_RULES(FUNC(match_no)),
- },
- {}
- },
- },
- {
- .name = "inactive-2nd_or_active-inactive",
- .expected_active = BIT(1),
- .entries = (const struct xe_rtp_entry[]) {
- { XE_RTP_NAME("r1"),
- XE_RTP_RULES(FUNC(match_no)),
+ { XE_RTP_NAME("r2"),
+ XE_RTP_RULES(FUNC(match_yes)),
},
- { XE_RTP_NAME("r2_or_conditions"),
- XE_RTP_RULES(FUNC(match_no), OR,
- FUNC(match_yes), OR,
- FUNC(match_no)) },
{ XE_RTP_NAME("r3"),
XE_RTP_RULES(FUNC(match_no)),
},
@@ -489,33 +397,15 @@ static const struct rtp_test_case rtp_cases[] = {
},
},
{
- .name = "inactive-last_or_active-inactive",
- .expected_active = BIT(1),
+ .name = "inactive-inactive-inactive",
+ .expected_active = 0,
.entries = (const struct xe_rtp_entry[]) {
{ XE_RTP_NAME("r1"),
XE_RTP_RULES(FUNC(match_no)),
},
- { XE_RTP_NAME("r2_or_conditions"),
- XE_RTP_RULES(FUNC(match_no), OR,
- FUNC(match_no), OR,
- FUNC(match_yes)) },
- { XE_RTP_NAME("r3"),
- XE_RTP_RULES(FUNC(match_no)),
- },
- {}
- },
- },
- {
- .name = "inactive-no_or_active-inactive",
- .expected_active = 0,
- .entries = (const struct xe_rtp_entry[]) {
- { XE_RTP_NAME("r1"),
+ { XE_RTP_NAME("r2"),
XE_RTP_RULES(FUNC(match_no)),
},
- { XE_RTP_NAME("r2_or_conditions"),
- XE_RTP_RULES(FUNC(match_no), OR,
- FUNC(match_no), OR,
- FUNC(match_no)) },
{ XE_RTP_NAME("r3"),
XE_RTP_RULES(FUNC(match_no)),
},
--
2.53.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 6.12.y 4/5] drm/xe/rtp: Add struct types for RTP tables
2026-08-01 12:07 ` [PATCH 6.12.y 1/5] drm/xe/mcr: Extract reg_in_steering_type_ranges() Sasha Levin
2026-08-01 12:07 ` [PATCH 6.12.y 2/5] drm/xe/reg_sr: Do sanity check for MCR vs non-MCR Sasha Levin
2026-08-01 12:07 ` [PATCH 6.12.y 3/5] drm/xe/rtp: Drop rule matching cases from rtp_to_sr_cases and rtp_cases Sasha Levin
@ 2026-08-01 12:07 ` Sasha Levin
2026-08-01 12:07 ` [PATCH 6.12.y 5/5] drm/xe/rtp: Maintain OA whitelists separately Sasha Levin
3 siblings, 0 replies; 7+ messages in thread
From: Sasha Levin @ 2026-08-01 12:07 UTC (permalink / raw)
To: stable
Cc: Gustavo Sousa, Matt Roper, Violet Monti, Thomas Hellström,
Sasha Levin
From: Gustavo Sousa <gustavo.sousa@intel.com>
[ Upstream commit e23fafb8594ea886ee03e005cc32dfda24f417cf ]
We currently have a mixture of styles for our RTP tables with respect of
how we define the number of entries:
* xe_rtp_process_to_sr() expects to receive the number of entries as
arguments;
* xe_rtp_process() expects the array to have a sentinel at the end of
the array;
* in xe_rtp_test.c, even though xe_rtp_process_to_sr() does not
require a sentinel value, we need to rely on that technique to be
able to count xe_rtp_entry_sr entries because simply using
ARRAY_SIZE() is not possible.
The style used by xe_rtp_process_to_sr() makes it hard to share the
tables with other compilation units (e.g. kunit tests), since the number
of entries is calculated with ARRAY_SIZE(), which is done at compile
time.
Since we use the size of the tables to create some bitmasks, using a
sentinel style doesn't seem great either.
A way to reconcile things into a single style is to have a struct type
that would hold the entries array and the number of entries. Since we
have xe_rtp_entry and xe_rtp_entry_sr, we would have one type for each.
The advantage of the proposed approach is that now we have a nice way to
share the tables directly to kunit tests with information about their
size.
v6:
- Removed sentinels that are not needed
v5:
- Removed added code from conflict resolution issues
v4:
- Removed conflicts with main branch
v3:
- No changes
v2:
- Add compatibility with new xe_rtp_table_sr format for
"bad-mcr-reg-forced-to-regular" and
"bad-regular-reg-forced-to-mcr"
Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support")
Cc: stable@vger.kernel.org # v6.12+
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Violet Monti <violet.monti@intel.com>
Link: https://patch.msgid.link/20260601200947.2032784-7-violet.monti@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
(cherry picked from commit 5ff004fdc7377905f2fe5264b8829d35e14608b8)
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Stable-dep-of: 4fe2844b0f0c ("drm/xe/rtp: Generalize whitelist_apply_to_hwe")
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/gpu/drm/xe/tests/xe_rtp_test.c | 102 ++++++++++---------------
drivers/gpu/drm/xe/xe_hw_engine.c | 14 ++--
drivers/gpu/drm/xe/xe_reg_whitelist.c | 7 +-
drivers/gpu/drm/xe/xe_rtp.c | 35 +++++----
drivers/gpu/drm/xe/xe_rtp.h | 14 +++-
drivers/gpu/drm/xe/xe_rtp_types.h | 10 +++
drivers/gpu/drm/xe/xe_tuning.c | 23 +++---
drivers/gpu/drm/xe/xe_wa.c | 70 +++++++++--------
8 files changed, 134 insertions(+), 141 deletions(-)
diff --git a/drivers/gpu/drm/xe/tests/xe_rtp_test.c b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
index e0972d42f96c..0aeff548bb73 100644
--- a/drivers/gpu/drm/xe/tests/xe_rtp_test.c
+++ b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
@@ -45,13 +45,13 @@ struct rtp_to_sr_test_case {
unsigned long expected_count_sr_entries;
unsigned int expected_sr_errors;
unsigned long expected_active;
- const struct xe_rtp_entry_sr *entries;
+ const struct xe_rtp_table_sr table;
};
struct rtp_test_case {
const char *name;
unsigned long expected_active;
- const struct xe_rtp_entry *entries;
+ const struct xe_rtp_table table;
};
static bool fake_xe_gt_mcr_check_reg(struct xe_gt *gt, struct xe_reg reg)
@@ -90,7 +90,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
.expected_active = BIT(0) | BIT(1),
.expected_count_sr_entries = 1,
/* Different bits on the same register: create a single entry */
- .entries = (const struct xe_rtp_entry_sr[]) {
+ .table = XE_RTP_TABLE_SR(
{ XE_RTP_NAME("basic-1"),
XE_RTP_RULES(FUNC(match_yes)),
XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
@@ -99,8 +99,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
XE_RTP_RULES(FUNC(match_yes)),
XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
},
- {}
- },
+ ),
},
{
.name = "no-match-no-add",
@@ -110,7 +109,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
.expected_active = BIT(0),
.expected_count_sr_entries = 1,
/* Don't coalesce second entry since rules don't match */
- .entries = (const struct xe_rtp_entry_sr[]) {
+ .table = XE_RTP_TABLE_SR(
{ XE_RTP_NAME("basic-1"),
XE_RTP_RULES(FUNC(match_yes)),
XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
@@ -119,8 +118,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
XE_RTP_RULES(FUNC(match_no)),
XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
},
- {}
- },
+ ),
},
{
.name = "two-regs-two-entries",
@@ -130,7 +128,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
.expected_active = BIT(0) | BIT(1),
.expected_count_sr_entries = 2,
/* Same bits on different registers are not coalesced */
- .entries = (const struct xe_rtp_entry_sr[]) {
+ .table = XE_RTP_TABLE_SR(
{ XE_RTP_NAME("basic-1"),
XE_RTP_RULES(FUNC(match_yes)),
XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
@@ -139,8 +137,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
XE_RTP_RULES(FUNC(match_yes)),
XE_RTP_ACTIONS(SET(REGULAR_REG2, REG_BIT(0)))
},
- {}
- },
+ ),
},
{
.name = "clr-one-set-other",
@@ -150,7 +147,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
.expected_active = BIT(0) | BIT(1),
.expected_count_sr_entries = 1,
/* Check clr vs set actions on different bits */
- .entries = (const struct xe_rtp_entry_sr[]) {
+ .table = XE_RTP_TABLE_SR(
{ XE_RTP_NAME("basic-1"),
XE_RTP_RULES(FUNC(match_yes)),
XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
@@ -159,8 +156,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
XE_RTP_RULES(FUNC(match_yes)),
XE_RTP_ACTIONS(CLR(REGULAR_REG1, REG_BIT(1)))
},
- {}
- },
+ ),
},
{
#define TEMP_MASK REG_GENMASK(10, 8)
@@ -172,14 +168,13 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
.expected_active = BIT(0),
.expected_count_sr_entries = 1,
/* Check FIELD_SET works */
- .entries = (const struct xe_rtp_entry_sr[]) {
+ .table = XE_RTP_TABLE_SR(
{ XE_RTP_NAME("basic-1"),
XE_RTP_RULES(FUNC(match_yes)),
XE_RTP_ACTIONS(FIELD_SET(REGULAR_REG1,
TEMP_MASK, TEMP_FIELD))
},
- {}
- },
+ ),
#undef TEMP_MASK
#undef TEMP_FIELD
},
@@ -191,7 +186,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
.expected_active = BIT(0) | BIT(1),
.expected_count_sr_entries = 1,
.expected_sr_errors = 1,
- .entries = (const struct xe_rtp_entry_sr[]) {
+ .table = XE_RTP_TABLE_SR(
{ XE_RTP_NAME("basic-1"),
XE_RTP_RULES(FUNC(match_yes)),
XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
@@ -201,8 +196,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
XE_RTP_RULES(FUNC(match_yes)),
XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
},
- {}
- },
+ ),
},
{
.name = "conflict-not-disjoint",
@@ -212,7 +206,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
.expected_active = BIT(0) | BIT(1),
.expected_count_sr_entries = 1,
.expected_sr_errors = 1,
- .entries = (const struct xe_rtp_entry_sr[]) {
+ .table = XE_RTP_TABLE_SR(
{ XE_RTP_NAME("basic-1"),
XE_RTP_RULES(FUNC(match_yes)),
XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
@@ -222,8 +216,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
XE_RTP_RULES(FUNC(match_yes)),
XE_RTP_ACTIONS(CLR(REGULAR_REG1, REG_GENMASK(1, 0)))
},
- {}
- },
+ ),
},
{
.name = "conflict-reg-type",
@@ -233,7 +226,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
.expected_active = BIT(0) | BIT(1) | BIT(2),
.expected_count_sr_entries = 1,
.expected_sr_errors = 2,
- .entries = (const struct xe_rtp_entry_sr[]) {
+ .table = XE_RTP_TABLE_SR(
{ XE_RTP_NAME("basic-1"),
XE_RTP_RULES(FUNC(match_yes)),
XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
@@ -248,8 +241,7 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
XE_RTP_RULES(FUNC(match_yes)),
XE_RTP_ACTIONS(SET(MASKED_REG1, REG_BIT(0)))
},
- {}
- },
+ ),
},
{
.name = "bad-mcr-reg-forced-to-regular",
@@ -259,13 +251,12 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
.expected_active = BIT(0),
.expected_count_sr_entries = 1,
.expected_sr_errors = 1,
- .entries = (const struct xe_rtp_entry_sr[]) {
+ .table = XE_RTP_TABLE_SR(
{ XE_RTP_NAME("bad-mcr-regular-reg"),
XE_RTP_RULES(FUNC(match_yes)),
XE_RTP_ACTIONS(SET(BAD_MCR_REG4, REG_BIT(0)))
},
- {}
- },
+ ),
},
{
.name = "bad-regular-reg-forced-to-mcr",
@@ -275,13 +266,12 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
.expected_active = BIT(0),
.expected_count_sr_entries = 1,
.expected_sr_errors = 1,
- .entries = (const struct xe_rtp_entry_sr[]) {
+ .table = XE_RTP_TABLE_SR(
{ XE_RTP_NAME("bad-regular-reg"),
XE_RTP_RULES(FUNC(match_yes)),
XE_RTP_ACTIONS(SET(BAD_REGULAR_REG5, REG_BIT(0)))
},
- {}
- },
+ ),
},
};
@@ -293,15 +283,12 @@ static void xe_rtp_process_to_sr_tests(struct kunit *test)
struct xe_reg_sr *reg_sr = >->reg_sr;
const struct xe_reg_sr_entry *sre, *sr_entry = NULL;
struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
- unsigned long idx, count_sr_entries = 0, count_rtp_entries = 0, active = 0;
+ unsigned long idx, count_sr_entries = 0, active = 0;
xe_reg_sr_init(reg_sr, "xe_rtp_to_sr_tests", xe);
- while (param->entries[count_rtp_entries].rules)
- count_rtp_entries++;
-
- xe_rtp_process_ctx_enable_active_tracking(&ctx, &active, count_rtp_entries);
- xe_rtp_process_to_sr(&ctx, param->entries, reg_sr);
+ xe_rtp_process_ctx_enable_active_tracking(&ctx, &active, param->table.n_entries);
+ xe_rtp_process_to_sr(&ctx, ¶m->table, reg_sr);
xa_for_each(®_sr->xa, idx, sre) {
if (idx == param->expected_reg.addr)
@@ -334,56 +321,52 @@ static const struct rtp_test_case rtp_cases[] = {
{
.name = "active1",
.expected_active = BIT(0),
- .entries = (const struct xe_rtp_entry[]) {
+ .table = XE_RTP_TABLE(
{ XE_RTP_NAME("r1"),
XE_RTP_RULES(FUNC(match_yes)),
},
- {}
- },
+ ),
},
{
.name = "active2",
.expected_active = BIT(0) | BIT(1),
- .entries = (const struct xe_rtp_entry[]) {
+ .table = XE_RTP_TABLE(
{ XE_RTP_NAME("r1"),
XE_RTP_RULES(FUNC(match_yes)),
},
{ XE_RTP_NAME("r2"),
XE_RTP_RULES(FUNC(match_yes)),
},
- {}
- },
+ ),
},
{
.name = "active-inactive",
.expected_active = BIT(0),
- .entries = (const struct xe_rtp_entry[]) {
+ .table = XE_RTP_TABLE(
{ XE_RTP_NAME("r1"),
XE_RTP_RULES(FUNC(match_yes)),
},
{ XE_RTP_NAME("r2"),
XE_RTP_RULES(FUNC(match_no)),
},
- {}
- },
+ ),
},
{
.name = "inactive-active",
.expected_active = BIT(1),
- .entries = (const struct xe_rtp_entry[]) {
+ .table = XE_RTP_TABLE(
{ XE_RTP_NAME("r1"),
XE_RTP_RULES(FUNC(match_no)),
},
{ XE_RTP_NAME("r2"),
XE_RTP_RULES(FUNC(match_yes)),
},
- {}
- },
+ ),
},
{
.name = "inactive-active-inactive",
.expected_active = BIT(1),
- .entries = (const struct xe_rtp_entry[]) {
+ .table = XE_RTP_TABLE(
{ XE_RTP_NAME("r1"),
XE_RTP_RULES(FUNC(match_no)),
},
@@ -393,13 +376,12 @@ static const struct rtp_test_case rtp_cases[] = {
{ XE_RTP_NAME("r3"),
XE_RTP_RULES(FUNC(match_no)),
},
- {}
- },
+ ),
},
{
.name = "inactive-inactive-inactive",
.expected_active = 0,
- .entries = (const struct xe_rtp_entry[]) {
+ .table = XE_RTP_TABLE(
{ XE_RTP_NAME("r1"),
XE_RTP_RULES(FUNC(match_no)),
},
@@ -409,8 +391,7 @@ static const struct rtp_test_case rtp_cases[] = {
{ XE_RTP_NAME("r3"),
XE_RTP_RULES(FUNC(match_no)),
},
- {}
- },
+ ),
},
};
@@ -420,13 +401,10 @@ static void xe_rtp_process_tests(struct kunit *test)
struct xe_device *xe = test->priv;
struct xe_gt *gt = xe_device_get_root_tile(xe)->primary_gt;
struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
- unsigned long count_rtp_entries = 0, active = 0;
-
- while (param->entries[count_rtp_entries].rules)
- count_rtp_entries++;
+ unsigned long active = 0;
- xe_rtp_process_ctx_enable_active_tracking(&ctx, &active, count_rtp_entries);
- xe_rtp_process(&ctx, param->entries);
+ xe_rtp_process_ctx_enable_active_tracking(&ctx, &active, param->table.n_entries);
+ xe_rtp_process(&ctx, ¶m->table);
KUNIT_EXPECT_EQ(test, active, param->expected_active);
}
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 45d0ae074e65..6b37b12f5a71 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -366,7 +366,7 @@ xe_hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe)
u32 blit_cctl_val = REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, mocs_write_idx) |
REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, mocs_read_idx);
struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
- const struct xe_rtp_entry_sr lrc_setup[] = {
+ const struct xe_rtp_table_sr lrc_setup = XE_RTP_TABLE_SR(
/*
* Some blitter commands do not have a field for MOCS, those
* commands will use MOCS index pointed by BLIT_CCTL.
@@ -389,10 +389,9 @@ xe_hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe)
PREEMPT_GPGPU_THREAD_GROUP_LEVEL)),
XE_RTP_ENTRY_FLAG(FOREACH_ENGINE)
},
- {}
- };
+ );
- xe_rtp_process_to_sr(&ctx, lrc_setup, &hwe->reg_lrc);
+ xe_rtp_process_to_sr(&ctx, &lrc_setup, &hwe->reg_lrc);
}
static void
@@ -417,7 +416,7 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe)
u32 ring_cmd_cctl_val = REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, mocs_write_idx) |
REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, mocs_read_idx);
struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
- const struct xe_rtp_entry_sr engine_entries[] = {
+ const struct xe_rtp_table_sr engine_sr = XE_RTP_TABLE_SR(
{ XE_RTP_NAME("RING_CMD_CCTL_default_MOCS"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED)),
XE_RTP_ACTIONS(FIELD_SET(RING_CMD_CCTL(0),
@@ -454,10 +453,9 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe)
XE_RTP_ACTIONS(FIELD_SET(RCU_MODE, RCU_MODE_FIXED_SLICE_CCS_MODE,
RCU_MODE_FIXED_SLICE_CCS_MODE))
},
- {}
- };
+ );
- xe_rtp_process_to_sr(&ctx, engine_entries, &hwe->reg_sr);
+ xe_rtp_process_to_sr(&ctx, &engine_sr, &hwe->reg_sr);
}
static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index 3de0a867149d..4c442f643e68 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -23,7 +23,7 @@ static bool match_not_render(const struct xe_gt *gt,
return hwe->class != XE_ENGINE_CLASS_RENDER;
}
-static const struct xe_rtp_entry_sr register_whitelist[] = {
+static const struct xe_rtp_table_sr register_whitelist = XE_RTP_TABLE_SR(
{ XE_RTP_NAME("WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(WHITELIST(PS_INVOCATION_COUNT,
@@ -86,8 +86,7 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
RING_FORCE_TO_NONPRIV_ACCESS_RD |
RING_FORCE_TO_NONPRIV_RANGE_4))
},
- {}
-};
+);
/**
* xe_reg_whitelist_process_engine - process table of registers to whitelist
@@ -101,7 +100,7 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
{
struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
- xe_rtp_process_to_sr(&ctx, register_whitelist, &hwe->reg_whitelist);
+ xe_rtp_process_to_sr(&ctx, ®ister_whitelist, &hwe->reg_whitelist);
}
/**
diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
index 86c705d18c0d..867f2e3b2647 100644
--- a/drivers/gpu/drm/xe/xe_rtp.c
+++ b/drivers/gpu/drm/xe/xe_rtp.c
@@ -236,20 +236,19 @@ static void rtp_mark_active(struct xe_device *xe,
* xe_rtp_process_to_sr - Process all rtp @entries, adding the matching ones to
* the save-restore argument.
* @ctx: The context for processing the table, with one of device, gt or hwe
- * @entries: Table with RTP definitions
+ * @table: Table with RTP definitions
* @sr: Save-restore struct where matching rules execute the action. This can be
* viewed as the "coalesced view" of multiple the tables. The bits for each
* register set are expected not to collide with previously added entries
*
- * Walk the table pointed by @entries (with an empty sentinel) and add all
- * entries with matching rules to @sr. If @hwe is not NULL, its mmio_base is
- * used to calculate the right register offset
+ * Walk the table pointed by @table and add all entries with matching rules to
+ * @sr. If @hwe is not NULL, its mmio_base is used to calculate the right
+ * register offset
*/
void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,
- const struct xe_rtp_entry_sr *entries,
+ const struct xe_rtp_table_sr *table,
struct xe_reg_sr *sr)
{
- const struct xe_rtp_entry_sr *entry;
struct xe_hw_engine *hwe = NULL;
struct xe_gt *gt = NULL;
struct xe_device *xe = NULL;
@@ -259,7 +258,10 @@ void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,
if (IS_SRIOV_VF(xe))
return;
- for (entry = entries; entry && entry->name; entry++) {
+ xe_assert(xe, table->entries);
+
+ for (size_t i = 0; i < table->n_entries; i++) {
+ const struct xe_rtp_entry_sr *entry = &table->entries[i];
bool match = false;
if (entry->flags & XE_RTP_ENTRY_FLAG_FOREACH_ENGINE) {
@@ -274,37 +276,40 @@ void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,
}
if (match)
- rtp_mark_active(xe, ctx, entry - entries);
+ rtp_mark_active(xe, ctx, i);
}
}
EXPORT_SYMBOL_IF_KUNIT(xe_rtp_process_to_sr);
/**
- * xe_rtp_process - Process all rtp @entries, without running any action
+ * xe_rtp_process - Process all entries in rtp @table, without running any action
* @ctx: The context for processing the table, with one of device, gt or hwe
- * @entries: Table with RTP definitions
+ * @table: Table with RTP definitions
*
- * Walk the table pointed by @entries (with an empty sentinel), executing the
+ * Walk the table pointed by @table, executing the
* rules. One difference from xe_rtp_process_to_sr(): there is no action
* associated with each entry since this uses struct xe_rtp_entry. Its main use
* is for marking active workarounds via
* xe_rtp_process_ctx_enable_active_tracking().
*/
void xe_rtp_process(struct xe_rtp_process_ctx *ctx,
- const struct xe_rtp_entry *entries)
+ const struct xe_rtp_table *table)
{
- const struct xe_rtp_entry *entry;
struct xe_hw_engine *hwe;
struct xe_gt *gt;
struct xe_device *xe;
rtp_get_context(ctx, &hwe, >, &xe);
- for (entry = entries; entry && entry->rules; entry++) {
+ xe_assert(xe, table->entries);
+
+ for (size_t i = 0; i < table->n_entries; i++) {
+ const struct xe_rtp_entry *entry = &table->entries[i];
+
if (!rule_matches(xe, gt, hwe, entry->rules, entry->n_rules))
continue;
- rtp_mark_active(xe, ctx, entry - entries);
+ rtp_mark_active(xe, ctx, i);
}
}
EXPORT_SYMBOL_IF_KUNIT(xe_rtp_process);
diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
index 827d932b6908..21650bd37e5d 100644
--- a/drivers/gpu/drm/xe/xe_rtp.h
+++ b/drivers/gpu/drm/xe/xe_rtp.h
@@ -420,6 +420,16 @@ struct xe_reg_sr;
XE_RTP_PASTE_FOREACH(ACTION_, COMMA, (__VA_ARGS__)) \
}
+#define XE_RTP_TABLE_SR(...) { \
+ .entries = (const struct xe_rtp_entry_sr[]){__VA_ARGS__}, \
+ .n_entries = ARRAY_SIZE(((const struct xe_rtp_entry_sr[]){__VA_ARGS__})), \
+}
+
+#define XE_RTP_TABLE(...) { \
+ .entries = (const struct xe_rtp_entry[]){__VA_ARGS__}, \
+ .n_entries = ARRAY_SIZE(((const struct xe_rtp_entry[]){__VA_ARGS__})), \
+}
+
#define XE_RTP_PROCESS_CTX_INITIALIZER(arg__) _Generic((arg__), \
struct xe_hw_engine * : (struct xe_rtp_process_ctx){ { (void *)(arg__) }, XE_RTP_PROCESS_TYPE_ENGINE }, \
struct xe_gt * : (struct xe_rtp_process_ctx){ { (void *)(arg__) }, XE_RTP_PROCESS_TYPE_GT })
@@ -429,11 +439,11 @@ void xe_rtp_process_ctx_enable_active_tracking(struct xe_rtp_process_ctx *ctx,
size_t n_entries);
void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,
- const struct xe_rtp_entry_sr *entries,
+ const struct xe_rtp_table_sr *table,
struct xe_reg_sr *sr);
void xe_rtp_process(struct xe_rtp_process_ctx *ctx,
- const struct xe_rtp_entry *entries);
+ const struct xe_rtp_table *table);
/* Match functions to be used with XE_RTP_MATCH_FUNC */
diff --git a/drivers/gpu/drm/xe/xe_rtp_types.h b/drivers/gpu/drm/xe/xe_rtp_types.h
index 1b76b947c706..348786d25aae 100644
--- a/drivers/gpu/drm/xe/xe_rtp_types.h
+++ b/drivers/gpu/drm/xe/xe_rtp_types.h
@@ -109,6 +109,16 @@ struct xe_rtp_entry {
u8 n_rules;
};
+struct xe_rtp_table_sr {
+ const struct xe_rtp_entry_sr *entries;
+ size_t n_entries;
+};
+
+struct xe_rtp_table {
+ const struct xe_rtp_entry *entries;
+ size_t n_entries;
+};
+
enum xe_rtp_process_type {
XE_RTP_PROCESS_TYPE_GT,
XE_RTP_PROCESS_TYPE_ENGINE,
diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index 1fb12da21c9e..07c3687cb310 100644
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -15,7 +15,7 @@
#undef XE_REG_MCR
#define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
-static const struct xe_rtp_entry_sr gt_tunings[] = {
+static const struct xe_rtp_table_sr gt_tunings = XE_RTP_TABLE_SR(
{ XE_RTP_NAME("Tuning: Blend Fill Caching Optimization Disable"),
XE_RTP_RULES(PLATFORM(DG2)),
XE_RTP_ACTIONS(SET(XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS))
@@ -83,20 +83,17 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
XE_RTP_RULES(MEDIA_VERSION(2000)),
XE_RTP_ACTIONS(SET(XE2LPM_SCRATCH3_LBCF, RWFLUSHALLEN))
},
+);
- {}
-};
-
-static const struct xe_rtp_entry_sr engine_tunings[] = {
+static const struct xe_rtp_table_sr engine_tunings = XE_RTP_TABLE_SR(
{ XE_RTP_NAME("Tuning: Set Indirect State Override"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1274),
ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(SAMPLER_MODE, INDIRECT_STATE_BASE_ADDR_OVERRIDE))
},
- {}
-};
+);
-static const struct xe_rtp_entry_sr lrc_tunings[] = {
+static const struct xe_rtp_table_sr lrc_tunings = XE_RTP_TABLE_SR(
/* DG2 */
{ XE_RTP_NAME("Tuning: L3 cache"),
@@ -131,15 +128,13 @@ static const struct xe_rtp_entry_sr lrc_tunings[] = {
XE_RTP_ACTIONS(FIELD_SET(FF_MODE, VS_HIT_MAX_VALUE_MASK,
REG_FIELD_PREP(VS_HIT_MAX_VALUE_MASK, 0x3f)))
},
-
- {}
-};
+);
void xe_tuning_process_gt(struct xe_gt *gt)
{
struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
- xe_rtp_process_to_sr(&ctx, gt_tunings, >->reg_sr);
+ xe_rtp_process_to_sr(&ctx, >_tunings, >->reg_sr);
}
EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_gt);
@@ -147,7 +142,7 @@ void xe_tuning_process_engine(struct xe_hw_engine *hwe)
{
struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
- xe_rtp_process_to_sr(&ctx, engine_tunings, &hwe->reg_sr);
+ xe_rtp_process_to_sr(&ctx, &engine_tunings, &hwe->reg_sr);
}
EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_engine);
@@ -163,5 +158,5 @@ void xe_tuning_process_lrc(struct xe_hw_engine *hwe)
{
struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
- xe_rtp_process_to_sr(&ctx, lrc_tunings, &hwe->reg_lrc);
+ xe_rtp_process_to_sr(&ctx, &lrc_tunings, &hwe->reg_lrc);
}
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index a2af1a44b0e0..0da125a5c808 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -97,7 +97,7 @@
__diag_push();
__diag_ignore_all("-Woverride-init", "Allow field overrides in table");
-static const struct xe_rtp_entry_sr gt_was[] = {
+static const struct xe_rtp_table_sr gt_was = XE_RTP_TABLE_SR(
{ XE_RTP_NAME("14011060649"),
XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255),
ENGINE_CLASS(VIDEO_DECODE),
@@ -278,11 +278,9 @@ static const struct xe_rtp_entry_sr gt_was[] = {
XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), RAMDFTUNIT_CLKGATE_DIS)),
XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
},
+);
- {}
-};
-
-static const struct xe_rtp_entry_sr engine_was[] = {
+static const struct xe_rtp_table_sr engine_was = XE_RTP_TABLE_SR(
{ XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE),
@@ -595,11 +593,9 @@ static const struct xe_rtp_entry_sr engine_was[] = {
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
},
+);
- {}
-};
-
-static const struct xe_rtp_entry_sr lrc_was[] = {
+static const struct xe_rtp_table_sr lrc_was = XE_RTP_TABLE_SR(
{ XE_RTP_NAME("16011163337"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
/* read verification is ignored due to 1608008084. */
@@ -805,16 +801,18 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
DIS_PARTIAL_AUTOSTRIP |
DIS_AUTOSTRIP))
},
+);
- {}
-};
-
-static __maybe_unused const struct xe_rtp_entry oob_was[] = {
+static const struct xe_rtp_entry oob_was_entries[] = {
#include <generated/xe_wa_oob.c>
- {}
};
-static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT);
+static_assert(ARRAY_SIZE(oob_was_entries) == _XE_WA_OOB_COUNT);
+
+static __maybe_unused const struct xe_rtp_table oob_was = {
+ .entries = oob_was_entries,
+ .n_entries = ARRAY_SIZE(oob_was_entries),
+};
__diag_pop();
@@ -830,9 +828,9 @@ void xe_wa_process_oob(struct xe_gt *gt)
struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob,
- ARRAY_SIZE(oob_was));
+ oob_was.n_entries);
gt->wa_active.oob_initialized = true;
- xe_rtp_process(&ctx, oob_was);
+ xe_rtp_process(&ctx, &oob_was);
}
/**
@@ -847,8 +845,8 @@ void xe_wa_process_gt(struct xe_gt *gt)
struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt,
- ARRAY_SIZE(gt_was));
- xe_rtp_process_to_sr(&ctx, gt_was, >->reg_sr);
+ gt_was.n_entries);
+ xe_rtp_process_to_sr(&ctx, >_was, >->reg_sr);
}
EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt);
@@ -865,8 +863,8 @@ void xe_wa_process_engine(struct xe_hw_engine *hwe)
struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine,
- ARRAY_SIZE(engine_was));
- xe_rtp_process_to_sr(&ctx, engine_was, &hwe->reg_sr);
+ engine_was.n_entries);
+ xe_rtp_process_to_sr(&ctx, &engine_was, &hwe->reg_sr);
}
/**
@@ -882,8 +880,8 @@ void xe_wa_process_lrc(struct xe_hw_engine *hwe)
struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc,
- ARRAY_SIZE(lrc_was));
- xe_rtp_process_to_sr(&ctx, lrc_was, &hwe->reg_lrc);
+ lrc_was.n_entries);
+ xe_rtp_process_to_sr(&ctx, &lrc_was, &hwe->reg_lrc);
}
/**
@@ -898,10 +896,10 @@ int xe_wa_init(struct xe_gt *gt)
size_t n_oob, n_lrc, n_engine, n_gt, total;
unsigned long *p;
- n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was));
- n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was));
- n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was));
- n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was));
+ n_gt = BITS_TO_LONGS(gt_was.n_entries);
+ n_engine = BITS_TO_LONGS(engine_was.n_entries);
+ n_lrc = BITS_TO_LONGS(lrc_was.n_entries);
+ n_oob = BITS_TO_LONGS(oob_was.n_entries);
total = n_gt + n_engine + n_lrc + n_oob;
p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
@@ -924,21 +922,21 @@ void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p)
size_t idx;
drm_printf(p, "GT Workarounds\n");
- for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was))
- drm_printf_indent(p, 1, "%s\n", gt_was[idx].name);
+ for_each_set_bit(idx, gt->wa_active.gt, gt_was.n_entries)
+ drm_printf_indent(p, 1, "%s\n", gt_was.entries[idx].name);
drm_printf(p, "\nEngine Workarounds\n");
- for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was))
- drm_printf_indent(p, 1, "%s\n", engine_was[idx].name);
+ for_each_set_bit(idx, gt->wa_active.engine, engine_was.n_entries)
+ drm_printf_indent(p, 1, "%s\n", engine_was.entries[idx].name);
drm_printf(p, "\nLRC Workarounds\n");
- for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was))
- drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name);
+ for_each_set_bit(idx, gt->wa_active.lrc, lrc_was.n_entries)
+ drm_printf_indent(p, 1, "%s\n", lrc_was.entries[idx].name);
drm_printf(p, "\nOOB Workarounds\n");
- for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was))
- if (oob_was[idx].name)
- drm_printf_indent(p, 1, "%s\n", oob_was[idx].name);
+ for_each_set_bit(idx, gt->wa_active.oob, oob_was.n_entries)
+ if (oob_was.entries[idx].name)
+ drm_printf_indent(p, 1, "%s\n", oob_was.entries[idx].name);
}
/*
--
2.53.0
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