FAILED: patch "[PATCH] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX" failed to apply to 6.18-stable tree

FAILED: patch "[PATCH] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX" failed to apply to 6.18-stable tree

[gregkh]

The patch below does not apply to the 6.18-stable tree.
If someone wants it applied there, or to any other stable or longterm
tree, then please email the backport, including the original git commit
id to <stable@vger.kernel.org>.

To reproduce the conflict and resubmit, you may use the following commands:

git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.18.y
git checkout FETCH_HEAD
git cherry-pick -x f342810a141f8a7e8b3786a6e4b6c0695a078a74
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<stable@vger.kernel.org>' --in-reply-to '2026082047-manned-outer-503f@gregkh' --subject-prefix 'PATCH 6.18.y' 'HEAD^..'

Possible dependencies:



thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From f342810a141f8a7e8b3786a6e4b6c0695a078a74 Mon Sep 17 00:00:00 2001
From: Jia Yao <jia.yao@intel.com>
Date: Tue, 4 Aug 2026 16:50:56 +0000
Subject: [PATCH] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

On iGPU, the UM queue BO is allocated in system memory. On dGFX, the BO
was previously created in system memory and later reallocated in
xe_guc_realloc_post_hwconfig().  Allocate the UM queue BO directly in
VRAM on dGFX, where it is ultimately required.

Fixes: 9c57bc08652a ("drm/xe/lnl: Drop force_probe requirement")
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: <stable@vger.kernel.org> # v6.12+
Signed-off-by: Jia Yao <jia.yao@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patch.msgid.link/20260804165057.129529-3-jia.yao@intel.com
(cherry picked from commit ace076ef0a854ab5940bacc539bf66afd61d118c)
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>

diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 21cf3edef922..4023700ff2a9 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -714,12 +714,6 @@ static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc)
 	if (ret)
 		return ret;
 
-	if (guc->ads.um_queue_bo) {
-		ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.um_queue_bo);
-		if (ret)
-			return ret;
-	}
-
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index a411d6440ba6..b6d07f2e73bf 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -393,15 +393,17 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
 		/*
 		 * Allocate a separate BO for the HW fault ring (UM queues).
 		 *
-		 * Round the size up to the next power of two so that
+		 * Round the size up to the next power of two so that on iGPU
 		 * (system memory, no IOMMU) the TTM pool issues a single
 		 * alloc_pages(order=N) call, maximising the chance of getting
 		 * a physically contiguous block.  GuC requires contiguous DPA.
 		 */
-		size_t um_size = roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
+		size_t um_size = IS_DGFX(xe) ?
+				 GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX :
+				 roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
 						    GUC_UM_HW_QUEUE_MAX);
 
-		u32 um_flags = XE_BO_FLAG_SYSTEM |
+		u32 um_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) |
 			       XE_BO_FLAG_GGTT |
 			       XE_BO_FLAG_GGTT_INVALIDATE |
 			       XE_BO_FLAG_PINNED_NORESTORE;

[PATCH 6.18.y] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX

[Jia Yao]

On iGPU, the UM queue BO is allocated in system memory. On dGFX, the BO
was previously created in system memory and later reallocated in
xe_guc_realloc_post_hwconfig().  Allocate the UM queue BO directly in
VRAM on dGFX, where it is ultimately required.

Fixes: 9c57bc08652a ("drm/xe/lnl: Drop force_probe requirement")
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: <stable@vger.kernel.org> # v6.12+
Signed-off-by: Jia Yao <jia.yao@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patch.msgid.link/20260804165057.129529-3-jia.yao@intel.com
(cherry picked from commit ace076ef0a854ab5940bacc539bf66afd61d118c)
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
(cherry picked from commit f342810a141f8a7e8b3786a6e4b6c0695a078a74)
---
 drivers/gpu/drm/xe/xe_guc.c     | 6 ------
 drivers/gpu/drm/xe/xe_guc_ads.c | 8 +++++---
 2 files changed, 5 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index cc5741f751b9..ae0c88da422b 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -700,12 +700,6 @@ static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc)
 	if (ret)
 		return ret;
 
-	if (guc->ads.um_queue_bo) {
-		ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.um_queue_bo);
-		if (ret)
-			return ret;
-	}
-
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 806c2618a7cd..4c3e21b5e60e 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -392,15 +392,17 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
 		/*
 		 * Allocate a separate BO for the HW fault ring (UM queues).
 		 *
-		 * Round the size up to the next power of two so that
+		 * Round the size up to the next power of two so that on iGPU
 		 * (system memory, no IOMMU) the TTM pool issues a single
 		 * alloc_pages(order=N) call, maximising the chance of getting
 		 * a physically contiguous block.  GuC requires contiguous DPA.
 		 */
-		size_t um_size = roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
+		size_t um_size = IS_DGFX(xe) ?
+				 GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX :
+				 roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
 						    GUC_UM_HW_QUEUE_MAX);
 
-		u32 um_flags = XE_BO_FLAG_SYSTEM |
+		u32 um_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) |
 			       XE_BO_FLAG_GGTT |
 			       XE_BO_FLAG_GGTT_INVALIDATE |
 			       XE_BO_FLAG_PINNED_NORESTORE;
-- 
2.43.0

Re: [PATCH 6.18.y] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX

[Greg KH]

On Thu, Aug 20, 2026 at 04:11:28PM +0000, Jia Yao wrote:
> On iGPU, the UM queue BO is allocated in system memory. On dGFX, the BO
> was previously created in system memory and later reallocated in
> xe_guc_realloc_post_hwconfig().  Allocate the UM queue BO directly in
> VRAM on dGFX, where it is ultimately required.
> 
> Fixes: 9c57bc08652a ("drm/xe/lnl: Drop force_probe requirement")
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: <stable@vger.kernel.org> # v6.12+
> Signed-off-by: Jia Yao <jia.yao@intel.com>
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Link: https://patch.msgid.link/20260804165057.129529-3-jia.yao@intel.com
> (cherry picked from commit ace076ef0a854ab5940bacc539bf66afd61d118c)
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> (cherry picked from commit f342810a141f8a7e8b3786a6e4b6c0695a078a74)
> ---
>  drivers/gpu/drm/xe/xe_guc.c     | 6 ------
>  drivers/gpu/drm/xe/xe_guc_ads.c | 8 +++++---
>  2 files changed, 5 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index cc5741f751b9..ae0c88da422b 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -700,12 +700,6 @@ static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc)
>  	if (ret)
>  		return ret;
>  
> -	if (guc->ads.um_queue_bo) {
> -		ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.um_queue_bo);
> -		if (ret)
> -			return ret;
> -	}
> -
>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index 806c2618a7cd..4c3e21b5e60e 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -392,15 +392,17 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
>  		/*
>  		 * Allocate a separate BO for the HW fault ring (UM queues).
>  		 *
> -		 * Round the size up to the next power of two so that
> +		 * Round the size up to the next power of two so that on iGPU
>  		 * (system memory, no IOMMU) the TTM pool issues a single
>  		 * alloc_pages(order=N) call, maximising the chance of getting
>  		 * a physically contiguous block.  GuC requires contiguous DPA.
>  		 */
> -		size_t um_size = roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
> +		size_t um_size = IS_DGFX(xe) ?
> +				 GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX :
> +				 roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
>  						    GUC_UM_HW_QUEUE_MAX);
>  
> -		u32 um_flags = XE_BO_FLAG_SYSTEM |
> +		u32 um_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) |
>  			       XE_BO_FLAG_GGTT |
>  			       XE_BO_FLAG_GGTT_INVALIDATE |
>  			       XE_BO_FLAG_PINNED_NORESTORE;
> -- 
> 2.43.0
> 
> 

Does not apply at all, are you sure you made this properly?

thanks,

greg k-h

Re: [PATCH 6.18.y] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX

[Greg KH]

On Mon, Aug 24, 2026 at 08:09:23AM +0200, Greg KH wrote:
> On Thu, Aug 20, 2026 at 04:11:28PM +0000, Jia Yao wrote:
> > On iGPU, the UM queue BO is allocated in system memory. On dGFX, the BO
> > was previously created in system memory and later reallocated in
> > xe_guc_realloc_post_hwconfig().  Allocate the UM queue BO directly in
> > VRAM on dGFX, where it is ultimately required.
> > 
> > Fixes: 9c57bc08652a ("drm/xe/lnl: Drop force_probe requirement")
> > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > Cc: Matthew Auld <matthew.auld@intel.com>
> > Cc: <stable@vger.kernel.org> # v6.12+
> > Signed-off-by: Jia Yao <jia.yao@intel.com>
> > Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> > Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> > Link: https://patch.msgid.link/20260804165057.129529-3-jia.yao@intel.com
> > (cherry picked from commit ace076ef0a854ab5940bacc539bf66afd61d118c)
> > Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> > (cherry picked from commit f342810a141f8a7e8b3786a6e4b6c0695a078a74)
> > ---
> >  drivers/gpu/drm/xe/xe_guc.c     | 6 ------
> >  drivers/gpu/drm/xe/xe_guc_ads.c | 8 +++++---
> >  2 files changed, 5 insertions(+), 9 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> > index cc5741f751b9..ae0c88da422b 100644
> > --- a/drivers/gpu/drm/xe/xe_guc.c
> > +++ b/drivers/gpu/drm/xe/xe_guc.c
> > @@ -700,12 +700,6 @@ static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc)
> >  	if (ret)
> >  		return ret;
> >  
> > -	if (guc->ads.um_queue_bo) {
> > -		ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.um_queue_bo);
> > -		if (ret)
> > -			return ret;
> > -	}
> > -
> >  	return 0;
> >  }
> >  
> > diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> > index 806c2618a7cd..4c3e21b5e60e 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> > +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> > @@ -392,15 +392,17 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
> >  		/*
> >  		 * Allocate a separate BO for the HW fault ring (UM queues).
> >  		 *
> > -		 * Round the size up to the next power of two so that
> > +		 * Round the size up to the next power of two so that on iGPU
> >  		 * (system memory, no IOMMU) the TTM pool issues a single
> >  		 * alloc_pages(order=N) call, maximising the chance of getting
> >  		 * a physically contiguous block.  GuC requires contiguous DPA.
> >  		 */
> > -		size_t um_size = roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
> > +		size_t um_size = IS_DGFX(xe) ?
> > +				 GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX :
> > +				 roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
> >  						    GUC_UM_HW_QUEUE_MAX);
> >  
> > -		u32 um_flags = XE_BO_FLAG_SYSTEM |
> > +		u32 um_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) |
> >  			       XE_BO_FLAG_GGTT |
> >  			       XE_BO_FLAG_GGTT_INVALIDATE |
> >  			       XE_BO_FLAG_PINNED_NORESTORE;
> > -- 
> > 2.43.0
> > 
> > 
> 
> Does not apply at all, are you sure you made this properly?
> 
> thanks,
> 
> greg k-h

Ah, it needed to be applied after a different one?  Can you send these 3
patches as a patch series, as that will tell us what order to apply them
in.  Same for the 6.12 versions.

thanks,

greg k-h

Re: [PATCH 6.18.y] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX

[Sasha Levin]

On Mon, Aug 24, 2026 at 08:10:49AM +0200, Greg KH wrote:
> Ah, it needed to be applied after a different one?  Can you send these 3
> patches as a patch series, as that will tell us what order to apply them
> in.  Same for the 6.12 versions.

Jia Yao, on top of the series formatting there is a second problem: the
set as sent does not build on either branch.

Patch 1 calls xe_guc_using_main_gamctrl_queues(), which has no definition
on 6.18 or 6.12 - it only exists on 7.1. On 6.12 the same patch also uses
XE_BO_FLAG_PINNED_NORESTORE, which is undefined there.

-- 
Thanks,
Sasha