[PATCH 0/6] drm/i915/ptl+: Fix eDP support on TypeC PHYs

[PATCH 0/6] drm/i915/ptl+: Fix eDP support on TypeC PHYs

[Imre Deak]

This patchset fixes the PHY type and TypeC port mapping for eDP on PTL+
platforms where port B's DDI is connected to a C20 TypeC PHY.

Cc: stable@vger.kernel.org # 6.14+

Imre Deak (6):
  drm/i915/dp_aux: Take the TypeC port lock after the PPS lock
  drm/i915/pps: Hold a TypeC link reference for PPS VDD
  drm/i915/pps: Reset PPS state after TypeC port init on resume
  drm/i915/ptl+: Add TypeC HPD pin selection for port B
  drm/i915/mtl+: Use PHY type to identify TypeC ports in PLL ID lookup
  drm/i915/ptl+: Fix TypeC detection for eDP on port B

 drivers/gpu/drm/i915/display/intel_ddi.c      |  6 ++-
 drivers/gpu/drm/i915/display/intel_display.c  | 11 ++++++
 drivers/gpu/drm/i915/display/intel_dp_aux.c   | 39 +++++++++----------
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  2 +-
 drivers/gpu/drm/i915/display/intel_pps.c      | 14 +++++++
 drivers/gpu/drm/i915/display/intel_tc.c       |  9 ++++-
 6 files changed, 56 insertions(+), 25 deletions(-)

-- 
2.49.1

[PATCH 1/6] drm/i915/dp_aux: Take the TypeC port lock after the PPS lock

[Imre Deak]

An upcoming change will need to acquire a TypeC port link reference
along with an AUX power domain reference when enabling PPS VDD for the
port during an AUX transfer. Acquiring the link reference requires
holding the TypeC port lock.

To allow the PPS VDD code to take this lock itself, acquire the TypeC
port lock in the AUX transfer function only after locking PPS and
enabling VDD.

CC: stable@vger.kernel.org # 6.14+
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_aux.c | 39 ++++++++++-----------
 1 file changed, 19 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 394326d17e0da..63bd72e537ec3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -269,22 +269,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
 	for (i = 0; i < ARRAY_SIZE(ch_data); i++)
 		ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
 
-	intel_digital_port_lock(encoder);
-	/*
-	 * Abort transfers on a disconnected port as required by
-	 * DP 1.4a link CTS 4.2.1.5, also avoiding the long AUX
-	 * timeouts that would otherwise happen.
-	 */
-	if (!intel_dp_is_edp(intel_dp) &&
-	    !intel_digital_port_connected_locked(&dig_port->base)) {
-		ret = -ENXIO;
-		goto out_unlock;
-	}
-
-	aux_domain = intel_aux_power_domain(dig_port);
-
-	aux_wakeref = intel_display_power_get(display, aux_domain);
-
 	/*
 	 * The PPS state needs to be locked for:
 	 * - eDP on all platforms, since AUX transfers on eDP need VDD power
@@ -307,6 +291,21 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
 	 */
 	vdd = intel_pps_vdd_on_unlocked(intel_dp);
 
+	intel_digital_port_lock(encoder);
+	/*
+	 * Abort transfers on a disconnected port as required by
+	 * DP 1.4a link CTS 4.2.1.5, also avoiding the long AUX
+	 * timeouts that would otherwise happen.
+	 */
+	if (!intel_dp_is_edp(intel_dp) &&
+	    !intel_digital_port_connected_locked(&dig_port->base)) {
+		ret = -ENXIO;
+		goto out_unlock;
+	}
+
+	aux_domain = intel_aux_power_domain(dig_port);
+	aux_wakeref = intel_display_power_get(display, aux_domain);
+
 	/*
 	 * dp aux is extremely sensitive to irq latency, hence request the
 	 * lowest possible wakeup latency and so prevent the cpu from going into
@@ -450,16 +449,16 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
 out:
 	cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
 
+	intel_display_power_put_async(display, aux_domain, aux_wakeref);
+out_unlock:
+	intel_digital_port_unlock(encoder);
+
 	if (vdd)
 		intel_pps_vdd_off_unlocked(intel_dp, false);
 
 	if (pps_wakeref)
 		intel_pps_unlock(intel_dp, pps_wakeref);
 
-	intel_display_power_put_async(display, aux_domain, aux_wakeref);
-out_unlock:
-	intel_digital_port_unlock(encoder);
-
 	return ret;
 }
 
-- 
2.49.1

[PATCH 2/6] drm/i915/pps: Hold a TypeC link reference for PPS VDD

[Imre Deak]

On TypeC ports, the AUX power domain reference held for PPS VDD requires
the TypeC mode to remain unchanged. Hold a TypeC link reference for the
lifetime of the PPS VDD power reference.

This prepares for an upcoming change that will use the TypeC port type
for eDP on TypeC ports. Allow the additional PPS link reference when
sanitizing the TypeC mode.

CC: stable@vger.kernel.org # 6.14+
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_pps.c | 14 ++++++++++++++
 drivers/gpu/drm/i915/display/intel_tc.c  |  9 +++++++--
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index d4c98b150fa2b..8f1bfe4340971 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -23,6 +23,7 @@
 #include "intel_pps.h"
 #include "intel_pps_regs.h"
 #include "intel_quirks.h"
+#include "intel_tc.h"
 
 static void vlv_steal_power_sequencer(struct intel_display *display,
 				      enum pipe pipe);
@@ -758,6 +759,9 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
 	if (edp_have_panel_vdd(intel_dp))
 		return need_to_disable;
 
+	if (intel_encoder_is_tc(&dig_port->base))
+		intel_tc_port_get_link(dig_port, 1);
+
 	drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);
 	intel_dp->pps.vdd_wakeref = intel_display_power_get(display,
 							    intel_aux_power_domain(dig_port));
@@ -864,6 +868,9 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
 	intel_display_power_put(display,
 				intel_aux_power_domain(dig_port),
 				fetch_and_zero(&intel_dp->pps.vdd_wakeref));
+
+	if (intel_encoder_is_tc(&dig_port->base))
+		intel_tc_port_put_link(dig_port);
 }
 
 void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
@@ -1066,6 +1073,9 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp)
 	intel_display_power_put(display,
 				intel_aux_power_domain(dig_port),
 				fetch_and_zero(&intel_dp->pps.vdd_wakeref));
+
+	if (intel_encoder_is_tc(&dig_port->base))
+		intel_tc_port_put_link(dig_port);
 }
 
 void intel_pps_off(struct intel_dp *intel_dp)
@@ -1334,6 +1344,10 @@ static void pps_vdd_init(struct intel_dp *intel_dp)
 		    "[ENCODER:%d:%s] %s VDD left on by BIOS, adjusting state tracking\n",
 		    dig_port->base.base.base.id, dig_port->base.base.name,
 		    pps_name(intel_dp));
+
+	if (intel_encoder_is_tc(&dig_port->base))
+		intel_tc_port_get_link(dig_port, 1);
+
 	drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);
 	intel_dp->pps.vdd_wakeref = intel_display_power_get(display,
 							    intel_aux_power_domain(dig_port));
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index f2d86b29c4154..f878494bcb388 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -1669,7 +1669,7 @@ void intel_tc_port_sanitize_mode(struct intel_digital_port *dig_port,
 
 	mutex_lock(&tc->lock);
 
-	drm_WARN_ON(display->drm, tc->link_refcount != 1);
+	drm_WARN_ON(display->drm, tc->link_refcount < 1);
 	if (!tc_port_has_active_streams(tc, crtc_state)) {
 		/*
 		 * TBT-alt is the default mode in any case the PHY ownership is not
@@ -1683,7 +1683,12 @@ void intel_tc_port_sanitize_mode(struct intel_digital_port *dig_port,
 				    "Port %s: PHY left in %s mode on disabled port, disconnecting it\n",
 				    tc->port_name,
 				    tc_port_mode_name(tc->init_mode));
-		tc_phy_disconnect(tc);
+		/*
+		 * A link reference taken during a preceding (eDP) connector initialization will be
+		 * dropped later, also disconnecting the PHY.
+		 */
+		if (tc->link_refcount == 1)
+			tc_phy_disconnect(tc);
 		__intel_tc_port_put_link(tc);
 	}
 
-- 
2.49.1

[PATCH 3/6] drm/i915/pps: Reset PPS state after TypeC port init on resume

[Imre Deak]

Resetting the PPS state involves acquiring an AUX power domain
reference. On TypeC ports, the AUX power domain depends on the TypeC
mode of the port using the PPS.

An upcoming change will set the port/PHY type to TypeC for eDP ports on
PTL+ platforms with an eDP DDI mapped to a TypeC PHY. Prepare for this by
resetting the PPS state on resume only after initializing the port's
TypeC mode.

CC: stable@vger.kernel.org # 6.14+
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a46ab5d3d70fc..dda95709c7c73 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4723,10 +4723,10 @@ static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
 	intel_dp->reset_link_params = true;
 	intel_dp_invalidate_source_oui(intel_dp);
 
-	intel_pps_encoder_reset(intel_dp);
-
 	if (intel_encoder_is_tc(&dig_port->base))
 		intel_tc_port_init_mode(dig_port);
+
+	intel_pps_encoder_reset(intel_dp);
 }
 
 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder)
-- 
2.49.1

[PATCH 4/6] drm/i915/ptl+: Add TypeC HPD pin selection for port B

[Imre Deak]

Handle the TypeC PHY on port B case while mapping the port to an HPD
pin. This prepares for an upcoming change that will set port B's PHY
type to TypeC on PTL+ platforms with an eDP panel connected to a TypeC
PHY.

Keep the existing port >= PORT_TC1 case and its HPD pin mapping for
DG2, where PORT_TC1 has a non-TypeC PHY.

CC: stable@vger.kernel.org # 6.14+
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index dda95709c7c73..5950246e45a06 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5053,6 +5053,8 @@ static enum hpd_pin xelpd_hpd_pin(struct intel_display *display, enum port port)
 		return HPD_PORT_D + port - PORT_D_XELPD;
 	else if (port >= PORT_TC1)
 		return HPD_PORT_TC1 + port - PORT_TC1;
+	else if (intel_phy_is_tc(display, intel_port_to_phy(display, port)))
+		return HPD_PORT_TC1 + intel_port_to_tc(display, port) - TC_PORT_1;
 	else
 		return HPD_PORT_A + port - PORT_A;
 }
-- 
2.49.1

[PATCH 5/6] drm/i915/mtl+: Use PHY type to identify TypeC ports in PLL ID lookup

[Imre Deak]

Use the PHY type to identify TypeC ports in the PLL ID lookup function.
This ensures that port B takes the TypeC path when an upcoming change
sets its PHY type to TypeC on PTL+ platforms with an eDP panel connected
to a TypeC PHY.

CC: stable@vger.kernel.org # 6.14+
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index bfd6f0a197253..563db12cf2ef3 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -207,7 +207,7 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
 
 enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display, enum port port)
 {
-	if (port >= PORT_TC1)
+	if (intel_phy_is_tc(display, intel_port_to_phy(display, port)))
 		return icl_tc_port_to_pll_id(intel_port_to_tc(display, port));
 
 	switch (port) {
-- 
2.49.1

[PATCH 6/6] drm/i915/ptl+: Fix TypeC detection for eDP on port B

[Imre Deak]

On PTL+ platforms with eDP on TypeC, port B's DDI is connected to a C20
TypeC PHY. Identify PHY B as TypeC and map port B to TC_PORT_1 when eDP
TypeC support is enabled.

Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/9196
CC: stable@vger.kernel.org # 6.14+
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5e40487e9ab06..10af12846e730 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1904,6 +1904,11 @@ bool intel_phy_is_combo(struct intel_display *display, enum phy phy)
 		return false;
 }
 
+static bool intel_phy_is_edp_on_tc(struct intel_display *display, enum phy phy)
+{
+	return DISPLAY_RUNTIME_INFO(display)->edp_typec_support && phy == PHY_B;
+}
+
 /*
  * This function returns true if the DDI port respective to the PHY enumeration
  * is a Type-C capable port.
@@ -1924,6 +1929,9 @@ bool intel_phy_is_tc(struct intel_display *display, enum phy phy)
 	if (display->platform.dgfx)
 		return false;
 
+	if (intel_phy_is_edp_on_tc(display, phy))
+		return true;
+
 	if (DISPLAY_VER(display) >= 13)
 		return phy >= PHY_F && phy <= PHY_I;
 	else if (display->platform.tigerlake)
@@ -1974,6 +1982,9 @@ enum phy intel_port_to_phy(struct intel_display *display, enum port port)
  */
 enum tc_port intel_port_to_tc(struct intel_display *display, enum port port)
 {
+	if (intel_phy_is_edp_on_tc(display, intel_port_to_phy(display, port)))
+		return TC_PORT_1;
+
 	if (DISPLAY_VER(display) >= 12)
 		return TC_PORT_1 + port - PORT_TC1;
 	else
-- 
2.49.1

[PATCH v2 5/6] drm/i915/mtl+: Use PHY type to identify TypeC ports in PLL ID lookup

[Imre Deak]

Use the PHY type to identify TypeC ports in the PLL ID lookup function.
This ensures that port B takes the TypeC path when an upcoming change
sets its PHY type to TypeC on PTL+ platforms with an eDP panel connected
to a TypeC PHY.

Keep the existing port >= PORT_TC1 case for BMG, where PORT_TC1 has a
a TypeC DDI (and so uses the TypeC DDI register addresses, has a C20 PHY
and the corresponding TC port -> PLL ID mapping), but this C20 PHY is
not a TypeC PHY (i.e. it's not controlled by the TypeC Subsystem and so
the driver doesn't need to run the TypeC PHY connect/disconnect,
power-on/power-off sequences for the PHY).

v2: Keep handling the BMG TypeC DDI but non-TypeC PHY cases. (Sashiko)

CC: stable@vger.kernel.org # 6.14+
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index bfd6f0a197253..ac9d3f1102747 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -207,7 +207,8 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
 
 enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display, enum port port)
 {
-	if (port >= PORT_TC1)
+	if (port >= PORT_TC1 ||
+	    intel_phy_is_tc(display, intel_port_to_phy(display, port)))
 		return icl_tc_port_to_pll_id(intel_port_to_tc(display, port));
 
 	switch (port) {
-- 
2.49.1

RE: [PATCH 1/6] drm/i915/dp_aux: Take the TypeC port lock after the PPS lock

[Kahola, Mika]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Imre Deak
> Sent: Thursday, 29 October 2026 13.30
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: stable@vger.kernel.org
> Subject: [PATCH 1/6] drm/i915/dp_aux: Take the TypeC port lock after the PPS lock
> 
> An upcoming change will need to acquire a TypeC port link reference
> along with an AUX power domain reference when enabling PPS VDD for the
> port during an AUX transfer. Acquiring the link reference requires
> holding the TypeC port lock.
> 
> To allow the PPS VDD code to take this lock itself, acquire the TypeC
> port lock in the AUX transfer function only after locking PPS and
> enabling VDD.
> 
> CC: stable@vger.kernel.org # 6.14+
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp_aux.c | 39 ++++++++++-----------
>  1 file changed, 19 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> index 394326d17e0da..63bd72e537ec3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> @@ -269,22 +269,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>  	for (i = 0; i < ARRAY_SIZE(ch_data); i++)
>  		ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
> 
> -	intel_digital_port_lock(encoder);
> -	/*
> -	 * Abort transfers on a disconnected port as required by
> -	 * DP 1.4a link CTS 4.2.1.5, also avoiding the long AUX
> -	 * timeouts that would otherwise happen.
> -	 */
> -	if (!intel_dp_is_edp(intel_dp) &&
> -	    !intel_digital_port_connected_locked(&dig_port->base)) {
> -		ret = -ENXIO;
> -		goto out_unlock;
> -	}
> -
> -	aux_domain = intel_aux_power_domain(dig_port);
> -
> -	aux_wakeref = intel_display_power_get(display, aux_domain);
> -
>  	/*
>  	 * The PPS state needs to be locked for:
>  	 * - eDP on all platforms, since AUX transfers on eDP need VDD power
> @@ -307,6 +291,21 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>  	 */
>  	vdd = intel_pps_vdd_on_unlocked(intel_dp);
> 
> +	intel_digital_port_lock(encoder);
> +	/*
> +	 * Abort transfers on a disconnected port as required by
> +	 * DP 1.4a link CTS 4.2.1.5, also avoiding the long AUX
> +	 * timeouts that would otherwise happen.
> +	 */
> +	if (!intel_dp_is_edp(intel_dp) &&
> +	    !intel_digital_port_connected_locked(&dig_port->base)) {
> +		ret = -ENXIO;
> +		goto out_unlock;
> +	}
> +
> +	aux_domain = intel_aux_power_domain(dig_port);
> +	aux_wakeref = intel_display_power_get(display, aux_domain);
> +
>  	/*
>  	 * dp aux is extremely sensitive to irq latency, hence request the
>  	 * lowest possible wakeup latency and so prevent the cpu from going into
> @@ -450,16 +449,16 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>  out:
>  	cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
> 
> +	intel_display_power_put_async(display, aux_domain, aux_wakeref);
> +out_unlock:
> +	intel_digital_port_unlock(encoder);
> +
>  	if (vdd)
>  		intel_pps_vdd_off_unlocked(intel_dp, false);
> 
>  	if (pps_wakeref)
>  		intel_pps_unlock(intel_dp, pps_wakeref);
> 
> -	intel_display_power_put_async(display, aux_domain, aux_wakeref);
> -out_unlock:
> -	intel_digital_port_unlock(encoder);
> -
>  	return ret;
>  }
> 
> --
> 2.49.1

RE: [PATCH 2/6] drm/i915/pps: Hold a TypeC link reference for PPS VDD

[Kahola, Mika]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Imre Deak
> Sent: Thursday, 29 October 2026 13.30
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: stable@vger.kernel.org
> Subject: [PATCH 2/6] drm/i915/pps: Hold a TypeC link reference for PPS VDD
> 
> On TypeC ports, the AUX power domain reference held for PPS VDD requires
> the TypeC mode to remain unchanged. Hold a TypeC link reference for the
> lifetime of the PPS VDD power reference.
> 
> This prepares for an upcoming change that will use the TypeC port type
> for eDP on TypeC ports. Allow the additional PPS link reference when
> sanitizing the TypeC mode.
> 
> CC: stable@vger.kernel.org # 6.14+
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_pps.c | 14 ++++++++++++++
>  drivers/gpu/drm/i915/display/intel_tc.c  |  9 +++++++--
>  2 files changed, 21 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index d4c98b150fa2b..8f1bfe4340971 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -23,6 +23,7 @@
>  #include "intel_pps.h"
>  #include "intel_pps_regs.h"
>  #include "intel_quirks.h"
> +#include "intel_tc.h"
> 
>  static void vlv_steal_power_sequencer(struct intel_display *display,
>  				      enum pipe pipe);
> @@ -758,6 +759,9 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
>  	if (edp_have_panel_vdd(intel_dp))
>  		return need_to_disable;
> 
> +	if (intel_encoder_is_tc(&dig_port->base))
> +		intel_tc_port_get_link(dig_port, 1);
> +
>  	drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);
>  	intel_dp->pps.vdd_wakeref = intel_display_power_get(display,
>  							    intel_aux_power_domain(dig_port));
> @@ -864,6 +868,9 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
>  	intel_display_power_put(display,
>  				intel_aux_power_domain(dig_port),
>  				fetch_and_zero(&intel_dp->pps.vdd_wakeref));
> +
> +	if (intel_encoder_is_tc(&dig_port->base))
> +		intel_tc_port_put_link(dig_port);
>  }
> 
>  void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
> @@ -1066,6 +1073,9 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp)
>  	intel_display_power_put(display,
>  				intel_aux_power_domain(dig_port),
>  				fetch_and_zero(&intel_dp->pps.vdd_wakeref));
> +
> +	if (intel_encoder_is_tc(&dig_port->base))
> +		intel_tc_port_put_link(dig_port);
>  }
> 
>  void intel_pps_off(struct intel_dp *intel_dp)
> @@ -1334,6 +1344,10 @@ static void pps_vdd_init(struct intel_dp *intel_dp)
>  		    "[ENCODER:%d:%s] %s VDD left on by BIOS, adjusting state tracking\n",
>  		    dig_port->base.base.base.id, dig_port->base.base.name,
>  		    pps_name(intel_dp));
> +
> +	if (intel_encoder_is_tc(&dig_port->base))
> +		intel_tc_port_get_link(dig_port, 1);
> +
>  	drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);
>  	intel_dp->pps.vdd_wakeref = intel_display_power_get(display,
>  							    intel_aux_power_domain(dig_port));
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index f2d86b29c4154..f878494bcb388 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -1669,7 +1669,7 @@ void intel_tc_port_sanitize_mode(struct intel_digital_port *dig_port,
> 
>  	mutex_lock(&tc->lock);
> 
> -	drm_WARN_ON(display->drm, tc->link_refcount != 1);
> +	drm_WARN_ON(display->drm, tc->link_refcount < 1);
>  	if (!tc_port_has_active_streams(tc, crtc_state)) {
>  		/*
>  		 * TBT-alt is the default mode in any case the PHY ownership is not
> @@ -1683,7 +1683,12 @@ void intel_tc_port_sanitize_mode(struct intel_digital_port *dig_port,
>  				    "Port %s: PHY left in %s mode on disabled port, disconnecting it\n",
>  				    tc->port_name,
>  				    tc_port_mode_name(tc->init_mode));
> -		tc_phy_disconnect(tc);
> +		/*
> +		 * A link reference taken during a preceding (eDP) connector initialization will be
> +		 * dropped later, also disconnecting the PHY.
> +		 */
> +		if (tc->link_refcount == 1)
> +			tc_phy_disconnect(tc);
>  		__intel_tc_port_put_link(tc);
>  	}
> 
> --
> 2.49.1

RE: [PATCH 3/6] drm/i915/pps: Reset PPS state after TypeC port init on resume

[Kahola, Mika]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Imre Deak
> Sent: Thursday, 29 October 2026 13.30
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: stable@vger.kernel.org
> Subject: [PATCH 3/6] drm/i915/pps: Reset PPS state after TypeC port init on resume
> 
> Resetting the PPS state involves acquiring an AUX power domain
> reference. On TypeC ports, the AUX power domain depends on the TypeC
> mode of the port using the PPS.
> 
> An upcoming change will set the port/PHY type to TypeC for eDP ports on
> PTL+ platforms with an eDP DDI mapped to a TypeC PHY. Prepare for this by
> resetting the PPS state on resume only after initializing the port's
> TypeC mode.
> 
> CC: stable@vger.kernel.org # 6.14+
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a46ab5d3d70fc..dda95709c7c73 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4723,10 +4723,10 @@ static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
>  	intel_dp->reset_link_params = true;
>  	intel_dp_invalidate_source_oui(intel_dp);
> 
> -	intel_pps_encoder_reset(intel_dp);
> -
>  	if (intel_encoder_is_tc(&dig_port->base))
>  		intel_tc_port_init_mode(dig_port);
> +
> +	intel_pps_encoder_reset(intel_dp);
>  }
> 
>  static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder)
> --
> 2.49.1

RE: [PATCH 4/6] drm/i915/ptl+: Add TypeC HPD pin selection for port B

[Kahola, Mika]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Imre Deak
> Sent: Thursday, 29 October 2026 13.30
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: stable@vger.kernel.org
> Subject: [PATCH 4/6] drm/i915/ptl+: Add TypeC HPD pin selection for port B
> 
> Handle the TypeC PHY on port B case while mapping the port to an HPD
> pin. This prepares for an upcoming change that will set port B's PHY
> type to TypeC on PTL+ platforms with an eDP panel connected to a TypeC
> PHY.
> 
> Keep the existing port >= PORT_TC1 case and its HPD pin mapping for
> DG2, where PORT_TC1 has a non-TypeC PHY.
> 
> CC: stable@vger.kernel.org # 6.14+
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index dda95709c7c73..5950246e45a06 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -5053,6 +5053,8 @@ static enum hpd_pin xelpd_hpd_pin(struct intel_display *display, enum port port)
>  		return HPD_PORT_D + port - PORT_D_XELPD;
>  	else if (port >= PORT_TC1)
>  		return HPD_PORT_TC1 + port - PORT_TC1;
> +	else if (intel_phy_is_tc(display, intel_port_to_phy(display, port)))
> +		return HPD_PORT_TC1 + intel_port_to_tc(display, port) - TC_PORT_1;
>  	else
>  		return HPD_PORT_A + port - PORT_A;
>  }
> --
> 2.49.1

RE: [PATCH v2 5/6] drm/i915/mtl+: Use PHY type to identify TypeC ports in PLL ID lookup

[Kahola, Mika]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Imre Deak
> Sent: Friday, 30 October 2026 13.45
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: stable@vger.kernel.org
> Subject: [PATCH v2 5/6] drm/i915/mtl+: Use PHY type to identify TypeC ports in PLL ID lookup
> 
> Use the PHY type to identify TypeC ports in the PLL ID lookup function.
> This ensures that port B takes the TypeC path when an upcoming change
> sets its PHY type to TypeC on PTL+ platforms with an eDP panel connected
> to a TypeC PHY.
> 
> Keep the existing port >= PORT_TC1 case for BMG, where PORT_TC1 has a
> a TypeC DDI (and so uses the TypeC DDI register addresses, has a C20 PHY
> and the corresponding TC port -> PLL ID mapping), but this C20 PHY is
> not a TypeC PHY (i.e. it's not controlled by the TypeC Subsystem and so
> the driver doesn't need to run the TypeC PHY connect/disconnect,
> power-on/power-off sequences for the PHY).
> 
> v2: Keep handling the BMG TypeC DDI but non-TypeC PHY cases. (Sashiko)
> 
> CC: stable@vger.kernel.org # 6.14+
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index bfd6f0a197253..ac9d3f1102747 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -207,7 +207,8 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
> 
>  enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display, enum port port)
>  {
> -	if (port >= PORT_TC1)
> +	if (port >= PORT_TC1 ||
> +	    intel_phy_is_tc(display, intel_port_to_phy(display, port)))
>  		return icl_tc_port_to_pll_id(intel_port_to_tc(display, port));
> 
>  	switch (port) {
> --
> 2.49.1

RE: [PATCH 6/6] drm/i915/ptl+: Fix TypeC detection for eDP on port B

[Kahola, Mika]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Imre Deak
> Sent: Thursday, 29 October 2026 13.30
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: stable@vger.kernel.org
> Subject: [PATCH 6/6] drm/i915/ptl+: Fix TypeC detection for eDP on port B
> 
> On PTL+ platforms with eDP on TypeC, port B's DDI is connected to a C20
> TypeC PHY. Identify PHY B as TypeC and map port B to TC_PORT_1 when eDP
> TypeC support is enabled.
> 
> Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/9196
> CC: stable@vger.kernel.org # 6.14+
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 5e40487e9ab06..10af12846e730 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1904,6 +1904,11 @@ bool intel_phy_is_combo(struct intel_display *display, enum phy phy)
>  		return false;
>  }
> 
> +static bool intel_phy_is_edp_on_tc(struct intel_display *display, enum phy phy)
> +{
> +	return DISPLAY_RUNTIME_INFO(display)->edp_typec_support && phy == PHY_B;
> +}
> +
>  /*
>   * This function returns true if the DDI port respective to the PHY enumeration
>   * is a Type-C capable port.
> @@ -1924,6 +1929,9 @@ bool intel_phy_is_tc(struct intel_display *display, enum phy phy)
>  	if (display->platform.dgfx)
>  		return false;
> 
> +	if (intel_phy_is_edp_on_tc(display, phy))
> +		return true;
> +
>  	if (DISPLAY_VER(display) >= 13)
>  		return phy >= PHY_F && phy <= PHY_I;
>  	else if (display->platform.tigerlake)
> @@ -1974,6 +1982,9 @@ enum phy intel_port_to_phy(struct intel_display *display, enum port port)
>   */
>  enum tc_port intel_port_to_tc(struct intel_display *display, enum port port)
>  {
> +	if (intel_phy_is_edp_on_tc(display, intel_port_to_phy(display, port)))
> +		return TC_PORT_1;
> +
>  	if (DISPLAY_VER(display) >= 12)
>  		return TC_PORT_1 + port - PORT_TC1;
>  	else
> --
> 2.49.1