[PATCH 1/2] drm/i915/dp: Fix error handling during 128b/132b link training

[PATCH 1/2] drm/i915/dp: Fix error handling during 128b/132b link training

[Imre Deak]

At the end of a 128b/132b link training sequence, the HW expects the
transcoder training pattern to be set to TPS2 and from that to normal
mode (disabling the training pattern). Transitioning from TPS1 directly
to normal mode leaves the transcoder in a stuck state, resulting in
page-flip timeouts later in the modeset sequence.

Atm, in case of a failure during link training, the transcoder may be
still set to output the TPS1 pattern. Later the transcoder is then set
from TPS1 directly to normal mode in intel_dp_stop_link_train(), leading
to modeset failures later as described above. Fix this by setting the
training patter to TPS2, if the link training failed at any point.

Cc: stable@vger.kernel.org # v5.18+
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../gpu/drm/i915/display/intel_dp_link_training.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 3cc06c916017d..11953b03bb6aa 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1563,7 +1563,7 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
 
 	if (wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) {
 		lt_err(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clear\n");
-		return false;
+		goto out;
 	}
 
 	if (intel_dp_128b132b_lane_eq(intel_dp, crtc_state) &&
@@ -1575,6 +1575,19 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
 	       passed ? "passed" : "failed",
 	       crtc_state->port_clock, crtc_state->lane_count);
 
+out:
+	/*
+	 * Ensure that the training pattern does get set to TPS2 even in case
+	 * of a failure, as is the case at the end of a passing link training
+	 * and what is expected by the transcoder. Leaving TPS1 set (and
+	 * disabling the link train mode in DP_TP_CTL later from TPS1 directly)
+	 * would result in a stuck transcoder HW state and flip-done timeouts
+	 * later in the modeset sequence.
+	 */
+	if (!passed)
+		intel_dp_program_link_training_pattern(intel_dp, crtc_state,
+						       DP_PHY_DPRX, DP_TRAINING_PATTERN_2);
+
 	return passed;
 }
 
-- 
2.44.2

Re: [PATCH 1/2] drm/i915/dp: Fix error handling during 128b/132b link training

[Jani Nikula]

On Tue, 18 Feb 2025, Imre Deak <imre.deak@intel.com> wrote:
> At the end of a 128b/132b link training sequence, the HW expects the
> transcoder training pattern to be set to TPS2 and from that to normal
> mode (disabling the training pattern). Transitioning from TPS1 directly
> to normal mode leaves the transcoder in a stuck state, resulting in
> page-flip timeouts later in the modeset sequence.
>
> Atm, in case of a failure during link training, the transcoder may be
> still set to output the TPS1 pattern. Later the transcoder is then set
> from TPS1 directly to normal mode in intel_dp_stop_link_train(), leading
> to modeset failures later as described above. Fix this by setting the
> training patter to TPS2, if the link training failed at any point.
>
> Cc: stable@vger.kernel.org # v5.18+
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

No bspec link for this?

Acked-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  .../gpu/drm/i915/display/intel_dp_link_training.c | 15 ++++++++++++++-
>  1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 3cc06c916017d..11953b03bb6aa 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -1563,7 +1563,7 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
>  
>  	if (wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) {
>  		lt_err(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clear\n");
> -		return false;
> +		goto out;
>  	}
>  
>  	if (intel_dp_128b132b_lane_eq(intel_dp, crtc_state) &&
> @@ -1575,6 +1575,19 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
>  	       passed ? "passed" : "failed",
>  	       crtc_state->port_clock, crtc_state->lane_count);
>  
> +out:
> +	/*
> +	 * Ensure that the training pattern does get set to TPS2 even in case
> +	 * of a failure, as is the case at the end of a passing link training
> +	 * and what is expected by the transcoder. Leaving TPS1 set (and
> +	 * disabling the link train mode in DP_TP_CTL later from TPS1 directly)
> +	 * would result in a stuck transcoder HW state and flip-done timeouts
> +	 * later in the modeset sequence.
> +	 */
> +	if (!passed)
> +		intel_dp_program_link_training_pattern(intel_dp, crtc_state,
> +						       DP_PHY_DPRX, DP_TRAINING_PATTERN_2);
> +
>  	return passed;
>  }

-- 
Jani Nikula, Intel

Re: [PATCH 1/2] drm/i915/dp: Fix error handling during 128b/132b link training

[Imre Deak]

On Tue, Feb 18, 2025 at 02:51:21PM +0200, Jani Nikula wrote:
> On Tue, 18 Feb 2025, Imre Deak <imre.deak@intel.com> wrote:
> > At the end of a 128b/132b link training sequence, the HW expects the
> > transcoder training pattern to be set to TPS2 and from that to normal
> > mode (disabling the training pattern). Transitioning from TPS1 directly
> > to normal mode leaves the transcoder in a stuck state, resulting in
> > page-flip timeouts later in the modeset sequence.
> >
> > Atm, in case of a failure during link training, the transcoder may be
> > still set to output the TPS1 pattern. Later the transcoder is then set
> > from TPS1 directly to normal mode in intel_dp_stop_link_train(), leading
> > to modeset failures later as described above. Fix this by setting the
> > training patter to TPS2, if the link training failed at any point.
> >
> > Cc: stable@vger.kernel.org # v5.18+
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> 
> No bspec link for this?

The only clue I see for this is PTL's (and other platforms') modeset
page (68849) "Enable Sequence" 6. n.: "If DP v2.0/128b, set DP_TP_CTL
link training pattern 2."

Since setting TPS2 is normally part of the link training (described by
6. l./m.), so the only reason mentioning it as a separate step for
128b/132b (vs. 8b/10b for which it is not mentioned), could be this HW
behavior.

It's obscure imo, could've been explained in the spec better. I can
clarify this in the commit log and also file a bspec ticket for it.

> Acked-by: Jani Nikula <jani.nikula@intel.com>

Thanks.

> 
> > ---
> >  .../gpu/drm/i915/display/intel_dp_link_training.c | 15 ++++++++++++++-
> >  1 file changed, 14 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > index 3cc06c916017d..11953b03bb6aa 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > @@ -1563,7 +1563,7 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
> >  
> >  	if (wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) {
> >  		lt_err(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clear\n");
> > -		return false;
> > +		goto out;
> >  	}
> >  
> >  	if (intel_dp_128b132b_lane_eq(intel_dp, crtc_state) &&
> > @@ -1575,6 +1575,19 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
> >  	       passed ? "passed" : "failed",
> >  	       crtc_state->port_clock, crtc_state->lane_count);
> >  
> > +out:
> > +	/*
> > +	 * Ensure that the training pattern does get set to TPS2 even in case
> > +	 * of a failure, as is the case at the end of a passing link training
> > +	 * and what is expected by the transcoder. Leaving TPS1 set (and
> > +	 * disabling the link train mode in DP_TP_CTL later from TPS1 directly)
> > +	 * would result in a stuck transcoder HW state and flip-done timeouts
> > +	 * later in the modeset sequence.
> > +	 */
> > +	if (!passed)
> > +		intel_dp_program_link_training_pattern(intel_dp, crtc_state,
> > +						       DP_PHY_DPRX, DP_TRAINING_PATTERN_2);
> > +
> >  	return passed;
> >  }
> 
> -- 
> Jani Nikula, Intel