Re: [PATCH v3] PCI/ASPM: Disable L1 before disabling L1ss

Re: [PATCH v3] PCI/ASPM: Disable L1 before disabling L1ss

[Macpaul Lin (林智斌)]

On Tue, 2024-10-22 at 17:30 -0500, Bjorn Helgaas wrote:
> On Mon, Oct 07, 2024 at 08:59:17AM +0530, Ajay Agarwal wrote:
> > The current sequence in the driver for L1ss update is as follows.
> > 
> > Disable L1ss
> > Disable L1
> > Enable L1ss as required
> > Enable L1 if required
> > 
> > With this sequence, a bus hang is observed during the L1ss
> > disable sequence when the RC CPU attempts to clear the RC L1ss
> > register after clearing the EP L1ss register. It looks like the
> > RC attempts to enter L1ss again and at the same time, access to
> > RC L1ss register fails because aux clk is still not active.
> > 
> > PCIe spec r6.2, section 5.5.4, recommends that setting either
> > or both of the enable bits for ASPM L1 PM Substates must be done
> > while ASPM L1 is disabled. My interpretation here is that
> > clearing L1ss should also be done when L1 is disabled. Thereby,
> > change the sequence as follows.
> > 
> > Disable L1
> > Disable L1ss
> > Enable L1ss as required
> > Enable L1 if required
> > 
> > Signed-off-by: Ajay Agarwal <ajayagarwal@google.com>
> 
> Applied to pci/aspm for v6.13, thank you, Ajay!

Thanks! MediaTek also found this issue will happen on some old kernel,
for example 6.11 or 6.12. would you please pick this patch also to some
stable tree?

LINK:https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/drivers/pci/pcie/aspm.c?id=7447990137bf06b2aeecad9c6081e01a9f47f2aa

Thanks a lot.
Macpaul Lin

Re: [PATCH v3] PCI/ASPM: Disable L1 before disabling L1ss

[Greg KH]

On Thu, Jun 05, 2025 at 11:23:02AM +0000, Macpaul Lin (林智斌) wrote:
> On Tue, 2024-10-22 at 17:30 -0500, Bjorn Helgaas wrote:
> > On Mon, Oct 07, 2024 at 08:59:17AM +0530, Ajay Agarwal wrote:
> > > The current sequence in the driver for L1ss update is as follows.
> > > 
> > > Disable L1ss
> > > Disable L1
> > > Enable L1ss as required
> > > Enable L1 if required
> > > 
> > > With this sequence, a bus hang is observed during the L1ss
> > > disable sequence when the RC CPU attempts to clear the RC L1ss
> > > register after clearing the EP L1ss register. It looks like the
> > > RC attempts to enter L1ss again and at the same time, access to
> > > RC L1ss register fails because aux clk is still not active.
> > > 
> > > PCIe spec r6.2, section 5.5.4, recommends that setting either
> > > or both of the enable bits for ASPM L1 PM Substates must be done
> > > while ASPM L1 is disabled. My interpretation here is that
> > > clearing L1ss should also be done when L1 is disabled. Thereby,
> > > change the sequence as follows.
> > > 
> > > Disable L1
> > > Disable L1ss
> > > Enable L1ss as required
> > > Enable L1 if required
> > > 
> > > Signed-off-by: Ajay Agarwal <ajayagarwal@google.com>
> > 
> > Applied to pci/aspm for v6.13, thank you, Ajay!
> 
> Thanks! MediaTek also found this issue will happen on some old kernel,
> for example 6.11 or 6.12. would you please pick this patch also to some
> stable tree?
> 
> LINK:https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/drivers/pci/pcie/aspm.c?id=7447990137bf06b2aeecad9c6081e01a9f47f2aa

Please submit it properly, with your signed-off-by and we will be glad
to consider it.

thanks,

greg k-h