[PATCH 1/2] drm/i915/cdclk: Avoid spurious cdclk sanitization on PTL+

[PATCH 1/2] drm/i915/cdclk: Avoid spurious cdclk sanitization on PTL+

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Apparently PTL+ no longer has the cd2x pipe select field in
CDCLK_CTL. Take that into account during CDCLK sanitization.

This currently triggers a spurious CDCLK sanitization during
driver load on PTL+ which will causes a visible glitch on all
active displays.

Cc: stable@vger.kernel.org
Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/8550
Fixes: 3f9de66f8acb ("drm/i915/cdclk: Fix up CDCLK_FREQ_DECIMAL without a full PLL re-enable")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index a53d88727177..9e5e15b0c4d1 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2381,8 +2381,10 @@ static void bxt_sanitize_cdclk(struct intel_display *display)
 	 * dividers both syncing to an active pipe, or asynchronously
 	 * (PIPE_NONE).
 	 */
-	cdctl &= ~bxt_cdclk_cd2x_pipe_mask(display);
-	cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
+	if (DISPLAY_VER(display) < 30) {
+		cdctl &= ~bxt_cdclk_cd2x_pipe_mask(display);
+		cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
+	}
 
 	if (cdctl != expected) {
 		if (DISPLAY_VER(display) < 20) {
-- 
2.54.0

Re: [PATCH 1/2] drm/i915/cdclk: Avoid spurious cdclk sanitization on PTL+

[Ville Syrjälä]

On Fri, Jul 17, 2026 at 06:51:06PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Apparently PTL+ no longer has the cd2x pipe select field in
> CDCLK_CTL. Take that into account during CDCLK sanitization.
> 
> This currently triggers a spurious CDCLK sanitization during
> driver load on PTL+ which will causes a visible glitch on all
> active displays.
> 
> Cc: stable@vger.kernel.org
> Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/8550
> Fixes: 3f9de66f8acb ("drm/i915/cdclk: Fix up CDCLK_FREQ_DECIMAL without a full PLL re-enable")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---

Unfortunately the regression itself has a cc:stable on it, so we'll
need to backport this fix as well.

To do that cleanly we need to pick up these as well:
commit cd16e794aead ("drm/i915/cdclk: Clean up CDCLK_CTL defines")
commit 67d77d9472c6 ("drm/i915/cdclk: Introduce bxt_cdclk_cd2x_pipe_mask() and use it")

>  drivers/gpu/drm/i915/display/intel_cdclk.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index a53d88727177..9e5e15b0c4d1 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2381,8 +2381,10 @@ static void bxt_sanitize_cdclk(struct intel_display *display)
>  	 * dividers both syncing to an active pipe, or asynchronously
>  	 * (PIPE_NONE).
>  	 */
> -	cdctl &= ~bxt_cdclk_cd2x_pipe_mask(display);
> -	cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
> +	if (DISPLAY_VER(display) < 30) {
> +		cdctl &= ~bxt_cdclk_cd2x_pipe_mask(display);
> +		cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
> +	}
>  
>  	if (cdctl != expected) {
>  		if (DISPLAY_VER(display) < 20) {
> -- 
> 2.54.0

-- 
Ville Syrjälä
Intel

Re: [PATCH 1/2] drm/i915/cdclk: Avoid spurious cdclk sanitization on PTL+

[Rodrigo Vivi]

On Fri, Jul 17, 2026 at 07:05:26PM +0300, Ville Syrjälä wrote:
> On Fri, Jul 17, 2026 at 06:51:06PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Apparently PTL+ no longer has the cd2x pipe select field in
> > CDCLK_CTL. Take that into account during CDCLK sanitization.
> > 
> > This currently triggers a spurious CDCLK sanitization during
> > driver load on PTL+ which will causes a visible glitch on all
> > active displays.
> > 
> > Cc: stable@vger.kernel.org
> > Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/8550
> > Fixes: 3f9de66f8acb ("drm/i915/cdclk: Fix up CDCLK_FREQ_DECIMAL without a full PLL re-enable")
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> 
> Unfortunately the regression itself has a cc:stable on it, so we'll

it has a fixes tag, not a cc:stable itself, but yeah, that is enough to
reach the stable backports indeed...

> need to backport this fix as well.
> 
> To do that cleanly we need to pick up these as well:
> commit cd16e794aead ("drm/i915/cdclk: Clean up CDCLK_CTL defines")

you meant
commit aa8faabadc59 ("drm/i915/cdclk: Clean up CDCLK_CTL defines")
right?

> commit 67d77d9472c6 ("drm/i915/cdclk: Introduce bxt_cdclk_cd2x_pipe_mask() and use it")

I can pick these for the -fixes round, but for the stable we need to remember
to tell Greg and Sasha whenever we get their automated email saying that the
patch has failed to apply...

> 
> >  drivers/gpu/drm/i915/display/intel_cdclk.c | 6 ++++--
> >  1 file changed, 4 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index a53d88727177..9e5e15b0c4d1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -2381,8 +2381,10 @@ static void bxt_sanitize_cdclk(struct intel_display *display)
> >  	 * dividers both syncing to an active pipe, or asynchronously
> >  	 * (PIPE_NONE).
> >  	 */
> > -	cdctl &= ~bxt_cdclk_cd2x_pipe_mask(display);
> > -	cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
> > +	if (DISPLAY_VER(display) < 30) {
> > +		cdctl &= ~bxt_cdclk_cd2x_pipe_mask(display);
> > +		cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
> > +	}
> >  
> >  	if (cdctl != expected) {
> >  		if (DISPLAY_VER(display) < 20) {
> > -- 
> > 2.54.0
> 
> -- 
> Ville Syrjälä
> Intel

RE: [PATCH 1/2] drm/i915/cdclk: Avoid spurious cdclk sanitization on PTL+

[Kandpal, Suraj]

> Subject: [PATCH 1/2] drm/i915/cdclk: Avoid spurious cdclk sanitization on PTL+
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Apparently PTL+ no longer has the cd2x pipe select field in CDCLK_CTL. Take
> that into account during CDCLK sanitization.
> 
> This currently triggers a spurious CDCLK sanitization during driver load on PTL+
> which will causes a visible glitch on all active displays.
> 
> Cc: stable@vger.kernel.org
> Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/8550
> Fixes: 3f9de66f8acb ("drm/i915/cdclk: Fix up CDCLK_FREQ_DECIMAL without a
> full PLL re-enable")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index a53d88727177..9e5e15b0c4d1 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2381,8 +2381,10 @@ static void bxt_sanitize_cdclk(struct intel_display
> *display)
>  	 * dividers both syncing to an active pipe, or asynchronously
>  	 * (PIPE_NONE).
>  	 */
> -	cdctl &= ~bxt_cdclk_cd2x_pipe_mask(display);
> -	cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
> +	if (DISPLAY_VER(display) < 30) {
> +		cdctl &= ~bxt_cdclk_cd2x_pipe_mask(display);
> +		cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
> +	}
> 
>  	if (cdctl != expected) {
>  		if (DISPLAY_VER(display) < 20) {
> --
> 2.54.0

Re: [PATCH 1/2] drm/i915/cdclk: Avoid spurious cdclk sanitization on PTL+

[Pierre Pinon]

On Fri, Jul 17, 2026 at 06:51:06PM +0300, Ville Syrjälä wrote:
> Apparently PTL+ no longer has the cd2x pipe select field in
> CDCLK_CTL. Take that into account during CDCLK sanitization.
>
> This currently triggers a spurious CDCLK sanitization during
> driver load on PTL+ which will causes a visible glitch on all
> active displays.

Tested on a Panther Lake laptop (Intel Graphics [8086:b090], xe driver,
internal eDP panel), Fedora 43.

For what it is worth, on this machine the symptom is more than a glitch:
the internal panel comes up corrupted on cold boot and stays corrupted
until a suspend/resume cycle. dmesg shows:

  xe 0000:00:02.0: [drm] Selective fetch area calculation failed in pipe A
  xe 0000:00:02.0: [drm] *ERROR* CPU pipe A FIFO underrun
  xe 0000:00:02.0: [drm] *ERROR* CPU pipe A FIFO underrun

Counting "CPU pipe A FIFO underrun" in dmesg across boots of the same
machine:

  6.17.1-300.fc43           unpatched   0   (unaffected)
  7.1.12-100.fc43           unpatched   2
  7.1.12 + this patch [*]   patched     0   (4 boots)
  7.1.13-100.fc43           unpatched   2
  7.3.0-rc1 + this patch    patched     0

  [*] 7.1.x predates bxt_cdclk_cd2x_pipe_mask() and needs a slightly
      different form, see below; the 7.3.0-rc1 build carries this patch
      as posted, unmodified.

With the patch the panel comes up clean from cold boot and the underruns
are gone.

Tested-by: Pierre Pinon <pierre@pinon1.fr>

This covers 1/2 only; I have not tested 2/2.

Note the "Selective fetch area calculation failed in pipe A" drm_info_once
is still printed with the patch applied. As far as I can tell that one is
unrelated -- it is the deliberate full-update fallback in
intel_psr2_sel_fetch_update() -- and harmless here.

I realise this is already committed, so the tag may well arrive too late
to be folded in. I am sending it anyway as a data point for the stable
backport, which is the part that matters to me here: neither 7.1.y nor
7.2.y carries the fix yet.

On 7.1.y the change does not apply as posted, since that tree predates
bxt_cdclk_cd2x_pipe_mask(). The form I have been running there guards the
two original lines instead:

	if (DISPLAY_VER(display) < 30) {
		cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
		cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
	}

That is the variant covered by the four 7.1.12 boots above. The same form
was posted independently by Chang Jiong as
<20260816062344.796615-1-xspeed1989@gmail.com>, which I only noticed
afterwards.