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From: Thomas Gleixner <tglx@linutronix.de>
To: Chen Yu <yu.c.chen@intel.com>
Cc: x86@kernel.org, linux-kernel@vger.kernel.org,
	Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
	Bin Gao <bin.gao@intel.com>, Len Brown <lenb@kernel.org>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	"3 . 14+ # 3 . 14+" <stable@vger.kernel.org>
Subject: Re: [PATCH] x86, tsc: Fix tsc ratio calibration to avoid broken mdelay
Date: Fri, 6 May 2016 11:47:19 +0200 (CEST)	[thread overview]
Message-ID: <alpine.DEB.2.11.1605061131580.3540@nanos> (raw)
In-Reply-To: <1462505619-5516-1-git-send-email-yu.c.chen@intel.com>

On Fri, 6 May 2016, yu.c.chen@intel.com wrote:
> From: Chen Yu <yu.c.chen@intel.com>
> 
> Currently we fetch the tsc radio by:
> ratio = (lo >> 8) & 0x1f;
> thus get bit8~bit12 of the MSR_PLATFORM_INFO, however according
> to Intel 64 and IA-32 Architectures Software Developer Manual 35.5,
> the ratio bit should be bit8~bit15, otherwise we might get incorrect
> tsc ratio and cause system hang later(mdelay corrupted).

The resulting issue is that both TSC frequency, which is used for udelay, and
the lapic timer frequency are wrong. mdelay is just the visible damage caused
by that.
 
Thanks,

	tglx

  reply	other threads:[~2016-05-06  9:47 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-06  3:33 [PATCH] x86, tsc: Fix tsc ratio calibration to avoid broken mdelay yu.c.chen
2016-05-06  9:47 ` Thomas Gleixner [this message]
2016-05-06  9:53   ` Thomas Gleixner
2016-05-06 12:43     ` Chen, Yu C

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