[PATCH 0/8] i3c: renesas: Add RZ/G3L support

[PATCH 0/8] i3c: renesas: Add RZ/G3L support

[Diogo Ivo]

Hi,

this series adds I3C support for the Renesas RZ/G3L (R9A08G046) SoC and
enables the controller on the RZ/G3L SMARC EVK.

It starts with a driver fix, which is independently applicable and
marked for stable: on a pure I3C bus, the I3C core leaves the I2C SCL
rate at zero, and the driver used to derive a zero-width open-drain SCL
from it. It now falls back to the 1 MHz FM+ limit instead. There is also
a small cosmetic patch removing a comma after the sentinel in the
compatible table, for consistency.

The rest of the series adds the DT bindings, the driver compatibility
ID, the CPG clocks and resets, and the SoC and board device tree
support for R9A08G046. The board enablement is guarded by the SW_I3C_EN
switch, as the pins are shared with RIIC3 and the audio codec behind
it.

The I3C I/O voltage can be set to 1.2V or 1.8V on the board through
the SYS.3 (I3C_IOVS) switch. As software needs to tell the pin
controller which voltage is in effect, the series also adds pin
controller support for the I3C power source on RZ/G3L together with the
matching board device tree configuration.

Signed-off-by: Diogo Ivo <diogo.ivo.sx@renesas.com>
---
Diogo Ivo (8):
      i3c: renesas: Fix zero I2C SCL rate on pure I3C buses
      i3c: renesas: Drop comma after OF match table sentinel
      dt-bindings: i3c: renesas,i3c: Add RZ/G3L support
      i3c: renesas: Add RZ/G3L support
      clk: renesas: r9a08g046: Add I3C clocks and resets
      pinctrl: renesas: rzg2l: Split SoC-specific masks in struct rzg2l_register_masks
      pinctrl: renesas: rzg2l: Add RZ/G3L support for selecting I3C power source
      arm64: dts: renesas: r9a08g046: Add I3C support

 .../devicetree/bindings/i3c/renesas,i3c.yaml       | 17 +++++++++++
 arch/arm64/boot/dts/renesas/r9a08g046.dtsi         | 35 ++++++++++++++++++++++
 arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts | 21 +++++++++++++
 arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi   |  4 +++
 drivers/clk/renesas/r9a08g046-cpg.c                |  7 +++++
 drivers/i3c/master/renesas-i3c.c                   | 16 ++++++++--
 drivers/pinctrl/renesas/pinctrl-rzg2l.c            | 25 ++++++++--------
 7 files changed, 110 insertions(+), 15 deletions(-)
---
base-commit: 5d13f5297a1bd1fdff5fab7efcdbc9bfe407e457
change-id: 20261020-divo-ssgrlpcsrc-2966-i3c-bca85b48f943

Best regards,
--  
Diogo Ivo <diogo.ivo.sx@renesas.com>

[PATCH 1/8] i3c: renesas: Fix zero I2C SCL rate on pure I3C buses

[Diogo Ivo]

On a pure I3C bus there are no I2C devices, so the I3C core leaves
bus->scl_rate.i2c at zero if i2c-scl-hz is not specified in DT.
Deriving i2c_total_ticks from that zero rate programs a zero-width
open-drain SCL into the STDBR open-drain fields, which are still used
in pure I3C mode for example in DAA.

Fall back to the 1 MHz FM+ limit instead, the fastest rate an I2C
device could have, so that a sane open-drain timing is programmed.

Fixes: d028219a9f14 ("i3c: master: Add basic driver for the Renesas I3C controller")
Cc: stable@vger.kernel.org
Signed-off-by: Diogo Ivo <diogo.ivo.sx@renesas.com>
---
 drivers/i3c/master/renesas-i3c.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/i3c/master/renesas-i3c.c b/drivers/i3c/master/renesas-i3c.c
index 8b264f72e55c..1fa115bdab6b 100644
--- a/drivers/i3c/master/renesas-i3c.c
+++ b/drivers/i3c/master/renesas-i3c.c
@@ -579,7 +579,18 @@ static int renesas_i3c_bus_init(struct i3c_master_controller *m)
 	if (!i3c->rate)
 		return -EINVAL;
 
-	i2c_total_ticks = DIV_ROUND_UP(i3c->rate, bus->scl_rate.i2c);
+	/*
+	 * A pure I3C bus has no I2C devices, so the I3C core leaves
+	 * scl_rate.i2c at zero if not explicitly defined in DT. The
+	 * open-drain SCL fields of STDBR, which are used for the DAA
+	 * pending read, are derived from it though, so fall back to
+	 * the 1 MHz FM+ limit instead of programming a zero-width clock.
+	 */
+	if (!bus->scl_rate.i2c)
+		i2c_total_ticks = DIV_ROUND_UP(i3c->rate, I3C_BUS_I2C_FM_PLUS_SCL_MAX_RATE);
+	else
+		i2c_total_ticks = DIV_ROUND_UP(i3c->rate, bus->scl_rate.i2c);
+
 	i3c_total_ticks = DIV_ROUND_UP(i3c->rate, bus->scl_rate.i3c);
 
 	i2c_parse_fw_timings(&m->dev, &t, true);

-- 
2.56.0

Re: [PATCH 1/8] i3c: renesas: Fix zero I2C SCL rate on pure I3C buses

[Geert Uytterhoeven]

Hi Diogo,

On Tue, 20 Oct 2026 at 11:15, Diogo Ivo <diogo.ivo.sx@renesas.com> wrote:
> On a pure I3C bus there are no I2C devices, so the I3C core leaves
> bus->scl_rate.i2c at zero if i2c-scl-hz is not specified in DT.
> Deriving i2c_total_ticks from that zero rate programs a zero-width
> open-drain SCL into the STDBR open-drain fields, which are still used
> in pure I3C mode for example in DAA.
>
> Fall back to the 1 MHz FM+ limit instead, the fastest rate an I2C
> device could have, so that a sane open-drain timing is programmed.
>
> Fixes: d028219a9f14 ("i3c: master: Add basic driver for the Renesas I3C controller")
> Cc: stable@vger.kernel.org
> Signed-off-by: Diogo Ivo <diogo.ivo.sx@renesas.com>

Thanks for your patch!

> --- a/drivers/i3c/master/renesas-i3c.c
> +++ b/drivers/i3c/master/renesas-i3c.c
> @@ -579,7 +579,18 @@ static int renesas_i3c_bus_init(struct i3c_master_controller *m)
>         if (!i3c->rate)
>                 return -EINVAL;
>
> -       i2c_total_ticks = DIV_ROUND_UP(i3c->rate, bus->scl_rate.i2c);
> +       /*
> +        * A pure I3C bus has no I2C devices, so the I3C core leaves
> +        * scl_rate.i2c at zero if not explicitly defined in DT. The
> +        * open-drain SCL fields of STDBR, which are used for the DAA
> +        * pending read, are derived from it though, so fall back to
> +        * the 1 MHz FM+ limit instead of programming a zero-width clock.
> +        */
> +       if (!bus->scl_rate.i2c)
> +               i2c_total_ticks = DIV_ROUND_UP(i3c->rate, I3C_BUS_I2C_FM_PLUS_SCL_MAX_RATE);
> +       else
> +               i2c_total_ticks = DIV_ROUND_UP(i3c->rate, bus->scl_rate.i2c);
> +
>         i3c_total_ticks = DIV_ROUND_UP(i3c->rate, bus->scl_rate.i3c);

This looks like a good opportunity to use the shortened tertiary ?:-operator:

    bus->scl_rate.i2c ?: I3C_BUS_I2C_FM_PLUS_SCL_MAX_RATE

>
>         i2c_parse_fw_timings(&m->dev, &t, true);

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/8] i3c: renesas: Fix zero I2C SCL rate on pure I3C buses

[Diogo Ivo]

Hi Geert,

On 10/20/2026 10:27 AM, Geert Uytterhoeven wrote:
> 
> Hi Diogo,
> 
> On Tue, 20 Oct 2026 at 11:15, Diogo Ivo <diogo.ivo.sx@renesas.com> wrote:
>> On a pure I3C bus there are no I2C devices, so the I3C core leaves
>> bus->scl_rate.i2c at zero if i2c-scl-hz is not specified in DT.
>> Deriving i2c_total_ticks from that zero rate programs a zero-width
>> open-drain SCL into the STDBR open-drain fields, which are still used
>> in pure I3C mode for example in DAA.
>>
>> Fall back to the 1 MHz FM+ limit instead, the fastest rate an I2C
>> device could have, so that a sane open-drain timing is programmed.
>>
>> Fixes: d028219a9f14 ("i3c: master: Add basic driver for the Renesas I3C controller")
>> Cc: stable@vger.kernel.org
>> Signed-off-by: Diogo Ivo <diogo.ivo.sx@renesas.com>
> 
> Thanks for your patch!
> 
>> --- a/drivers/i3c/master/renesas-i3c.c
>> +++ b/drivers/i3c/master/renesas-i3c.c
>> @@ -579,7 +579,18 @@ static int renesas_i3c_bus_init(struct i3c_master_controller *m)
>>          if (!i3c->rate)
>>                  return -EINVAL;
>>
>> -       i2c_total_ticks = DIV_ROUND_UP(i3c->rate, bus->scl_rate.i2c);
>> +       /*
>> +        * A pure I3C bus has no I2C devices, so the I3C core leaves
>> +        * scl_rate.i2c at zero if not explicitly defined in DT. The
>> +        * open-drain SCL fields of STDBR, which are used for the DAA
>> +        * pending read, are derived from it though, so fall back to
>> +        * the 1 MHz FM+ limit instead of programming a zero-width clock.
>> +        */
>> +       if (!bus->scl_rate.i2c)
>> +               i2c_total_ticks = DIV_ROUND_UP(i3c->rate, I3C_BUS_I2C_FM_PLUS_SCL_MAX_RATE);
>> +       else
>> +               i2c_total_ticks = DIV_ROUND_UP(i3c->rate, bus->scl_rate.i2c);
>> +
>>          i3c_total_ticks = DIV_ROUND_UP(i3c->rate, bus->scl_rate.i3c);
> 
> This looks like a good opportunity to use the shortened tertiary ?:-operator:
> 
>      bus->scl_rate.i2c ?: I3C_BUS_I2C_FM_PLUS_SCL_MAX_RATE

Ack, will change in v2.

Thanks for the review,
Diogo

>>
>>          i2c_parse_fw_timings(&m->dev, &t, true);
> 
> Gr{oetje,eeting}s,
> 
>                          Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                  -- Linus Torvalds

Re: [PATCH 1/8] i3c: renesas: Fix zero I2C SCL rate on pure I3C buses

[Wolfram Sang]

On Tue, Oct 20, 2026 at 10:14:55AM +0100, Diogo Ivo wrote:
> On a pure I3C bus there are no I2C devices, so the I3C core leaves
> bus->scl_rate.i2c at zero if i2c-scl-hz is not specified in DT.
> Deriving i2c_total_ticks from that zero rate programs a zero-width
> open-drain SCL into the STDBR open-drain fields, which are still used
> in pure I3C mode for example in DAA.
> 
> Fall back to the 1 MHz FM+ limit instead, the fastest rate an I2C
> device could have, so that a sane open-drain timing is programmed.
> 
> Fixes: d028219a9f14 ("i3c: master: Add basic driver for the Renesas I3C controller")
> Cc: stable@vger.kernel.org
> Signed-off-by: Diogo Ivo <diogo.ivo.sx@renesas.com>

Great catch! Kudos for adding a good comment. I agree with Geert about
using the ternary operator, though. After that, you can add my:

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Re: [PATCH 1/8] i3c: renesas: Fix zero I2C SCL rate on pure I3C buses

[Diogo Ivo]

On 10/23/2026 11:27 AM, Wolfram Sang wrote:
> On Tue, Oct 20, 2026 at 10:14:55AM +0100, Diogo Ivo wrote:
>> On a pure I3C bus there are no I2C devices, so the I3C core leaves
>> bus->scl_rate.i2c at zero if i2c-scl-hz is not specified in DT.
>> Deriving i2c_total_ticks from that zero rate programs a zero-width
>> open-drain SCL into the STDBR open-drain fields, which are still used
>> in pure I3C mode for example in DAA.
>>
>> Fall back to the 1 MHz FM+ limit instead, the fastest rate an I2C
>> device could have, so that a sane open-drain timing is programmed.
>>
>> Fixes: d028219a9f14 ("i3c: master: Add basic driver for the Renesas I3C controller")
>> Cc: stable@vger.kernel.org
>> Signed-off-by: Diogo Ivo <diogo.ivo.sx@renesas.com>
> 
> Great catch! Kudos for adding a good comment. I agree with Geert about
> using the ternary operator, though. After that, you can add my:
> 
> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Ok, will do.

Thanks,
Diogo