Re: [PATCH 08/14] rockchip: rk3568-rock-3a: Enable boot from SPI NOR flash

[Kever Yang <kever.yang@rock-chips.com>]

On 2023/4/22 09:23, Jonas Karlman wrote:
> Add sfc and flash node to device tree and config options to enable
> support for booting from SPI NOR flash on Radxa ROCK 3 Model A.
>
> Unlike prior generation SoCs the BootRom in RK3568 can read all data and
> look for idbloader at 0x8000, same as on SD and eMMC.
>
> Use the rksd format and modify the mkimage offset to generate a bootable
> u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. The
> FIT image is loaded from 0x60000.
>
>    => sf probe
>    SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 MiB
>
>    => load mmc 1:1 10000000 u-boot-rockchip-spi.bin
>    1384448 bytes read in 119 ms (11.1 MiB/s)
>
>    => sf update $fileaddr 0 $filesize
>    device 0 offset 0x0, size 0x152000
>    1179648 bytes written, 204800 bytes skipped in 9.901s, speed 143185 B/s
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 25 +++++++++++++++++++++++++
>   arch/arm/dts/rk356x-u-boot.dtsi         | 11 +++++++++++
>   configs/rock-3a-rk3568_defconfig        | 10 ++++++++++
>   3 files changed, 46 insertions(+)
>
> diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
> index b2af3b1dbed6..7cd2dc80c317 100644
> --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
> +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
> @@ -7,6 +7,10 @@
>   #include "rk356x-u-boot.dtsi"
>   
>   / {
> +	aliases {
> +		spi0 = &sfc;
> +	};
> +
>   	chosen {
>   		stdout-path = &uart2;
>   		u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
> @@ -33,6 +37,10 @@
>   	bootph-pre-ram;
>   };
>   
> +&fspi_pins {
> +	bootph-pre-ram;
> +};
> +
>   &sdmmc0_bus4 {
>   	bootph-pre-ram;
>   };
> @@ -65,6 +73,23 @@
>   	bootph-pre-ram;
>   };
>   
> +&sfc {
> +	bootph-pre-ram;
> +	u-boot,spl-sfc-no-dma;
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	status = "okay";
> +
> +	flash@0 {
> +		bootph-pre-ram;
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <24000000>;
> +		spi-rx-bus-width = <4>;
> +		spi-tx-bus-width = <1>;
> +	};
> +};
> +
>   &sdhci {
>   	cap-mmc-highspeed;
>   	mmc-ddr-1_8v;
> diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi
> index a1c2d03c52f0..c340c2bba6ff 100644
> --- a/arch/arm/dts/rk356x-u-boot.dtsi
> +++ b/arch/arm/dts/rk356x-u-boot.dtsi
> @@ -68,3 +68,14 @@
>   	bootph-pre-ram;
>   	status = "okay";
>   };
> +
> +#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
> +&binman {
> +	simple-bin-spi {
> +		mkimage {
> +			args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
> +			offset = <0x8000>;
> +		};
> +	};
> +};
> +#endif
> diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
> index 2e556dc2c1a2..64864a300153 100644
> --- a/configs/rock-3a-rk3568_defconfig
> +++ b/configs/rock-3a-rk3568_defconfig
> @@ -8,15 +8,20 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
>   CONFIG_NR_DRAM_BANKS=2
>   CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
>   CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
> +CONFIG_SF_DEFAULT_SPEED=24000000
> +CONFIG_SF_DEFAULT_MODE=0x2000
>   CONFIG_DEFAULT_DEVICE_TREE="rk3568-rock-3a"
>   CONFIG_ROCKCHIP_RK3568=y
>   CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
> +CONFIG_ROCKCHIP_SPI_IMAGE=y
>   CONFIG_SPL_SERIAL=y
>   CONFIG_SPL_STACK_R_ADDR=0x600000
>   CONFIG_TARGET_EVB_RK3568=y
>   CONFIG_SPL_STACK=0x400000
>   CONFIG_DEBUG_UART_BASE=0xFE660000
>   CONFIG_DEBUG_UART_CLOCK=24000000
> +CONFIG_SPL_SPI_FLASH_SUPPORT=y
> +CONFIG_SPL_SPI=y
>   CONFIG_SYS_LOAD_ADDR=0xc00800
>   CONFIG_DEBUG_UART=y
>   CONFIG_FIT=y
> @@ -34,6 +39,8 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
>   # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
>   # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
>   CONFIG_SPL_STACK_R=y
> +CONFIG_SPL_SPI_LOAD=y
> +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
>   CONFIG_SPL_ATF=y
>   CONFIG_CMD_GPIO=y
>   CONFIG_CMD_GPT=y
> @@ -59,6 +66,8 @@ CONFIG_MMC_DW_ROCKCHIP=y
>   CONFIG_MMC_SDHCI=y
>   CONFIG_MMC_SDHCI_SDMA=y
>   CONFIG_MMC_SDHCI_ROCKCHIP=y
> +CONFIG_SPI_FLASH_MACRONIX=y
> +CONFIG_SPI_FLASH_XTX=y
>   CONFIG_ETH_DESIGNWARE=y
>   CONFIG_GMAC_ROCKCHIP=y
>   CONFIG_PHY_ROCKCHIP_INNO_USB2=y
> @@ -72,6 +81,7 @@ CONFIG_SPL_RAM=y
>   CONFIG_BAUDRATE=1500000
>   CONFIG_DEBUG_UART_SHIFT=2
>   CONFIG_SYS_NS16550_MEM32=y
> +CONFIG_ROCKCHIP_SFC=y
>   CONFIG_SYSRESET=y
>   CONFIG_USB=y
>   CONFIG_USB_XHCI_HCD=y