* [U-Boot] [PATCH] usb: tegra: Fix PHY configuration for Tegra 3
@ 2014-02-13 19:21 Stefan Agner
2014-02-13 20:33 ` Tom Warren
2014-02-14 10:59 ` Jim Lin
0 siblings, 2 replies; 3+ messages in thread
From: Stefan Agner @ 2014-02-13 19:21 UTC (permalink / raw)
To: u-boot
On Tegra 3, the PTS (parallel transceiver select) and STS (serial
transceiver select) are part of the HOSTPC1_DEVLC_0 register rather
than PORTSC1_0 register. Since the reset configuration usually
matches the configured registers, this error did not show up on
Tegra 3 devices.
Also clear the forced powerdown bit in the UTMIP_PLL_CFG2_0 register
which brings USB2 in UTMI mode to work. This was clearly missing
since the forced powerdown bit is set in reset by default for all
USB ports.
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
drivers/usb/host/ehci-tegra.c | 22 ++++++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index 0b42aa5..fdd56c9 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -461,6 +461,9 @@ static int init_utmi_usb_controller(struct fdt_usb *config)
if (config->periph_id == PERIPH_ID_USBD)
clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
UTMIP_FORCE_PD_SAMP_A_POWERDOWN);
+ if (config->periph_id == PERIPH_ID_USB2)
+ clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
+ UTMIP_FORCE_PD_SAMP_B_POWERDOWN);
if (config->periph_id == PERIPH_ID_USB3)
clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
UTMIP_FORCE_PD_SAMP_C_POWERDOWN);
@@ -483,9 +486,15 @@ static int init_utmi_usb_controller(struct fdt_usb *config)
clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
/* Select UTMI parallel interface */
- clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
- PTS_UTMI << PTS_SHIFT);
- clrbits_le32(&usbctlr->port_sc1, STS);
+ if (!controller->has_hostpc) {
+ clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
+ PTS_UTMI << PTS_SHIFT);
+ clrbits_le32(&usbctlr->port_sc1, STS);
+ } else {
+ clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
+ PTS_UTMI << PTS_SHIFT);
+ clrbits_le32(&usbctlr->hostpc1_devlc, STS);
+ }
/* Deassert power down state */
clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
@@ -543,7 +552,12 @@ static int init_ulpi_usb_controller(struct fdt_usb *config)
ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP);
/* Select ULPI parallel interface */
- clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT);
+ if (!controller->has_hostpc) {
+ clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
+ PTS_ULPI << PTS_SHIFT);
+ else
+ clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
+ PTS_ULPI << PTS_SHIFT);
/* enable ULPI transceiver */
setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
--
1.8.5.4
^ permalink raw reply related [flat|nested] 3+ messages in thread* [U-Boot] [PATCH] usb: tegra: Fix PHY configuration for Tegra 3
2014-02-13 19:21 [U-Boot] [PATCH] usb: tegra: Fix PHY configuration for Tegra 3 Stefan Agner
@ 2014-02-13 20:33 ` Tom Warren
2014-02-14 10:59 ` Jim Lin
1 sibling, 0 replies; 3+ messages in thread
From: Tom Warren @ 2014-02-13 20:33 UTC (permalink / raw)
To: u-boot
Adding Jim Lin (NV USB expert) to the review
> -----Original Message-----
> From: Stefan Agner [mailto:stefan at agner.ch]
> Sent: Thursday, February 13, 2014 12:21 PM
> To: u-boot at lists.denx.de; swarren at wwwdotorg.org; Tom Warren;
> sjg at chromium.org; dev at lynxeye.de
> Cc: stefan at agner.ch
> Subject: [PATCH] usb: tegra: Fix PHY configuration for Tegra 3
>
> On Tegra 3, the PTS (parallel transceiver select) and STS (serial transceiver
> select) are part of the HOSTPC1_DEVLC_0 register rather than PORTSC1_0
> register. Since the reset configuration usually matches the configured
> registers, this error did not show up on Tegra 3 devices.
>
> Also clear the forced powerdown bit in the UTMIP_PLL_CFG2_0 register
> which brings USB2 in UTMI mode to work. This was clearly missing since the
> forced powerdown bit is set in reset by default for all USB ports.
>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---
> drivers/usb/host/ehci-tegra.c | 22 ++++++++++++++++++----
> 1 file changed, 18 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
> index 0b42aa5..fdd56c9 100644
> --- a/drivers/usb/host/ehci-tegra.c
> +++ b/drivers/usb/host/ehci-tegra.c
> @@ -461,6 +461,9 @@ static int init_utmi_usb_controller(struct fdt_usb
> *config)
> if (config->periph_id == PERIPH_ID_USBD)
> clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
>
> UTMIP_FORCE_PD_SAMP_A_POWERDOWN);
> + if (config->periph_id == PERIPH_ID_USB2)
> + clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
> +
> UTMIP_FORCE_PD_SAMP_B_POWERDOWN);
> if (config->periph_id == PERIPH_ID_USB3)
> clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
>
> UTMIP_FORCE_PD_SAMP_C_POWERDOWN); @@ -483,9 +486,15 @@ static
> int init_utmi_usb_controller(struct fdt_usb *config)
> clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
>
> /* Select UTMI parallel interface */
> - clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
> - PTS_UTMI << PTS_SHIFT);
> - clrbits_le32(&usbctlr->port_sc1, STS);
> + if (!controller->has_hostpc) {
> + clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
> + PTS_UTMI << PTS_SHIFT);
> + clrbits_le32(&usbctlr->port_sc1, STS);
> + } else {
> + clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
> + PTS_UTMI << PTS_SHIFT);
> + clrbits_le32(&usbctlr->hostpc1_devlc, STS);
> + }
>
> /* Deassert power down state */
> clrbits_le32(&usbctlr->utmip_xcvr_cfg0,
> UTMIP_FORCE_PD_POWERDOWN | @@ -543,7 +552,12 @@ static int
> init_ulpi_usb_controller(struct fdt_usb *config)
> ULPI_CLKOUT_PINMUX_BYP |
> ULPI_OUTPUT_PINMUX_BYP);
>
> /* Select ULPI parallel interface */
> - clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI <<
> PTS_SHIFT);
> + if (!controller->has_hostpc) {
> + clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
> + PTS_ULPI << PTS_SHIFT);
> + else
> + clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
> + PTS_ULPI << PTS_SHIFT);
>
> /* enable ULPI transceiver */
> setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
> --
> 1.8.5.4
--
nvpublic
^ permalink raw reply [flat|nested] 3+ messages in thread* [U-Boot] [PATCH] usb: tegra: Fix PHY configuration for Tegra 3
2014-02-13 19:21 [U-Boot] [PATCH] usb: tegra: Fix PHY configuration for Tegra 3 Stefan Agner
2014-02-13 20:33 ` Tom Warren
@ 2014-02-14 10:59 ` Jim Lin
1 sibling, 0 replies; 3+ messages in thread
From: Jim Lin @ 2014-02-14 10:59 UTC (permalink / raw)
To: u-boot
On Fri, 2014-02-14 at 03:21 +0800, Stefan Agner wrote:
> On Tegra 3, the PTS (parallel transceiver select) and STS (serial
> transceiver select) are part of the HOSTPC1_DEVLC_0 register rather
> than PORTSC1_0 register. Since the reset configuration usually
> matches the configured registers, this error did not show up on
> Tegra 3 devices.
>
> Also clear the forced powerdown bit in the UTMIP_PLL_CFG2_0 register
> which brings USB2 in UTMI mode to work. This was clearly missing
> since the forced powerdown bit is set in reset by default for all
> USB ports.
>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---
> drivers/usb/host/ehci-tegra.c | 22 ++++++++++++++++++----
> 1 file changed, 18 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
> index 0b42aa5..fdd56c9 100644
> --- a/drivers/usb/host/ehci-tegra.c
> +++ b/drivers/usb/host/ehci-tegra.c
> @@ -461,6 +461,9 @@ static int init_utmi_usb_controller(struct fdt_usb *config)
> if (config->periph_id == PERIPH_ID_USBD)
> clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
> UTMIP_FORCE_PD_SAMP_A_POWERDOWN);
> + if (config->periph_id == PERIPH_ID_USB2)
> + clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
> + UTMIP_FORCE_PD_SAMP_B_POWERDOWN);
> if (config->periph_id == PERIPH_ID_USB3)
> clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
> UTMIP_FORCE_PD_SAMP_C_POWERDOWN);
> @@ -483,9 +486,15 @@ static int init_utmi_usb_controller(struct fdt_usb *config)
> clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
>
> /* Select UTMI parallel interface */
> - clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
> - PTS_UTMI << PTS_SHIFT);
> - clrbits_le32(&usbctlr->port_sc1, STS);
> + if (!controller->has_hostpc) {
> + clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
> + PTS_UTMI << PTS_SHIFT);
> + clrbits_le32(&usbctlr->port_sc1, STS);
> + } else {
> + clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
> + PTS_UTMI << PTS_SHIFT);
> + clrbits_le32(&usbctlr->hostpc1_devlc, STS);
> + }
Could you help to change above code like this?
Thanks.
+ if (!controller->has_hostpc) {
+ if (config->periph_id == PERIPH_ID_USBD) {
+ clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK,
+ PTS_UTMI << PTS1_SHIFT);
+ clrbits_le32(&usbctlr->port_sc1, STS1);
+ } else {
+ clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
+ PTS_UTMI << PTS_SHIFT);
+ clrbits_le32(&usbctlr->port_sc1, STS);
+ }
+ } else {
+ clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
+ PTS_UTMI << PTS_SHIFT);
+ clrbits_le32(&usbctlr->hostpc1_devlc, STS);
+ }
Others look good.
--nvpublic
^ permalink raw reply [flat|nested] 3+ messages in thread
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2014-02-13 19:21 [U-Boot] [PATCH] usb: tegra: Fix PHY configuration for Tegra 3 Stefan Agner
2014-02-13 20:33 ` Tom Warren
2014-02-14 10:59 ` Jim Lin
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