[PATCH 0/3] clk/qcom: fixes and more SC7280 clocks

[PATCH 0/3] clk/qcom: fixes and more SC7280 clocks

[Caleb Connolly]

Refactor qcom_gate_clk_en() so that it will actually report an error if
we try to enable a clock that isn't defined. This will help a lot during
bringup and ensure we don't miss any clocks.

Additionally, add a bunch of clocks for SC7280, preparing for i2c and
PCIe support, plus some debug data.

---
Caleb Connolly (3):
      clk/qcom: bubble up qcom_gate_clk_en() errors
      clk/qcom: sc7280: add some debug data
      clk/qcom: sc7280: add GENI, PCIe, and more USB clocks

 drivers/clk/qcom/clock-apq8016.c  |   3 +-
 drivers/clk/qcom/clock-qcm2290.c  |   4 +-
 drivers/clk/qcom/clock-qcom.h     |  12 +++-
 drivers/clk/qcom/clock-sa8775p.c  |   4 +-
 drivers/clk/qcom/clock-sc7280.c   | 124 +++++++++++++++++++++++++++++++++-----
 drivers/clk/qcom/clock-sdm845.c   |   4 +-
 drivers/clk/qcom/clock-sm6115.c   |   4 +-
 drivers/clk/qcom/clock-sm8150.c   |   4 +-
 drivers/clk/qcom/clock-sm8250.c   |   4 +-
 drivers/clk/qcom/clock-sm8550.c   |   4 +-
 drivers/clk/qcom/clock-sm8650.c   |   4 +-
 drivers/clk/qcom/clock-x1e80100.c |   4 +-
 12 files changed, 129 insertions(+), 46 deletions(-)
---
base-commit: 9805321dfdeb5225fe5c5e0721abf49c0875637e

Caleb Connolly <caleb.connolly@linaro.org>

[PATCH 1/3] clk/qcom: bubble up qcom_gate_clk_en() errors

[Caleb Connolly]

If we try to enable a gate clock that doesn't exist, we used to just
fail silently. This may make sense for early bringup of some core
peripherals that we know are already enabled, but it only makes
debugging missing clocks more difficult.

Bubble up errors now that qcom_gate_clk_en() can return an error code to
catch any still-missing clocks and make it easier to find missing ones
as more complicated peripherals are enabled.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 drivers/clk/qcom/clock-apq8016.c  |  3 +--
 drivers/clk/qcom/clock-qcm2290.c  |  4 +---
 drivers/clk/qcom/clock-qcom.h     | 12 +++++++++---
 drivers/clk/qcom/clock-sa8775p.c  |  4 +---
 drivers/clk/qcom/clock-sc7280.c   |  4 +---
 drivers/clk/qcom/clock-sdm845.c   |  4 +---
 drivers/clk/qcom/clock-sm6115.c   |  4 +---
 drivers/clk/qcom/clock-sm8150.c   |  4 +---
 drivers/clk/qcom/clock-sm8250.c   |  4 +---
 drivers/clk/qcom/clock-sm8550.c   |  4 +---
 drivers/clk/qcom/clock-sm8650.c   |  4 +---
 drivers/clk/qcom/clock-x1e80100.c |  4 +---
 12 files changed, 20 insertions(+), 35 deletions(-)

diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
index b5def55dbc2ac671130624dec56592288a0ceb3d..3bafbfea3b6f5bf903f6f5a593e1f062bd40c53a 100644
--- a/drivers/clk/qcom/clock-apq8016.c
+++ b/drivers/clk/qcom/clock-apq8016.c
@@ -144,11 +144,10 @@ static int apq8016_clk_enable(struct clk *clk)
 		return 0;
 	}
 
 	debug("%s: clk %s\n", __func__, apq8016_clks[clk->id].name);
-	qcom_gate_clk_en(priv, clk->id);
 
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static struct msm_clk_data apq8016_clk_data = {
 	.set_rate = apq8016_clk_set_rate,
diff --git a/drivers/clk/qcom/clock-qcm2290.c b/drivers/clk/qcom/clock-qcm2290.c
index c78705cb8cf19a75508f5a3a0fbc7c04d750d273..1326b770c3ebd723120de4b6657aafac726023d6 100644
--- a/drivers/clk/qcom/clock-qcm2290.c
+++ b/drivers/clk/qcom/clock-qcm2290.c
@@ -133,11 +133,9 @@ static int qcm2290_enable(struct clk *clk)
 		qcom_gate_clk_en(priv, GCC_USB3_PRIM_CLKREF_CLK);
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map qcm2290_gcc_resets[] = {
 	[GCC_CAMSS_OPE_BCR] = { 0x55000 },
diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
index ff336dea39cf5cbe35f37f93669285897ba185a4..e9eb659f3ed37522a71e04e9418f48091bf9a0aa 100644
--- a/drivers/clk/qcom/clock-qcom.h
+++ b/drivers/clk/qcom/clock-qcom.h
@@ -6,8 +6,9 @@
 #define _CLOCK_QCOM_H
 
 #include <asm/io.h>
 #include <linux/bitfield.h>
+#include <errno.h>
 
 #define CFG_CLK_SRC_CXO   (0 << 8)
 #define CFG_CLK_SRC_GPLL0 (1 << 8)
 #define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8)
@@ -104,15 +105,20 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr,
 void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div,
 		      int source);
 void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled);
 
-static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
+static inline int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
 {
 	u32 val;
-	if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0)
-		return;
+	if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0) {
+		log_err("gcc@%#08llx: unknown clock ID %lu!\n",
+			priv->base, id);
+		return -ENOENT;
+	}
 
 	val = readl(priv->base + priv->data->clks[id].reg);
 	writel(val | priv->data->clks[id].en_val, priv->base + priv->data->clks[id].reg);
+
+	return 0;
 }
 
 #endif
diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c
index e31f24ed4f0ca989f20d1eadcff5f24f173455fa..527cecf5c8282a7c2e16740e6520241a230bca73 100644
--- a/drivers/clk/qcom/clock-sa8775p.c
+++ b/drivers/clk/qcom/clock-sa8775p.c
@@ -72,11 +72,9 @@ static int sa8775p_enable(struct clk *clk)
 		qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map sa8775p_gcc_resets[] = {
 	[GCC_CAMERA_BCR] = { 0x32000 },
diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c
index 5d343f120519da02d8ec3e269d348ab46cde70a8..8ffd1f43f23e51140c7822f0f523fdfd8ab1de7a 100644
--- a/drivers/clk/qcom/clock-sc7280.c
+++ b/drivers/clk/qcom/clock-sc7280.c
@@ -72,11 +72,9 @@ static int sc7280_enable(struct clk *clk)
 		qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map sc7280_gcc_resets[] = {
 	[GCC_PCIE_0_BCR] = { 0x6b000 },
diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c
index adffb0cb2402a6b27e0e998af2f121c519301820..6a0bf16ba2dce7f922adf971817399c71ac35586 100644
--- a/drivers/clk/qcom/clock-sdm845.c
+++ b/drivers/clk/qcom/clock-sdm845.c
@@ -161,11 +161,9 @@ static int sdm845_clk_enable(struct clk *clk)
 		qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK);
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map sdm845_gcc_resets[] = {
 	[GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
diff --git a/drivers/clk/qcom/clock-sm6115.c b/drivers/clk/qcom/clock-sm6115.c
index 9057dfe0bb1873e9edcfd8c01c0a81b6b8b4ca2c..17c2e5617580aae9ad3f0d802bbc6882c2c81043 100644
--- a/drivers/clk/qcom/clock-sm6115.c
+++ b/drivers/clk/qcom/clock-sm6115.c
@@ -145,11 +145,9 @@ static int sm6115_enable(struct clk *clk)
 		qcom_gate_clk_en(priv, GCC_USB3_PRIM_CLKREF_CLK);
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map sm6115_gcc_resets[] = {
 	[GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
diff --git a/drivers/clk/qcom/clock-sm8150.c b/drivers/clk/qcom/clock-sm8150.c
index 88f2e678f43cfcc9b80917f26c211049ebca6f9d..7dd0d56eb43031e893541e4031cbda2e92ae402d 100644
--- a/drivers/clk/qcom/clock-sm8150.c
+++ b/drivers/clk/qcom/clock-sm8150.c
@@ -242,11 +242,9 @@ static int sm8150_clk_enable(struct clk *clk)
 		qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK);
 		break;
 	};
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map sm8150_gcc_resets[] = {
 	[GCC_EMAC_BCR] = { 0x6000 },
diff --git a/drivers/clk/qcom/clock-sm8250.c b/drivers/clk/qcom/clock-sm8250.c
index e322a923a5c048769dd5134c6c24e16bb74e7317..26396847d85964d5056cf9af62b8bc89be34dc43 100644
--- a/drivers/clk/qcom/clock-sm8250.c
+++ b/drivers/clk/qcom/clock-sm8250.c
@@ -194,11 +194,9 @@ static int sm8250_enable(struct clk *clk)
 		qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK);
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map sm8250_gcc_resets[] = {
 	[GCC_GPU_BCR] = { 0x71000 },
diff --git a/drivers/clk/qcom/clock-sm8550.c b/drivers/clk/qcom/clock-sm8550.c
index 62b5a409e8e08243ad53a0bc58af1c7754a3d950..7c06489b9c4df9ce94fa9b44a762c10133377423 100644
--- a/drivers/clk/qcom/clock-sm8550.c
+++ b/drivers/clk/qcom/clock-sm8550.c
@@ -219,11 +219,9 @@ static int sm8550_enable(struct clk *clk)
 		clk_phy_mux_enable(priv->base, 0x8d078, true);
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map sm8550_gcc_resets[] = {
 	[GCC_CAMERA_BCR] = { 0x26000 },
diff --git a/drivers/clk/qcom/clock-sm8650.c b/drivers/clk/qcom/clock-sm8650.c
index 9baaecb571f6c575c0e7c48d66214c1331b6642f..364454644a699c495479b3099f590562c415ce82 100644
--- a/drivers/clk/qcom/clock-sm8650.c
+++ b/drivers/clk/qcom/clock-sm8650.c
@@ -216,11 +216,9 @@ static int sm8650_enable(struct clk *clk)
 		clk_phy_mux_enable(priv->base, 0x8d078, true);
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map sm8650_gcc_resets[] = {
 	[GCC_CAMERA_BCR] = { 0x26000 },
diff --git a/drivers/clk/qcom/clock-x1e80100.c b/drivers/clk/qcom/clock-x1e80100.c
index bd9c6ed1c8a0b4ca0b5164d849efa5c0755c1e2e..542d6248d658d2921ef18877c70389549c471ab8 100644
--- a/drivers/clk/qcom/clock-x1e80100.c
+++ b/drivers/clk/qcom/clock-x1e80100.c
@@ -173,11 +173,9 @@ static int x1e80100_enable(struct clk *clk)
 		clk_phy_mux_enable(priv->base, 0x31088, true);
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map x1e80100_gcc_resets[] = {
 	[GCC_AV1E_BCR] = { 0x4a000 },

-- 
2.48.1

Re: [PATCH 1/3] clk/qcom: bubble up qcom_gate_clk_en() errors

[Neil Armstrong]

On 14/03/2025 16:31, Caleb Connolly wrote:
> If we try to enable a gate clock that doesn't exist, we used to just
> fail silently. This may make sense for early bringup of some core
> peripherals that we know are already enabled, but it only makes
> debugging missing clocks more difficult.
> 
> Bubble up errors now that qcom_gate_clk_en() can return an error code to
> catch any still-missing clocks and make it easier to find missing ones
> as more complicated peripherals are enabled.
> 
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>   drivers/clk/qcom/clock-apq8016.c  |  3 +--
>   drivers/clk/qcom/clock-qcm2290.c  |  4 +---
>   drivers/clk/qcom/clock-qcom.h     | 12 +++++++++---
>   drivers/clk/qcom/clock-sa8775p.c  |  4 +---
>   drivers/clk/qcom/clock-sc7280.c   |  4 +---
>   drivers/clk/qcom/clock-sdm845.c   |  4 +---
>   drivers/clk/qcom/clock-sm6115.c   |  4 +---
>   drivers/clk/qcom/clock-sm8150.c   |  4 +---
>   drivers/clk/qcom/clock-sm8250.c   |  4 +---
>   drivers/clk/qcom/clock-sm8550.c   |  4 +---
>   drivers/clk/qcom/clock-sm8650.c   |  4 +---
>   drivers/clk/qcom/clock-x1e80100.c |  4 +---
>   12 files changed, 20 insertions(+), 35 deletions(-)
> 
> diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
> index b5def55dbc2ac671130624dec56592288a0ceb3d..3bafbfea3b6f5bf903f6f5a593e1f062bd40c53a 100644
> --- a/drivers/clk/qcom/clock-apq8016.c
> +++ b/drivers/clk/qcom/clock-apq8016.c
> @@ -144,11 +144,10 @@ static int apq8016_clk_enable(struct clk *clk)
>   		return 0;
>   	}
>   
>   	debug("%s: clk %s\n", __func__, apq8016_clks[clk->id].name);
> -	qcom_gate_clk_en(priv, clk->id);
>   
> -	return 0;
> +	return qcom_gate_clk_en(priv, clk->id);
>   }
>   
>   static struct msm_clk_data apq8016_clk_data = {
>   	.set_rate = apq8016_clk_set_rate,
> diff --git a/drivers/clk/qcom/clock-qcm2290.c b/drivers/clk/qcom/clock-qcm2290.c
> index c78705cb8cf19a75508f5a3a0fbc7c04d750d273..1326b770c3ebd723120de4b6657aafac726023d6 100644
> --- a/drivers/clk/qcom/clock-qcm2290.c
> +++ b/drivers/clk/qcom/clock-qcm2290.c
> @@ -133,11 +133,9 @@ static int qcm2290_enable(struct clk *clk)
>   		qcom_gate_clk_en(priv, GCC_USB3_PRIM_CLKREF_CLK);
>   		break;
>   	}
>   
> -	qcom_gate_clk_en(priv, clk->id);
> -
> -	return 0;
> +	return qcom_gate_clk_en(priv, clk->id);
>   }
>   
>   static const struct qcom_reset_map qcm2290_gcc_resets[] = {
>   	[GCC_CAMSS_OPE_BCR] = { 0x55000 },
> diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
> index ff336dea39cf5cbe35f37f93669285897ba185a4..e9eb659f3ed37522a71e04e9418f48091bf9a0aa 100644
> --- a/drivers/clk/qcom/clock-qcom.h
> +++ b/drivers/clk/qcom/clock-qcom.h
> @@ -6,8 +6,9 @@
>   #define _CLOCK_QCOM_H
>   
>   #include <asm/io.h>
>   #include <linux/bitfield.h>
> +#include <errno.h>
>   
>   #define CFG_CLK_SRC_CXO   (0 << 8)
>   #define CFG_CLK_SRC_GPLL0 (1 << 8)
>   #define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8)
> @@ -104,15 +105,20 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr,
>   void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div,
>   		      int source);
>   void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled);
>   
> -static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
> +static inline int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
>   {
>   	u32 val;
> -	if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0)
> -		return;
> +	if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0) {
> +		log_err("gcc@%#08llx: unknown clock ID %lu!\n",
> +			priv->base, id);
> +		return -ENOENT;
> +	}
>   
>   	val = readl(priv->base + priv->data->clks[id].reg);
>   	writel(val | priv->data->clks[id].en_val, priv->base + priv->data->clks[id].reg);
> +
> +	return 0;
>   }
>   
>   #endif
> diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c
> index e31f24ed4f0ca989f20d1eadcff5f24f173455fa..527cecf5c8282a7c2e16740e6520241a230bca73 100644
> --- a/drivers/clk/qcom/clock-sa8775p.c
> +++ b/drivers/clk/qcom/clock-sa8775p.c
> @@ -72,11 +72,9 @@ static int sa8775p_enable(struct clk *clk)
>   		qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
>   		break;
>   	}
>   
> -	qcom_gate_clk_en(priv, clk->id);
> -
> -	return 0;
> +	return qcom_gate_clk_en(priv, clk->id);
>   }
>   
>   static const struct qcom_reset_map sa8775p_gcc_resets[] = {
>   	[GCC_CAMERA_BCR] = { 0x32000 },
> diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c
> index 5d343f120519da02d8ec3e269d348ab46cde70a8..8ffd1f43f23e51140c7822f0f523fdfd8ab1de7a 100644
> --- a/drivers/clk/qcom/clock-sc7280.c
> +++ b/drivers/clk/qcom/clock-sc7280.c
> @@ -72,11 +72,9 @@ static int sc7280_enable(struct clk *clk)
>   		qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
>   		break;
>   	}
>   
> -	qcom_gate_clk_en(priv, clk->id);
> -
> -	return 0;
> +	return qcom_gate_clk_en(priv, clk->id);
>   }
>   
>   static const struct qcom_reset_map sc7280_gcc_resets[] = {
>   	[GCC_PCIE_0_BCR] = { 0x6b000 },
> diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c
> index adffb0cb2402a6b27e0e998af2f121c519301820..6a0bf16ba2dce7f922adf971817399c71ac35586 100644
> --- a/drivers/clk/qcom/clock-sdm845.c
> +++ b/drivers/clk/qcom/clock-sdm845.c
> @@ -161,11 +161,9 @@ static int sdm845_clk_enable(struct clk *clk)
>   		qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK);
>   		break;
>   	}
>   
> -	qcom_gate_clk_en(priv, clk->id);
> -
> -	return 0;
> +	return qcom_gate_clk_en(priv, clk->id);
>   }
>   
>   static const struct qcom_reset_map sdm845_gcc_resets[] = {
>   	[GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
> diff --git a/drivers/clk/qcom/clock-sm6115.c b/drivers/clk/qcom/clock-sm6115.c
> index 9057dfe0bb1873e9edcfd8c01c0a81b6b8b4ca2c..17c2e5617580aae9ad3f0d802bbc6882c2c81043 100644
> --- a/drivers/clk/qcom/clock-sm6115.c
> +++ b/drivers/clk/qcom/clock-sm6115.c
> @@ -145,11 +145,9 @@ static int sm6115_enable(struct clk *clk)
>   		qcom_gate_clk_en(priv, GCC_USB3_PRIM_CLKREF_CLK);
>   		break;
>   	}
>   
> -	qcom_gate_clk_en(priv, clk->id);
> -
> -	return 0;
> +	return qcom_gate_clk_en(priv, clk->id);
>   }
>   
>   static const struct qcom_reset_map sm6115_gcc_resets[] = {
>   	[GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
> diff --git a/drivers/clk/qcom/clock-sm8150.c b/drivers/clk/qcom/clock-sm8150.c
> index 88f2e678f43cfcc9b80917f26c211049ebca6f9d..7dd0d56eb43031e893541e4031cbda2e92ae402d 100644
> --- a/drivers/clk/qcom/clock-sm8150.c
> +++ b/drivers/clk/qcom/clock-sm8150.c
> @@ -242,11 +242,9 @@ static int sm8150_clk_enable(struct clk *clk)
>   		qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK);
>   		break;
>   	};
>   
> -	qcom_gate_clk_en(priv, clk->id);
> -
> -	return 0;
> +	return qcom_gate_clk_en(priv, clk->id);
>   }
>   
>   static const struct qcom_reset_map sm8150_gcc_resets[] = {
>   	[GCC_EMAC_BCR] = { 0x6000 },
> diff --git a/drivers/clk/qcom/clock-sm8250.c b/drivers/clk/qcom/clock-sm8250.c
> index e322a923a5c048769dd5134c6c24e16bb74e7317..26396847d85964d5056cf9af62b8bc89be34dc43 100644
> --- a/drivers/clk/qcom/clock-sm8250.c
> +++ b/drivers/clk/qcom/clock-sm8250.c
> @@ -194,11 +194,9 @@ static int sm8250_enable(struct clk *clk)
>   		qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK);
>   		break;
>   	}
>   
> -	qcom_gate_clk_en(priv, clk->id);
> -
> -	return 0;
> +	return qcom_gate_clk_en(priv, clk->id);
>   }
>   
>   static const struct qcom_reset_map sm8250_gcc_resets[] = {
>   	[GCC_GPU_BCR] = { 0x71000 },
> diff --git a/drivers/clk/qcom/clock-sm8550.c b/drivers/clk/qcom/clock-sm8550.c
> index 62b5a409e8e08243ad53a0bc58af1c7754a3d950..7c06489b9c4df9ce94fa9b44a762c10133377423 100644
> --- a/drivers/clk/qcom/clock-sm8550.c
> +++ b/drivers/clk/qcom/clock-sm8550.c
> @@ -219,11 +219,9 @@ static int sm8550_enable(struct clk *clk)
>   		clk_phy_mux_enable(priv->base, 0x8d078, true);
>   		break;
>   	}
>   
> -	qcom_gate_clk_en(priv, clk->id);
> -
> -	return 0;
> +	return qcom_gate_clk_en(priv, clk->id);
>   }
>   
>   static const struct qcom_reset_map sm8550_gcc_resets[] = {
>   	[GCC_CAMERA_BCR] = { 0x26000 },
> diff --git a/drivers/clk/qcom/clock-sm8650.c b/drivers/clk/qcom/clock-sm8650.c
> index 9baaecb571f6c575c0e7c48d66214c1331b6642f..364454644a699c495479b3099f590562c415ce82 100644
> --- a/drivers/clk/qcom/clock-sm8650.c
> +++ b/drivers/clk/qcom/clock-sm8650.c
> @@ -216,11 +216,9 @@ static int sm8650_enable(struct clk *clk)
>   		clk_phy_mux_enable(priv->base, 0x8d078, true);
>   		break;
>   	}
>   
> -	qcom_gate_clk_en(priv, clk->id);
> -
> -	return 0;
> +	return qcom_gate_clk_en(priv, clk->id);
>   }
>   
>   static const struct qcom_reset_map sm8650_gcc_resets[] = {
>   	[GCC_CAMERA_BCR] = { 0x26000 },
> diff --git a/drivers/clk/qcom/clock-x1e80100.c b/drivers/clk/qcom/clock-x1e80100.c
> index bd9c6ed1c8a0b4ca0b5164d849efa5c0755c1e2e..542d6248d658d2921ef18877c70389549c471ab8 100644
> --- a/drivers/clk/qcom/clock-x1e80100.c
> +++ b/drivers/clk/qcom/clock-x1e80100.c
> @@ -173,11 +173,9 @@ static int x1e80100_enable(struct clk *clk)
>   		clk_phy_mux_enable(priv->base, 0x31088, true);
>   		break;
>   	}
>   
> -	qcom_gate_clk_en(priv, clk->id);
> -
> -	return 0;
> +	return qcom_gate_clk_en(priv, clk->id);
>   }
>   
>   static const struct qcom_reset_map x1e80100_gcc_resets[] = {
>   	[GCC_AV1E_BCR] = { 0x4a000 },
> 

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

[PATCH 2/3] clk/qcom: sc7280: add some debug data

[Caleb Connolly]

Dump a few PCIe and USB clocks

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 drivers/clk/qcom/clock-sc7280.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c
index 8ffd1f43f23e51140c7822f0f523fdfd8ab1de7a..2cbc01b6e0a4f1db0e4a894cd869b532d6b3fa45 100644
--- a/drivers/clk/qcom/clock-sc7280.c
+++ b/drivers/clk/qcom/clock-sc7280.c
@@ -99,8 +99,20 @@ static const struct qcom_power_map sc7280_gdscs[] = {
 	[GCC_UFS_PHY_GDSC] = { 0x77004 },
 	[GCC_USB30_PRIM_GDSC] = { 0xf004 },
 };
 
+static const phys_addr_t sc7280_rcg_addrs[] = {
+	0x10f020, // USB30_PRIM_MASTER_CLK_CMD_RCGR
+	0x10f038, // USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR
+	0x18d058, // PCIE_1_AUX_CLK_CMD_RCGR
+};
+
+static const char *const sc7280_rcg_names[] = {
+	"USB30_PRIM_MASTER_CLK_SRC",
+	"USB30_PRIM_MOCK_UTMI_CLK_SRC",
+	"GCC_PCIE_1_AUX_CLK_SRC",
+};
+
 static struct msm_clk_data qcs404_gcc_data = {
 	.resets = sc7280_gcc_resets,
 	.num_resets = ARRAY_SIZE(sc7280_gcc_resets),
 	.clks = sc7280_clks,
@@ -110,8 +122,12 @@ static struct msm_clk_data qcs404_gcc_data = {
 	.num_power_domains = ARRAY_SIZE(sc7280_gdscs),
 
 	.enable = sc7280_enable,
 	.set_rate = sc7280_set_rate,
+
+	.dbg_rcg_addrs = sc7280_rcg_addrs,
+	.num_rcgs = ARRAY_SIZE(sc7280_rcg_addrs),
+	.dbg_rcg_names = sc7280_rcg_names,
 };
 
 static const struct udevice_id gcc_sc7280_of_match[] = {
 	{

-- 
2.48.1

Re: [PATCH 2/3] clk/qcom: sc7280: add some debug data

[Neil Armstrong]

On 14/03/2025 16:31, Caleb Connolly wrote:
> Dump a few PCIe and USB clocks
> 
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>   drivers/clk/qcom/clock-sc7280.c | 16 ++++++++++++++++
>   1 file changed, 16 insertions(+)
> 
> diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c
> index 8ffd1f43f23e51140c7822f0f523fdfd8ab1de7a..2cbc01b6e0a4f1db0e4a894cd869b532d6b3fa45 100644
> --- a/drivers/clk/qcom/clock-sc7280.c
> +++ b/drivers/clk/qcom/clock-sc7280.c
> @@ -99,8 +99,20 @@ static const struct qcom_power_map sc7280_gdscs[] = {
>   	[GCC_UFS_PHY_GDSC] = { 0x77004 },
>   	[GCC_USB30_PRIM_GDSC] = { 0xf004 },
>   };
>   
> +static const phys_addr_t sc7280_rcg_addrs[] = {
> +	0x10f020, // USB30_PRIM_MASTER_CLK_CMD_RCGR
> +	0x10f038, // USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR
> +	0x18d058, // PCIE_1_AUX_CLK_CMD_RCGR
> +};
> +
> +static const char *const sc7280_rcg_names[] = {
> +	"USB30_PRIM_MASTER_CLK_SRC",
> +	"USB30_PRIM_MOCK_UTMI_CLK_SRC",
> +	"GCC_PCIE_1_AUX_CLK_SRC",
> +};
> +
>   static struct msm_clk_data qcs404_gcc_data = {
>   	.resets = sc7280_gcc_resets,
>   	.num_resets = ARRAY_SIZE(sc7280_gcc_resets),
>   	.clks = sc7280_clks,
> @@ -110,8 +122,12 @@ static struct msm_clk_data qcs404_gcc_data = {
>   	.num_power_domains = ARRAY_SIZE(sc7280_gdscs),
>   
>   	.enable = sc7280_enable,
>   	.set_rate = sc7280_set_rate,
> +
> +	.dbg_rcg_addrs = sc7280_rcg_addrs,
> +	.num_rcgs = ARRAY_SIZE(sc7280_rcg_addrs),
> +	.dbg_rcg_names = sc7280_rcg_names,
>   };
>   
>   static const struct udevice_id gcc_sc7280_of_match[] = {
>   	{
> 

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

[PATCH 3/3] clk/qcom: sc7280: add GENI, PCIe, and more USB clocks

[Caleb Connolly]

Add support for a bunch of new clocks, including PCIe, GENI (for all
peripherals used on the RB3 Gen 2), and some missing USB clocks.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 drivers/clk/qcom/clock-sc7280.c | 104 +++++++++++++++++++++++++++++++++++-----
 1 file changed, 93 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c
index 2cbc01b6e0a4f1db0e4a894cd869b532d6b3fa45..8691f08109b39639d8a5defe75161049399bf682 100644
--- a/drivers/clk/qcom/clock-sc7280.c
+++ b/drivers/clk/qcom/clock-sc7280.c
@@ -15,31 +15,66 @@
 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
 
 #include "clock-qcom.h"
 
-#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
 #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020
+#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
+#define USB30_SEC_MASTER_CLK_CMD_RCGR 0x9e020
+#define USB30_SEC_MOCK_UTMI_CLK_CMD_RCGR 0x9e038
+#define PCIE_1_AUX_CLK_CMD_RCGR 0x8d058
+#define PCIE1_PHY_RCHNG_CMD_RCGR 0x8d03c
+#define PCIE_1_PIPE_CLK_PHY_MUX 0x8d054
+
+static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
+	F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
+	F(133333333, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
+	F(200000000, CFG_CLK_SRC_GPLL0_ODD, 1, 0, 0),
+	F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0),
+	{ }
+};
+
+static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk_src[] = {
+	F(60000000, CFG_CLK_SRC_GPLL0_EVEN, 5, 0, 0),
+	F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0),
+	{ }
+};
 
 static ulong sc7280_set_rate(struct clk *clk, ulong rate)
 {
 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+	const struct freq_tbl *freq;
 
 	if (clk->id < priv->data->num_clks)
 		debug("%s: %s, requested rate=%ld\n", __func__, priv->data->clks[clk->id].name, rate);
 
 	switch (clk->id) {
-	case GCC_USB30_PRIM_MOCK_UTMI_CLK:
-		WARN(rate != 19200000, "Unexpected rate for USB30_PRIM_MOCK_UTMI_CLK: %lu\n", rate);
-		clk_rcg_set_rate(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
-		return rate;
 	case GCC_USB30_PRIM_MASTER_CLK:
-		WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate);
+		freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate);
 		clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
-				     1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8);
-		clk_rcg_set_rate(priv->base, 0xf064, 0, 0);
-		return rate;
+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
+		return freq->freq;
+	case GCC_USB30_PRIM_MOCK_UTMI_CLK:
+		clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
+		return 19200000;
+	case GCC_USB3_PRIM_PHY_AUX_CLK_SRC:
+		clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
+		return 19200000;
+	case GCC_USB30_SEC_MASTER_CLK:
+		freq = qcom_find_freq(ftbl_gcc_usb30_sec_master_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, USB30_SEC_MASTER_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
+		return freq->freq;
+	case GCC_USB30_SEC_MOCK_UTMI_CLK:
+		clk_rcg_set_rate(priv->base, USB30_SEC_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
+		return 19200000;
+	case GCC_USB3_SEC_PHY_AUX_CLK_SRC:
+		clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
+		return 19200000;
+	case GCC_PCIE1_PHY_RCHNG_CLK:
+		clk_rcg_set_rate(priv->base, PCIE1_PHY_RCHNG_CMD_RCGR, 5, CFG_CLK_SRC_GPLL0_EVEN);
+		return 100000000;
 	default:
-		return 0;
+		return rate;
 	}
 }
 
 static const struct gate_clk sc7280_clks[] = {
@@ -49,15 +84,37 @@ static const struct gate_clk sc7280_clks[] = {
 	GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0xf018, 1),
 	GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0xf01c, 1),
 	GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf054, 1),
 	GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf058, 1),
+	GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x9e07c, 1),
+	GATE_CLK(GCC_USB30_SEC_MASTER_CLK, 0x9e010, 1),
+	GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x9e080, 1),
+	GATE_CLK(GCC_USB30_SEC_SLEEP_CLK, 0x9e018, 1),
+	GATE_CLK(GCC_USB30_SEC_MOCK_UTMI_CLK, 0x9e01c, 1),
+	GATE_CLK(GCC_USB3_SEC_PHY_AUX_CLK, 0x9e054, 1),
+	GATE_CLK(GCC_USB3_SEC_PHY_COM_AUX_CLK, 0x9e058, 1),
+	GATE_CLK(GCC_PCIE_CLKREF_EN, 0x8c004, 1),
+	GATE_CLK(GCC_PCIE_1_PIPE_CLK, 0x52000, BIT(30)),
+	GATE_CLK(GCC_PCIE_1_AUX_CLK, 0x52000, BIT(29)),
+	GATE_CLK(GCC_PCIE_1_CFG_AHB_CLK, 0x52000, BIT(28)),
+	GATE_CLK(GCC_PCIE_1_MSTR_AXI_CLK, 0x52000, BIT(27)),
+	GATE_CLK(GCC_PCIE_1_SLV_AXI_CLK, 0x52000, BIT(26)),
+	GATE_CLK(GCC_PCIE_1_SLV_Q2A_AXI_CLK, 0x52000, BIT(25)),
+	GATE_CLK(GCC_PCIE1_PHY_RCHNG_CLK, 0x52000, BIT(23)),
+	GATE_CLK(GCC_DDRSS_PCIE_SF_CLK, 0x52000, BIT(19)),
+	GATE_CLK(GCC_AGGRE_NOC_PCIE_TBU_CLK, 0x52000, BIT(18)),
+	GATE_CLK(GCC_AGGRE_NOC_PCIE_1_AXI_CLK, 0x52000, BIT(11)),
+	GATE_CLK(GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK, 0x52008, BIT(28)),
+	GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x52008, BIT(10)),
+	GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x52008, BIT(11)),
+	GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x52008, BIT(13)),
 };
 
 static int sc7280_enable(struct clk *clk)
 {
 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
 
-	if (priv->data->num_clks < clk->id) {
+	if (priv->data->num_clks <= clk->id) {
 		debug("%s: unknown clk id %lu\n", __func__, clk->id);
 		return 0;
 	}
 
@@ -70,8 +127,31 @@ static int sc7280_enable(struct clk *clk)
 	case GCC_USB30_PRIM_MASTER_CLK:
 		qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
 		qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
 		break;
+	case GCC_AGGRE_USB3_SEC_AXI_CLK:
+		qcom_gate_clk_en(priv, GCC_USB30_SEC_MASTER_CLK);
+		fallthrough;
+	case GCC_USB30_SEC_MASTER_CLK:
+		qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK);
+		qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK);
+		break;
+	case GCC_PCIE_1_PIPE_CLK:
+		clk_phy_mux_enable(priv->base, PCIE_1_PIPE_CLK_PHY_MUX, true);
+		break;
+	case GCC_PCIE_1_AUX_CLK:
+		clk_rcg_set_rate_mnd(priv->base, PCIE_1_AUX_CLK_CMD_RCGR, 1, 0, 0,
+				     CFG_CLK_SRC_CXO, 16);
+		break;
+	case GCC_QUPV3_WRAP0_S0_CLK:
+		clk_rcg_set_rate_mnd(priv->base, 0x17010, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
+		break;
+	case GCC_QUPV3_WRAP0_S1_CLK:
+		clk_rcg_set_rate_mnd(priv->base, 0x17140, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
+		break;
+	case GCC_QUPV3_WRAP0_S3_CLK:
+		clk_rcg_set_rate_mnd(priv->base, 0x173a0, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
+		break;
 	}
 
 	return qcom_gate_clk_en(priv, clk->id);
 }
@@ -97,8 +177,10 @@ static const struct qcom_reset_map sc7280_gcc_resets[] = {
 
 static const struct qcom_power_map sc7280_gdscs[] = {
 	[GCC_UFS_PHY_GDSC] = { 0x77004 },
 	[GCC_USB30_PRIM_GDSC] = { 0xf004 },
+	[GCC_USB30_SEC_GDSC] = { 0x9e004 },
+	[GCC_PCIE_1_GDSC] = { 0x8d004 },
 };
 
 static const phys_addr_t sc7280_rcg_addrs[] = {
 	0x10f020, // USB30_PRIM_MASTER_CLK_CMD_RCGR

-- 
2.48.1

Re: [PATCH 3/3] clk/qcom: sc7280: add GENI, PCIe, and more USB clocks

[Neil Armstrong]

On 14/03/2025 16:31, Caleb Connolly wrote:
> Add support for a bunch of new clocks, including PCIe, GENI (for all
> peripherals used on the RB3 Gen 2), and some missing USB clocks.
> 
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>   drivers/clk/qcom/clock-sc7280.c | 104 +++++++++++++++++++++++++++++++++++-----
>   1 file changed, 93 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c
> index 2cbc01b6e0a4f1db0e4a894cd869b532d6b3fa45..8691f08109b39639d8a5defe75161049399bf682 100644
> --- a/drivers/clk/qcom/clock-sc7280.c
> +++ b/drivers/clk/qcom/clock-sc7280.c
> @@ -15,31 +15,66 @@
>   #include <dt-bindings/clock/qcom,gcc-sc7280.h>
>   
>   #include "clock-qcom.h"
>   
> -#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
>   #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020
> +#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
> +#define USB30_SEC_MASTER_CLK_CMD_RCGR 0x9e020
> +#define USB30_SEC_MOCK_UTMI_CLK_CMD_RCGR 0x9e038
> +#define PCIE_1_AUX_CLK_CMD_RCGR 0x8d058
> +#define PCIE1_PHY_RCHNG_CMD_RCGR 0x8d03c
> +#define PCIE_1_PIPE_CLK_PHY_MUX 0x8d054
> +
> +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
> +	F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
> +	F(133333333, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
> +	F(200000000, CFG_CLK_SRC_GPLL0_ODD, 1, 0, 0),
> +	F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0),
> +	{ }
> +};
> +
> +static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk_src[] = {
> +	F(60000000, CFG_CLK_SRC_GPLL0_EVEN, 5, 0, 0),
> +	F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0),
> +	{ }
> +};
>   
>   static ulong sc7280_set_rate(struct clk *clk, ulong rate)
>   {
>   	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> +	const struct freq_tbl *freq;
>   
>   	if (clk->id < priv->data->num_clks)
>   		debug("%s: %s, requested rate=%ld\n", __func__, priv->data->clks[clk->id].name, rate);
>   
>   	switch (clk->id) {
> -	case GCC_USB30_PRIM_MOCK_UTMI_CLK:
> -		WARN(rate != 19200000, "Unexpected rate for USB30_PRIM_MOCK_UTMI_CLK: %lu\n", rate);
> -		clk_rcg_set_rate(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
> -		return rate;
>   	case GCC_USB30_PRIM_MASTER_CLK:
> -		WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate);
> +		freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate);
>   		clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
> -				     1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8);
> -		clk_rcg_set_rate(priv->base, 0xf064, 0, 0);
> -		return rate;
> +				     freq->pre_div, freq->m, freq->n, freq->src, 8);
> +		return freq->freq;
> +	case GCC_USB30_PRIM_MOCK_UTMI_CLK:
> +		clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
> +		return 19200000;
> +	case GCC_USB3_PRIM_PHY_AUX_CLK_SRC:
> +		clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
> +		return 19200000;
> +	case GCC_USB30_SEC_MASTER_CLK:
> +		freq = qcom_find_freq(ftbl_gcc_usb30_sec_master_clk_src, rate);
> +		clk_rcg_set_rate_mnd(priv->base, USB30_SEC_MASTER_CLK_CMD_RCGR,
> +				     freq->pre_div, freq->m, freq->n, freq->src, 8);
> +		return freq->freq;
> +	case GCC_USB30_SEC_MOCK_UTMI_CLK:
> +		clk_rcg_set_rate(priv->base, USB30_SEC_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
> +		return 19200000;
> +	case GCC_USB3_SEC_PHY_AUX_CLK_SRC:
> +		clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
> +		return 19200000;
> +	case GCC_PCIE1_PHY_RCHNG_CLK:
> +		clk_rcg_set_rate(priv->base, PCIE1_PHY_RCHNG_CMD_RCGR, 5, CFG_CLK_SRC_GPLL0_EVEN);
> +		return 100000000;
>   	default:
> -		return 0;
> +		return rate;
>   	}
>   }
>   
>   static const struct gate_clk sc7280_clks[] = {
> @@ -49,15 +84,37 @@ static const struct gate_clk sc7280_clks[] = {
>   	GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0xf018, 1),
>   	GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0xf01c, 1),
>   	GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf054, 1),
>   	GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf058, 1),
> +	GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x9e07c, 1),
> +	GATE_CLK(GCC_USB30_SEC_MASTER_CLK, 0x9e010, 1),
> +	GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x9e080, 1),
> +	GATE_CLK(GCC_USB30_SEC_SLEEP_CLK, 0x9e018, 1),
> +	GATE_CLK(GCC_USB30_SEC_MOCK_UTMI_CLK, 0x9e01c, 1),
> +	GATE_CLK(GCC_USB3_SEC_PHY_AUX_CLK, 0x9e054, 1),
> +	GATE_CLK(GCC_USB3_SEC_PHY_COM_AUX_CLK, 0x9e058, 1),
> +	GATE_CLK(GCC_PCIE_CLKREF_EN, 0x8c004, 1),
> +	GATE_CLK(GCC_PCIE_1_PIPE_CLK, 0x52000, BIT(30)),
> +	GATE_CLK(GCC_PCIE_1_AUX_CLK, 0x52000, BIT(29)),
> +	GATE_CLK(GCC_PCIE_1_CFG_AHB_CLK, 0x52000, BIT(28)),
> +	GATE_CLK(GCC_PCIE_1_MSTR_AXI_CLK, 0x52000, BIT(27)),
> +	GATE_CLK(GCC_PCIE_1_SLV_AXI_CLK, 0x52000, BIT(26)),
> +	GATE_CLK(GCC_PCIE_1_SLV_Q2A_AXI_CLK, 0x52000, BIT(25)),
> +	GATE_CLK(GCC_PCIE1_PHY_RCHNG_CLK, 0x52000, BIT(23)),
> +	GATE_CLK(GCC_DDRSS_PCIE_SF_CLK, 0x52000, BIT(19)),
> +	GATE_CLK(GCC_AGGRE_NOC_PCIE_TBU_CLK, 0x52000, BIT(18)),
> +	GATE_CLK(GCC_AGGRE_NOC_PCIE_1_AXI_CLK, 0x52000, BIT(11)),
> +	GATE_CLK(GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK, 0x52008, BIT(28)),
> +	GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x52008, BIT(10)),
> +	GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x52008, BIT(11)),
> +	GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x52008, BIT(13)),
>   };
>   
>   static int sc7280_enable(struct clk *clk)
>   {
>   	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
>   
> -	if (priv->data->num_clks < clk->id) {
> +	if (priv->data->num_clks <= clk->id) {
>   		debug("%s: unknown clk id %lu\n", __func__, clk->id);
>   		return 0;
>   	}
>   
> @@ -70,8 +127,31 @@ static int sc7280_enable(struct clk *clk)
>   	case GCC_USB30_PRIM_MASTER_CLK:
>   		qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
>   		qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
>   		break;
> +	case GCC_AGGRE_USB3_SEC_AXI_CLK:
> +		qcom_gate_clk_en(priv, GCC_USB30_SEC_MASTER_CLK);
> +		fallthrough;
> +	case GCC_USB30_SEC_MASTER_CLK:
> +		qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK);
> +		qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK);
> +		break;
> +	case GCC_PCIE_1_PIPE_CLK:
> +		clk_phy_mux_enable(priv->base, PCIE_1_PIPE_CLK_PHY_MUX, true);
> +		break;
> +	case GCC_PCIE_1_AUX_CLK:
> +		clk_rcg_set_rate_mnd(priv->base, PCIE_1_AUX_CLK_CMD_RCGR, 1, 0, 0,
> +				     CFG_CLK_SRC_CXO, 16);
> +		break;
> +	case GCC_QUPV3_WRAP0_S0_CLK:
> +		clk_rcg_set_rate_mnd(priv->base, 0x17010, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
> +		break;
> +	case GCC_QUPV3_WRAP0_S1_CLK:
> +		clk_rcg_set_rate_mnd(priv->base, 0x17140, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
> +		break;
> +	case GCC_QUPV3_WRAP0_S3_CLK:
> +		clk_rcg_set_rate_mnd(priv->base, 0x173a0, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
> +		break;
>   	}
>   
>   	return qcom_gate_clk_en(priv, clk->id);
>   }
> @@ -97,8 +177,10 @@ static const struct qcom_reset_map sc7280_gcc_resets[] = {
>   
>   static const struct qcom_power_map sc7280_gdscs[] = {
>   	[GCC_UFS_PHY_GDSC] = { 0x77004 },
>   	[GCC_USB30_PRIM_GDSC] = { 0xf004 },
> +	[GCC_USB30_SEC_GDSC] = { 0x9e004 },
> +	[GCC_PCIE_1_GDSC] = { 0x8d004 },
>   };
>   
>   static const phys_addr_t sc7280_rcg_addrs[] = {
>   	0x10f020, // USB30_PRIM_MASTER_CLK_CMD_RCGR
> 

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>