[U-Boot] [PATCH v2 0/8] x86: quark: Add ACPI support

[U-Boot] [PATCH v2 0/8] x86: quark: Add ACPI support

[Bin Meng]

This series adds basic ACPI support to Intel Quark platform, enables
the support on the Intel Galileo board.

Testing was performed by booting Linux kernel from an SD card. All
interrupts are routed to I/O APIC based on information provided in
the ACPI tables, and typing 'reboot' from shell can successfully
reboot to U-Boot.

This series is available at u-boot-x86/quark-acpi.

Changes in v2:
- Use __ASSEMBLY__ define
- Use __ASSEMBLY__ in device.h

Bin Meng (8):
  x86: acpi: Create a common irqlinks ASL file
  x86: acpi: Make irqroute.asl common
  acpi: Pass -D__ASSEMBLY__ when compiling ASL files
  x86: quark: Prepare device.h for inclusion by ASL
  x86: quark: Add platform ASL files
  x86: quark: Generate ACPI FADT/MADT tables
  x86: galileo: Enable ACPI table generation
  x86: baytrail: acpi: Fix I/O APIC ID in the MADT table

 arch/x86/cpu/baytrail/acpi.c                       |   2 +-
 arch/x86/cpu/quark/Makefile                        |   1 +
 arch/x86/cpu/quark/acpi.c                          | 163 ++++++++++++++++++
 .../asm/{arch-baytrail => }/acpi/irq_helper.h      |   2 +-
 .../asm/{arch-baytrail => }/acpi/irqlinks.asl      |  33 ++--
 .../asm/{arch-baytrail => }/acpi/irqroute.asl      |   0
 arch/x86/include/asm/arch-baytrail/acpi/lpc.asl    |  23 ++-
 .../asm/arch-baytrail/acpi/southcluster.asl        |   2 +-
 arch/x86/include/asm/arch-quark/acpi/irqroute.h    |  15 ++
 arch/x86/include/asm/arch-quark/acpi/lpc.asl       | 125 ++++++++++++++
 arch/x86/include/asm/arch-quark/acpi/platform.asl  |  33 ++++
 .../include/asm/arch-quark/acpi/sleepstates.asl    |  10 ++
 .../include/asm/arch-quark/acpi/southcluster.asl   | 184 +++++++++++++++++++++
 arch/x86/include/asm/arch-quark/device.h           |  21 ++-
 arch/x86/include/asm/arch-quark/iomap.h            |  47 ++++++
 arch/x86/include/asm/arch-quark/irq.h              |  19 +++
 board/intel/galileo/.gitignore                     |   3 +
 board/intel/galileo/Makefile                       |   1 +
 board/intel/galileo/acpi/mainboard.asl             |  11 ++
 board/intel/galileo/dsdt.asl                       |  14 ++
 configs/galileo_defconfig                          |   1 +
 doc/README.x86                                     |   5 +-
 scripts/Makefile.lib                               |   2 +-
 23 files changed, 685 insertions(+), 32 deletions(-)
 create mode 100644 arch/x86/cpu/quark/acpi.c
 rename arch/x86/include/asm/{arch-baytrail => }/acpi/irq_helper.h (98%)
 rename arch/x86/include/asm/{arch-baytrail => }/acpi/irqlinks.asl (92%)
 rename arch/x86/include/asm/{arch-baytrail => }/acpi/irqroute.asl (100%)
 create mode 100644 arch/x86/include/asm/arch-quark/acpi/irqroute.h
 create mode 100644 arch/x86/include/asm/arch-quark/acpi/lpc.asl
 create mode 100644 arch/x86/include/asm/arch-quark/acpi/platform.asl
 create mode 100644 arch/x86/include/asm/arch-quark/acpi/sleepstates.asl
 create mode 100644 arch/x86/include/asm/arch-quark/acpi/southcluster.asl
 create mode 100644 arch/x86/include/asm/arch-quark/iomap.h
 create mode 100644 arch/x86/include/asm/arch-quark/irq.h
 create mode 100644 board/intel/galileo/.gitignore
 create mode 100644 board/intel/galileo/acpi/mainboard.asl
 create mode 100644 board/intel/galileo/dsdt.asl

-- 
1.8.2.1

[U-Boot] [PATCH v2 1/8] x86: acpi: Create a common irqlinks ASL file

[Bin Meng]

Move the irqlinks.asl file currently in the BayTrail directory to
a common place to be shared among all x86 platforms. As the PIRQ
routing control programming interface is common to Intel chipsets,
leave the common part in the common file, and move the platform
specific part to the platform files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 .../asm/{arch-baytrail => }/acpi/irqlinks.asl      | 33 +++++++++-------------
 arch/x86/include/asm/arch-baytrail/acpi/lpc.asl    | 23 ++++++++++++++-
 2 files changed, 35 insertions(+), 21 deletions(-)
 rename arch/x86/include/asm/{arch-baytrail => }/acpi/irqlinks.asl (92%)

diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl b/arch/x86/include/asm/acpi/irqlinks.asl
similarity index 92%
rename from arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
rename to arch/x86/include/asm/acpi/irqlinks.asl
index 0affa23..84c1e53 100644
--- a/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
+++ b/arch/x86/include/asm/acpi/irqlinks.asl
@@ -7,26 +7,19 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-Scope (\)
-{
-	/* Intel Legacy Block */
-	OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
-	Field(ILBS, AnyAcc, NoLock, Preserve) {
-		Offset (0x8),
-		PRTA, 8,
-		PRTB, 8,
-		PRTC, 8,
-		PRTD, 8,
-		PRTE, 8,
-		PRTF, 8,
-		PRTG, 8,
-		PRTH, 8,
-		Offset (0x88),
-		    , 3,
-		UI3E, 1,
-		UI4E, 1
-	}
-}
+/*
+ * Intel chipset PIRQ routing control ASL description
+ *
+ * The programming interface is common to most Intel chipsets. But the PRTx
+ * registers may be mapped to different blocks. Some chipsets map them to LPC
+ * device (00:1f:00) PCI configuration space (like TunnelCreek, Quark), while
+ * some newer Atom SoCs (like BayTrail, Braswell) map them to Intel Legacy
+ * Block (ILB) memory space.
+ *
+ * This file defines 8 PCI IRQ link devices which corresponds to 8 PIRQ lines
+ * PIRQ A/B/C/D/E/F/G/H. To incorperate this file, the PRTx registers must be
+ * defined somewhere else in the platform's ASL files.
+ */
 
 Device (LNKA)
 {
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
index 385671c..22f0d68 100644
--- a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
+++ b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
@@ -10,6 +10,27 @@
 
 /* Intel LPC Bus Device - 0:1f.0 */
 
+Scope (\)
+{
+	/* Intel Legacy Block */
+	OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+	Field(ILBS, AnyAcc, NoLock, Preserve) {
+		Offset (0x8),
+		PRTA, 8,
+		PRTB, 8,
+		PRTC, 8,
+		PRTD, 8,
+		PRTE, 8,
+		PRTF, 8,
+		PRTG, 8,
+		PRTH, 8,
+		Offset (0x88),
+		    , 3,
+		UI3E, 1,
+		UI4E, 1
+	}
+}
+
 Device (LPCB)
 {
 	Name(_ADR, 0x001f0000)
@@ -23,7 +44,7 @@ Device (LPCB)
 		Offset(0x84)
 	}
 
-	#include "irqlinks.asl"
+	#include <asm/acpi/irqlinks.asl>
 
 	/* Firmware Hub */
 	Device (FWH)
-- 
1.8.2.1

[U-Boot] [PATCH v2 1/8] x86: acpi: Create a common irqlinks ASL file

[Bin Meng]

On Thu, May 26, 2016 at 10:19 AM, Bin Meng <bmeng.cn@gmail.com> wrote:
> Move the irqlinks.asl file currently in the BayTrail directory to
> a common place to be shared among all x86 platforms. As the PIRQ
> routing control programming interface is common to Intel chipsets,
> leave the common part in the common file, and move the platform
> specific part to the platform files.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  .../asm/{arch-baytrail => }/acpi/irqlinks.asl      | 33 +++++++++-------------
>  arch/x86/include/asm/arch-baytrail/acpi/lpc.asl    | 23 ++++++++++++++-
>  2 files changed, 35 insertions(+), 21 deletions(-)
>  rename arch/x86/include/asm/{arch-baytrail => }/acpi/irqlinks.asl (92%)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v2 2/8] x86: acpi: Make irqroute.asl common

[Bin Meng]

The irqroute.asl file is already common enough to all x86 platforms.
Platform ASL files need only provide a irqroute.h to describe how
internal PCI devices and PCIe downstream port devices' INTx pins are
routed to which PIRQ pin.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/x86/include/asm/{arch-baytrail => }/acpi/irq_helper.h | 2 +-
 arch/x86/include/asm/{arch-baytrail => }/acpi/irqroute.asl | 0
 arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl   | 2 +-
 3 files changed, 2 insertions(+), 2 deletions(-)
 rename arch/x86/include/asm/{arch-baytrail => }/acpi/irq_helper.h (98%)
 rename arch/x86/include/asm/{arch-baytrail => }/acpi/irqroute.asl (100%)

diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h b/arch/x86/include/asm/acpi/irq_helper.h
similarity index 98%
rename from arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h
rename to arch/x86/include/asm/acpi/irq_helper.h
index 2c3585a..f0b3a6b 100644
--- a/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h
+++ b/arch/x86/include/asm/acpi/irq_helper.h
@@ -108,4 +108,4 @@ Device (prefix_ ## 0 ## func_) \
 }
 
 /* SoC specific PIRQ route configuration */
-#include "irqroute.h"
+#include <asm/arch/acpi/irqroute.h>
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl b/arch/x86/include/asm/acpi/irqroute.asl
similarity index 100%
rename from arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl
rename to arch/x86/include/asm/acpi/irqroute.asl
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
index 34d3951..e89ff26 100644
--- a/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
+++ b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
@@ -207,5 +207,5 @@ Device (PCI0)
 	#include "xhci.asl"
 
 	/* IRQ routing for each PCI device */
-	#include "irqroute.asl"
+	#include <asm/acpi/irqroute.asl>
 }
-- 
1.8.2.1

[U-Boot] [PATCH v2 2/8] x86: acpi: Make irqroute.asl common

[Bin Meng]

On Thu, May 26, 2016 at 10:19 AM, Bin Meng <bmeng.cn@gmail.com> wrote:
> The irqroute.asl file is already common enough to all x86 platforms.
> Platform ASL files need only provide a irqroute.h to describe how
> internal PCI devices and PCIe downstream port devices' INTx pins are
> routed to which PIRQ pin.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  arch/x86/include/asm/{arch-baytrail => }/acpi/irq_helper.h | 2 +-
>  arch/x86/include/asm/{arch-baytrail => }/acpi/irqroute.asl | 0
>  arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl   | 2 +-
>  3 files changed, 2 insertions(+), 2 deletions(-)
>  rename arch/x86/include/asm/{arch-baytrail => }/acpi/irq_helper.h (98%)
>  rename arch/x86/include/asm/{arch-baytrail => }/acpi/irqroute.asl (100%)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v2 3/8] acpi: Pass -D__ASSEMBLY__ when compiling ASL files

[Bin Meng]

ASL files may include various U-Boot header files, but IASL compiler
does not understand any C language embedded in these header files.
To reuse those header files for ASL compiling, use __ASSEMBLY__ in
the header files to exclude everything that is not liked by IASL.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

---

Changes in v2:
- Use __ASSEMBLY__ define

 scripts/Makefile.lib | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 97a09a2..e720562 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -325,7 +325,7 @@ $(obj)/%.S: $(src)/%.ttf
 # ---------------------------------------------------------------------------
 quiet_cmd_acpi_c_asl= ASL     $<
 cmd_acpi_c_asl=         \
-	$(CPP) -x assembler-with-cpp -P $(UBOOTINCLUDE) -o $<.tmp $<; \
+	$(CPP) -x assembler-with-cpp -D__ASSEMBLY__ -P $(UBOOTINCLUDE) -o $<.tmp $<; \
 	iasl -p $< -tc $<.tmp $(if $(KBUILD_VERBOSE:1=), >/dev/null); \
 	mv $(patsubst %.asl,%.hex,$<) $@
 
-- 
1.8.2.1

[U-Boot] [PATCH v2 3/8] acpi: Pass -D__ASSEMBLY__ when compiling ASL files

[Bin Meng]

On Thu, May 26, 2016 at 10:19 AM, Bin Meng <bmeng.cn@gmail.com> wrote:
> ASL files may include various U-Boot header files, but IASL compiler
> does not understand any C language embedded in these header files.
> To reuse those header files for ASL compiling, use __ASSEMBLY__ in
> the header files to exclude everything that is not liked by IASL.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
>
> ---
>
> Changes in v2:
> - Use __ASSEMBLY__ define
>
>  scripts/Makefile.lib | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v2 4/8] x86: quark: Prepare device.h for inclusion by ASL

[Bin Meng]

There is a device.h for quark on-chip devices, mainly for definitions
of internal PCI device numbers, but it's not ready to be included by
ASL files. Update to use hex numbers for PCI dev and __ASSEMBLY__.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

---

Changes in v2:
- Use __ASSEMBLY__ in device.h

 arch/x86/include/asm/arch-quark/device.h | 21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/arch/x86/include/asm/arch-quark/device.h b/arch/x86/include/asm/arch-quark/device.h
index 7882f33..4760aa2 100644
--- a/arch/x86/include/asm/arch-quark/device.h
+++ b/arch/x86/include/asm/arch-quark/device.h
@@ -7,12 +7,17 @@
 #ifndef _QUARK_DEVICE_H_
 #define _QUARK_DEVICE_H_
 
-#include <pci.h>
+/*
+ * Internal PCI device numbers within the SoC.
+ *
+ * Note it must start with 0x_ prefix, as the device number macro will be
+ * included in the ACPI ASL files (see irq_helper.h and irq_route.h).
+ */
 
-#define QUARK_HOST_BRIDGE_DEV	0
+#define QUARK_HOST_BRIDGE_DEV	0x00
 #define QUARK_HOST_BRIDGE_FUNC	0
 
-#define QUARK_DEV_20		20
+#define QUARK_DEV_20		0x14
 #define QUARK_MMC_SDIO_FUNC	0
 #define QUARK_UART0_FUNC	1
 #define QUARK_USB_DEVICE_FUNC	2
@@ -22,18 +27,21 @@
 #define QUARK_EMAC0_FUNC	6
 #define QUARK_EMAC1_FUNC	7
 
-#define QUARK_DEV_21		21
+#define QUARK_DEV_21		0x15
 #define QUARK_SPI0_FUNC		0
 #define QUARK_SPI1_FUNC		1
 #define QUARK_I2C_GPIO_FUNC	2
 
-#define QUARK_DEV_23		23
+#define QUARK_DEV_23		0x17
 #define QUARK_PCIE0_FUNC	0
 #define QUARK_PCIE1_FUNC	1
 
-#define QUARK_LGC_BRIDGE_DEV	31
+#define QUARK_LGC_BRIDGE_DEV	0x1f
 #define QUARK_LGC_BRIDGE_FUNC	0
 
+#ifndef __ASSEMBLY__
+#include <pci.h>
+
 #define QUARK_HOST_BRIDGE	\
 	PCI_BDF(0, QUARK_HOST_BRIDGE_DEV, QUARK_HOST_BRIDGE_FUNC)
 #define QUARK_MMC_SDIO		\
@@ -64,5 +72,6 @@
 	PCI_BDF(0, QUARK_DEV_23, QUARK_PCIE1_FUNC)
 #define QUARK_LEGACY_BRIDGE	\
 	PCI_BDF(0, QUARK_LGC_BRIDGE_DEV, QUARK_LGC_BRIDGE_FUNC)
+#endif /* __ASSEMBLY__ */
 
 #endif /* _QUARK_DEVICE_H_ */
-- 
1.8.2.1

[U-Boot] [PATCH v2 4/8] x86: quark: Prepare device.h for inclusion by ASL

[Bin Meng]

On Thu, May 26, 2016 at 10:19 AM, Bin Meng <bmeng.cn@gmail.com> wrote:
> There is a device.h for quark on-chip devices, mainly for definitions
> of internal PCI device numbers, but it's not ready to be included by
> ASL files. Update to use hex numbers for PCI dev and __ASSEMBLY__.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
>
> ---
>
> Changes in v2:
> - Use __ASSEMBLY__ in device.h
>
>  arch/x86/include/asm/arch-quark/device.h | 21 +++++++++++++++------
>  1 file changed, 15 insertions(+), 6 deletions(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v2 5/8] x86: quark: Add platform ASL files

[Bin Meng]

This adds basic quark platform ASL files. They are intended to be
included in dsdt.asl of any board that is based on this platform.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/x86/include/asm/arch-quark/acpi/irqroute.h    |  15 ++
 arch/x86/include/asm/arch-quark/acpi/lpc.asl       | 125 ++++++++++++++
 arch/x86/include/asm/arch-quark/acpi/platform.asl  |  33 ++++
 .../include/asm/arch-quark/acpi/sleepstates.asl    |  10 ++
 .../include/asm/arch-quark/acpi/southcluster.asl   | 184 +++++++++++++++++++++
 arch/x86/include/asm/arch-quark/iomap.h            |  47 ++++++
 arch/x86/include/asm/arch-quark/irq.h              |  19 +++
 7 files changed, 433 insertions(+)
 create mode 100644 arch/x86/include/asm/arch-quark/acpi/irqroute.h
 create mode 100644 arch/x86/include/asm/arch-quark/acpi/lpc.asl
 create mode 100644 arch/x86/include/asm/arch-quark/acpi/platform.asl
 create mode 100644 arch/x86/include/asm/arch-quark/acpi/sleepstates.asl
 create mode 100644 arch/x86/include/asm/arch-quark/acpi/southcluster.asl
 create mode 100644 arch/x86/include/asm/arch-quark/iomap.h
 create mode 100644 arch/x86/include/asm/arch-quark/irq.h

diff --git a/arch/x86/include/asm/arch-quark/acpi/irqroute.h b/arch/x86/include/asm/arch-quark/acpi/irqroute.h
new file mode 100644
index 0000000..5ba31da
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/irqroute.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/device.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+	PCI_DEV_PIRQ_ROUTE(QUARK_DEV_20, E, F, G, H), \
+	PCI_DEV_PIRQ_ROUTE(QUARK_DEV_21, E, F, G, H), \
+	PCI_DEV_PIRQ_ROUTE(QUARK_DEV_23, A, B, C, D)
+
+#define PCIE_BRIDGE_IRQ_ROUTES \
+	PCIE_BRIDGE_DEV(RP, QUARK_DEV_23, A, B, C, D)
diff --git a/arch/x86/include/asm/arch-quark/acpi/lpc.asl b/arch/x86/include/asm/arch-quark/acpi/lpc.asl
new file mode 100644
index 0000000..c3b0b1d
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/lpc.asl
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Intel LPC Bus Device - 0:1f.0 */
+
+Device (LPCB)
+{
+	Name(_ADR, 0x001f0000)
+
+	OperationRegion(PRTX, PCI_Config, 0x60, 8)
+	Field(PRTX, AnyAcc, NoLock, Preserve) {
+		PRTA, 8,
+		PRTB, 8,
+		PRTC, 8,
+		PRTD, 8,
+		PRTE, 8,
+		PRTF, 8,
+		PRTG, 8,
+		PRTH, 8,
+	}
+
+	#include <asm/acpi/irqlinks.asl>
+
+	/* Firmware Hub */
+	Device (FWH)
+	{
+		Name(_HID, EISAID("INT0800"))
+		Name(_CRS, ResourceTemplate()
+		{
+			Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
+		})
+	}
+
+	/* 8259 Interrupt Controller */
+	Device (PIC)
+	{
+		Name(_HID, EISAID("PNP0000"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x20, 0x20, 0x01, 0x02)
+			IO(Decode16, 0x24, 0x24, 0x01, 0x02)
+			IO(Decode16, 0x28, 0x28, 0x01, 0x02)
+			IO(Decode16, 0x2c, 0x2c, 0x01, 0x02)
+			IO(Decode16, 0x30, 0x30, 0x01, 0x02)
+			IO(Decode16, 0x34, 0x34, 0x01, 0x02)
+			IO(Decode16, 0x38, 0x38, 0x01, 0x02)
+			IO(Decode16, 0x3c, 0x3c, 0x01, 0x02)
+			IO(Decode16, 0xa0, 0xa0, 0x01, 0x02)
+			IO(Decode16, 0xa4, 0xa4, 0x01, 0x02)
+			IO(Decode16, 0xa8, 0xa8, 0x01, 0x02)
+			IO(Decode16, 0xac, 0xac, 0x01, 0x02)
+			IO(Decode16, 0xb0, 0xb0, 0x01, 0x02)
+			IO(Decode16, 0xb4, 0xb4, 0x01, 0x02)
+			IO(Decode16, 0xb8, 0xb8, 0x01, 0x02)
+			IO(Decode16, 0xbc, 0xbc, 0x01, 0x02)
+			IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
+			IRQNoFlags () { 2 }
+		})
+	}
+
+	/* 8254 timer */
+	Device (TIMR)
+	{
+		Name(_HID, EISAID("PNP0100"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x40, 0x40, 0x01, 0x04)
+			IO(Decode16, 0x50, 0x50, 0x10, 0x04)
+			IRQNoFlags() { 0 }
+		})
+	}
+
+	/* HPET */
+	Device (HPET)
+	{
+		Name(_HID, EISAID("PNP0103"))
+		Name(_CID, 0x010CD041)
+		Name(_CRS, ResourceTemplate()
+		{
+			Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE)
+		})
+
+		Method(_STA)
+		{
+			Return (STA_VISIBLE)
+		}
+	}
+
+	/* Real Time Clock */
+	Device (RTC)
+	{
+		Name(_HID, EISAID("PNP0B00"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x70, 0x70, 1, 8)
+			IRQNoFlags() { 8 }
+		})
+	}
+
+	/* LPC device: Resource consumption */
+	Device (LDRC)
+	{
+		Name(_HID, EISAID("PNP0C02"))
+		Name(_UID, 2)
+
+		Name(RBUF, ResourceTemplate()
+		{
+			IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
+			IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
+			IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
+		})
+
+		Method(_CRS, 0, NotSerialized)
+		{
+			Return (RBUF)
+		}
+	}
+}
diff --git a/arch/x86/include/asm/arch-quark/acpi/platform.asl b/arch/x86/include/asm/arch-quark/acpi/platform.asl
new file mode 100644
index 0000000..bd72842
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/platform.asl
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/acpi/statdef.asl>
+#include <asm/arch/iomap.h>
+#include <asm/arch/irq.h>
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0.
+ */
+Method(_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+Method(_WAK, 1)
+{
+	Return (Package() {0, 0})
+}
+
+/* TODO: add CPU ASL support */
+
+Scope (\_SB)
+{
+	#include "southcluster.asl"
+}
+
+/* Chipset specific sleep states */
+#include "sleepstates.asl"
diff --git a/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl b/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl
new file mode 100644
index 0000000..63c82fa
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl
@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
+Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
+Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
+Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})
diff --git a/arch/x86/include/asm/arch-quark/acpi/southcluster.asl b/arch/x86/include/asm/arch-quark/acpi/southcluster.asl
new file mode 100644
index 0000000..a89cfaf
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/southcluster.asl
@@ -0,0 +1,184 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Device (PCI0)
+{
+	Name(_HID, EISAID("PNP0A08"))	/* PCIe */
+	Name(_CID, EISAID("PNP0A03"))	/* PCI */
+
+	Name(_ADR, 0)
+	Name(_BBN, 0)
+
+	Name(MCRS, ResourceTemplate()
+	{
+		/* Bus Numbers */
+		WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
+				0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
+
+		/* IO Region 0 */
+		WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
+
+		/* PCI Config Space */
+		IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+		/* IO Region 1 */
+		WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
+
+		/* VGA memory (0xa0000-0xbffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+				0x00020000, , , ASEG)
+
+		/* OPROM reserved (0xc0000-0xc3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+				0x00004000, , , OPR0)
+
+		/* OPROM reserved (0xc4000-0xc7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+				0x00004000, , , OPR1)
+
+		/* OPROM reserved (0xc8000-0xcbfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+				0x00004000, , , OPR2)
+
+		/* OPROM reserved (0xcc000-0xcffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+				0x00004000, , , OPR3)
+
+		/* OPROM reserved (0xd0000-0xd3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+				0x00004000, , , OPR4)
+
+		/* OPROM reserved (0xd4000-0xd7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+				0x00004000, , , OPR5)
+
+		/* OPROM reserved (0xd8000-0xdbfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+				0x00004000, , , OPR6)
+
+		/* OPROM reserved (0xdc000-0xdffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+				0x00004000, , , OPR7)
+
+		/* BIOS Extension (0xe0000-0xe3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+				0x00004000, , , ESG0)
+
+		/* BIOS Extension (0xe4000-0xe7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+				0x00004000, , , ESG1)
+
+		/* BIOS Extension (0xe8000-0xebfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+				0x00004000, , , ESG2)
+
+		/* BIOS Extension (0xec000-0xeffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+				0x00004000, , , ESG3)
+
+		/* System BIOS (0xf0000-0xfffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+				0x00010000, , , FSEG)
+
+		/* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x00000000, 0x00000000, 0x00000000,
+				0x00000000, , , PMEM)
+	})
+
+	Method(_CRS, 0, Serialized)
+	{
+		/* Update PCI resource area */
+		CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
+		CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
+		CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
+
+		/*
+		 * Hardcode TOLM to 2GB for now (see DRAM_MAX_SIZE in quark.h)
+		 *
+		 * TODO: for generic usage, read TOLM value from register, or
+		 * from global NVS (not implemented by U-Boot yet).
+		 */
+		Store(0x80000000, PMIN)
+		Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX)
+		Add(Subtract(PMAX, PMIN), 1, PLEN)
+
+		Return (MCRS)
+	}
+
+	/* Device Resource Consumption */
+	Device (PDRC)
+	{
+		Name(_HID, EISAID("PNP0C02"))
+		Name(_UID, 1)
+
+		Name(PDRS, ResourceTemplate() {
+			Memory32Fixed(ReadWrite, CONFIG_ESRAM_BASE, 0x80000)
+			Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
+			Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
+			IO(Decode16, SPI_DMA_BASE_ADDRESS, SPI_DMA_BASE_ADDRESS, 0x0010, SPI_DMA_BASE_SIZE)
+			IO(Decode16, GPIO_BASE_ADDRESS, GPIO_BASE_ADDRESS, 0x0080, GPIO_BASE_SIZE)
+			IO(Decode16, WDT_BASE_ADDRESS, WDT_BASE_ADDRESS, 0x0040, WDT_BASE_SIZE)
+		})
+
+		/* Current Resource Settings */
+		Method(_CRS, 0, Serialized)
+		{
+			Return (PDRS)
+		}
+	}
+
+	Method(_OSC, 4)
+	{
+		/* Check for proper GUID */
+		If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+			/* Let OS control everything */
+			Return (Arg3)
+		} Else {
+			/* Unrecognized UUID */
+			CreateDWordField(Arg3, 0, CDW1)
+			Or(CDW1, 4, CDW1)
+			Return (Arg3)
+		}
+	}
+
+	/* LPC Bridge 0:1f.0 */
+	#include "lpc.asl"
+
+	/* IRQ routing for each PCI device */
+	#include <asm/acpi/irqroute.asl>
+}
diff --git a/arch/x86/include/asm/arch-quark/iomap.h b/arch/x86/include/asm/arch-quark/iomap.h
new file mode 100644
index 0000000..fd1ef98
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/iomap.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _QUARK_IOMAP_H_
+#define _QUARK_IOMAP_H_
+
+/* Memory Mapped IO bases */
+
+/* ESRAM */
+#define ESRAM_BASE_ADDRESS		CONFIG_ESRAM_BASE
+#define ESRAM_BASE_SIZE			ESRAM_SIZE
+
+/* PCI Configuration Space */
+#define MCFG_BASE_ADDRESS		CONFIG_PCIE_ECAM_BASE
+#define MCFG_BASE_SIZE			0x10000000
+
+/* High Performance Event Timer */
+#define HPET_BASE_ADDRESS		0xfed00000
+#define HPET_BASE_SIZE			0x400
+
+/* Root Complex Base Address */
+#define RCBA_BASE_ADDRESS		CONFIG_RCBA_BASE
+#define RCBA_BASE_SIZE			0x4000
+
+/* IO Port bases */
+#define ACPI_PM1_BASE_ADDRESS		CONFIG_ACPI_PM1_BASE
+#define ACPI_PM1_BASE_SIZE		0x10
+
+#define ACPI_PBLK_BASE_ADDRESS		CONFIG_ACPI_PBLK_BASE
+#define ACPI_PBLK_BASE_SIZE		0x10
+
+#define SPI_DMA_BASE_ADDRESS		CONFIG_SPI_DMA_BASE
+#define SPI_DMA_BASE_SIZE		0x10
+
+#define GPIO_BASE_ADDRESS		CONFIG_GPIO_BASE
+#define GPIO_BASE_SIZE			0x80
+
+#define ACPI_GPE0_BASE_ADDRESS		CONFIG_ACPI_GPE0_BASE
+#define ACPI_GPE0_BASE_SIZE		0x40
+
+#define WDT_BASE_ADDRESS		CONFIG_WDT_BASE
+#define WDT_BASE_SIZE			0x40
+
+#endif /* _QUARK_IOMAP_H_ */
diff --git a/arch/x86/include/asm/arch-quark/irq.h b/arch/x86/include/asm/arch-quark/irq.h
new file mode 100644
index 0000000..21e6830
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/irq.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _QUARK_IRQ_H_
+#define _QUARK_IRQ_H_
+
+#define PIRQA_APIC_IRQ	16
+#define PIRQB_APIC_IRQ	17
+#define PIRQC_APIC_IRQ	18
+#define PIRQD_APIC_IRQ	19
+#define PIRQE_APIC_IRQ	20
+#define PIRQF_APIC_IRQ	21
+#define PIRQG_APIC_IRQ	22
+#define PIRQH_APIC_IRQ	23
+
+#endif /* _QUARK_IRQ_H_ */
-- 
1.8.2.1

[U-Boot] [PATCH v2 5/8] x86: quark: Add platform ASL files

[Bin Meng]

On Thu, May 26, 2016 at 10:19 AM, Bin Meng <bmeng.cn@gmail.com> wrote:
> This adds basic quark platform ASL files. They are intended to be
> included in dsdt.asl of any board that is based on this platform.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  arch/x86/include/asm/arch-quark/acpi/irqroute.h    |  15 ++
>  arch/x86/include/asm/arch-quark/acpi/lpc.asl       | 125 ++++++++++++++
>  arch/x86/include/asm/arch-quark/acpi/platform.asl  |  33 ++++
>  .../include/asm/arch-quark/acpi/sleepstates.asl    |  10 ++
>  .../include/asm/arch-quark/acpi/southcluster.asl   | 184 +++++++++++++++++++++
>  arch/x86/include/asm/arch-quark/iomap.h            |  47 ++++++
>  arch/x86/include/asm/arch-quark/irq.h              |  19 +++
>  7 files changed, 433 insertions(+)
>  create mode 100644 arch/x86/include/asm/arch-quark/acpi/irqroute.h
>  create mode 100644 arch/x86/include/asm/arch-quark/acpi/lpc.asl
>  create mode 100644 arch/x86/include/asm/arch-quark/acpi/platform.asl
>  create mode 100644 arch/x86/include/asm/arch-quark/acpi/sleepstates.asl
>  create mode 100644 arch/x86/include/asm/arch-quark/acpi/southcluster.asl
>  create mode 100644 arch/x86/include/asm/arch-quark/iomap.h
>  create mode 100644 arch/x86/include/asm/arch-quark/irq.h
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v2 6/8] x86: quark: Generate ACPI FADT/MADT tables

[Bin Meng]

Generate quark platform-specific FADT/MADT tables.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/x86/cpu/quark/Makefile |   1 +
 arch/x86/cpu/quark/acpi.c   | 163 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 164 insertions(+)
 create mode 100644 arch/x86/cpu/quark/acpi.c

diff --git a/arch/x86/cpu/quark/Makefile b/arch/x86/cpu/quark/Makefile
index 6d670d7..93ce412 100644
--- a/arch/x86/cpu/quark/Makefile
+++ b/arch/x86/cpu/quark/Makefile
@@ -6,3 +6,4 @@
 
 obj-y += car.o dram.o irq.o msg_port.o quark.o
 obj-y += mrc.o mrc_util.o hte.o smc.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o
diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c
new file mode 100644
index 0000000..8f69829
--- /dev/null
+++ b/arch/x86/cpu/quark/acpi.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/acpi_table.h>
+#include <asm/ioapic.h>
+#include <asm/mpspec.h>
+#include <asm/tables.h>
+#include <asm/arch/iomap.h>
+
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+		      void *dsdt)
+{
+	struct acpi_table_header *header = &(fadt->header);
+	u16 pmbase = ACPI_PM1_BASE_ADDRESS;
+
+	memset((void *)fadt, 0, sizeof(struct acpi_fadt));
+
+	acpi_fill_header(header, "FACP");
+	header->length = sizeof(struct acpi_fadt);
+	header->revision = 4;
+
+	fadt->firmware_ctrl = (u32)facs;
+	fadt->dsdt = (u32)dsdt;
+	fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED;
+	fadt->sci_int = 9;
+	fadt->smi_cmd = 0;
+	fadt->acpi_enable = 0;
+	fadt->acpi_disable = 0;
+	fadt->s4bios_req = 0;
+	fadt->pstate_cnt = 0;
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = 0x0;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = ACPI_GPE0_BASE_ADDRESS;
+	fadt->gpe1_blk = 0;
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 0;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = 0;
+	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
+	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 3;
+	fadt->day_alrm = 0x00;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x00;
+	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES;
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+		ACPI_FADT_POWER_BUTTON | ACPI_FADT_SLEEP_BUTTON |
+		ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER |
+		ACPI_FADT_PLATFORM_CLOCK;
+
+	fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+	fadt->reset_reg.addrl = IO_PORT_RESET;
+	fadt->reset_reg.addrh = 0;
+	fadt->reset_value = SYS_RST | RST_CPU;
+
+	fadt->x_firmware_ctl_l = (u32)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (u32)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.access_size = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+	fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.access_size = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+	fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.access_size = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = table_compute_checksum(fadt, header->length);
+}
+
+static int acpi_create_madt_irq_overrides(u32 current)
+{
+	struct acpi_madt_irqoverride *irqovr;
+	u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
+	int length = 0;
+
+	irqovr = (void *)current;
+	length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
+
+	irqovr = (void *)(current + length);
+	length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
+
+	return length;
+}
+
+u32 acpi_fill_madt(u32 current)
+{
+	current += acpi_create_madt_lapics(current);
+
+	current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
+			io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
+
+	current += acpi_create_madt_irq_overrides(current);
+
+	return current;
+}
-- 
1.8.2.1

[U-Boot] [PATCH v2 6/8] x86: quark: Generate ACPI FADT/MADT tables

[Bin Meng]

On Thu, May 26, 2016 at 10:19 AM, Bin Meng <bmeng.cn@gmail.com> wrote:
> Generate quark platform-specific FADT/MADT tables.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  arch/x86/cpu/quark/Makefile |   1 +
>  arch/x86/cpu/quark/acpi.c   | 163 ++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 164 insertions(+)
>  create mode 100644 arch/x86/cpu/quark/acpi.c
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v2 7/8] x86: galileo: Enable ACPI table generation

[Bin Meng]

Enable ACPI table generation by creating a DSDT table.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 board/intel/galileo/.gitignore         |  3 +++
 board/intel/galileo/Makefile           |  1 +
 board/intel/galileo/acpi/mainboard.asl | 11 +++++++++++
 board/intel/galileo/dsdt.asl           | 14 ++++++++++++++
 configs/galileo_defconfig              |  1 +
 doc/README.x86                         |  5 ++++-
 6 files changed, 34 insertions(+), 1 deletion(-)
 create mode 100644 board/intel/galileo/.gitignore
 create mode 100644 board/intel/galileo/acpi/mainboard.asl
 create mode 100644 board/intel/galileo/dsdt.asl

diff --git a/board/intel/galileo/.gitignore b/board/intel/galileo/.gitignore
new file mode 100644
index 0000000..6eb8a54
--- /dev/null
+++ b/board/intel/galileo/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
diff --git a/board/intel/galileo/Makefile b/board/intel/galileo/Makefile
index 8356df1..bbe2f8b 100644
--- a/board/intel/galileo/Makefile
+++ b/board/intel/galileo/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y	+= galileo.o start.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/intel/galileo/acpi/mainboard.asl b/board/intel/galileo/acpi/mainboard.asl
new file mode 100644
index 0000000..21785ea
--- /dev/null
+++ b/board/intel/galileo/acpi/mainboard.asl
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+	Name(_HID, EISAID("PNP0C0C"))
+}
diff --git a/board/intel/galileo/dsdt.asl b/board/intel/galileo/dsdt.asl
new file mode 100644
index 0000000..6042011
--- /dev/null
+++ b/board/intel/galileo/dsdt.asl
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+
+	/* board specific */
+	#include "acpi/mainboard.asl"
+}
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index f8d3c3b..080c2ed 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -5,6 +5,7 @@ CONFIG_TARGET_GALILEO=y
 CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
diff --git a/doc/README.x86 b/doc/README.x86
index 4d50feb..a548b54 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -1028,12 +1028,15 @@ Features that are optional:
    those legacy stuff into U-Boot. ACPI spec allows a system that does not
    support SMI (a legacy-free system).
 
-So far ACPI is enabled on BayTrail based boards. Testing was done by booting
+ACPI was initially enabled on BayTrail based boards. Testing was done by booting
 a pre-installed Ubuntu 14.04 from a SATA drive. Installing Ubuntu 14.04 and
 Windows 8.1/10 to a SATA drive and booting from there is also tested. Most
 devices seem to work correctly and the board can respond a reboot/shutdown
 command from the OS.
 
+For other platform boards, ACPI support status can be checked by examining their
+board defconfig files to see if CONFIG_GENERATE_ACPI_TABLE is set to y.
+
 TODO List
 ---------
 - Audio
-- 
1.8.2.1

[U-Boot] [PATCH v2 7/8] x86: galileo: Enable ACPI table generation

[Bin Meng]

On Thu, May 26, 2016 at 10:19 AM, Bin Meng <bmeng.cn@gmail.com> wrote:
> Enable ACPI table generation by creating a DSDT table.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  board/intel/galileo/.gitignore         |  3 +++
>  board/intel/galileo/Makefile           |  1 +
>  board/intel/galileo/acpi/mainboard.asl | 11 +++++++++++
>  board/intel/galileo/dsdt.asl           | 14 ++++++++++++++
>  configs/galileo_defconfig              |  1 +
>  doc/README.x86                         |  5 ++++-
>  6 files changed, 34 insertions(+), 1 deletion(-)
>  create mode 100644 board/intel/galileo/.gitignore
>  create mode 100644 board/intel/galileo/acpi/mainboard.asl
>  create mode 100644 board/intel/galileo/dsdt.asl
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v2 8/8] x86: baytrail: acpi: Fix I/O APIC ID in the MADT table

[Bin Meng]

So far this is hardcoded to 2, but it should really be read
from the I/O APIC register.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

---

Changes in v2: None

 arch/x86/cpu/baytrail/acpi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c
index 1d54f7d..5ee4868 100644
--- a/arch/x86/cpu/baytrail/acpi.c
+++ b/arch/x86/cpu/baytrail/acpi.c
@@ -155,7 +155,7 @@ u32 acpi_fill_madt(u32 current)
 	current += acpi_create_madt_lapics(current);
 
 	current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
-			2, IO_APIC_ADDR, 0);
+			io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
 
 	current += acpi_create_madt_irq_overrides(current);
 
-- 
1.8.2.1

[U-Boot] [PATCH v2 8/8] x86: baytrail: acpi: Fix I/O APIC ID in the MADT table

[Bin Meng]

On Thu, May 26, 2016 at 10:19 AM, Bin Meng <bmeng.cn@gmail.com> wrote:
> So far this is hardcoded to 2, but it should really be read
> from the I/O APIC register.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
>
> ---
>
> Changes in v2: None
>
>  arch/x86/cpu/baytrail/acpi.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

applied to u-boot-x86, thanks!