From: Andre Przywara <andre.przywara@arm.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v3 01/26] sun6i: Restrict some register initialization to Allwinner A31 SoC
Date: Mon, 19 Dec 2016 01:49:51 +0000 [thread overview]
Message-ID: <1482112216-12983-2-git-send-email-andre.przywara@arm.com> (raw)
In-Reply-To: <1482112216-12983-1-git-send-email-andre.przywara@arm.com>
These days many Allwinner SoCs use clock_sun6i.c, although out of them
only the (original sun6i) A31 has a second MBUS clock register.
Also the requirement for setting up the PRCM PLL_CTLR1 register to provide
the proper voltage seems to be a property of older SoCs only as well.
Restrict the MBUS initialization to this SoC only to avoid writing bogus
values to (undefined) registers in other chips.
I can only verify that the PLL voltage setup is not needed for H3 and
A64, so for now we only spare those two SoCs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/mach-sunxi/clock_sun6i.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index ed8cd9b..80cfc0b 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -21,6 +21,8 @@ void clock_init_safe(void)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+#if !defined(CONFIG_MACH_SUN8I_H3) && !defined(CONFIG_MACH_SUN50I)
struct sunxi_prcm_reg * const prcm =
(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
@@ -31,6 +33,7 @@ void clock_init_safe(void)
PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
+#endif
clock_set_pll1(408000000);
@@ -41,7 +44,8 @@ void clock_init_safe(void)
writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
- writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
+ if (IS_ENABLED(CONFIG_MACH_SUN6I))
+ writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
}
#endif
--
2.8.2
next prev parent reply other threads:[~2016-12-19 1:49 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-19 1:49 [U-Boot] [PATCH v3 00/26] sunxi: Allwinner A64: SPL support Andre Przywara
2016-12-19 1:49 ` Andre Przywara [this message]
2016-12-19 1:49 ` [U-Boot] [PATCH v3 02/26] armv8: prevent using THUMB Andre Przywara
2016-12-19 1:49 ` [U-Boot] [PATCH v3 03/26] armv8: add lowlevel_init.S Andre Przywara
2016-12-26 5:23 ` Simon Glass
2016-12-19 1:49 ` [U-Boot] [PATCH v3 04/26] SPL: tiny-printf: add "l" modifier Andre Przywara
2016-12-19 1:49 ` [U-Boot] [PATCH v3 05/26] SPL: tiny-printf: ignore "-" modifier Andre Przywara
2016-12-26 5:23 ` Simon Glass
2016-12-19 1:49 ` [U-Boot] [PATCH v3 06/26] move UL() macro from armv8/mmu.h into common.h Andre Przywara
2016-12-19 1:49 ` [U-Boot] [PATCH v3 07/26] SPL: make struct spl_image 64-bit safe Andre Przywara
2016-12-19 1:49 ` [U-Boot] [PATCH v3 08/26] armv8: add simple sdelay implementation Andre Przywara
2016-12-19 1:49 ` [U-Boot] [PATCH v3 09/26] armv8: move reset branch into boot hook Andre Przywara
2016-12-19 1:50 ` [U-Boot] [PATCH v3 10/26] ARM: boot0 hook: remove macro, include whole header file Andre Przywara
2016-12-30 20:41 ` Steve Rae
2016-12-19 1:50 ` [U-Boot] [PATCH v3 11/26] sunxi: introduce extra config option for boot0 header Andre Przywara
2016-12-19 1:50 ` [U-Boot] [PATCH v3 12/26] sunxi: A64: do an RMR switch if started in AArch32 mode Andre Przywara
2016-12-19 9:43 ` Maxime Ripard
2016-12-19 1:50 ` [U-Boot] [PATCH v3 13/26] sunxi: provide default DRAM config for sun50i in Kconfig Andre Przywara
2016-12-19 9:43 ` Maxime Ripard
2016-12-19 1:50 ` [U-Boot] [PATCH v3 14/26] sunxi: H3: Rework MBUS priority setup Andre Przywara
2016-12-19 9:44 ` Maxime Ripard
2016-12-19 1:50 ` [U-Boot] [PATCH v3 15/26] sunxi: H3: add and rename some DRAM contoller registers Andre Przywara
2016-12-19 1:50 ` [U-Boot] [PATCH v3 16/26] sunxi: H3: add DRAM controller single bit delay support Andre Przywara
2016-12-19 9:57 ` Maxime Ripard
2016-12-19 10:53 ` Andre Przywara
2016-12-20 13:48 ` Maxime Ripard
2016-12-19 1:50 ` [U-Boot] [PATCH v3 17/26] sunxi: clocks: Use the correct pattern register for PLL11 Andre Przywara
2016-12-19 9:58 ` Maxime Ripard
2016-12-19 1:50 ` [U-Boot] [PATCH v3 18/26] sunxi: A64: use H3 DRAM initialization code for A64 as well Andre Przywara
2016-12-19 10:00 ` Maxime Ripard
2016-12-19 1:50 ` [U-Boot] [PATCH v3 19/26] sunxi: H3/A64: fix non-ODT setting Andre Przywara
2016-12-19 10:01 ` Maxime Ripard
2016-12-19 10:33 ` Andre Przywara
2016-12-19 14:32 ` Jens Kuske
2016-12-20 10:49 ` Maxime Ripard
2016-12-19 1:50 ` [U-Boot] [PATCH v3 20/26] sunxi: DRAM: fix H3 DRAM size display on aarch64 Andre Przywara
2016-12-19 10:01 ` Maxime Ripard
2016-12-19 1:50 ` [U-Boot] [PATCH v3 21/26] sunxi: A64: enable SPL Andre Przywara
2016-12-19 10:01 ` Maxime Ripard
2016-12-26 5:23 ` Simon Glass
2016-12-19 1:50 ` [U-Boot] [PATCH v3 22/26] SPL: read and store arch property from U-Boot image Andre Przywara
2016-12-19 1:50 ` [U-Boot] [PATCH v3 23/26] Makefile: use "arm64" architecture for U-Boot image files Andre Przywara
2016-12-19 1:50 ` [U-Boot] [PATCH v3 24/26] ARM: SPL/FIT: differentiate between arm and arm64 arch properties Andre Przywara
2016-12-19 1:50 ` [U-Boot] [PATCH v3 25/26] sunxi: introduce RMR switch to enter payloads in 64-bit mode Andre Przywara
2016-12-19 10:03 ` Maxime Ripard
2016-12-19 1:50 ` [U-Boot] [PATCH v3 26/26] sunxi: A64: add 32-bit SPL support Andre Przywara
2016-12-19 10:05 ` Maxime Ripard
2017-01-01 19:02 ` [U-Boot] [PATCH v3 00/26] sunxi: Allwinner A64: " Jagan Teki
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