From: Bin Meng <bmeng.cn@gmail.com>
To: u-boot@lists.denx.de
Subject: [PATCH 3/4] test/py: Update u_boot_utils.find_ram_base to bypass the low 2MiB memory
Date: Thu, 26 Mar 2020 09:05:23 -0700 [thread overview]
Message-ID: <1585238724-2928-3-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1585238724-2928-1-git-send-email-bmeng.cn@gmail.com>
On some RISC-V targets the low memory is protected that prevents
S-mode U-Boot from access.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
test/py/u_boot_utils.py | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/test/py/u_boot_utils.py b/test/py/u_boot_utils.py
index bf2a0fc..939d82e 100644
--- a/test/py/u_boot_utils.py
+++ b/test/py/u_boot_utils.py
@@ -237,10 +237,11 @@ def find_ram_base(u_boot_console):
raise Exception('Failed to find RAM bank start in `bdinfo`')
# We don't want ram_base to be zero as some functions test if the given
- # address is NULL (0). Let's add 2MiB then (size of an ARM LPAE/v8 section).
+ # address is NULL (0). Besides, on some RISC-V targets the low memory
+ # is protected that prevents S-mode U-Boot from access.
+ # Let's add 2MiB then (size of an ARM LPAE/v8 section).
- if ram_base == 0:
- ram_base += 1024 * 1024 * 2
+ ram_base += 1024 * 1024 * 2
return ram_base
--
2.7.4
next prev parent reply other threads:[~2020-03-26 16:05 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-26 16:05 [PATCH 1/4] travis: Remove qemu-riscv64 testing Bin Meng
2020-03-26 16:05 ` [PATCH 2/4] azure/gitlab: Add qemu-riscv32 testing Bin Meng
2020-03-26 16:05 ` Bin Meng [this message]
2020-03-26 16:05 ` [PATCH 4/4] azure/gitlab: Add RISC-V SPL testing Bin Meng
2020-03-26 16:10 ` [PATCH 1/4] travis: Remove qemu-riscv64 testing Tom Rini
2020-03-27 1:51 ` Bin Meng
2020-03-27 2:01 ` Tom Rini
2020-03-27 2:19 ` Bin Meng
2020-03-27 2:20 ` Tom Rini
2020-03-27 5:19 ` David Abdurachmanov
2020-03-27 5:31 ` Bin Meng
2020-03-27 5:39 ` David Abdurachmanov
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