From: Bin Meng <bmeng.cn@gmail.com>
To: u-boot@lists.denx.de
Subject: [PATCH 4/4] azure/gitlab: Add RISC-V SPL testing
Date: Thu, 26 Mar 2020 09:05:24 -0700 [thread overview]
Message-ID: <1585238724-2928-4-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1585238724-2928-1-git-send-email-bmeng.cn@gmail.com>
This adds QEMU RISC-V 32/64 SPL testing. Unlike QEMU RISC-V 32/64,
we test SPL running in M-mode and U-Boot proper running in S-mode,
with a 4-core SMP configuration.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
.azure-pipelines.yml | 16 ++++++++++++++++
.gitlab-ci.yml | 24 ++++++++++++++++++++++++
2 files changed, 40 insertions(+)
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 99a93cc..55a2d75 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -223,6 +223,14 @@ jobs:
TEST_PY_BD: "qemu-riscv64"
TEST_PY_TEST_SPEC: "not sleep"
BUILDMAN: "^qemu-riscv64$"
+ qemu_riscv32_spl:
+ TEST_PY_BD: "qemu-riscv32_spl"
+ TEST_PY_TEST_SPEC: "not sleep"
+ BUILDMAN: "^qemu-riscv32_spl$"
+ qemu_riscv64_spl:
+ TEST_PY_BD: "qemu-riscv64_spl"
+ TEST_PY_TEST_SPEC: "not sleep"
+ BUILDMAN: "^qemu-riscv64_spl$"
qemu_x86:
TEST_PY_BD: "qemu-x86"
TEST_PY_TEST_SPEC: "not sleep"
@@ -270,6 +278,14 @@ jobs:
cp /opt/grub/grubriscv32.efi ~/grub_riscv32.efi
cp /opt/grub/grubaa64.efi ~/grub_arm64.efi
cp /opt/grub/grubarm.efi ~/grub_arm.efi
+ if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
+ wget -O - https://github.com/riscv/opensbi/releases/download/v0.6/opensbi-0.6-rv32-bin.tar.xz | tar -C /tmp -xJ
+ export OPENSBI=/tmp/opensbi-0.6-rv32-bin/platform/qemu/virt/firmware/fw_dynamic.bin
+ fi
+ if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then
+ wget -O - https://github.com/riscv/opensbi/releases/download/v0.6/opensbi-0.6-rv64-bin.tar.xz | tar -C /tmp -xJ
+ export OPENSBI=/tmp/opensbi-0.6-rv64-bin/platform/qemu/virt/firmware/fw_dynamic.bin
+ fi
# the below corresponds to .gitlab-ci.yml "script"
cd ${WORK_DIR}
if [[ "${BUILDMAN}" != "" ]]; then
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 39437ce..a393a10 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -24,6 +24,14 @@ stages:
- cp /opt/grub/grubriscv32.efi ~/grub_riscv32.efi
- cp /opt/grub/grubaa64.efi ~/grub_arm64.efi
- cp /opt/grub/grubarm.efi ~/grub_arm.efi
+ - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
+ wget -O - https://github.com/riscv/opensbi/releases/download/v0.6/opensbi-0.6-rv32-bin.tar.xz | tar -C /tmp -xJ
+ export OPENSBI=/tmp/opensbi-0.6-rv32-bin/platform/qemu/virt/firmware/fw_dynamic.bin
+ fi
+ - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then
+ wget -O - https://github.com/riscv/opensbi/releases/download/v0.6/opensbi-0.6-rv64-bin.tar.xz | tar -C /tmp -xJ
+ export OPENSBI=/tmp/opensbi-0.6-rv64-bin/platform/qemu/virt/firmware/fw_dynamic.bin
+ fi
after_script:
- rm -rf /tmp/uboot-test-hooks /tmp/venv
@@ -313,6 +321,22 @@ qemu-riscv64 test.py:
BUILDMAN: "^qemu-riscv64$"
<<: *buildman_and_testpy_dfn
+qemu-riscv32_spl test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "qemu-riscv32_spl"
+ TEST_PY_TEST_SPEC: "not sleep"
+ BUILDMAN: "^qemu-riscv32_spl$"
+ <<: *buildman_and_testpy_dfn
+
+qemu-riscv64_spl test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "qemu-riscv64_spl"
+ TEST_PY_TEST_SPEC: "not sleep"
+ BUILDMAN: "^qemu-riscv64_spl$"
+ <<: *buildman_and_testpy_dfn
+
qemu-x86 test.py:
tags: [ 'all' ]
variables:
--
2.7.4
next prev parent reply other threads:[~2020-03-26 16:05 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-26 16:05 [PATCH 1/4] travis: Remove qemu-riscv64 testing Bin Meng
2020-03-26 16:05 ` [PATCH 2/4] azure/gitlab: Add qemu-riscv32 testing Bin Meng
2020-03-26 16:05 ` [PATCH 3/4] test/py: Update u_boot_utils.find_ram_base to bypass the low 2MiB memory Bin Meng
2020-03-26 16:05 ` Bin Meng [this message]
2020-03-26 16:10 ` [PATCH 1/4] travis: Remove qemu-riscv64 testing Tom Rini
2020-03-27 1:51 ` Bin Meng
2020-03-27 2:01 ` Tom Rini
2020-03-27 2:19 ` Bin Meng
2020-03-27 2:20 ` Tom Rini
2020-03-27 5:19 ` David Abdurachmanov
2020-03-27 5:31 ` Bin Meng
2020-03-27 5:39 ` David Abdurachmanov
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