[U-Boot] [PATCH 03/13 v4] ARM: OMAP3: Add overo pin mux, omap3 and prototype headers

[U-Boot] [PATCH 03/13 v4] ARM: OMAP3: Add overo pin mux, omap3 and prototype headers

[dirk.behme at googlemail.com]

Subject: [PATCH 03/13 v4] ARM: OMAP3: Add overo pin mux, omap3 and prototype headers

From: Dirk Behme <dirk.behme@gmail.com>

Add overo pin mux, omap3 and prototype headers

Signed-off-by: Dirk Behme <dirk.behme@gmail.com>

---

Changes in version v3:

- Replace space by tabs in headers as proposed by Jean-Christophe PLAGNIOL-VILLARD

Changes in version v2:

- Update Overo pin mux to add and pull down X_GATE, by Steve Sakoman.

 include/asm-arm/arch-omap3/mux.h       |  332 +++++++++++++++++++++++++++++++++
 include/asm-arm/arch-omap3/omap3.h     |  135 +++++++++++++
 include/asm-arm/arch-omap3/sys_proto.h |   72 +++++++
 3 files changed, 539 insertions(+)

Index: u-boot-arm/include/asm-arm/arch-omap3/mux.h
===================================================================
--- u-boot-arm.orig/include/asm-arm/arch-omap3/mux.h
+++ u-boot-arm/include/asm-arm/arch-omap3/mux.h
@@ -751,4 +751,336 @@
  MUX_VAL(CP(sdrc_cke0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
  MUX_VAL(CP(sdrc_cke1),		(IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
 
+#define MUX_DEFAULT_OVERO() \
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0),		(IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1),		(IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2),		(IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3),		(IEN  | PTD | DIS | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4),		(IEN  | PTD | DIS | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5),		(IEN  | PTD | DIS | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6),		(IEN  | PTD | DIS | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7),		(IEN  | PTD | DIS | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_nCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
+ MUX_VAL(CP(GPMC_nCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_nCS2),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_nCS3),		(IEN  | PTU | EN  | M4)) /*GPIO_54*/\
+							 /* - MMC1_WP*/\
+ MUX_VAL(CP(GPMC_nCS4),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS4*/\
+ MUX_VAL(CP(GPMC_nCS5),		(IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
+ MUX_VAL(CP(GPMC_nCS6),		(IEN  | PTD | DIS | M0)) /*GPMC_nCS6*/\
+ MUX_VAL(CP(GPMC_nCS7),		(IEN  | PTU | EN  | M0)) /*GPMC_nCS7*/\
+ MUX_VAL(CP(GPMC_nBE1),		(IEN  | PTD | DIS | M0)) /*GPMC_nCS3*/\
+ MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_nADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_nOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_nWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_nBE0_CLE),	(IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+ MUX_VAL(CP(GPMC_nWP),		(IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
+ MUX_VAL(CP(GPMC_WAIT0),	(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT1),	(IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
+ MUX_VAL(CP(GPMC_WAIT2),	(IEN  | PTU | EN  | M0)) /*GPMC_nCS3*/\
+ MUX_VAL(CP(GPMC_WAIT3),	(IEN  | PTU | EN  | M0)) /*GPMC_nCS3*/\
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS),	(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+ MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10),	(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11),	(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12),	(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13),	(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14),	(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15),	(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16),	(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17),	(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18),	(IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+ MUX_VAL(CP(DSS_DATA19),	(IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+ MUX_VAL(CP(DSS_DATA20),	(IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+ MUX_VAL(CP(DSS_DATA21),	(IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+ MUX_VAL(CP(DSS_DATA22),	(IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+ MUX_VAL(CP(DSS_DATA23),	(IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+ /*CAMERA*/\
+ MUX_VAL(CP(CAM_HS), 		(IEN  | PTU | EN  | M0)) /*CAM_HS */\
+ MUX_VAL(CP(CAM_VS), 		(IEN  | PTU | EN  | M0)) /*CAM_VS */\
+ MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*CAM_FLD*/\
+ MUX_VAL(CP(CAM_D0), 		(IEN  | PTD | DIS | M0)) /*CAM_D0*/\
+ MUX_VAL(CP(CAM_D1), 		(IEN  | PTD | DIS | M0)) /*CAM_D1*/\
+ MUX_VAL(CP(CAM_D2), 		(IEN  | PTD | DIS | M0)) /*CAM_D2*/\
+ MUX_VAL(CP(CAM_D3), 		(IEN  | PTD | DIS | M0)) /*CAM_D3*/\
+ MUX_VAL(CP(CAM_D4), 		(IEN  | PTD | DIS | M0)) /*CAM_D4*/\
+ MUX_VAL(CP(CAM_D5), 		(IEN  | PTD | DIS | M0)) /*CAM_D5*/\
+ MUX_VAL(CP(CAM_D6), 		(IEN  | PTD | DIS | M0)) /*CAM_D6*/\
+ MUX_VAL(CP(CAM_D7), 		(IEN  | PTD | DIS | M0)) /*CAM_D7*/\
+ MUX_VAL(CP(CAM_D8), 		(IEN  | PTD | DIS | M0)) /*CAM_D8*/\
+ MUX_VAL(CP(CAM_D9), 		(IEN  | PTD | DIS | M0)) /*CAM_D9*/\
+ MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M0)) /*CAM_WEN*/\
+ MUX_VAL(CP(CAM_STROBE),	(IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
+ MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
+ MUX_VAL(CP(CSI2_DY1),		(IEN  | PTU | EN  | M4)) /*GPIO_115*/\
+ /*Audio Interface */\
+ MUX_VAL(CP(McBSP2_FSX),	(IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(McBSP2_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+ MUX_VAL(CP(McBSP2_DR),		(IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(McBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card */\
+ MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
+ MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
+ MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
+ MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
+ /*Wireless LAN */\
+ MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M0)) /*MMC2_CLK*/\
+ MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT2*/\
+ MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT3*/\
+ MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M1)) /*MMC2_DIR_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M1)) /*MMC2_DIR_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | EN  | M1)) /*MMC2_DIR_CMD*/\
+ MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M1)) /*MMC2_CLKIN*/\
+ /*Bluetooth*/\
+ MUX_VAL(CP(McBSP3_DX),		(IEN  | PTD | DIS | M1)) /*UART2_CTS*/\
+ MUX_VAL(CP(McBSP3_DR),		(IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+ MUX_VAL(CP(McBSP3_CLKX),	(IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+ MUX_VAL(CP(McBSP3_FSX),	(IEN  | PTD | DIS | M1)) /*UART2_RX*/\
+ MUX_VAL(CP(UART2_CTS),		(IDIS | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\
+ MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M4)) /*GPIO_145*/\
+ MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M4)) /*GPIO_146*/\
+ MUX_VAL(CP(UART2_RX),		(IDIS | PTD | DIS | M4)) /*GPIO_147*/\
+ MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_RTS),		(IEN  | PTU | DIS | M4)) /*GPIO_149*/ \
+ MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\
+ MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX*/\
+ MUX_VAL(CP(McBSP4_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP4_CLKX*/\
+ MUX_VAL(CP(McBSP4_DR),		(IEN  | PTD | DIS | M0)) /*McBSP4_DR*/\
+ MUX_VAL(CP(McBSP4_DX),		(IEN  | PTD | DIS | M0)) /*McBSP4_DX*/\
+ MUX_VAL(CP(McBSP4_FSX),	(IEN  | PTD | DIS | M0)) /*McBSP4_FSX*/\
+ MUX_VAL(CP(McBSP1_CLKR),	(IEN  | PTD | DIS | M0)) /*McBSP1_CLKR*/\
+ MUX_VAL(CP(McBSP1_FSR),	(IEN  | PTD | DIS | M0)) /*McBSP1_FSR*/\
+ MUX_VAL(CP(McBSP1_DX),		(IEN  | PTD | DIS | M0)) /*McBSP1_DX*/\
+ MUX_VAL(CP(McBSP1_DR),		(IEN  | PTD | DIS | M0)) /*McBSP1_DR*/\
+ MUX_VAL(CP(McBSP_CLKS),	(IEN  | PTU | DIS | M0)) /*McBSP_CLKS*/\
+ MUX_VAL(CP(McBSP1_FSX),	(IEN  | PTD | DIS | M0)) /*McBSP1_FSX*/\
+ MUX_VAL(CP(McBSP1_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP1_CLKX*/\
+ /*Serial Interface*/\
+ MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0)) /*UART3_CTS_RCTX*/\
+ MUX_VAL(CP(UART3_RTS_SD),	(IEN  | PTU | EN  | M4)) /*GPIO_164 W2W_*/\
+							 /* BT_NRESET*/\
+ MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTU | EN  | M0)) /*UART3_RX_IRRX*/\
+ MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ MUX_VAL(CP(HSUSB0_CLK),	(IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP),	(IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT),	(IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M4)) /*GPIO_168*/\
+							 /* - USBH_CPEN*/\
+ MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M4)) /*GPIO_183*/\
+							 /* - USBH_RESET*/\
+ MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
+ MUX_VAL(CP(HDQ_SIO),		(IDIS | PTU | EN  | M4)) /*HDQ_SIO*/\
+ MUX_VAL(CP(McSPI1_CLK),	(IEN  | PTD | DIS | M0)) /*McSPI1_CLK*/\
+ MUX_VAL(CP(McSPI1_SIMO),	(IEN  | PTD | DIS | M0)) /*McSPI1_SIMO */\
+ MUX_VAL(CP(McSPI1_SOMI),	(IEN  | PTD | DIS | M0)) /*McSPI1_SOMI */\
+ MUX_VAL(CP(McSPI1_CS0),	(IEN  | PTD | EN  | M0)) /*McSPI1_CS0*/\
+ MUX_VAL(CP(McSPI1_CS1),	(IDIS | PTD | EN  | M0)) /*McSPI1_CS1*/\
+ MUX_VAL(CP(McSPI1_CS2),	(IDIS | PTD | DIS | M4)) /*GPIO_176*/\
+ MUX_VAL(CP(McSPI1_CS3),	(IEN  | PTD | DIS | M3)) /*HSUSB2_DATA2*/\
+ MUX_VAL(CP(McSPI2_CLK),	(IEN  | PTD | DIS | M3)) /*HSUSB2_DATA7*/\
+ MUX_VAL(CP(McSPI2_SIMO),	(IEN  | PTD | DIS | M3)) /*HSUSB2_DATA4*/\
+ MUX_VAL(CP(McSPI2_SOMI),	(IEN  | PTD | DIS | M3)) /*HSUSB2_DATA5*/\
+ MUX_VAL(CP(McSPI2_CS0),	(IEN  | PTD | DIS | M3)) /*HSUSB2_DATA6*/\
+ MUX_VAL(CP(McSPI2_CS1),	(IEN  | PTD | DIS | M3)) /*HSUSB2_DATA3*/\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ),	(IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_nIRQ),		(IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+ MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3 */\
+ MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
+ MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+ MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+ MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
+ MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/\
+ MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
+ MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M4)) /*GPIO_186*/\
+ MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M2)) /*MMC3_CLK*/\
+ MUX_VAL(CP(ETK_CTL_ES2),	(IEN  | PTU | EN  | M2)) /*MMC3_CMD*/\
+ MUX_VAL(CP(ETK_D0_ES2),	(IEN  | PTU | EN  | M2)) /*MMC3_DAT4*/\
+ MUX_VAL(CP(ETK_D1_ES2),	(IEN  | PTD | EN  | M4)) /*GPIO_15 - X_GATE*/\
+ MUX_VAL(CP(ETK_D2_ES2),	(IEN  | PTU | EN  | M4)) /*GPIO_16*/\
+							 /* - W2W_NRESET*/\
+ MUX_VAL(CP(ETK_D3_ES2),	(IEN  | PTU | EN  | M2)) /*MMC3_DAT3*/\
+ MUX_VAL(CP(ETK_D4_ES2),	(IEN  | PTU | EN  | M2)) /*MMC3_DAT0*/\
+ MUX_VAL(CP(ETK_D5_ES2),	(IEN  | PTU | EN  | M2)) /*MMC3_DAT1*/\
+ MUX_VAL(CP(ETK_D6_ES2),	(IEN  | PTU | EN  | M2)) /*MMC3_DAT2*/\
+ MUX_VAL(CP(ETK_D7_ES2),	(IEN  | PTU | EN  | M2)) /*MMC3_DAT7*/\
+ MUX_VAL(CP(ETK_D8_ES2),	(IEN  | PTU | EN  | M2)) /*MMC3_DAT6*/\
+ MUX_VAL(CP(ETK_D9_ES2),	(IEN  | PTU | EN  | M2)) /*MMC3_DAT5*/\
+ MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
+ MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | EN  | M3)) /*HSUSB2_STP*/\
+ MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M3)) /*HSUSB2_DIR*/\
+ MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M3)) /*HSUSB2_NXT*/\
+ MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M3)) /*HSUSB2_DATA0*/\
+ MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M3)) /*HSUSB2_DATA1*/\
+ /* die to die */\
+ MUX_VAL(CP(d2d_mcad1),		(IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
+ MUX_VAL(CP(d2d_mcad2),		(IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
+ MUX_VAL(CP(d2d_mcad3),		(IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
+ MUX_VAL(CP(d2d_mcad4),		(IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
+ MUX_VAL(CP(d2d_mcad5),		(IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
+ MUX_VAL(CP(d2d_mcad6),		(IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
+ MUX_VAL(CP(d2d_mcad7),		(IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
+ MUX_VAL(CP(d2d_mcad8),		(IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
+ MUX_VAL(CP(d2d_mcad9),		(IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
+ MUX_VAL(CP(d2d_mcad10),	(IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
+ MUX_VAL(CP(d2d_mcad11),	(IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
+ MUX_VAL(CP(d2d_mcad12),	(IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
+ MUX_VAL(CP(d2d_mcad13),	(IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
+ MUX_VAL(CP(d2d_mcad14),	(IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
+ MUX_VAL(CP(d2d_mcad15),	(IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
+ MUX_VAL(CP(d2d_mcad16),	(IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
+ MUX_VAL(CP(d2d_mcad17),	(IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
+ MUX_VAL(CP(d2d_mcad18),	(IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
+ MUX_VAL(CP(d2d_mcad19),	(IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
+ MUX_VAL(CP(d2d_mcad20),	(IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
+ MUX_VAL(CP(d2d_mcad21),	(IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
+ MUX_VAL(CP(d2d_mcad22),	(IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
+ MUX_VAL(CP(d2d_mcad23),	(IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
+ MUX_VAL(CP(d2d_mcad24),	(IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
+ MUX_VAL(CP(d2d_mcad25),	(IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
+ MUX_VAL(CP(d2d_mcad26),	(IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
+ MUX_VAL(CP(d2d_mcad27),	(IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
+ MUX_VAL(CP(d2d_mcad28),	(IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
+ MUX_VAL(CP(d2d_mcad29),	(IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
+ MUX_VAL(CP(d2d_mcad30),	(IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
+ MUX_VAL(CP(d2d_mcad31),	(IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
+ MUX_VAL(CP(d2d_mcad32),	(IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
+ MUX_VAL(CP(d2d_mcad33),	(IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
+ MUX_VAL(CP(d2d_mcad34),	(IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
+ MUX_VAL(CP(d2d_mcad35),	(IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
+ MUX_VAL(CP(d2d_mcad36),	(IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
+ MUX_VAL(CP(d2d_clk26mi),	(IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
+ MUX_VAL(CP(d2d_nrespwron),	(IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
+ MUX_VAL(CP(d2d_nreswarm),	(IEN  | PTU | EN  | M0)) /*d2d_nreswarm */\
+ MUX_VAL(CP(d2d_arm9nirq),	(IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */\
+ MUX_VAL(CP(d2d_uma2p6fiq),	(IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+ MUX_VAL(CP(d2d_spint),		(IEN  | PTD | EN  | M0)) /*d2d_spint*/\
+ MUX_VAL(CP(d2d_frint),		(IEN  | PTD | EN  | M0)) /*d2d_frint*/\
+ MUX_VAL(CP(d2d_dmareq0),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
+ MUX_VAL(CP(d2d_dmareq1),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
+ MUX_VAL(CP(d2d_dmareq2),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
+ MUX_VAL(CP(d2d_dmareq3),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
+ MUX_VAL(CP(d2d_n3gtrst),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+ MUX_VAL(CP(d2d_n3gtdi),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+ MUX_VAL(CP(d2d_n3gtdo),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+ MUX_VAL(CP(d2d_n3gtms),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
+ MUX_VAL(CP(d2d_n3gtck),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
+ MUX_VAL(CP(d2d_n3grtck),	(IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
+ MUX_VAL(CP(d2d_mstdby),	(IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
+ MUX_VAL(CP(d2d_swakeup),	(IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
+ MUX_VAL(CP(d2d_idlereq),	(IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
+ MUX_VAL(CP(d2d_idleack),	(IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
+ MUX_VAL(CP(d2d_mwrite),	(IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
+ MUX_VAL(CP(d2d_swrite),	(IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
+ MUX_VAL(CP(d2d_mread),		(IEN  | PTD | DIS | M0)) /*d2d_mread*/\
+ MUX_VAL(CP(d2d_sread),		(IEN  | PTD | DIS | M0)) /*d2d_sread*/\
+ MUX_VAL(CP(d2d_mbusflag),	(IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
+ MUX_VAL(CP(d2d_sbusflag),	(IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
+ MUX_VAL(CP(sdrc_cke0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(sdrc_cke1),		(IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
+
 #endif
Index: u-boot-arm/include/asm-arm/arch-omap3/omap3.h
===================================================================
--- /dev/null
+++ u-boot-arm/include/asm-arm/arch-omap3/omap3.h
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OMAP3_H_
+#define _OMAP3_H_
+
+/* Stuff on L3 Interconnect */
+#define SMX_APE_BASE			0x68000000
+
+/* GPMC */
+#define OMAP34XX_GPMC_BASE		(0x6E000000)
+
+/* SMS */
+#define OMAP34XX_SMS_BASE		0x6C000000
+
+/* SDRC */
+#define OMAP34XX_SDRC_BASE		0x6D000000
+
+/*
+ * L4 Peripherals - L4 Wakeup and L4 Core now
+ */
+#define OMAP34XX_CORE_L4_IO_BASE	0x48000000
+#define OMAP34XX_WAKEUP_L4_IO_BASE	0x48300000
+#define OMAP34XX_L4_PER			0x49000000
+#define OMAP34XX_L4_IO_BASE		OMAP34XX_CORE_L4_IO_BASE
+
+/* CONTROL */
+#define OMAP34XX_CTRL_BASE		(OMAP34XX_L4_IO_BASE+0x2000)
+
+/* UART */
+#define OMAP34XX_UART1			(OMAP34XX_L4_IO_BASE+0x6a000)
+#define OMAP34XX_UART2			(OMAP34XX_L4_IO_BASE+0x6c000)
+#define OMAP34XX_UART3			(OMAP34XX_L4_PER+0x20000)
+
+/* General Purpose Timers */
+#define OMAP34XX_GPT1			0x48318000
+#define OMAP34XX_GPT2			0x49032000
+#define OMAP34XX_GPT3			0x49034000
+#define OMAP34XX_GPT4			0x49036000
+#define OMAP34XX_GPT5			0x49038000
+#define OMAP34XX_GPT6			0x4903A000
+#define OMAP34XX_GPT7			0x4903C000
+#define OMAP34XX_GPT8			0x4903E000
+#define OMAP34XX_GPT9			0x49040000
+#define OMAP34XX_GPT10			0x48086000
+#define OMAP34XX_GPT11			0x48088000
+#define OMAP34XX_GPT12			0x48304000
+
+/* WatchDog Timers (1 secure, 3 GP) */
+#define WD1_BASE			(0x4830C000)
+#define WD2_BASE			(0x48314000)
+#define WD3_BASE			(0x49030000)
+
+/* 32KTIMER */
+#define SYNC_32KTIMER_BASE		(0x48320000)
+#define S32K_CR				(SYNC_32KTIMER_BASE+0x10)
+
+/* omap3 GPIO registers */
+#define OMAP34XX_GPIO1_BASE		0x48310000
+#define OMAP34XX_GPIO2_BASE		0x49050000
+#define OMAP34XX_GPIO3_BASE		0x49052000
+#define OMAP34XX_GPIO4_BASE		0x49054000
+#define OMAP34XX_GPIO5_BASE		0x49056000
+#define OMAP34XX_GPIO6_BASE		0x49058000
+
+/* base address for indirect vectors (internal boot mode) */
+#define SRAM_OFFSET0			0x40000000
+#define SRAM_OFFSET1			0x00200000
+#define SRAM_OFFSET2			0x0000F800
+#define SRAM_VECT_CODE			(SRAM_OFFSET0|SRAM_OFFSET1|\
+					 SRAM_OFFSET2)
+
+#define LOW_LEVEL_SRAM_STACK		0x4020FFFC
+
+#define DEBUG_LED1			149	/* gpio */
+#define DEBUG_LED2			150	/* gpio */
+
+#define XDR_POP		5	/* package on package part */
+#define SDR_DISCRETE	4	/* 128M memory SDR module */
+#define DDR_STACKED	3	/* stacked part on 2422 */
+#define DDR_COMBO	2	/* combo part on cpu daughter card */
+#define DDR_DISCRETE	1	/* 2x16 parts on daughter card */
+
+#define DDR_100		100	/* type found on most mem d-boards */
+#define DDR_111		111	/* some combo parts */
+#define DDR_133		133	/* most combo, some mem d-boards */
+#define DDR_165		165	/* future parts */
+
+#define CPU_3430	0x3430
+
+/* 343x real hardware:
+ *  ES1     = rev 0
+ */
+
+/* 343x code defines:
+ * ES1     = 0+1 = 1
+ * ES1     = 1+1 = 1
+ */
+#define CPU_3430_ES1		1
+#define CPU_3430_ES2		2
+
+#define WIDTH_8BIT		0x0000
+#define WIDTH_16BIT		0x1000	/* bit pos for 16 bit in gpmc */
+
+/* SDP definitions according to FPGA Rev. Is this OK?? */
+#define SDP_3430_V1		0x1
+#define SDP_3430_V2		0x2
+
+/* EVM definitions */
+#define OMAP3EVM_V1		0x1
+#define OMAP3EVM_V2		0x2
+
+#endif
Index: u-boot-arm/include/asm-arm/arch-omap3/sys_proto.h
===================================================================
--- /dev/null
+++ u-boot-arm/include/asm-arm/arch-omap3/sys_proto.h
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+  */
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+typedef struct {
+	u32 board_type_v1;
+	u32 board_type_v2;
+	char *cpu_string;
+	char *board_string;
+} omap3_sysinfo;
+
+void prcm_init(void);
+void per_clocks_enable(void);
+
+void memif_init(void);
+void sdrc_init(void);
+void do_sdrc_init(u32, u32);
+void gpmc_init(void);
+
+void watchdog_init(void);
+void set_muxconf_regs(void);
+
+u32 get_cpu_type(void);
+u32 get_cpu_rev(void);
+u32 get_mem_type(void);
+u32 get_sysboot_value(void);
+u32 get_gpmc0_base(void);
+u32 is_gpmc_muxed(void);
+u32 get_gpmc0_type(void);
+u32 get_gpmc0_width(void);
+u32 get_board_type(void);
+void display_board_info(u32);
+u32 get_sdr_cs_size(u32);
+u32 get_sdr_cs_offset(u32);
+u32 running_in_sdram(void);
+u32 running_in_sram(void);
+u32 running_in_flash(void);
+u32 running_from_internal_boot(void);
+u32 get_device_type(void);
+void l2cache_enable(void);
+void secureworld_exit(void);
+void setup_auxcr(void);
+void try_unlock_memory(void);
+u32 get_boot_type(void);
+void arm_cache_flush(void);
+void v7_flush_dcache_all(u32);
+void sr32(u32, u32, u32, u32);
+u32 wait_on_value(u32, u32, u32, u32);
+void sdelay(unsigned long);
+void make_cs1_contiguous(void);
+void omap_nand_switch_ecc(int);
+
+#endif

[U-Boot] [PATCH 04/13 v4] ARM: OMAP3: Add ARM Cortex A8 common directory

[dirk.behme at googlemail.com]

From: Dirk Behme <dirk.behme@gmail.com>

Add ARM Cortex A8 common directory

Signed-off-by: Dirk Behme <dirk.behme@gmail.com>

---
 cpu/arm_cortexa8/Makefile  |   43 +++
 cpu/arm_cortexa8/config.mk |   36 +++
 cpu/arm_cortexa8/cpu.c     |  221 +++++++++++++++++++
 cpu/arm_cortexa8/start.S   |  522 +++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 822 insertions(+)

Index: u-boot-arm/cpu/arm_cortexa8/cpu.c
===================================================================
--- /dev/null
+++ u-boot-arm/cpu/arm_cortexa8/cpu.c
@@ -0,0 +1,221 @@
+/*
+ * (C) Copyright 2008 Texas Insturments
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/sys_proto.h>
+
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+#ifndef CONFIG_L2_OFF
+void l2cache_disable(void);
+#endif
+
+/* read co-processor 15, register #1 (control register) */
+static unsigned long read_p15_c1(void)
+{
+	unsigned long value;
+
+	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0\
+			     @ read control reg\n":"=r"(value)
+			     ::"memory");
+	return value;
+}
+
+/* write to co-processor 15, register #1 (control register) */
+static void write_p15_c1(unsigned long value)
+{
+	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0\
+			     @ write it back\n"::"r"(value)
+			     : "memory");
+
+	read_p15_c1();
+}
+
+static void cp_delay(void)
+{
+	volatile int i;
+
+	/* Many OMAP regs need at least 2 nops */
+	for (i = 0; i < 100; i++) ;
+}
+
+/* See also ARM Ref. Man. */
+#define C1_MMU		(1<<0)	/* mmu off/on */
+#define C1_ALIGN	(1<<1)	/* alignment faults off/on */
+#define C1_DC		(1<<2)	/* dcache off/on */
+#define C1_WB		(1<<3)	/* merging write buffer on/off */
+#define C1_BIG_ENDIAN	(1<<7)	/* big endian off/on */
+#define C1_SYS_PROT	(1<<8)	/* system protection */
+#define C1_ROM_PROT	(1<<9)	/* ROM protection */
+#define C1_IC		(1<<12)	/* icache off/on */
+#define C1_HIGH_VECTORS	(1<<13)	/* location of vectors: low/high addresses */
+#define RESERVED_1	(0xf << 3)	/* must be 111b for R/W */
+
+int cpu_init(void)
+{
+	/*
+	 * setup up stacks if necessary
+	 */
+#ifdef CONFIG_USE_IRQ
+	IRQ_STACK_START =
+	    _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
+	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
+#endif
+	return 0;
+}
+
+int cleanup_before_linux(void)
+{
+	unsigned int i;
+
+	/*
+	 * this function is called just before we call linux
+	 * it prepares the processor for linux
+	 *
+	 * we turn off caches etc ...
+	 */
+	disable_interrupts();
+
+	/* turn off I/D-cache */
+	asm("mrc p15, 0, %0, c1, c0, 0":"=r"(i));
+	i &= ~(C1_DC | C1_IC);
+	asm("mcr p15, 0, %0, c1, c0, 0": :"r"(i));
+
+	/* invalidate I-cache */
+	arm_cache_flush();
+#ifndef CONFIG_L2_OFF
+	/* turn off L2 cache */
+	l2cache_disable();
+	/* invalidate L2 cache also */
+	v7_flush_dcache_all(get_device_type());
+#endif
+	i = 0;
+	/* mem barrier to sync up things */
+	asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
+
+#ifndef CONFIG_L2_OFF
+	l2cache_enable();
+#endif
+
+	return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	disable_interrupts();
+	reset_cpu(0);
+
+	/* NOTREACHED */
+	return 0;
+}
+
+void icache_enable(void)
+{
+	ulong reg;
+
+	reg = read_p15_c1();	/* get control reg. */
+	cp_delay();
+	write_p15_c1(reg | C1_IC);
+}
+
+void icache_disable(void)
+{
+	ulong reg;
+
+	reg = read_p15_c1();
+	cp_delay();
+	write_p15_c1(reg & ~C1_IC);
+}
+
+void l2cache_enable()
+{
+	unsigned long i;
+	volatile unsigned int j;
+
+	/* ES2 onwards we can disable/enable L2 ourselves */
+	if (get_cpu_rev() == CPU_3430_ES2) {
+		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
+		__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
+		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
+	} else {
+		/* Save r0, r12 and restore them after usage */
+		__asm__ __volatile__("mov %0, r12":"=r"(j));
+		__asm__ __volatile__("mov %0, r0":"=r"(i));
+
+		/* GP Device ROM code API usage here */
+		/* r12 = AUXCR Write function and r0 value */
+		__asm__ __volatile__("mov r12, #0x3");
+		__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
+		__asm__ __volatile__("orr r0, r0, #0x2");
+		/* SMI instruction to call ROM Code API */
+		__asm__ __volatile__(".word 0xE1600070");
+		__asm__ __volatile__("mov r0, %0":"=r"(i));
+		__asm__ __volatile__("mov r12, %0":"=r"(j));
+	}
+
+}
+
+void l2cache_disable()
+{
+	unsigned long i;
+	volatile unsigned int j;
+
+	/* ES2 onwards we can disable/enable L2 ourselves */
+	if (get_cpu_rev() == CPU_3430_ES2) {
+		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
+		__asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
+		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
+	} else {
+		/* Save r0, r12 and restore them after usage */
+		__asm__ __volatile__("mov %0, r12":"=r"(j));
+		__asm__ __volatile__("mov %0, r0":"=r"(i));
+
+		/* GP Device ROM code API usage here */
+		/* r12 = AUXCR Write function and r0 value */
+		__asm__ __volatile__("mov r12, #0x3");
+		__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
+		__asm__ __volatile__("bic r0, r0, #0x2");
+		/* SMI instruction to call ROM Code API */
+		__asm__ __volatile__(".word 0xE1600070");
+		__asm__ __volatile__("mov r0, %0":"=r"(i));
+		__asm__ __volatile__("mov r12, %0":"=r"(j));
+	}
+}
+
+int icache_status(void)
+{
+	return (read_p15_c1() & C1_IC) != 0;
+}
Index: u-boot-arm/cpu/arm_cortexa8/Makefile
===================================================================
--- /dev/null
+++ u-boot-arm/cpu/arm_cortexa8/Makefile
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(CPU).a
+
+START	:= start.o
+OBJS	:= cpu.o
+
+all:	.depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(START:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
\ No newline at end of file
Index: u-boot-arm/cpu/arm_cortexa8/config.mk
===================================================================
--- /dev/null
+++ u-boot-arm/cpu/arm_cortexa8/config.mk
@@ -0,0 +1,36 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
+		     -msoft-float
+
+# Make ARMv5 to allow more compilers to work, even though its v7a.
+PLATFORM_CPPFLAGS += -march=armv5
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# =========================================================================
+PLATFORM_CPPFLAGS +=$(call cc-option)
+PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
+		    $(call cc-option,-malignment-traps,))
\ No newline at end of file
Index: u-boot-arm/cpu/arm_cortexa8/start.S
===================================================================
--- /dev/null
+++ u-boot-arm/cpu/arm_cortexa8/start.S
@@ -0,0 +1,522 @@
+/*
+ *  armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
+ *
+ *  Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
+ *
+ *  Copyright (c) 2001	Marius Gr??ger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Z??pke <azu@sysgo.de>
+ *  Copyright (c) 2002	Gary Jennejohn <gj@denx.de>
+ *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
+ *  Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+.globl _start
+_start: b	reset
+	ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+	ldr	pc, _not_used
+	ldr	pc, _irq
+	ldr	pc, _fiq
+
+_undefined_instruction: .word undefined_instruction
+_software_interrupt:	.word software_interrupt
+_prefetch_abort:	.word prefetch_abort
+_data_abort:		.word data_abort
+_not_used:		.word not_used
+_irq:			.word irq
+_fiq:			.word fiq
+_pad:			.word 0x12345678 /* now 16*4=64 */
+.global _end_vect
+_end_vect:
+
+	.balignl 16,0xdeadbeef
+/*************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************/
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+.globl _armboot_start
+_armboot_start:
+	.word _start
+
+/*
+ * These are defined in the board-specific linker script.
+ */
+.globl _bss_start
+_bss_start:
+	.word __bss_start
+
+.globl _bss_end
+_bss_end:
+	.word _end
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word	0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+/*
+ * the actual reset code
+ */
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x1f
+	orr	r0,r0,#0xd3
+	msr	cpsr,r0
+
+#if (CONFIG_OMAP34XX)
+	/* Copy vectors to mask ROM indirect addr */
+	adr	r0, _start		@ r0 <- current position of code
+	add	r0, r0, #4		@ skip reset vector
+	mov	r2, #64			@ r2 <- size to copy
+	add	r2, r0, r2		@ r2 <- source end address
+	mov	r1, #SRAM_OFFSET0	@ build vect addr
+	mov	r3, #SRAM_OFFSET1
+	add	r1, r1, r3
+	mov	r3, #SRAM_OFFSET2
+	add	r1, r1, r3
+next:
+	ldmia	r0!, {r3-r10}		@ copy from source address [r0]
+	stmia	r1!, {r3-r10}		@ copy to   target address [r1]
+	cmp	r0, r2			@ until source end address [r2]
+	bne	next			@ loop until equal */
+#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
+	/* No need to copy/exec the clock code - DPLL adjust already done
+	 * in NAND/oneNAND Boot.
+	 */
+	bl	cpy_clk_code		@ put dpll adjust code behind vectors
+#endif /* NAND Boot */
+#endif
+	/* the mask ROM code should have PLL and others stable */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	bl	cpu_init_crit
+#endif
+
+#ifndef CONFIG_SKIP_RELOCATE_UBOOT
+relocate:				@ relocate U-Boot to RAM
+	adr	r0, _start		@ r0 <- current position of code
+	ldr	r1, _TEXT_BASE		@ test if we run from flash or RAM
+	cmp	r0, r1			@ don't reloc during debug
+	beq	stack_setup
+
+	ldr	r2, _armboot_start
+	ldr	r3, _bss_start
+	sub	r2, r3, r2		@ r2 <- size of armboot
+	add	r2, r0, r2		@ r2 <- source end address
+
+copy_loop:				@ copy 32 bytes at a time
+	ldmia	r0!, {r3-r10}		@ copy from source address [r0]
+	stmia	r1!, {r3-r10}		@ copy to   target address [r1]
+	cmp	r0, r2			@ until source end addreee [r2]
+	ble	copy_loop
+#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
+
+	/* Set up the stack */
+stack_setup:
+	ldr	r0, _TEXT_BASE		@ upper 128 KiB: relocated uboot
+	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN @ malloc area
+	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE @ bdinfo
+#ifdef CONFIG_USE_IRQ
+	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
+#endif
+	sub	sp, r0, #12		@ leave 3 words for abort-stack
+	and	sp, sp, #~7		@ 8 byte alinged for (ldr/str)d
+
+	/* Clear BSS (if any). Is below tx (watch load addr - need space) */
+clear_bss:
+	ldr	r0, _bss_start		@ find start of bss segment
+	ldr	r1, _bss_end		@ stop here
+	mov 	r2, #0x00000000		@ clear value
+clbss_l:
+	str	r2, [r0]		@ clear BSS location
+	cmp	r0, r1			@ are we at the end yet
+	add	r0, r0, #4		@ increment clear index pointer
+	bne	clbss_l			@ keep clearing till at end
+
+	ldr	pc, _start_armboot	@ jump to C code
+
+_start_armboot: .word start_armboot
+
+
+/*************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************/
+cpu_init_crit:
+	/*
+	 * Invalidate L1 I/D
+	 */
+	mov	r0, #0			@ set up for MCR
+	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
+	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002000	@ clear bits 13 (--V-)
+	bic	r0, r0, #0x00000007	@ clear bits 2:0 (-CAM)
+	orr	r0, r0, #0x00000002	@ set bit 1 (--A-) Align
+	orr	r0, r0, #0x00000800	@ set bit 12 (Z---) BTB
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/*
+	 * Jump to board specific initialization...
+	 * The Mask ROM will have already initialized
+	 * basic memory. Go here to bump up clock rate and handle
+	 * wake up conditions.
+	 */
+	mov	ip, lr			@ persevere link reg across call
+	bl	lowlevel_init		@ go setup pll,mux,memory
+	mov	lr, ip			@ restore link
+	mov	pc, lr			@ back to my caller
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE	72
+
+#define S_OLD_R0	68
+#define S_PSR		64
+#define S_PC		60
+#define S_LR		56
+#define S_SP		52
+
+#define S_IP		48
+#define S_FP		44
+#define S_R10		40
+#define S_R9		36
+#define S_R8		32
+#define S_R7		28
+#define S_R6		24
+#define S_R5		20
+#define S_R4		16
+#define S_R3		12
+#define S_R2		8
+#define S_R1		4
+#define S_R0		0
+
+#define MODE_SVC 0x13
+#define I_BIT	 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+	.macro	bad_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current
+						@ user stack
+	stmia	sp, {r0 - r12}			@ Save user registers (now in
+						@ svc mode) r0-r12
+
+	ldr	r2, _armboot_start
+	sub	r2, r2, #(CONFIG_SYS_MALLOC_LEN)
+	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)	@ set base 2 words into abort
+						@ stack
+	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc
+						@ and cpsr (into parm regs)
+	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
+
+	add	r5, sp, #S_SP
+	mov	r1, lr
+	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
+	mov	r0, sp				@ save current stack into r0
+						@ (param register)
+	.endm
+
+	.macro	irq_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	add	r8, sp, #S_PC			@ !! R8 NEEDS to be saved !!
+						@ a reserved stack spot would
+						@ be good.
+	stmdb	r8, {sp, lr}^			@ Calling SP, LR
+	str	lr, [r8, #0]			@ Save calling PC
+	mrs	r6, spsr
+	str	r6, [r8, #4]			@ Save CPSR
+	str	r0, [r8, #8]			@ Save OLD_R0
+	mov	r0, sp
+	.endm
+
+	.macro	irq_restore_user_regs
+	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
+	mov	r0, r0
+	ldr	lr, [sp, #S_PC]			@ Get PC
+	add	sp, sp, #S_FRAME_SIZE
+	subs	pc, lr, #4			@ return & move spsr_svc into
+						@ cpsr
+	.endm
+
+	.macro get_bad_stack
+	ldr	r13, _armboot_start		@ setup our mode stack (enter
+						@ in banked mode)
+	sub	r13, r13, #(CONFIG_SYS_MALLOC_LEN)	@ move past malloc pool
+	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move to reserved a couple
+						@ spots for abort stack
+
+	str	lr, [r13]			@ save caller lr in position 0
+						@ of saved stack
+	mrs	lr, spsr			@ get the spsr
+	str	lr, [r13, #4]			@ save spsr in position 1 of
+						@ saved stack
+
+	mov	r13, #MODE_SVC			@ prepare SVC-Mode
+	@ msr	spsr_c, r13
+	msr	spsr, r13			@ switch modes, make sure
+						@ moves will execute
+	mov	lr, pc				@ capture return pc
+	movs	pc, lr				@ jump to next instruction &
+						@ switch modes.
+	.endm
+
+	.macro get_bad_stack_swi
+	sub	r13, r13, #4			@ space on current stack for
+						@ scratch reg.
+	str	r0, [r13]			@ save R0's value.
+	ldr	r0, _armboot_start		@ get data regions start
+	sub	r0, r0, #(CONFIG_SYS_MALLOC_LEN)	@ move past malloc pool
+	sub	r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE+8)	@ move past gbl and a couple
+						@ spots for abort stack
+	str	lr, [r0]			@ save caller lr in position 0
+						@ of saved stack
+	mrs	r0, spsr			@ get the spsr
+	str	lr, [r0, #4]			@ save spsr in position 1 of
+						@ saved stack
+	ldr	r0, [r13]			@ restore r0
+	add	r13, r13, #4			@ pop stack entry
+	.endm
+
+	.macro get_irq_stack			@ setup IRQ stack
+	ldr	sp, IRQ_STACK_START
+	.endm
+
+	.macro get_fiq_stack			@ setup FIQ stack
+	ldr	sp, FIQ_STACK_START
+	.endm
+
+/*
+ * exception handlers
+ */
+	.align	5
+undefined_instruction:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_undefined_instruction
+
+	.align	5
+software_interrupt:
+	get_bad_stack_swi
+	bad_save_user_regs
+	bl	do_software_interrupt
+
+	.align	5
+prefetch_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_prefetch_abort
+
+	.align	5
+data_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_data_abort
+
+	.align	5
+not_used:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+	.align	5
+irq:
+	get_irq_stack
+	irq_save_user_regs
+	bl	do_irq
+	irq_restore_user_regs
+
+	.align	5
+fiq:
+	get_fiq_stack
+	/* someone ought to write a more effiction fiq_save_user_regs */
+	irq_save_user_regs
+	bl	do_fiq
+	irq_restore_user_regs
+
+#else
+
+	.align	5
+irq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_irq
+
+	.align	5
+fiq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_fiq
+
+#endif
+	.align 5
+.global arm_cache_flush
+arm_cache_flush:
+	mcr	p15, 0, r1, c7, c5, 0		@ invalidate I cache
+	mov	pc, lr				@ back to caller
+
+/*
+ *	v7_flush_dcache_all()
+ *
+ *	Flush the whole D-cache.
+ *
+ *	Corrupted registers: r0-r5, r7, r9-r11
+ *
+ *	- mm	- mm_struct describing address space
+ */
+	.align 5
+.global v7_flush_dcache_all
+v7_flush_dcache_all:
+	stmfd	r13!, {r0-r5, r7, r9-r12,r14}
+
+	mov	r7, r0				@ take a backup of device type
+	cmp	r0, #0x3			@ check if the device type is
+						@ GP
+	moveq r12, #0x1				@ set up to invalide L2
+smi: 	.word 0x01600070			@ Call SMI monitor (smieq)
+	cmp	r7, #0x3			@ compare again in case its
+						@ lost
+	beq	finished_inval			@ if GP device, inval done
+						@ above
+
+	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
+	ands	r3, r0, #0x7000000		@ extract loc from clidr
+	mov	r3, r3, lsr #23			@ left align loc bit field
+	beq	finished_inval			@ if loc is 0, then no need to
+						@ clean
+	mov	r10, #0				@ start clean@cache level 0
+inval_loop1:
+	add	r2, r10, r10, lsr #1		@ work out 3x current cache
+						@ level
+	mov	r1, r0, lsr r2			@ extract cache type bits from
+						@ clidr
+	and	r1, r1, #7			@ mask of the bits for current
+						@ cache only
+	cmp	r1, #2				@ see what cache we have at
+						@ this level
+	blt	skip_inval			@ skip if no cache, or just
+						@ i-cache
+	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level
+						@ in cssr
+	mov	r2, #0				@ operand for mcr SBZ
+	mcr	p15, 0, r2, c7, c5, 4		@ flush prefetch buffer to
+						@ sych the new cssr&csidr,
+						@ with armv7 this is 'isb',
+						@ but we compile with armv5
+	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
+	and	r2, r1, #7			@ extract the length of the
+						@ cache lines
+	add	r2, r2, #4			@ add 4 (line length offset)
+	ldr	r4, =0x3ff
+	ands	r4, r4, r1, lsr #3		@ find maximum number on the
+						@ way size
+	clz	r5, r4				@ find bit position of way
+						@ size increment
+	ldr	r7, =0x7fff
+	ands	r7, r7, r1, lsr #13		@ extract max number of the
+						@ index size
+inval_loop2:
+	mov	r9, r4				@ create working copy of max
+						@ way size
+inval_loop3:
+	orr	r11, r10, r9, lsl r5		@ factor way and cache number
+						@ into r11
+	orr	r11, r11, r7, lsl r2		@ factor index number into r11
+	mcr	p15, 0, r11, c7, c6, 2		@ invalidate by set/way
+	subs	r9, r9, #1			@ decrement the way
+	bge	inval_loop3
+	subs	r7, r7, #1			@ decrement the index
+	bge	inval_loop2
+skip_inval:
+	add	r10, r10, #2			@ increment cache number
+	cmp	r3, r10
+	bgt	inval_loop1
+finished_inval:
+	mov	r10, #0				@ swith back to cache level 0
+	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level
+						@ in cssr
+	mcr	p15, 0, r10, c7, c5, 4		@ flush prefetch buffer,
+						@ with armv7 this is 'isb',
+						@ but we compile with armv5
+
+	ldmfd	r13!, {r0-r5, r7, r9-r12,pc}
+
+
+	.align	5
+.global reset_cpu
+reset_cpu:
+	ldr	r1, rstctl			@ get addr for global reset
+						@ reg
+	mov	r3, #0x2			@ full reset pll + mpu
+	str	r3, [r1]			@ force reset
+	mov	r0, r0
+_loop_forever:
+	b	_loop_forever
+rstctl:
+	.word	PRM_RSTCTRL
+

[U-Boot] [PATCH 05/13 v4] ARM: OMAP3: Add lowlevel init and sys_info common files

[dirk.behme at googlemail.com]

Subject: [PATCH 05/13 v4] ARM: OMAP3: Add lowlevel init and sys_info common files

From: Dirk Behme <dirk.behme@gmail.com>

Add assembly lowlevel init and sys_info common files

Signed-off-by: Dirk Behme <dirk.behme@gmail.com>

---

Changes in version v3:
- Add detection and support for 128MB/256MB RAM by Mans Rullgard

Changes in version v2:

- Move common ARM Cortex A8 code to cpu/arm_cortexa8/ and OMAP3 SoC specific common code to cpu/arm_cortexa8/omap3 as proposed by Wolfgang.

 cpu/arm_cortexa8/omap3/Makefile        |   43 +++
 cpu/arm_cortexa8/omap3/config.mk       |   36 +++
 cpu/arm_cortexa8/omap3/lowlevel_init.S |  360 +++++++++++++++++++++++++++++++++
 cpu/arm_cortexa8/omap3/sys_info.c      |  333 ++++++++++++++++++++++++++++++
 4 files changed, 772 insertions(+)

Index: u-boot-arm/cpu/arm_cortexa8/omap3/Makefile
===================================================================
--- /dev/null
+++ u-boot-arm/cpu/arm_cortexa8/omap3/Makefile
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(SOC).a
+
+SOBJS	:= lowlevel_init.o
+OBJS	:= sys_info.o
+
+all:	.depend $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:	Makefile $(OBJS:.o=.c) $(SOBJS:.o=.S)
+		$(CC) -M $(CFLAGS) $(OBJS:.o=.c) $(SOBJS:.o=.S) > $@
+
+sinclude .depend
+
+#########################################################################
Index: u-boot-arm/cpu/arm_cortexa8/omap3/config.mk
===================================================================
--- /dev/null
+++ u-boot-arm/cpu/arm_cortexa8/omap3/config.mk
@@ -0,0 +1,36 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
+		     -msoft-float
+
+# Make ARMv5 to allow more compilers to work, even though its v7a.
+PLATFORM_CPPFLAGS += -march=armv5
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# =========================================================================
+PLATFORM_CPPFLAGS +=$(call cc-option)
+PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
+		    $(call cc-option,-malignment-traps,))
Index: u-boot-arm/cpu/arm_cortexa8/omap3/lowlevel_init.S
===================================================================
--- /dev/null
+++ u-boot-arm/cpu/arm_cortexa8/omap3/lowlevel_init.S
@@ -0,0 +1,360 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Initial Code by:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks_omap3.h>
+
+_TEXT_BASE:
+	.word	TEXT_BASE	/* sdram load addr from config.mk */
+
+#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
+/**************************************************************************
+ * cpy_clk_code: relocates clock code into SRAM where its safer to execute
+ * R1 = SRAM destination address.
+ *************************************************************************/
+.global cpy_clk_code
+ cpy_clk_code:
+	/* Copy DPLL code into SRAM */
+	adr	r0, go_to_speed		/* get addr of clock setting code */
+	mov	r2, #384		/* r2 size to copy (div by 32 bytes) */
+	mov	r1, r1			/* r1 <- dest address (passed in) */
+	add	r2, r2, r0		/* r2 <- source end address */
+next2:
+	ldmia	r0!, {r3-r10}		/* copy from source address [r0] */
+	stmia	r1!, {r3-r10}		/* copy to   target address [r1] */
+	cmp	r0, r2			/* until source end address [r2] */
+	bne	next2
+	mov	pc, lr			/* back to caller */
+
+/* ***************************************************************************
+ *  go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
+ *               -executed from SRAM.
+ *  R0 = CM_CLKEN_PLL-bypass value
+ *  R1 = CM_CLKSEL1_PLL-m, n, and divider values
+ *  R2 = CM_CLKSEL_CORE-divider values
+ *  R3 = CM_IDLEST_CKGEN - addr dpll lock wait
+ *
+ *  Note: If core unlocks/relocks and SDRAM is running fast already it gets
+ *        confused.  A reset of the controller gets it back.  Taking away its
+ *        L3 when its not in self refresh seems bad for it.  Normally, this
+ *	  code runs from flash before SDR is init so that should be ok.
+ ****************************************************************************/
+.global go_to_speed
+ go_to_speed:
+	stmfd sp!, {r4-r6}
+
+	/* move into fast relock bypass */
+	ldr	r4, pll_ctl_add
+	str	r0, [r4]
+wait1:
+	ldr	r5, [r3]		/* get status */
+	and	r5, r5, #0x1		/* isolate core status */
+	cmp	r5, #0x1		/* still locked? */
+	beq	wait1			/* if lock, loop */
+
+	/* set new dpll dividers _after_ in bypass */
+	ldr	r5, pll_div_add1
+	str	r1, [r5]		/* set m, n, m2 */
+	ldr	r5, pll_div_add2
+	str	r2, [r5]		/* set l3/l4/.. dividers*/
+	ldr	r5, pll_div_add3	/* wkup */
+	ldr	r2, pll_div_val3	/* rsm val */
+	str	r2, [r5]
+	ldr	r5, pll_div_add4	/* gfx */
+	ldr	r2, pll_div_val4
+	str	r2, [r5]
+	ldr	r5, pll_div_add5	/* emu */
+	ldr	r2, pll_div_val5
+	str	r2, [r5]
+
+	/* now prepare GPMC (flash) for new dpll speed */
+	/* flash needs to be stable when we jump back to it */
+	ldr	r5, flash_cfg3_addr
+	ldr	r2, flash_cfg3_val
+	str	r2, [r5]
+	ldr	r5, flash_cfg4_addr
+	ldr	r2, flash_cfg4_val
+	str	r2, [r5]
+	ldr	r5, flash_cfg5_addr
+	ldr	r2, flash_cfg5_val
+	str	r2, [r5]
+	ldr	r5, flash_cfg1_addr
+	ldr	r2, [r5]
+	orr	r2, r2, #0x3		/* up gpmc divider */
+	str	r2, [r5]
+
+	/* lock DPLL3 and wait a bit */
+	orr	r0, r0, #0x7	/* set up for lock mode */
+	str	r0, [r4]	/* lock */
+	nop			/* ARM slow at this point working at sys_clk */
+	nop
+	nop
+	nop
+wait2:
+	ldr	r5, [r3]	/* get status */
+	and	r5, r5, #0x1	/* isolate core status */
+	cmp	r5, #0x1	/* still locked? */
+	bne	wait2		/* if lock, loop */
+	nop
+	nop
+	nop
+	nop
+	ldmfd sp!, {r4-r6}
+	mov	pc, lr		/* back to caller, locked */
+
+_go_to_speed: .word go_to_speed
+
+/* these constants need to be close for PIC code */
+/* The Nor has to be in the Flash Base CS0 for this condition to happen */
+flash_cfg1_addr:
+	.word (GPMC_CONFIG_CS0 + GPMC_CONFIG1)
+flash_cfg3_addr:
+	.word (GPMC_CONFIG_CS0 + GPMC_CONFIG3)
+flash_cfg3_val:
+	.word STNOR_GPMC_CONFIG3
+flash_cfg4_addr:
+	.word (GPMC_CONFIG_CS0 + GPMC_CONFIG4)
+flash_cfg4_val:
+	.word STNOR_GPMC_CONFIG4
+flash_cfg5_val:
+	.word STNOR_GPMC_CONFIG5
+flash_cfg5_addr:
+	.word (GPMC_CONFIG_CS0 + GPMC_CONFIG5)
+pll_ctl_add:
+	.word CM_CLKEN_PLL
+pll_div_add1:
+	.word CM_CLKSEL1_PLL
+pll_div_add2:
+	.word CM_CLKSEL_CORE
+pll_div_add3:
+	.word CM_CLKSEL_WKUP
+pll_div_val3:
+	.word (WKUP_RSM << 1)
+pll_div_add4:
+	.word CM_CLKSEL_GFX
+pll_div_val4:
+	.word (GFX_DIV << 0)
+pll_div_add5:
+	.word CM_CLKSEL1_EMU
+pll_div_val5:
+	.word CLSEL1_EMU_VAL
+
+#endif
+
+.globl lowlevel_init
+lowlevel_init:
+	ldr	sp,	SRAM_STACK
+	str	ip,	[sp]	/* stash old link register */
+	mov	ip,	lr	/* save link reg across call */
+	bl	 s_init		/* go setup pll,mux,memory */
+	ldr	ip,	[sp]	/* restore save ip */
+	mov	lr,	ip	/* restore link reg */
+
+	/* back to arch calling code */
+	mov	pc,	lr
+
+	/* the literal pools origin */
+	.ltorg
+
+REG_CONTROL_STATUS:
+	.word CONTROL_STATUS
+SRAM_STACK:
+	.word LOW_LEVEL_SRAM_STACK
+
+/* DPLL(1-4) PARAM TABLES */
+/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
+ * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c).
+ * The values are defined for all possible sysclk and for ES1 and ES2.
+ */
+
+mpu_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x0FE,0x07,0x05,0x01
+/* ES2 */
+.word 0x0FA,0x05,0x07,0x01
+/* 3410 */
+.word 0x085,0x05,0x07,0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x17D,0x0C,0x03,0x01
+/* ES2 */
+.word 0x1F4,0x0C,0x03,0x01
+/* 3410 */
+.word 0x10A,0x0C,0x03,0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x179,0x12,0x04,0x01
+/* ES2 */
+.word 0x271,0x17,0x03,0x01
+/* 3410 */
+.word 0x14C,0x17,0x03,0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x17D,0x19,0x03,0x01
+/* ES2 */
+.word 0x0FA,0x0C,0x07,0x01
+/* 3410 */
+.word 0x085,0x0C,0x07,0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x1FA,0x32,0x03,0x01
+/* ES2 */
+.word 0x271,0x2F,0x03,0x01
+/* 3410 */
+.word 0x14C,0x2F,0x03,0x01
+
+
+.globl get_mpu_dpll_param
+get_mpu_dpll_param:
+	adr r0, mpu_dpll_param
+	mov pc, lr
+
+iva_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x07D,0x05,0x07,0x01
+/* ES2 */
+.word 0x0B4,0x05,0x07,0x01
+/* 3410 */
+.word 0x085,0x05,0x07,0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x0FA,0x0C,0x03,0x01
+/* ES2 */
+.word 0x168,0x0C,0x03,0x01
+/* 3410 */
+.word 0x10A,0x0C,0x03,0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x082,0x09,0x07,0x01
+/* ES2 */
+.word 0x0E1,0x0B,0x06,0x01
+/* 3410 */
+.word 0x14C,0x17,0x03,0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x07D,0x0C,0x07,0x01
+/* ES2 */
+.word 0x0B4,0x0C,0x07,0x01
+/* 3410 */
+.word 0x085,0x0C,0x07,0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x13F,0x30,0x03,0x01
+/* ES2 */
+.word 0x0E1,0x17,0x06,0x01
+/* 3410 */
+.word 0x14C,0x2F,0x03,0x01
+
+
+.globl get_iva_dpll_param
+get_iva_dpll_param:
+	adr r0, iva_dpll_param
+	mov pc, lr
+
+/* Core DPLL targets for L3@166 & L133 */
+core_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1
+/* ES2 */
+.word M_12,N_12,FSEL_12,M2_12
+/* 3410 */
+.word M_12,N_12,FSEL_12,M2_12
+
+/* 13MHz */
+/* ES1 */
+.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1
+/* ES2 */
+.word M_13,N_13,FSEL_13,M2_13
+/* 3410 */
+.word M_13,N_13,FSEL_13,M2_13
+
+/* 19.2MHz */
+/* ES1 */
+.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1
+/* ES2 */
+.word M_19p2,N_19p2,FSEL_19p2,M2_19p2
+/* 3410 */
+.word M_19p2,N_19p2,FSEL_19p2,M2_19p2
+
+/* 26MHz */
+/* ES1 */
+.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1
+/* ES2 */
+.word M_26,N_26,FSEL_26,M2_26
+/* 3410 */
+.word M_26,N_26,FSEL_26,M2_26
+
+/* 38.4MHz */
+/* ES1 */
+.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1
+/* ES2 */
+.word M_38p4,N_38p4,FSEL_38p4,M2_38p4
+/* 3410 */
+.word M_38p4,N_38p4,FSEL_38p4,M2_38p4
+
+.globl get_core_dpll_param
+get_core_dpll_param:
+	adr r0, core_dpll_param
+	mov pc, lr
+
+/* PER DPLL values are same for both ES1 and ES2 */
+per_dpll_param:
+/* 12MHz */
+.word 0xD8,0x05,0x07,0x09
+
+/* 13MHz */
+.word 0x1B0,0x0C,0x03,0x09
+
+/* 19.2MHz */
+.word 0xE1,0x09,0x07,0x09
+
+/* 26MHz */
+.word 0xD8,0x0C,0x07,0x09
+
+/* 38.4MHz */
+.word 0xE1,0x13,0x07,0x09
+
+.globl get_per_dpll_param
+get_per_dpll_param:
+	adr r0, per_dpll_param
+	mov pc, lr
+
Index: u-boot-arm/cpu/arm_cortexa8/omap3/sys_info.c
===================================================================
--- /dev/null
+++ u-boot-arm/cpu/arm_cortexa8/omap3/sys_info.c
@@ -0,0 +1,333 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *      Manikandan Pillai <mani.pillai@ti.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *      Richard Woodruff <r-woodruff2@ti.com>
+ *      Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mem.h>	/* get mem tables */
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+
+extern omap3_sysinfo sysinfo;
+
+/**************************************************************************
+ * get_gpmc0_type()
+ ***************************************************************************/
+u32 get_gpmc0_type(void)
+{
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
+	return 1; /* OneNAND */
+#else
+	return 2; /* NAND */
+#endif
+}
+
+/****************************************************
+ * get_cpu_type() - low level get cpu type
+ * - no C globals yet.
+ ****************************************************/
+u32 get_cpu_type(void)
+{
+	/* fixme, need to get register defines for OMAP3 */
+	return CPU_3430;
+}
+
+/******************************************
+ * get_cpu_rev(void) - extract version info
+ ******************************************/
+u32 get_cpu_rev(void)
+{
+	u32 cpuid = 0;
+	/* On ES1.0 the IDCODE register is not exposed on L4
+	 * so using CPU ID to differentiate
+	 * between ES2.0 and ES1.0.
+	 */
+	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
+	if ((cpuid & 0xf) == 0x0)
+		return CPU_3430_ES1;
+	else
+		return CPU_3430_ES2;
+
+}
+
+/****************************************************
+ * is_mem_sdr() - return 1 if mem type in use is SDR
+ ****************************************************/
+u32 is_mem_sdr(void)
+{
+	volatile u32 *burst = (volatile u32 *) (SDRC_MR_0 + SDRC_CS0_OSET);
+	if (*burst == SDP_SDRC_MR_0_SDR)
+		return 1;
+	return 0;
+}
+
+/***********************************************************
+ * get_mem_type() - identify type of mDDR part used.
+ ***********************************************************/
+u32 get_mem_type(void)
+{
+#ifdef CONFIG_OMAP3_BEAGLE
+	return DDR_STACKED;
+#else
+	return DDR_DISCRETE;
+#endif
+}
+
+/***********************************************************************
+ * get_cs0_size() - get size of chip select 0/1
+ ************************************************************************/
+u32 get_sdr_cs_size(u32 offset)
+{
+	u32 size;
+
+	/* get ram size field */
+	size = readl(SDRC_MCFG_0 + offset) >> 8;
+	size &= 0x3FF;		/* remove unwanted bits */
+	size *= SZ_2M;		/* find size in MB */
+	return size;
+}
+
+/***********************************************************************
+ * get_sdr_cs_offset() - get offset of cs from cs0 start
+ ************************************************************************/
+u32 get_sdr_cs_offset(u32 cs)
+{
+	u32 offset;
+
+	if (!cs)
+		return 0;
+
+	offset = readl(SDRC_CS_CFG);
+	offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
+
+	return offset;
+}
+
+/***********************************************************************
+ * get_board_type() - get board type based on current production stats.
+ *  - NOTE-1-: 2 I2C EEPROMs will someday be populated with proper info.
+ *    when they are available we can get info from there.  This should
+ *    be correct of all known boards up until today.
+ *  - NOTE-2- EEPROMs are populated but they are updated very slowly.  To
+ *    avoid waiting on them we will use ES version of the chip to get info.
+ *    A later version of the FPGA migth solve their speed issue.
+ ************************************************************************/
+u32 get_board_type(void)
+{
+	if (get_cpu_rev() == CPU_3430_ES2)
+		return sysinfo.board_type_v2;
+	else
+		return sysinfo.board_type_v1;
+}
+
+/******************************************************************
+ * get_sysboot_value() - get init word settings
+ ******************************************************************/
+inline u32 get_sysboot_value(void)
+{
+	return 0x0000003F & readl(CONTROL_STATUS);
+}
+
+/***************************************************************************
+ *  get_gpmc0_base() - Return current address hardware will be
+ *     fetching from. The below effectively gives what is correct, its a bit
+ *   mis-leading compared to the TRM.  For the most general case the mask
+ *   needs to be also taken into account this does work in practice.
+ *   - for u-boot we currently map:
+ *       -- 0 to nothing,
+ *       -- 4 to flash
+ *       -- 8 to enent
+ *       -- c to wifi
+ ****************************************************************************/
+u32 get_gpmc0_base(void)
+{
+	u32 b;
+
+	b = readl(GPMC_CONFIG_CS0 + GPMC_CONFIG7);
+	b &= 0x1F;		/* keep base [5:0] */
+	b = b << 24;		/* ret 0x0b000000 */
+	return b;
+}
+
+/*******************************************************************
+ * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
+ *******************************************************************/
+u32 get_gpmc0_width(void)
+{
+	return WIDTH_16BIT;
+}
+
+/*************************************************************************
+ * get_board_rev() - setup to pass kernel board revision information
+ * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
+ *************************************************************************/
+u32 get_board_rev(void)
+{
+	return 0x20;
+}
+
+/*********************************************************************
+ *  display_board_info() - print banner with board info.
+ *********************************************************************/
+void display_board_info(u32 btype)
+{
+	char *bootmode[] = {
+		"NOR",
+		"ONENAND",
+		"NAND",
+		"P2a",
+		"NOR",
+		"NOR",
+		"P2a",
+		"P2b",
+	};
+	u32 brev = get_board_rev();
+	char db_ver[] = "0.0";	/* board type */
+	char mem_sdr[] = "mSDR";	/* memory type */
+	char mem_ddr[] = "LPDDR";
+	char t_tst[] = "TST";	/* security level */
+	char t_emu[] = "EMU";
+	char t_hs[] = "HS";
+	char t_gp[] = "GP";
+	char unk[] = "?";
+#ifdef CONFIG_LED_INFO
+	char led_string[CONFIG_LED_LEN] = { 0 };
+#endif
+	char p_l3[] = "165";
+	char p_cpu[] = "2";
+
+	char *db_s, *mem_s, *sec_s;
+	u32 cpu, rev, sec;
+
+	rev = get_cpu_rev();
+	cpu = get_cpu_type();
+	sec = get_device_type();
+
+	if (is_mem_sdr())
+		mem_s = mem_sdr;
+	else
+		mem_s = mem_ddr;
+
+	db_s = db_ver;
+	db_s[0] += (brev >> 4) & 0xF;
+	db_s[2] += brev & 0xF;
+
+	switch (sec) {
+	case TST_DEVICE:
+		sec_s = t_tst;
+		break;
+	case EMU_DEVICE:
+		sec_s = t_emu;
+		break;
+	case HS_DEVICE:
+		sec_s = t_hs;
+		break;
+	case GP_DEVICE:
+		sec_s = t_gp;
+		break;
+	default:
+		sec_s = unk;
+	}
+
+	printf("OMAP%s-%s rev %d, CPU-OPP%s L3-%sMHz\n", sysinfo.cpu_string,
+	       sec_s, rev, p_cpu, p_l3);
+	printf("%s + %s/%s\n", sysinfo.board_string,
+	       mem_s, bootmode[get_gpmc0_type()]);
+
+}
+
+/********************************************************
+ *  get_base(); get upper addr of current execution
+ *******************************************************/
+u32 get_base(void)
+{
+	u32 val;
+
+	__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
+	val &= 0xF0000000;
+	val >>= 28;
+	return val;
+}
+
+/********************************************************
+ *  running_in_flash() - tell if currently running in
+ *   flash.
+ *******************************************************/
+u32 running_in_flash(void)
+{
+	if (get_base() < 4)
+		return 1;	/* in flash */
+
+	return 0;		/* running in SRAM or SDRAM */
+}
+
+/********************************************************
+ *  running_in_sram() - tell if currently running in
+ *   sram.
+ *******************************************************/
+u32 running_in_sram(void)
+{
+	if (get_base() == 4)
+		return 1;	/* in SRAM */
+
+	return 0;		/* running in FLASH or SDRAM */
+}
+
+/********************************************************
+ *  running_in_sdram() - tell if currently running in
+ *   flash.
+ *******************************************************/
+u32 running_in_sdram(void)
+{
+	if (get_base() > 4)
+		return 1;	/* in sdram */
+
+	return 0;		/* running in SRAM or FLASH */
+}
+
+/***************************************************************
+ *  get_boot_type() - Is this an XIP type device or a stream one
+ *   bits 4-0 specify type.  Bit 5 sys mem/perif
+ ***************************************************************/
+u32 get_boot_type(void)
+{
+	u32 v;
+
+	v = get_sysboot_value() & (BIT4 | BIT3 | BIT2 | BIT1 | BIT0);
+	return v;
+}
+
+/*************************************************************
+ *  get_device_type(): tell if GP/HS/EMU/TST
+ *************************************************************/
+u32 get_device_type(void)
+{
+	int mode;
+
+	mode = readl(CONTROL_STATUS) & (DEVICE_MASK);
+	return mode >>= 8;
+}

[U-Boot] [PATCH 06/13 v4] ARM: OMAP3: Add board, clock and interrupts common files

[dirk.behme at googlemail.com]

Subject: [PATCH 06/13 v4] ARM: OMAP3: Add board, clock and interrupts common files

From: Dirk Behme <dirk.behme@gmail.com>

Add board, clock, cpu and interrupts common files

Signed-off-by: Dirk Behme <dirk.behme@gmail.com>

---

Changes in version v3:

- Add detection and support for 128MB/256MB RAM by Mans Rullgard

Changes in version v2:

- Move common ARM Cortex A8 code to cpu/arm_cortexa8/ and OMAP3 SoC specific common code to cpu/arm_cortexa8/omap3 as proposed by Wolfgang.

 cpu/arm_cortexa8/omap3/Makefile     |    2 
 cpu/arm_cortexa8/omap3/board.c      |  326 ++++++++++++++++++++++++++++++++++++
 cpu/arm_cortexa8/omap3/clock.c      |  305 +++++++++++++++++++++++++++++++++
 cpu/arm_cortexa8/omap3/interrupts.c |  304 +++++++++++++++++++++++++++++++++
 4 files changed, 936 insertions(+), 1 deletion(-)

Index: u-boot-arm/cpu/arm_cortexa8/omap3/Makefile
===================================================================
--- u-boot-arm.orig/cpu/arm_cortexa8/omap3/Makefile
+++ u-boot-arm/cpu/arm_cortexa8/omap3/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(SOC).a
 
 SOBJS	:= lowlevel_init.o
-OBJS	:= sys_info.o
+OBJS	:= sys_info.o board.o clock.o interrupts.o
 
 all:	.depend $(LIB)
 
Index: u-boot-arm/cpu/arm_cortexa8/omap3/board.c
===================================================================
--- /dev/null
+++ u-boot-arm/cpu/arm_cortexa8/omap3/board.c
@@ -0,0 +1,326 @@
+/*
+ *
+ * Common board functions for OMAP3 based boards.
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *      Sunil Kumar <sunilsaini05@gmail.com>
+ *      Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *      Richard Woodruff <r-woodruff2@ti.com>
+ *      Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+
+#define NOT_EARLY 0
+
+/* Permission values for registers -Full fledged permissions to all */
+#define UNLOCK_1 0xFFFFFFFF
+#define UNLOCK_2 0x00000000
+#define UNLOCK_3 0x0000FFFF
+
+/******************************************************************************
+ * Routine: delay
+ * Description: spinning delay to use before udelay works
+ *****************************************************************************/
+static inline void delay(unsigned long loops)
+{
+	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+			  "bne 1b":"=r" (loops):"0"(loops));
+}
+
+/******************************************************************************
+ * Routine: secure_unlock
+ * Description: Setup security registers for access
+ *              (GP Device only)
+ *****************************************************************************/
+void secure_unlock_mem(void)
+{
+	/* Protection Module Register Target APE (PM_RT) */
+	writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
+	writel(UNLOCK_1, RT_READ_PERMISSION_0);
+	writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
+	writel(UNLOCK_2, RT_ADDR_MATCH_1);
+
+	writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
+	writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
+	writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
+
+	writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
+	writel(UNLOCK_3, OCM_READ_PERMISSION_0);
+	writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
+	writel(UNLOCK_2, OCM_ADDR_MATCH_2);
+
+	/* IVA Changes */
+	writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
+	writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
+	writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
+
+	writel(UNLOCK_1, SMS_RG_ATT0);	/* SDRC region 0 public */
+}
+
+/******************************************************************************
+ * Routine: secureworld_exit()
+ * Description: If chip is EMU and boot type is external
+ *		configure secure registers and exit secure world
+ *              general use.
+ *****************************************************************************/
+void secureworld_exit()
+{
+	unsigned long i;
+
+	/* configrue non-secure access control register */
+	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
+	/* enabling co-processor CP10 and CP11 accesses in NS world */
+	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
+	/* allow allocation of locked TLBs and L2 lines in NS world */
+	/* allow use of PLE registers in NS world also */
+	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
+	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
+
+	/* Enable ASA in ACR register */
+	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
+	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
+	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
+
+	/* Exiting secure world */
+	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
+	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
+	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
+}
+
+/******************************************************************************
+ * Routine: setup_auxcr()
+ * Description: Write to AuxCR desired value using SMI.
+ *              general use.
+ *****************************************************************************/
+void setup_auxcr()
+{
+	unsigned long i;
+	volatile unsigned int j;
+	/* Save r0, r12 and restore them after usage */
+	__asm__ __volatile__("mov %0, r12":"=r"(j));
+	__asm__ __volatile__("mov %0, r0":"=r"(i));
+
+	/* GP Device ROM code API usage here */
+	/* r12 = AUXCR Write function and r0 value */
+	__asm__ __volatile__("mov r12, #0x3");
+	__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
+	/* Enabling ASA */
+	__asm__ __volatile__("orr r0, r0, #0x10");
+	/* SMI instruction to call ROM Code API */
+	__asm__ __volatile__(".word 0xE1600070");
+	__asm__ __volatile__("mov r0, %0":"=r"(i));
+	__asm__ __volatile__("mov r12, %0":"=r"(j));
+}
+
+/******************************************************************************
+ * Routine: try_unlock_sram()
+ * Description: If chip is GP/EMU(special) type, unlock the SRAM for
+ *              general use.
+ *****************************************************************************/
+void try_unlock_memory()
+{
+	int mode;
+	int in_sdram = running_in_sdram();
+
+	/* if GP device unlock device SRAM for general use */
+	/* secure code breaks for Secure/Emulation device - HS/E/T */
+	mode = get_device_type();
+	if (mode == GP_DEVICE)
+		secure_unlock_mem();
+
+	/* If device is EMU and boot is XIP external booting
+	 * Unlock firewalls and disable L2 and put chip
+	 * out of secure world
+	 */
+	/* Assuming memories are unlocked by the demon who put us in SDRAM */
+	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
+	    && (!in_sdram)) {
+		secure_unlock_mem();
+		secureworld_exit();
+	}
+
+	return;
+}
+
+/******************************************************************************
+ * Routine: s_init
+ * Description: Does early system init of muxing and clocks.
+ *              - Called path is with SRAM stack.
+ *****************************************************************************/
+void s_init(void)
+{
+	int in_sdram = running_in_sdram();
+
+	watchdog_init();
+
+	try_unlock_memory();
+
+	/* Right now flushing@low MPU speed.
+	   Need to move after clock init */
+	v7_flush_dcache_all(get_device_type());
+#ifndef CONFIG_ICACHE_OFF
+	icache_enable();
+#endif
+
+#ifdef CONFIG_L2_OFF
+	l2cache_disable();
+#else
+	l2cache_enable();
+#endif
+	/* Writing to AuxCR in U-boot using SMI for GP DEV */
+	/* Currently SMI in Kernel on ES2 devices seems to have an isse
+	 * Once that is resolved, we can postpone this config to kernel
+	 */
+	if (get_device_type() == GP_DEVICE)
+		setup_auxcr();
+
+	set_muxconf_regs();
+	delay(100);
+
+	prcm_init();
+
+	per_clocks_enable();
+
+	if (!in_sdram)
+		sdrc_init();
+}
+
+/******************************************************************************
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ *****************************************************************************/
+void wait_for_command_complete(unsigned int wd_base)
+{
+	int pending = 1;
+	do {
+		pending = readl(wd_base + WWPS);
+	} while (pending);
+}
+
+/******************************************************************************
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ *****************************************************************************/
+void watchdog_init(void)
+{
+	/* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
+	 * either taken care of by ROM (HS/EMU) or not accessible (GP).
+	 * We need to take care of WD2-MPU or take a PRCM reset. WD3
+	 * should not be running and does not generate a PRCM reset.
+	 */
+
+	sr32(CM_FCLKEN_WKUP, 5, 1, 1);
+	sr32(CM_ICLKEN_WKUP, 5, 1, 1);
+	wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5);	/* some issue here */
+
+	writel(WD_UNLOCK1, WD2_BASE + WSPR);
+	wait_for_command_complete(WD2_BASE);
+	writel(WD_UNLOCK2, WD2_BASE + WSPR);
+}
+
+/******************************************************************************
+ * Routine: dram_init
+ * Description: sets uboots idea of sdram size
+ *****************************************************************************/
+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned int size0 = 0, size1 = 0;
+	u32 mtype, btype;
+
+	btype = get_board_type();
+	mtype = get_mem_type();
+
+	display_board_info(btype);
+
+	/* If a second bank of DDR is attached to CS1 this is
+	 * where it can be started.  Early init code will init
+	 * memory on CS0.
+	 */
+	if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
+		do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
+		make_cs1_contiguous();
+	}
+
+	size0 = get_sdr_cs_size(SDRC_CS0_OSET);
+	size1 = get_sdr_cs_size(SDRC_CS1_OSET);
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = size0;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(1);
+	gd->bd->bi_dram[1].size = size1;
+
+	return 0;
+}
+
+/******************************************************************************
+ * Dummy function to handle errors for EABI incompatibility
+ *****************************************************************************/
+void raise(void)
+{
+}
+
+/******************************************************************************
+ * Dummy function to handle errors for EABI incompatibility
+ *****************************************************************************/
+void abort(void)
+{
+}
+
+#ifdef CONFIG_NAND_OMAP_GPMC
+/******************************************************************************
+ * OMAP3 specific command to switch between NAND HW and SW ecc
+ *****************************************************************************/
+static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	if (argc != 2)
+		goto usage;
+	if (strncmp(argv[1], "hw", 2) == 0)
+		omap_nand_switch_ecc(1);
+	else if (strncmp(argv[1], "sw", 2) == 0)
+		omap_nand_switch_ecc(0);
+	else
+		goto usage;
+
+	return 0;
+
+usage:
+	printf ("Usage: nandecc %s\n", cmdtp->help);
+	return 1;
+}
+
+U_BOOT_CMD(
+	nandecc, 2, 1,	do_switch_ecc,
+	"nandecc - switch OMAP3 NAND ECC calculation algorithm\n",
+	"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm\n"
+	);
+
+#endif /* CONFIG_NAND_OMAP_GPMC */
Index: u-boot-arm/cpu/arm_cortexa8/omap3/clock.c
===================================================================
--- /dev/null
+++ u-boot-arm/cpu/arm_cortexa8/omap3/clock.c
@@ -0,0 +1,305 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *      Manikandan Pillai <mani.pillai@ti.com>
+ *
+ * Derived from Beagle Board and OMAP3 SDP code by
+ *      Richard Woodruff <r-woodruff2@ti.com>
+ *      Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/clocks_omap3.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <environment.h>
+#include <command.h>
+
+/******************************************************************************
+ * get_sys_clk_speed() - determine reference oscillator speed
+ *                       based on known 32kHz clock and gptimer.
+ *****************************************************************************/
+u32 get_osc_clk_speed(void)
+{
+	u32 start, cstart, cend, cdiff, val;
+
+	val = readl(PRM_CLKSRC_CTRL);
+
+	/* If SYS_CLK is being divided by 2, remove for now */
+	val = (val & (~BIT7)) | BIT6;
+	writel(val, PRM_CLKSRC_CTRL);
+
+	/* enable timer2 */
+	val = readl(CM_CLKSEL_WKUP) | BIT0;
+	writel(val, CM_CLKSEL_WKUP);	/* select sys_clk for GPT1 */
+
+	/* Enable I and F Clocks for GPT1 */
+	val = readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
+	writel(val, CM_ICLKEN_WKUP);
+	val = readl(CM_FCLKEN_WKUP) | BIT0;
+	writel(val, CM_FCLKEN_WKUP);
+
+	writel(0, OMAP34XX_GPT1 + TLDR);	/* start counting at 0 */
+	writel(GPT_EN, OMAP34XX_GPT1 + TCLR);	/* enable clock */
+
+	/* enable 32kHz source, determine sys_clk via gauging */
+	start = 20 + readl(S32K_CR);	/* start time in 20 cycles */
+	while (readl(S32K_CR) < start) ;	/* dead loop till start time */
+	/* get start sys_clk count */
+	cstart = readl(OMAP34XX_GPT1 + TCRR);
+	/* wait for 40 cycles */
+	while (readl(S32K_CR) < (start + 20)) ;
+	cend = readl(OMAP34XX_GPT1 + TCRR);  /* get end sys_clk count */
+	cdiff = cend - cstart;	/* get elapsed ticks */
+
+	/* based on number of ticks assign speed */
+	if (cdiff > 19000)
+		return S38_4M;
+	else if (cdiff > 15200)
+		return S26M;
+	else if (cdiff > 13000)
+		return S24M;
+	else if (cdiff > 9000)
+		return S19_2M;
+	else if (cdiff > 7600)
+		return S13M;
+	else
+		return S12M;
+}
+
+/******************************************************************************
+ * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
+ *                       input oscillator clock frequency.
+ *****************************************************************************/
+void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
+{
+	if (osc_clk == S38_4M)
+		*sys_clkin_sel = 4;
+	else if (osc_clk == S26M)
+		*sys_clkin_sel = 3;
+	else if (osc_clk == S19_2M)
+		*sys_clkin_sel = 2;
+	else if (osc_clk == S13M)
+		*sys_clkin_sel = 1;
+	else if (osc_clk == S12M)
+		*sys_clkin_sel = 0;
+}
+
+/******************************************************************************
+ * prcm_init() - inits clocks for PRCM as defined in clocks.h
+ *               called from SRAM, or Flash (using temp SRAM stack).
+ *****************************************************************************/
+void prcm_init(void)
+{
+	void (*f_lock_pll) (u32, u32, u32, u32);
+	int xip_safe, p0, p1, p2, p3;
+	u32 osc_clk = 0, sys_clkin_sel;
+	u32 clk_index, sil_index;
+	dpll_param *dpll_param_p;
+
+	f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
+			       SRAM_VECT_CODE);
+
+	xip_safe = running_in_sram();
+
+	/* Gauge the input clock speed and find out the sys_clkin_sel
+	 * value corresponding to the input clock.
+	 */
+	osc_clk = get_osc_clk_speed();
+	get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
+
+	sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel);	/* set input crystal speed */
+
+	/* If the input clock is greater than 19.2M always divide/2 */
+	if (sys_clkin_sel > 2) {
+		sr32(PRM_CLKSRC_CTRL, 6, 2, 2);	/* input clock divider */
+		clk_index = sys_clkin_sel / 2;
+	} else {
+		sr32(PRM_CLKSRC_CTRL, 6, 2, 1);	/* input clock divider */
+		clk_index = sys_clkin_sel;
+	}
+
+	/* The DPLL tables are defined according to sysclk value and
+	 * silicon revision. The clk_index value will be used to get
+	 * the values for that input sysclk from the DPLL param table
+	 * and sil_index will get the values for that SysClk for the
+	 * appropriate silicon rev.
+	 */
+	sil_index = get_cpu_rev() - 1;
+	/* Unlock MPU DPLL (slows things down, and needed later) */
+	sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
+	wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
+
+	/* Getting the base address of Core DPLL param table */
+	dpll_param_p = (dpll_param *) get_core_dpll_param();
+	/* Moving it to the right sysclk and ES rev base */
+	dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
+	if (xip_safe) {
+		/* CORE DPLL */
+		/* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
+		sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
+		wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
+		/* For OMAP3 ES1.0 Errata 1.50, default value directly doesnt
+		   work. write another value and then default value. */
+		sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1);	/* m3x2 */
+		sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2);	        /* m3x2 */
+		sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2);	/* Set M2 */
+		sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m);	/* Set M */
+		sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n);	/* Set N */
+		sr32(CM_CLKSEL1_PLL, 6, 1, 0);	                /* 96M Src */
+		sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV);	/* ssi */
+		sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV);	/* fsusb */
+		sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV);	/* l4 */
+		sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV);	/* l3 */
+		sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV);	        /* gfx */
+		sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM);	        /* reset mgr */
+		sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel);	/* FREQSEL */
+		sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK);	        /* lock mode */
+		wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
+	} else if (running_in_flash()) {
+		/* if running from flash, jump to small relocated code
+		   area in SRAM. */
+		p0 = readl(CM_CLKEN_PLL);
+		sr32((u32) &p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
+		sr32((u32) &p0, 4, 4, dpll_param_p->fsel);	/* FREQSEL */
+
+		p1 = readl(CM_CLKSEL1_PLL);
+		sr32((u32) &p1, 27, 2, dpll_param_p->m2);	/* Set M2 */
+		sr32((u32) &p1, 16, 11, dpll_param_p->m);	/* Set M */
+		sr32((u32) &p1, 8, 7, dpll_param_p->n);	        /* Set N */
+		sr32((u32) &p1, 6, 1, 0);	    /* set source for 96M */
+		p2 = readl(CM_CLKSEL_CORE);
+		sr32((u32) &p2, 8, 4, CORE_SSI_DIV);	/* ssi */
+		sr32((u32) &p2, 4, 2, CORE_FUSB_DIV);	/* fsusb */
+		sr32((u32) &p2, 2, 2, CORE_L4_DIV);	/* l4 */
+		sr32((u32) &p2, 0, 2, CORE_L3_DIV);	/* l3 */
+
+		p3 = CM_IDLEST_CKGEN;
+
+		(*f_lock_pll) (p0, p1, p2, p3);
+	}
+
+	/* PER DPLL */
+	sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
+	wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
+
+	/* Getting the base address to PER  DPLL param table */
+	/* Set N */
+	dpll_param_p = (dpll_param *) get_per_dpll_param();
+	/* Moving it to the right sysclk base */
+	dpll_param_p = dpll_param_p + clk_index;
+	/* Errata 1.50 Workaround for OMAP3 ES1.0 only */
+	/* If using default divisors, write default divisor + 1
+	   and then the actual divisor value */
+	sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2 + 1);	  /* set M6 */
+	sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2);	          /* set M6 */
+	sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2 + 1);	  /* set M5 */
+	sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2);	          /* set M5 */
+	sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2 + 1);	  /* set M4 */
+	sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2);	          /* set M4 */
+	sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2 + 1);	  /* set M3 */
+	sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2);	          /* set M3 */
+	sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2 + 1); /* set M2 */
+	sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2);	  /* set M2 */
+	/* Workaround end */
+	sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m);	/* set m */
+	sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n);	/* set n */
+	sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);	/* FREQSEL */
+	sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK);	/* lock mode */
+	wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
+
+	/* Getting the base address to MPU DPLL param table */
+	dpll_param_p = (dpll_param *) get_mpu_dpll_param();
+	/* Moving it to the right sysclk and ES rev base */
+	dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
+	/* MPU DPLL (unlocked already) */
+	sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2);	/* Set M2 */
+	sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m);	/* Set M */
+	sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n);	/* Set N */
+	sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel);	/* FREQSEL */
+	sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK);	/* lock mode */
+	wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
+
+	/* Getting the base address to IVA DPLL param table */
+	dpll_param_p = (dpll_param *) get_iva_dpll_param();
+	/* Moving it to the right sysclk and ES rev base */
+	dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
+	/* IVA DPLL (set to 12*20=240MHz) */
+	sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
+	wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
+	sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2);	/* set M2 */
+	sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m);	/* set M */
+	sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n);	/* set N */
+	sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel);	/* FREQSEL */
+	sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK);	/* lock mode */
+	wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
+
+	/* Set up GPTimers to sys_clk source only */
+	sr32(CM_CLKSEL_PER, 0, 8, 0xff);
+	sr32(CM_CLKSEL_WKUP, 0, 1, 1);
+
+	sdelay(5000);
+}
+
+/******************************************************************************
+ * peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
+ *****************************************************************************/
+void per_clocks_enable(void)
+{
+	/* Enable GP2 timer. */
+	sr32(CM_CLKSEL_PER, 0, 1, 0x1);	/* GPT2 = sys clk */
+	sr32(CM_ICLKEN_PER, 3, 1, 0x1);	/* ICKen GPT2 */
+	sr32(CM_FCLKEN_PER, 3, 1, 0x1);	/* FCKen GPT2 */
+
+#ifdef CONFIG_SYS_NS16550
+	/* Enable UART1 clocks */
+	sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
+	sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
+
+	/* UART 3 Clocks */
+	sr32(CM_FCLKEN_PER, 11, 1, 0x1);
+	sr32(CM_ICLKEN_PER, 11, 1, 0x1);
+#endif
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+	/* Turn on all 3 I2C clocks */
+	sr32(CM_FCLKEN1_CORE, 15, 3, 0x7);
+	sr32(CM_ICLKEN1_CORE, 15, 3, 0x7);	/* I2C1,2,3 = on */
+#endif
+	/* Enable the ICLK for 32K Sync Timer as its used in udelay */
+	sr32(CM_ICLKEN_WKUP, 2, 1, 0x1);
+
+	sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON);
+	sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON);
+	sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON);
+	sr32(CM_ICLKEN2_CORE, 0, 32, ICK_CORE2_ON);
+	sr32(CM_FCLKEN_WKUP, 0, 32, FCK_WKUP_ON);
+	sr32(CM_ICLKEN_WKUP, 0, 32, ICK_WKUP_ON);
+	sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON);
+	sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON);
+	sr32(CM_FCLKEN_CAM, 0, 32, FCK_CAM_ON);
+	sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON);
+	sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON);
+	sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON);
+
+	sdelay(1000);
+}
Index: u-boot-arm/cpu/arm_cortexa8/omap3/interrupts.c
===================================================================
--- /dev/null
+++ u-boot-arm/cpu/arm_cortexa8/omap3/interrupts.c
@@ -0,0 +1,304 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments
+ *
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Moahmmed Khasim <khasim@ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/bits.h>
+
+#include <asm/proc-armv/ptrace.h>
+
+#define TIMER_LOAD_VAL 0
+
+/* macro to read the 32 bit timer */
+#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+TCRR))
+
+#ifdef CONFIG_USE_IRQ
+/* enable IRQ interrupts */
+void enable_interrupts(void)
+{
+	unsigned long temp;
+	__asm__ __volatile__("mrs %0, cpsr\n"
+			     "bic %0, %0, #0x80\n" "msr cpsr_c, %0":"=r"(temp)
+			     ::"memory");
+}
+
+/*
+ * disable IRQ/FIQ interrupts
+ * returns true if interrupts had been enabled before we disabled them
+ */
+int disable_interrupts(void)
+{
+	unsigned long old, temp;
+	__asm__ __volatile__("mrs %0, cpsr\n"
+			     "orr %1, %0, #0xc0\n"
+			     "msr cpsr_c, %1":"=r"(old), "=r"(temp)
+			     ::"memory");
+	return (old & 0x80) == 0;
+}
+#else
+void enable_interrupts(void)
+{
+	return;
+}
+int disable_interrupts(void)
+{
+	return 0;
+}
+#endif
+
+void bad_mode(void)
+{
+	panic("Resetting CPU ...\n");
+	reset_cpu(0);
+}
+
+void show_regs(struct pt_regs *regs)
+{
+	unsigned long flags;
+	const char *processor_modes[] = {
+		"USER_26", "FIQ_26", "IRQ_26", "SVC_26",
+		"UK4_26", "UK5_26", "UK6_26", "UK7_26",
+		"UK8_26", "UK9_26", "UK10_26", "UK11_26",
+		"UK12_26", "UK13_26", "UK14_26", "UK15_26",
+		"USER_32", "FIQ_32", "IRQ_32", "SVC_32",
+		"UK4_32", "UK5_32", "UK6_32", "ABT_32",
+		"UK8_32", "UK9_32", "UK10_32", "UND_32",
+		"UK12_32", "UK13_32", "UK14_32", "SYS_32",
+	};
+
+	flags = condition_codes(regs);
+
+	printf("pc : [<%08lx>]    lr : [<%08lx>]\n"
+	       "sp : %08lx  ip : %08lx  fp : %08lx\n",
+	       instruction_pointer(regs),
+	       regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
+	printf("r10: %08lx  r9 : %08lx  r8 : %08lx\n",
+	       regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
+	printf("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
+	       regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
+	printf("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
+	       regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
+	printf("Flags: %c%c%c%c",
+	       flags & CC_N_BIT ? 'N' : 'n',
+	       flags & CC_Z_BIT ? 'Z' : 'z',
+	       flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
+	printf("  IRQs %s  FIQs %s  Mode %s%s\n",
+	       interrupts_enabled(regs) ? "on" : "off",
+	       fast_interrupts_enabled(regs) ? "on" : "off",
+	       processor_modes[processor_mode(regs)],
+	       thumb_mode(regs) ? " (T)" : "");
+}
+
+void do_undefined_instruction(struct pt_regs *pt_regs)
+{
+	printf("undefined instruction\n");
+	show_regs(pt_regs);
+	bad_mode();
+}
+
+void do_software_interrupt(struct pt_regs *pt_regs)
+{
+	printf("software interrupt\n");
+	show_regs(pt_regs);
+	bad_mode();
+}
+
+void do_prefetch_abort(struct pt_regs *pt_regs)
+{
+	printf("prefetch abort\n");
+	show_regs(pt_regs);
+	bad_mode();
+}
+
+void do_data_abort(struct pt_regs *pt_regs)
+{
+	printf("data abort\n");
+	show_regs(pt_regs);
+	bad_mode();
+}
+
+void do_not_used(struct pt_regs *pt_regs)
+{
+	printf("not used\n");
+	show_regs(pt_regs);
+	bad_mode();
+}
+
+void do_fiq(struct pt_regs *pt_regs)
+{
+	printf("fast interrupt request\n");
+	show_regs(pt_regs);
+	bad_mode();
+}
+
+void do_irq(struct pt_regs *pt_regs)
+{
+	printf("interrupt request\n");
+	show_regs(pt_regs);
+	bad_mode();
+}
+
+
+static ulong timestamp;
+static ulong lastinc;
+
+/* nothing really to do with interrupts, just starts up a counter. */
+int interrupt_init(void)
+{
+	int32_t val;
+
+	/* Start the counter ticking up */
+	/* reload value on overflow */
+	*((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL;
+	/* mask to enable timer */
+	val = (CONFIG_SYS_PVT << 2) | BIT5 | BIT1 | BIT0;
+	*((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val;	/* start timer */
+
+	reset_timer_masked();	/* init the timestamp and lastinc value */
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	timestamp = t;
+}
+
+/* delay x useconds AND perserve advance timstamp value */
+void udelay(unsigned long usec)
+{
+	ulong tmo, tmp;
+
+	/* if "big" number, spread normalization to seconds */
+	if (usec >= 1000) {
+		/* if "big" number, spread normalization to seconds */
+		tmo = usec / 1000;
+		/* find number of "ticks" to wait to achieve target */
+		tmo *= CONFIG_SYS_HZ;
+		tmo /= 1000;	/* finish normalize. */
+	} else {/* else small number, don't kill it prior to HZ multiply */
+		tmo = usec * CONFIG_SYS_HZ;
+		tmo /= (1000 * 1000);
+	}
+
+	tmp = get_timer(0);	/* get current timestamp */
+	/* if setting this forward will roll time stamp */
+	if ((tmo + tmp + 1) < tmp)
+		/* reset "advancing" timestamp to 0, set lastinc value */
+		reset_timer_masked();
+	else
+		tmo += tmp;	/* else, set advancing stamp wake up time */
+	while (get_timer_masked() < tmo)	/* loop till event */
+		 /*NOP*/;
+}
+
+void reset_timer_masked(void)
+{
+	/* reset time */
+	lastinc = READ_TIMER;	/* capture current incrementer value time */
+	timestamp = 0;		/* start "advancing" time stamp from 0 */
+}
+
+ulong get_timer_masked(void)
+{
+	ulong now = READ_TIMER;	/* current tick value */
+
+	if (now >= lastinc)	/* normal mode (non roll) */
+		/* move stamp fordward with absoulte diff ticks */
+		timestamp += (now - lastinc);
+	else	/* we have rollover of incrementer */
+		timestamp += (0xFFFFFFFF - lastinc) + now;
+	lastinc = now;
+	return timestamp;
+}
+
+/* waits specified delay value and resets timestamp */
+void udelay_masked(unsigned long usec)
+{
+	ulong tmo;
+	ulong endtime;
+	signed long diff;
+
+	/* if "big" number, spread normalization to seconds */
+	if (usec >= 1000) {
+		/* start to normalize for usec to ticks per sec */
+		tmo = usec / 1000;
+		/* find number of "ticks" to wait to achieve target */
+		tmo *= CONFIG_SYS_HZ;
+		tmo /= 1000;	/* finish normalize. */
+	} else {		/* else small number, */
+				/* don't kill it prior to HZ multiply */
+		tmo = usec * CONFIG_SYS_HZ;
+		tmo /= (1000 * 1000);
+	}
+	endtime = get_timer_masked() + tmo;
+
+	do {
+		ulong now = get_timer_masked();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	ulong tbclk;
+	tbclk = CONFIG_SYS_HZ;
+	return tbclk;
+}
+

[U-Boot] [PATCH 06/13 v4] ARM: OMAP3: Add board, clock and interrupts common files

[Jean-Christophe PLAGNIOL-VILLARD]

On 21:27 Fri 17 Oct     , dirk.behme at googlemail.com wrote:
> Subject: [PATCH 06/13 v4] ARM: OMAP3: Add board, clock and interrupts common files
> 
> From: Dirk Behme <dirk.behme@gmail.com>
> 
> Add board, clock, cpu and interrupts common files
> 
> Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
> 
> ---
> 
> Changes in version v3:
> 
> - Add detection and support for 128MB/256MB RAM by Mans Rullgard
> 
> Changes in version v2:
> 
> - Move common ARM Cortex A8 code to cpu/arm_cortexa8/ and OMAP3 SoC specific common code to cpu/arm_cortexa8/omap3 as proposed by Wolfgang.
> 
>  cpu/arm_cortexa8/omap3/Makefile     |    2 
>  cpu/arm_cortexa8/omap3/board.c      |  326 ++++++++++++++++++++++++++++++++++++
>  cpu/arm_cortexa8/omap3/clock.c      |  305 +++++++++++++++++++++++++++++++++
>  cpu/arm_cortexa8/omap3/interrupts.c |  304 +++++++++++++++++++++++++++++++++
>  4 files changed, 936 insertions(+), 1 deletion(-)
> 
> Index: u-boot-arm/cpu/arm_cortexa8/omap3/Makefile
> ===================================================================
> --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/Makefile
> +++ u-boot-arm/cpu/arm_cortexa8/omap3/Makefile
> @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
>  LIB	= lib$(SOC).a
>  
>  SOBJS	:= lowlevel_init.o
> -OBJS	:= sys_info.o
> +OBJS	:= sys_info.o board.o clock.o interrupts.o
>  
>  all:	.depend $(LIB)
please use the current way
to allow builddir
>  
> Index: u-boot-arm/cpu/arm_cortexa8/omap3/board.c
> ===================================================================
> --- /dev/null
> +++ u-boot-arm/cpu/arm_cortexa8/omap3/board.c
> @@ -0,0 +1,326 @@
> +/*
> + *
> + * Common board functions for OMAP3 based boards.
> + *
> + * (C) Copyright 2004-2008
> + * Texas Instruments, <www.ti.com>
> +
> +/******************************************************************************
> + * Dummy function to handle errors for EABI incompatibility
> + *****************************************************************************/
> +void abort(void)
> +{
> +}
> +
> +#ifdef CONFIG_NAND_OMAP_GPMC
> +/******************************************************************************
> + * OMAP3 specific command to switch between NAND HW and SW ecc
> + *****************************************************************************/
> +static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
> +{
> +	if (argc != 2)
> +		goto usage;
> +	if (strncmp(argv[1], "hw", 2) == 0)
> +		omap_nand_switch_ecc(1);
> +	else if (strncmp(argv[1], "sw", 2) == 0)
> +		omap_nand_switch_ecc(0);
> +	else
> +		goto usage;
> +
> +	return 0;
> +
> +usage:
> +	printf ("Usage: nandecc %s\n", cmdtp->help);
> +	return 1;
> +}
> +
> +U_BOOT_CMD(
> +	nandecc, 2, 1,	do_switch_ecc,
> +	"nandecc - switch OMAP3 NAND ECC calculation algorithm\n",
> +	"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm\n"
> +	);
> +
please add a README about it
> +#endif /* CONFIG_NAND_OMAP_GPMC */
> Index: u-boot-arm/cpu/arm_cortexa8/omap3/clock.c
> ===================================================================
> --- /dev/null
> +++ u-boot-arm/cpu/arm_cortexa8/omap3/clock.c
> @@ -0,0 +1,305 @@
> +/*
> + * (C) Copyright 2008
> + * Texas Instruments, <www.ti.com>
> + *
> + * Author :
> + *      Manikandan Pillai <mani.pillai@ti.com>
> + *
> + * Derived from Beagle Board and OMAP3 SDP code by
> + *      Richard Woodruff <r-woodruff2@ti.com>
> + *      Syed Mohammed Khasim <khasim@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/bits.h>
> +#include <asm/arch/clocks.h>
> +#include <asm/arch/clocks_omap3.h>
> +#include <asm/arch/mem.h>
> +#include <asm/arch/sys_proto.h>
> +#include <environment.h>
> +#include <command.h>
> +
> +/******************************************************************************
> + * get_sys_clk_speed() - determine reference oscillator speed
> + *                       based on known 32kHz clock and gptimer.
> + *****************************************************************************/
> +u32 get_osc_clk_speed(void)
> +{
> +	u32 start, cstart, cend, cdiff, val;
> +
> +	val = readl(PRM_CLKSRC_CTRL);
> +
> +	/* If SYS_CLK is being divided by 2, remove for now */
> +	val = (val & (~BIT7)) | BIT6;
> +	writel(val, PRM_CLKSRC_CTRL);
> +
> +	/* enable timer2 */
> +	val = readl(CM_CLKSEL_WKUP) | BIT0;
> +	writel(val, CM_CLKSEL_WKUP);	/* select sys_clk for GPT1 */
> +
> +	/* Enable I and F Clocks for GPT1 */
> +	val = readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
> +	writel(val, CM_ICLKEN_WKUP);
> +	val = readl(CM_FCLKEN_WKUP) | BIT0;
> +	writel(val, CM_FCLKEN_WKUP);
> +
> +	writel(0, OMAP34XX_GPT1 + TLDR);	/* start counting at 0 */
> +	writel(GPT_EN, OMAP34XX_GPT1 + TCLR);	/* enable clock */
> +
> +	/* enable 32kHz source, determine sys_clk via gauging */
> +	start = 20 + readl(S32K_CR);	/* start time in 20 cycles */
> +	while (readl(S32K_CR) < start) ;	/* dead loop till start time */
> +	/* get start sys_clk count */
> +	cstart = readl(OMAP34XX_GPT1 + TCRR);
> +	/* wait for 40 cycles */
> +	while (readl(S32K_CR) < (start + 20)) ;
> +	cend = readl(OMAP34XX_GPT1 + TCRR);  /* get end sys_clk count */
> +	cdiff = cend - cstart;	/* get elapsed ticks */
> +
> +	/* based on number of ticks assign speed */
> +	if (cdiff > 19000)
> +		return S38_4M;
> +	else if (cdiff > 15200)
> +		return S26M;
> +	else if (cdiff > 13000)
> +		return S24M;
> +	else if (cdiff > 9000)
> +		return S19_2M;
> +	else if (cdiff > 7600)
> +		return S13M;
> +	else
> +		return S12M;
> +}
> +
> +/******************************************************************************
> + * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
> + *                       input oscillator clock frequency.
> + *****************************************************************************/
> +void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
> +{
> +	if (osc_clk == S38_4M)
> +		*sys_clkin_sel = 4;
> +	else if (osc_clk == S26M)
> +		*sys_clkin_sel = 3;
> +	else if (osc_clk == S19_2M)
> +		*sys_clkin_sel = 2;
> +	else if (osc_clk == S13M)
> +		*sys_clkin_sel = 1;
> +	else if (osc_clk == S12M)
> +		*sys_clkin_sel = 0;
please use switch instead
> +}
> +
> +/******************************************************************************
> + * prcm_init() - inits clocks for PRCM as defined in clocks.h
> + *               called from SRAM, or Flash (using temp SRAM stack).
> + *****************************************************************************/
> +void prcm_init(void)
> +{
> +	void (*f_lock_pll) (u32, u32, u32, u32);
> +	int xip_safe, p0, p1, p2, p3;
> +	u32 osc_clk = 0, sys_clkin_sel;
> +	u32 clk_index, sil_index;
> +	dpll_param *dpll_param_p;
> +
> +	f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
> +			       SRAM_VECT_CODE);
> +
> +	xip_safe = running_in_sram();
> +
> +	/* Gauge the input clock speed and find out the sys_clkin_sel
> +	 * value corresponding to the input clock.
> +	 */
> +	osc_clk = get_osc_clk_speed();
> +	get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
> +
> +	sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel);	/* set input crystal speed */
> +
> +	/* If the input clock is greater than 19.2M always divide/2 */
> +	if (sys_clkin_sel > 2) {
> +		sr32(PRM_CLKSRC_CTRL, 6, 2, 2);	/* input clock divider */
> +		clk_index = sys_clkin_sel / 2;
> +	} else {
> +		sr32(PRM_CLKSRC_CTRL, 6, 2, 1);	/* input clock divider */
> +		clk_index = sys_clkin_sel;
> +	}
> +
> +	/* The DPLL tables are defined according to sysclk value and
> +	 * silicon revision. The clk_index value will be used to get
> +	 * the values for that input sysclk from the DPLL param table
> +	 * and sil_index will get the values for that SysClk for the
> +	 * appropriate silicon rev.
> +	 */
> +	sil_index = get_cpu_rev() - 1;
this part is unreadable maybe you can add some blank line
> +	/* Unlock MPU DPLL (slows things down, and needed later) */
> +	sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
> +	wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
> +
> +	/* Getting the base address of Core DPLL param table */
> +	dpll_param_p = (dpll_param *) get_core_dpll_param();
> +	/* Moving it to the right sysclk and ES rev base */
> +	dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
> +	if (xip_safe) {
> +		/* CORE DPLL */
> +		/* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
> +		sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
> +		wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
> +		/* For OMAP3 ES1.0 Errata 1.50, default value directly doesnt
> +		   work. write another value and then default value. */
please use this style of comment
/*
 *
 */
please also fix the whitespace
> +		sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1);	/* m3x2 */
> +		sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2);	        /* m3x2 */
> +		sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2);	/* Set M2 */
> +		sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m);	/* Set M */
> +		sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n);	/* Set N */
> +		sr32(CM_CLKSEL1_PLL, 6, 1, 0);	                /* 96M Src */
> +		sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV);	/* ssi */
> +		sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV);	/* fsusb */
> +		sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV);	/* l4 */


> Index: u-boot-arm/cpu/arm_cortexa8/omap3/interrupts.c
> ===================================================================
> --- /dev/null
> +++ u-boot-arm/cpu/arm_cortexa8/omap3/interrupts.c
> @@ -0,0 +1,304 @@
> +/*
> + * (C) Copyright 2008
> + * Texas Instruments
> + *
> + * Richard Woodruff <r-woodruff2@ti.com>
> + * Syed Moahmmed Khasim <khasim@ti.com>
> + *
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Marius Groeger <mgroeger@sysgo.de>
> + * Alex Zuepke <azu@sysgo.de>
> + *
> + * (C) Copyright 2002
> + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/arch/bits.h>
> +
> +#include <asm/proc-armv/ptrace.h>
> +
> +#define TIMER_LOAD_VAL 0
> +
> +/* macro to read the 32 bit timer */
> +#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+TCRR))
> +
> +#ifdef CONFIG_USE_IRQ
> +/* enable IRQ interrupts */
> +void enable_interrupts(void)
> +{
> +	unsigned long temp;
> +	__asm__ __volatile__("mrs %0, cpsr\n"
> +			     "bic %0, %0, #0x80\n" "msr cpsr_c, %0":"=r"(temp)
> +			     ::"memory");
> +}
> +
> +/*
> + * disable IRQ/FIQ interrupts
> + * returns true if interrupts had been enabled before we disabled them
> + */
> +int disable_interrupts(void)
> +{
> +	unsigned long old, temp;
> +	__asm__ __volatile__("mrs %0, cpsr\n"
> +			     "orr %1, %0, #0xc0\n"
> +			     "msr cpsr_c, %1":"=r"(old), "=r"(temp)
> +			     ::"memory");
> +	return (old & 0x80) == 0;
> +}
> +#else
> +void enable_interrupts(void)
> +{
> +	return;
> +}
> +int disable_interrupts(void)
> +{
> +	return 0;
> +}
> +#endif
> +
> +void bad_mode(void)
> +{
> +	panic("Resetting CPU ...\n");
> +	reset_cpu(0);
> +}
> +
> +void show_regs(struct pt_regs *regs)
> +{
> +	unsigned long flags;
> +	const char *processor_modes[] = {
> +		"USER_26", "FIQ_26", "IRQ_26", "SVC_26",
> +		"UK4_26", "UK5_26", "UK6_26", "UK7_26",
> +		"UK8_26", "UK9_26", "UK10_26", "UK11_26",
> +		"UK12_26", "UK13_26", "UK14_26", "UK15_26",
> +		"USER_32", "FIQ_32", "IRQ_32", "SVC_32",
> +		"UK4_32", "UK5_32", "UK6_32", "ABT_32",
> +		"UK8_32", "UK9_32", "UK10_32", "UND_32",
> +		"UK12_32", "UK13_32", "UK14_32", "SYS_32",
> +	};
> +
> +	flags = condition_codes(regs);
> +
please fix the whitespace
> +	printf("pc : [<%08lx>]    lr : [<%08lx>]\n"
> +	       "sp : %08lx  ip : %08lx  fp : %08lx\n",
> +	       instruction_pointer(regs),
> +	       regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
> +	printf("r10: %08lx  r9 : %08lx  r8 : %08lx\n",
> +	       regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
> +	printf("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
> +	       regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
> +	printf("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
> +	       regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
> +	printf("Flags: %c%c%c%c",
> +	       flags & CC_N_BIT ? 'N' : 'n',
> +	       flags & CC_Z_BIT ? 'Z' : 'z',
> +	       flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
> +	printf("  IRQs %s  FIQs %s  Mode %s%s\n",
> +	       interrupts_enabled(regs) ? "on" : "off",
> +	       fast_interrupts_enabled(regs) ? "on" : "off",
> +	       processor_modes[processor_mode(regs)],
> +	       thumb_mode(regs) ? " (T)" : "");
> +}
> +
> +void do_undefined_instruction(struct pt_regs *pt_regs)
> +{
> +	printf("undefined instruction\n");
> +	show_regs(pt_regs);
> +	bad_mode();
> +}
> +
> +void do_software_interrupt(struct pt_regs *pt_regs)
> +{
> +	printf("software interrupt\n");
> +	show_regs(pt_regs);
> +	bad_mode();
> +}
> +
> +void do_prefetch_abort(struct pt_regs *pt_regs)
> +{
> +	printf("prefetch abort\n");
> +	show_regs(pt_regs);
> +	bad_mode();
> +}
> +
> +void do_data_abort(struct pt_regs *pt_regs)
> +{
> +	printf("data abort\n");
> +	show_regs(pt_regs);
> +	bad_mode();
> +}
> +
> +void do_not_used(struct pt_regs *pt_regs)
> +{
> +	printf("not used\n");
> +	show_regs(pt_regs);
> +	bad_mode();
> +}
> +
> +void do_fiq(struct pt_regs *pt_regs)
> +{
> +	printf("fast interrupt request\n");
> +	show_regs(pt_regs);
> +	bad_mode();
> +}
> +
> +void do_irq(struct pt_regs *pt_regs)
> +{
> +	printf("interrupt request\n");
> +	show_regs(pt_regs);
> +	bad_mode();
> +}
> +
> +
> +static ulong timestamp;
> +static ulong lastinc;
> +
> +/* nothing really to do with interrupts, just starts up a counter. */
> +int interrupt_init(void)
> +{
> +	int32_t val;
> +
> +	/* Start the counter ticking up */
Best Regards,
J.

[U-Boot] [PATCH 05/13 v4] ARM: OMAP3: Add lowlevel init and sys_info common files

[Jean-Christophe PLAGNIOL-VILLARD]

On 21:27 Fri 17 Oct     , dirk.behme at googlemail.com wrote:
> Subject: [PATCH 05/13 v4] ARM: OMAP3: Add lowlevel init and sys_info common files
> 
> From: Dirk Behme <dirk.behme@gmail.com>
> 
> Add assembly lowlevel init and sys_info common files
> 
> Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
> 
> ---
> 
> Changes in version v3:
> - Add detection and support for 128MB/256MB RAM by Mans Rullgard
> 
> Changes in version v2:
> 
> - Move common ARM Cortex A8 code to cpu/arm_cortexa8/ and OMAP3 SoC specific common code to cpu/arm_cortexa8/omap3 as proposed by Wolfgang.
> 
>  cpu/arm_cortexa8/omap3/Makefile        |   43 +++
>  cpu/arm_cortexa8/omap3/config.mk       |   36 +++
>  cpu/arm_cortexa8/omap3/lowlevel_init.S |  360 +++++++++++++++++++++++++++++++++
>  cpu/arm_cortexa8/omap3/sys_info.c      |  333 ++++++++++++++++++++++++++++++
>  4 files changed, 772 insertions(+)
> 
> Index: u-boot-arm/cpu/arm_cortexa8/omap3/Makefile
> ===================================================================
> --- /dev/null
> +++ u-boot-arm/cpu/arm_cortexa8/omap3/Makefile
> @@ -0,0 +1,43 @@
> +#
> +# (C) Copyright 2000-2003
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB	= lib$(SOC).a
> +
> +SOBJS	:= lowlevel_init.o
> +OBJS	:= sys_info.o
> +
> +all:	.depend $(LIB)
> +
> +$(LIB):	$(OBJS) $(SOBJS)
> +	$(AR) crv $@ $(OBJS) $(SOBJS)
> +
> +#########################################################################
> +
> +.depend:	Makefile $(OBJS:.o=.c) $(SOBJS:.o=.S)
> +		$(CC) -M $(CFLAGS) $(OBJS:.o=.c) $(SOBJS:.o=.S) > $@
> +
> +sinclude .depend
please update Makefile to current way
as example cpu/arm1176/Makefile
> +
> +#########################################################################
> Index: u-boot-arm/cpu/arm_cortexa8/omap3/config.mk
> ===================================================================
> --- /dev/null
> +++ u-boot-arm/cpu/arm_cortexa8/omap3/config.mk
> @@ -0,0 +1,36 @@
> +#
> +# (C) Copyright 2002
> +# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
                                             ^
whitespace please remove
> +		     -msoft-float
> +
> +# Make ARMv5 to allow more compilers to work, even though its v7a.
> +PLATFORM_CPPFLAGS += -march=armv5
> +# =========================================================================
> +#
> +# Supply options according to compiler version
> +#
> +# =========================================================================
> +PLATFORM_CPPFLAGS +=$(call cc-option)
> +PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
> +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
> +		    $(call cc-option,-malignment-traps,))
> Index: u-boot-arm/cpu/arm_cortexa8/omap3/lowlevel_init.S
> ===================================================================
> --- /dev/null
> +++ u-boot-arm/cpu/arm_cortexa8/omap3/lowlevel_init.S
> @@ -0,0 +1,360 @@
> +/*
> + * Board specific setup info
> + *
> + * (C) Copyright 2008
> + * Texas Instruments, <www.ti.com>
> + *
> + * Initial Code by:
> + * Richard Woodruff <r-woodruff2@ti.com>
> + * Syed Mohammed Khasim <khasim@ti.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <config.h>
> +#include <version.h>
> +#include <asm/arch/mem.h>
> +#include <asm/arch/clocks_omap3.h>
> +
> +_TEXT_BASE:
> +	.word	TEXT_BASE	/* sdram load addr from config.mk */
> +
> +
for all files please add space after comma and please use MACRO instead of
value
> Index: u-boot-arm/cpu/arm_cortexa8/omap3/sys_info.c
> ===================================================================
> --- /dev/null
> +++ u-boot-arm/cpu/arm_cortexa8/omap3/sys_info.c
> @@ -0,0 +1,333 @@
> +/*
> + * (C) Copyright 2008
> + * Texas Instruments, <www.ti.com>
> + *
> + * Author :
> + *      Manikandan Pillai <mani.pillai@ti.com>
> + *
> + * Derived from Beagle Board and 3430 SDP code by
> + *      Richard Woodruff <r-woodruff2@ti.com>
> + *      Syed Mohammed Khasim <khasim@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/bits.h>
> +#include <asm/arch/mem.h>	/* get mem tables */
> +#include <asm/arch/sys_proto.h>
> +#include <i2c.h>
> +
> +extern omap3_sysinfo sysinfo;
> +
> +/**************************************************************************
> + * get_gpmc0_type()
> + ***************************************************************************/
> +u32 get_gpmc0_type(void)
> +{
> +#if defined(CONFIG_ENV_IS_IN_ONENAND)
> +	return 1; /* OneNAND */
> +#else
> +	return 2; /* NAND */
> +#endif
> +}
> +
> +/****************************************************
> + * get_cpu_type() - low level get cpu type
> + * - no C globals yet.
> + ****************************************************/
> +u32 get_cpu_type(void)
> +{
> +	/* fixme, need to get register defines for OMAP3 */
> +	return CPU_3430;
> +}
> +
> +/******************************************
> + * get_cpu_rev(void) - extract version info
> + ******************************************/
> +u32 get_cpu_rev(void)
> +{
> +	u32 cpuid = 0;
> +	/* On ES1.0 the IDCODE register is not exposed on L4
> +	 * so using CPU ID to differentiate
> +	 * between ES2.0 and ES1.0.
> +	 */
> +	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
> +	if ((cpuid & 0xf) == 0x0)
> +		return CPU_3430_ES1;
> +	else
> +		return CPU_3430_ES2;
> +
> +}
> +
> +/****************************************************
> + * is_mem_sdr() - return 1 if mem type in use is SDR
> + ****************************************************/
> +u32 is_mem_sdr(void)
> +{
> +	volatile u32 *burst = (volatile u32 *) (SDRC_MR_0 + SDRC_CS0_OSET);
> +	if (*burst == SDP_SDRC_MR_0_SDR)
> +		return 1;
> +	return 0;
> +}
> +
> +/***********************************************************
> + * get_mem_type() - identify type of mDDR part used.
> + ***********************************************************/
> +u32 get_mem_type(void)
> +{
> +#ifdef CONFIG_OMAP3_BEAGLE
> +	return DDR_STACKED;
> +#else
> +	return DDR_DISCRETE;
> +#endif
> +}
> +
> +/***********************************************************************
> + * get_cs0_size() - get size of chip select 0/1
> + ************************************************************************/
> +u32 get_sdr_cs_size(u32 offset)
> +{
> +	u32 size;
> +
> +	/* get ram size field */
> +	size = readl(SDRC_MCFG_0 + offset) >> 8;
> +	size &= 0x3FF;		/* remove unwanted bits */
> +	size *= SZ_2M;		/* find size in MB */
> +	return size;
> +}
> +
> +/***********************************************************************
> + * get_sdr_cs_offset() - get offset of cs from cs0 start
> + ************************************************************************/
> +u32 get_sdr_cs_offset(u32 cs)
> +{
> +	u32 offset;
> +
> +	if (!cs)
> +		return 0;
> +
> +	offset = readl(SDRC_CS_CFG);
> +	offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
> +
> +	return offset;
> +}
> +
> +/***********************************************************************
> + * get_board_type() - get board type based on current production stats.
> + *  - NOTE-1-: 2 I2C EEPROMs will someday be populated with proper info.
> + *    when they are available we can get info from there.  This should
> + *    be correct of all known boards up until today.
> + *  - NOTE-2- EEPROMs are populated but they are updated very slowly.  To
> + *    avoid waiting on them we will use ES version of the chip to get info.
> + *    A later version of the FPGA migth solve their speed issue.
> + ************************************************************************/
> +u32 get_board_type(void)
> +{
> +	if (get_cpu_rev() == CPU_3430_ES2)
> +		return sysinfo.board_type_v2;
> +	else
> +		return sysinfo.board_type_v1;
> +}
> +
> +/******************************************************************
> + * get_sysboot_value() - get init word settings
> + ******************************************************************/
> +inline u32 get_sysboot_value(void)
> +{
> +	return 0x0000003F & readl(CONTROL_STATUS);
> +}
> +
> +/***************************************************************************
> + *  get_gpmc0_base() - Return current address hardware will be
> + *     fetching from. The below effectively gives what is correct, its a bit
> + *   mis-leading compared to the TRM.  For the most general case the mask
> + *   needs to be also taken into account this does work in practice.
> + *   - for u-boot we currently map:
> + *       -- 0 to nothing,
> + *       -- 4 to flash
> + *       -- 8 to enent
> + *       -- c to wifi
> + ****************************************************************************/
> +u32 get_gpmc0_base(void)
> +{
> +	u32 b;
> +
> +	b = readl(GPMC_CONFIG_CS0 + GPMC_CONFIG7);
> +	b &= 0x1F;		/* keep base [5:0] */
> +	b = b << 24;		/* ret 0x0b000000 */
> +	return b;
> +}
> +
> +/*******************************************************************
> + * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
> + *******************************************************************/
> +u32 get_gpmc0_width(void)
> +{
> +	return WIDTH_16BIT;
> +}
> +
> +/*************************************************************************
> + * get_board_rev() - setup to pass kernel board revision information
> + * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
> + *************************************************************************/
> +u32 get_board_rev(void)
> +{
> +	return 0x20;
> +}
> +
> +/*********************************************************************
> + *  display_board_info() - print banner with board info.
> + *********************************************************************/
> +void display_board_info(u32 btype)
> +{
> +	char *bootmode[] = {
> +		"NOR",
> +		"ONENAND",
> +		"NAND",
> +		"P2a",
> +		"NOR",
> +		"NOR",
> +		"P2a",
> +		"P2b",
> +	};
> +	u32 brev = get_board_rev();
> +	char db_ver[] = "0.0";	/* board type */
> +	char mem_sdr[] = "mSDR";	/* memory type */
> +	char mem_ddr[] = "LPDDR";
> +	char t_tst[] = "TST";	/* security level */
> +	char t_emu[] = "EMU";
> +	char t_hs[] = "HS";
> +	char t_gp[] = "GP";
> +	char unk[] = "?";
> +#ifdef CONFIG_LED_INFO
> +	char led_string[CONFIG_LED_LEN] = { 0 };
> +#endif
> +	char p_l3[] = "165";
> +	char p_cpu[] = "2";
> +
> +	char *db_s, *mem_s, *sec_s;
> +	u32 cpu, rev, sec;
> +
> +	rev = get_cpu_rev();
> +	cpu = get_cpu_type();
> +	sec = get_device_type();
> +
> +	if (is_mem_sdr())
> +		mem_s = mem_sdr;
> +	else
> +		mem_s = mem_ddr;
> +
> +	db_s = db_ver;
> +	db_s[0] += (brev >> 4) & 0xF;
> +	db_s[2] += brev & 0xF;
> +
> +	switch (sec) {
> +	case TST_DEVICE:
> +		sec_s = t_tst;
> +		break;
> +	case EMU_DEVICE:
> +		sec_s = t_emu;
> +		break;
> +	case HS_DEVICE:
> +		sec_s = t_hs;
> +		break;
> +	case GP_DEVICE:
> +		sec_s = t_gp;
> +		break;
> +	default:
> +		sec_s = unk;
> +	}
> +
> +	printf("OMAP%s-%s rev %d, CPU-OPP%s L3-%sMHz\n", sysinfo.cpu_string,
> +	       sec_s, rev, p_cpu, p_l3);
> +	printf("%s + %s/%s\n", sysinfo.board_string,
> +	       mem_s, bootmode[get_gpmc0_type()]);
> +
> +}
> +
> +/********************************************************
> + *  get_base(); get upper addr of current execution
> + *******************************************************/
> +u32 get_base(void)
> +{
> +	u32 val;
> +
> +	__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
> +	val &= 0xF0000000;
> +	val >>= 28;
> +	return val;
> +}
> +
> +/********************************************************
> + *  running_in_flash() - tell if currently running in
> + *   flash.
> + *******************************************************/
> +u32 running_in_flash(void)
why not is_running_in_flash()?
> +{
> +	if (get_base() < 4)
> +		return 1;	/* in flash */
> +
> +	return 0;		/* running in SRAM or SDRAM */
> +}
> +
> +/********************************************************
> + *  running_in_sram() - tell if currently running in
> + *   sram.
> + *******************************************************/
> +u32 running_in_sram(void)
why not is_running_in_sram()?
> +{
> +	if (get_base() == 4)
> +		return 1;	/* in SRAM */
> +
> +	return 0;		/* running in FLASH or SDRAM */
> +}
> +
> +/********************************************************
> + *  running_in_sdram() - tell if currently running in
> + *   flash.
> + *******************************************************/
> +u32 running_in_sdram(void)
why not is_running_in_sdram()?
> +{
> +	if (get_base() > 4)
> +		return 1;	/* in sdram */
> +
> +	return 0;		/* running in SRAM or FLASH */
> +}
> +
> +/***************************************************************
> + *  get_boot_type() - Is this an XIP type device or a stream one
> + *   bits 4-0 specify type.  Bit 5 sys mem/perif
> + ***************************************************************/
> +u32 get_boot_type(void)
> +{
> +	u32 v;
> +
> +	v = get_sysboot_value() & (BIT4 | BIT3 | BIT2 | BIT1 | BIT0);
> +	return v;
> +}
> +
> +/*************************************************************
> + *  get_device_type(): tell if GP/HS/EMU/TST
> + *************************************************************/
> +u32 get_device_type(void)
> +{
> +	int mode;
> +
> +	mode = readl(CONTROL_STATUS) & (DEVICE_MASK);
> +	return mode >>= 8;
> +}
Best Regards,
J.

[U-Boot] [PATCH 04/13 v4] ARM: OMAP3: Add ARM Cortex A8 common directory

[Jean-Christophe PLAGNIOL-VILLARD]

On 21:27 Fri 17 Oct     , dirk.behme at googlemail.com wrote:
> From: Dirk Behme <dirk.behme@gmail.com>
> 
> Add ARM Cortex A8 common directory
> 
> Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
> 
> ---
>  cpu/arm_cortexa8/Makefile  |   43 +++
>  cpu/arm_cortexa8/config.mk |   36 +++
>  cpu/arm_cortexa8/cpu.c     |  221 +++++++++++++++++++
>  cpu/arm_cortexa8/start.S   |  522 +++++++++++++++++++++++++++++++++++++++++++++
>  4 files changed, 822 insertions(+)
> 
> Index: u-boot-arm/cpu/arm_cortexa8/cpu.c
> ===================================================================
> --- /dev/null
> +++ u-boot-arm/cpu/arm_cortexa8/cpu.c
> @@ -0,0 +1,221 @@
> +/*
> + * (C) Copyright 2008 Texas Insturments
> + *
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Marius Groeger <mgroeger@sysgo.de>
> + *
> + * (C) Copyright 2002
> + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +/*
> + * CPU specific code
> + */
> +
> +#include <common.h>
> +#include <command.h>
> +#include <asm/arch/sys_proto.h>
> +
> +#ifdef CONFIG_USE_IRQ
> +DECLARE_GLOBAL_DATA_PTR;
> +#endif
> +
> +#ifndef CONFIG_L2_OFF
> +void l2cache_disable(void);
> +#endif
> +
> +/* read co-processor 15, register #1 (control register) */
> +static unsigned long read_p15_c1(void)
> +{
> +	unsigned long value;
> +
> +	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0\
> +			     @ read control reg\n":"=r"(value)
> +			     ::"memory");
> +	return value;
> +}
> +
> +/* write to co-processor 15, register #1 (control register) */
> +static void write_p15_c1(unsigned long value)
> +{
> +	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0\
> +			     @ write it back\n"::"r"(value)
> +			     : "memory");
> +
> +	read_p15_c1();
> +}
> +
> +static void cp_delay(void)
> +{
> +	volatile int i;
> +
> +	/* Many OMAP regs need at least 2 nops */
> +	for (i = 0; i < 100; i++) ;
> +}
> +
> +/* See also ARM Ref. Man. */
> +#define C1_MMU		(1<<0)	/* mmu off/on */
> +#define C1_ALIGN	(1<<1)	/* alignment faults off/on */
> +#define C1_DC		(1<<2)	/* dcache off/on */
> +#define C1_WB		(1<<3)	/* merging write buffer on/off */
> +#define C1_BIG_ENDIAN	(1<<7)	/* big endian off/on */
> +#define C1_SYS_PROT	(1<<8)	/* system protection */
> +#define C1_ROM_PROT	(1<<9)	/* ROM protection */
> +#define C1_IC		(1<<12)	/* icache off/on */
> +#define C1_HIGH_VECTORS	(1<<13)	/* location of vectors: low/high addresses */
> +#define RESERVED_1	(0xf << 3)	/* must be 111b for R/W */
> +
> +int cpu_init(void)
> +{
> +	/*
> +	 * setup up stacks if necessary
> +	 */
> +#ifdef CONFIG_USE_IRQ
> +	IRQ_STACK_START =
> +	    _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
> +	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
> +#endif
> +	return 0;
> +}
> +
> +int cleanup_before_linux(void)
> +{
> +	unsigned int i;
> +
> +	/*
> +	 * this function is called just before we call linux
> +	 * it prepares the processor for linux
> +	 *
> +	 * we turn off caches etc ...
> +	 */
> +	disable_interrupts();
> +
> +	/* turn off I/D-cache */
> +	asm("mrc p15, 0, %0, c1, c0, 0":"=r"(i));
> +	i &= ~(C1_DC | C1_IC);
> +	asm("mcr p15, 0, %0, c1, c0, 0": :"r"(i));
> +
please do as done in cpu/arm1176/cpu.c
create i/dcache_disable() and cache_flush(), etc...
> +	/* invalidate I-cache */
> +	arm_cache_flush();
> +#ifndef CONFIG_L2_OFF
> +	/* turn off L2 cache */
> +	l2cache_disable();
> +	/* invalidate L2 cache also */
> +	v7_flush_dcache_all(get_device_type());
> +#endif
> +	i = 0;
> +	/* mem barrier to sync up things */
> +	asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
> +
> +#ifndef CONFIG_L2_OFF
> +	l2cache_enable();
> +#endif
> +
> +	return 0;
> +}
> +
> +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
> +{
> +	disable_interrupts();
> +	reset_cpu(0);
> +
> +	/* NOTREACHED */
> +	return 0;
> +}
> +
> +void icache_enable(void)
> +{
> +	ulong reg;
> +
> +	reg = read_p15_c1();	/* get control reg. */
> +	cp_delay();
> +	write_p15_c1(reg | C1_IC);
> +}
> +
> +void icache_disable(void)
> +{
> +	ulong reg;
> +
> +	reg = read_p15_c1();
> +	cp_delay();
> +	write_p15_c1(reg & ~C1_IC);
> +}
> +
> +void l2cache_enable()
> +{
> +	unsigned long i;
> +	volatile unsigned int j;
> +
> +	/* ES2 onwards we can disable/enable L2 ourselves */
> +	if (get_cpu_rev() == CPU_3430_ES2) {
> +		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
> +		__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
> +		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
> +	} else {
> +		/* Save r0, r12 and restore them after usage */
> +		__asm__ __volatile__("mov %0, r12":"=r"(j));
> +		__asm__ __volatile__("mov %0, r0":"=r"(i));
> +
> +		/* GP Device ROM code API usage here */
> +		/* r12 = AUXCR Write function and r0 value */
> +		__asm__ __volatile__("mov r12, #0x3");
> +		__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
> +		__asm__ __volatile__("orr r0, r0, #0x2");
> +		/* SMI instruction to call ROM Code API */
> +		__asm__ __volatile__(".word 0xE1600070");
> +		__asm__ __volatile__("mov r0, %0":"=r"(i));
> +		__asm__ __volatile__("mov r12, %0":"=r"(j));
> +	}
> +
> +}
> +
> +void l2cache_disable()
> +{
> +	unsigned long i;
> +	volatile unsigned int j;
> +
> +	/* ES2 onwards we can disable/enable L2 ourselves */
> +	if (get_cpu_rev() == CPU_3430_ES2) {
> +		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
> +		__asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
> +		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
> +	} else {
> +		/* Save r0, r12 and restore them after usage */
> +		__asm__ __volatile__("mov %0, r12":"=r"(j));
> +		__asm__ __volatile__("mov %0, r0":"=r"(i));
> +
> +		/* GP Device ROM code API usage here */
> +		/* r12 = AUXCR Write function and r0 value */
> +		__asm__ __volatile__("mov r12, #0x3");
> +		__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
> +		__asm__ __volatile__("bic r0, r0, #0x2");
> +		/* SMI instruction to call ROM Code API */
> +		__asm__ __volatile__(".word 0xE1600070");
> +		__asm__ __volatile__("mov r0, %0":"=r"(i));
> +		__asm__ __volatile__("mov r12, %0":"=r"(j));
> +	}
> +}
> +
> +int icache_status(void)
> +{
> +	return (read_p15_c1() & C1_IC) != 0;
> +}
> Index: u-boot-arm/cpu/arm_cortexa8/Makefile
> ===================================================================
> --- /dev/null
> +++ u-boot-arm/cpu/arm_cortexa8/Makefile
> @@ -0,0 +1,43 @@
> +#
> +# (C) Copyright 2000-2003
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB	= lib$(CPU).a
add $(obj)
> +
> +START	:= start.o
> +OBJS	:= cpu.o
> +
please add
SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
START	:= $(addprefix $(obj),$(START))

> +all:	.depend $(START) $(LIB)
> +
> +$(LIB):	$(OBJS)
> +	$(AR) crv $@ $(OBJS)
please replace crv with $(ARFLAGS)
> +
> +#########################################################################
> +
> +.depend:	Makefile $(START:.o=.S) $(OBJS:.o=.c)
> +		$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
please replace by
include $(SRCTREE)/rules.mk
> +
> +sinclude .depend
> +
> +#########################################################################
> \ No newline at end of file
> Index: u-boot-arm/cpu/arm_cortexa8/config.mk
> ===================================================================
> --- /dev/null
> +++ u-boot-arm/cpu/arm_cortexa8/config.mk
> @@ -0,0 +1,36 @@
> +#
> +# (C) Copyright 2002
> +# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
                                            ^
whitespace please remove
> +		     -msoft-float
> +
> +# Make ARMv5 to allow more compilers to work, even though its v7a.
> +PLATFORM_CPPFLAGS += -march=armv5
> +# =========================================================================
> +#
> +# Supply options according to compiler version
> +#
> +# =========================================================================
> +PLATFORM_CPPFLAGS +=$(call cc-option)
> +PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
> +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
> +		    $(call cc-option,-malignment-traps,))
> \ No newline at end of file
> Index: u-boot-arm/cpu/arm_cortexa8/start.S
> ===================================================================
> --- /dev/null
> +++ u-boot-arm/cpu/arm_cortexa8/start.S
> @@ -0,0 +1,522 @@
> +/*
> + *  armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
      ^
whitespace please remove
> + *
> + *  Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
      ^
whitespace please remove
> + *
> + *  Copyright (c) 2001	Marius Gr?ger <mag@sysgo.de>
      ^
whitespace please remove
> + *  Copyright (c) 2002	Alex Z?pke <azu@sysgo.de>
      ^
whitespace please remove
> + *  Copyright (c) 2002	Gary Jennejohn <gj@denx.de>
      ^
whitespace please remove
> + *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
      ^
whitespace please remove
> + *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
      ^
whitespace please remove
> + *  Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
      ^
whitespace please remove
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <config.h>
> +#include <version.h>
> +
> +.globl _start
> +_start: b	reset
> +	ldr	pc, _undefined_instruction
> +	ldr	pc, _software_interrupt
> +	ldr	pc, _prefetch_abort
> +	ldr	pc, _data_abort
> +	ldr	pc, _not_used
> +	ldr	pc, _irq
> +	ldr	pc, _fiq
> +
> +_undefined_instruction: .word undefined_instruction
> +_software_interrupt:	.word software_interrupt
> +_prefetch_abort:	.word prefetch_abort
> +_data_abort:		.word data_abort
> +_not_used:		.word not_used
> +_irq:			.word irq
> +_fiq:			.word fiq
> +_pad:			.word 0x12345678 /* now 16*4=64 */
> +.global _end_vect
> +_end_vect:
> +
> +	.balignl 16,0xdeadbeef
> +/*************************************************************************
> + *
> + * Startup Code (reset vector)
> + *
> + * do important init only if we don't start from memory!
> + * setup Memory and board specific bits prior to relocation.
> + * relocate armboot to ram
> + * setup stack
> + *
> + *************************************************************************/
> +
> +_TEXT_BASE:
> +	.word	TEXT_BASE
> +
> +.globl _armboot_start
> +_armboot_start:
> +	.word _start
> +
> +/*
> + * These are defined in the board-specific linker script.
> + */
> +.globl _bss_start
> +_bss_start:
> +	.word __bss_start
> +
> +.globl _bss_end
> +_bss_end:
> +	.word _end
> +
> +#ifdef CONFIG_USE_IRQ
> +/* IRQ stack memory (calculated at run-time) */
> +.globl IRQ_STACK_START
> +IRQ_STACK_START:
> +	.word	0x0badc0de
please macro instead of value on all
> +
> +/* IRQ stack memory (calculated at run-time) */
> +.globl FIQ_STACK_START
> +FIQ_STACK_START:
> +	.word 0x0badc0de
> +#endif
> +
> +/*
> + * the actual reset code
> + */
> +
> +reset:
> +	/*
> +	 * set the cpu to SVC32 mode
> +	 */
> +	mrs	r0,cpsr
> +	bic	r0,r0,#0x1f
> +	orr	r0,r0,#0xd3
> +	msr	cpsr,r0
> +
> +#if (CONFIG_OMAP34XX)
> +	/* Copy vectors to mask ROM indirect addr */
> +	adr	r0, _start		@ r0 <- current position of code
> +	add	r0, r0, #4		@ skip reset vector
> +	mov	r2, #64			@ r2 <- size to copy
> +	add	r2, r0, r2		@ r2 <- source end address
> +	mov	r1, #SRAM_OFFSET0	@ build vect addr
> +	mov	r3, #SRAM_OFFSET1
> +	add	r1, r1, r3
> +	mov	r3, #SRAM_OFFSET2
> +	add	r1, r1, r3
> +next:
> +	ldmia	r0!, {r3-r10}		@ copy from source address [r0]
please add space between '-'
> +	stmia	r1!, {r3-r10}		@ copy to   target address [r1]
> +	cmp	r0, r2			@ until source end address [r2]
> +	bne	next			@ loop until equal */
> +#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
> +	/* No need to copy/exec the clock code - DPLL adjust already done
> +	 * in NAND/oneNAND Boot.
> +	 */
> +	bl	cpy_clk_code		@ put dpll adjust code behind vectors
> +#endif /* NAND Boot */
> +#endif
> +	/* the mask ROM code should have PLL and others stable */
> +#ifndef CONFIG_SKIP_LOWLEVEL_INIT
> +	bl	cpu_init_crit
> +#endif
> +
> +#ifndef CONFIG_SKIP_RELOCATE_UBOOT
> +relocate:				@ relocate U-Boot to RAM
> +	adr	r0, _start		@ r0 <- current position of code
> +	ldr	r1, _TEXT_BASE		@ test if we run from flash or RAM
> +	cmp	r0, r1			@ don't reloc during debug
> +	beq	stack_setup
> +
> +	ldr	r2, _armboot_start
> +	ldr	r3, _bss_start
> +	sub	r2, r3, r2		@ r2 <- size of armboot
> +	add	r2, r0, r2		@ r2 <- source end address
> +
> +copy_loop:				@ copy 32 bytes at a time
> +	ldmia	r0!, {r3-r10}		@ copy from source address [r0]
> +	stmia	r1!, {r3-r10}		@ copy to   target address [r1]
> +	cmp	r0, r2			@ until source end addreee [r2]
> +	ble	copy_loop
> +#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
> +
> +	/* Set up the stack */
> +stack_setup:
> +	ldr	r0, _TEXT_BASE		@ upper 128 KiB: relocated uboot
> +	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN @ malloc area
> +	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE @ bdinfo
> +#ifdef CONFIG_USE_IRQ
> +	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
> +#endif
> +	sub	sp, r0, #12		@ leave 3 words for abort-stack
> +	and	sp, sp, #~7		@ 8 byte alinged for (ldr/str)d
> +
> +	/* Clear BSS (if any). Is below tx (watch load addr - need space) */
> +clear_bss:
> +	ldr	r0, _bss_start		@ find start of bss segment
> +	ldr	r1, _bss_end		@ stop here
> +	mov 	r2, #0x00000000		@ clear value
           ^
whitespace please remove
> +clbss_l:
> +	str	r2, [r0]		@ clear BSS location
> +	cmp	r0, r1			@ are we at the end yet
> +	add	r0, r0, #4		@ increment clear index pointer
> +	bne	clbss_l			@ keep clearing till at end
> +
> +	ldr	pc, _start_armboot	@ jump to C code
> +
> +_start_armboot: .word start_armboot
> +
> +
> +/*************************************************************************
> + *
> + * CPU_init_critical registers
> + *
> + * setup important registers
> + * setup memory timing
> + *
> + *************************************************************************/
> +cpu_init_crit:
> +	/*
> +	 * Invalidate L1 I/D
> +	 */
> +	mov	r0, #0			@ set up for MCR
> +	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
> +	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
why create function that could be call from c also
> +
> +	/*
> +	 * disable MMU stuff and caches
> +	 */
> +	mrc	p15, 0, r0, c1, c0, 0
> +	bic	r0, r0, #0x00002000	@ clear bits 13 (--V-)
> +	bic	r0, r0, #0x00000007	@ clear bits 2:0 (-CAM)
> +	orr	r0, r0, #0x00000002	@ set bit 1 (--A-) Align
> +	orr	r0, r0, #0x00000800	@ set bit 12 (Z---) BTB
> +	mcr	p15, 0, r0, c1, c0, 0
why create function that could be call from c also
this could be availlable for all cache/mmu/interruptions function
> +
> +	/*
> +	 * Jump to board specific initialization...
> +	 * The Mask ROM will have already initialized
> +	 * basic memory. Go here to bump up clock rate and handle
> +	 * wake up conditions.
> +	 */
> +	mov	ip, lr			@ persevere link reg across call
> +	bl	lowlevel_init		@ go setup pll,mux,memory
> +	mov	lr, ip			@ restore link
> +	mov	pc, lr			@ back to my caller
> +/*
> + *************************************************************************
> + *
> + * Interrupt handling
> + *
> + *************************************************************************
> + */
> +@
> +@ IRQ stack frame.
> +@
> +#define S_FRAME_SIZE	72
> +
> +#define S_OLD_R0	68
> +#define S_PSR		64
> +#define S_PC		60
> +#define S_LR		56
> +#define S_SP		52
> +
> +#define S_IP		48
> +#define S_FP		44
> +#define S_R10		40
> +#define S_R9		36
> +#define S_R8		32
> +#define S_R7		28
> +#define S_R6		24
> +#define S_R5		20
> +#define S_R4		16
> +#define S_R3		12
> +#define S_R2		8
> +#define S_R1		4
> +#define S_R0		0
> +
> +#define MODE_SVC 0x13
> +#define I_BIT	 0x80
> +
> +/*
> + * use bad_save_user_regs for abort/prefetch/undef/swi ...
> + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
> + */
> +
> +	.macro	bad_save_user_regs
> +	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current
> +						@ user stack
> +	stmia	sp, {r0 - r12}			@ Save user registers (now in
> +						@ svc mode) r0-r12
> +
> +	ldr	r2, _armboot_start
> +	sub	r2, r2, #(CONFIG_SYS_MALLOC_LEN)
> +	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)	@ set base 2 words into abort
please add space between '+'

Best Regards,
J.