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From: Vignesh R <vigneshr@ti.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/4] spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock
Date: Mon, 25 Jul 2016 15:45:45 +0530	[thread overview]
Message-ID: <20160725101547.18503-3-vigneshr@ti.com> (raw)
In-Reply-To: <20160725101547.18503-1-vigneshr@ti.com>

According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
the driver to use the same.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 drivers/spi/ti_qspi.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index fa7ee229878a..bb72cb03ec24 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -21,7 +21,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 /* ti qpsi register bit masks */
 #define QSPI_TIMEOUT                    2000000
-#define QSPI_FCLK                       192000000
+#define QSPI_FCLK			192000000
+#define QSPI_DRA7XX_FCLK                76800000
 /* clock control */
 #define QSPI_CLK_EN                     BIT(31)
 #define QSPI_CLK_DIV_MAX                0xffff
@@ -101,6 +102,7 @@ struct ti_qspi_priv {
 #endif
 	struct ti_qspi_regs *base;
 	void *ctrl_mod_mmap;
+	ulong fclk;
 	unsigned int mode;
 	u32 cmd;
 	u32 dc;
@@ -113,7 +115,7 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
 	if (!hz)
 		clk_div = 0;
 	else
-		clk_div = (QSPI_FCLK / hz) - 1;
+		clk_div = (priv->fclk / hz) - 1;
 
 	debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
 
@@ -366,8 +368,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
 	priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
 	priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
+	priv->fclk = QSPI_DRA7XX_FCLK;
 #else
 	priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
+	priv->fclk = QSPI_FCLK;
 #endif
 
 	ti_spi_set_speed(priv, max_hz);
@@ -520,7 +524,10 @@ static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
 
 static int ti_qspi_probe(struct udevice *bus)
 {
-	/* Nothing to do in probe */
+	struct ti_qspi_priv *priv = dev_get_priv(bus);
+
+	priv->fclk = dev_get_driver_data(bus);
+
 	return 0;
 }
 
@@ -572,8 +579,8 @@ static const struct dm_spi_ops ti_qspi_ops = {
 };
 
 static const struct udevice_id ti_qspi_ids[] = {
-	{ .compatible = "ti,dra7xxx-qspi" },
-	{ .compatible = "ti,am4372-qspi" },
+	{ .compatible = "ti,dra7xxx-qspi",	.data = QSPI_DRA7XX_FCLK},
+	{ .compatible = "ti,am4372-qspi",	.data = QSPI_FCLK},
 	{ }
 };
 
-- 
2.9.2

  parent reply	other threads:[~2016-07-25 10:15 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-07-25 10:15 [U-Boot] [PATCH 0/4] dra7xx: QSPI: Increase SPI bus speed Vignesh R
2016-07-25 10:15 ` [U-Boot] [PATCH 1/4] ARM: dra7xx: Change DPLL_PER_HS13 divider value Vignesh R
2016-07-25 13:38   ` Tom Rini
2016-07-29  8:42   ` Mugunthan V N
2016-07-29 18:18     ` Jagan Teki
2016-07-25 10:15 ` Vignesh R [this message]
2016-07-25 13:38   ` [U-Boot] [PATCH 2/4] spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock Tom Rini
2016-07-27  6:35   ` Jagan Teki
2016-07-27 12:10     ` Vignesh R
2016-07-28 13:36       ` Jagan Teki
2016-07-29  8:42   ` Mugunthan V N
2016-07-25 10:15 ` [U-Boot] [PATCH 3/4] configs: dra7xx: Update QSPI speed to 76.8MHz Vignesh R
2016-07-25 13:38   ` Tom Rini
2016-07-27  6:36     ` Jagan Teki
2016-07-29  8:44   ` Mugunthan V N
2016-07-25 10:15 ` [U-Boot] [PATCH 4/4] ARM: dts: dra7xx: Update spi-max-frequency for QSPI Vignesh R
2016-07-25 13:38   ` Tom Rini
2016-07-25 13:46     ` Vignesh R
2016-07-28 13:39       ` Jagan Teki
2016-07-29  8:45   ` Mugunthan V N
2016-07-25 13:38 ` [U-Boot] [PATCH 0/4] dra7xx: QSPI: Increase SPI bus speed Tom Rini
2016-07-26  6:34   ` Vignesh R
2016-07-29 18:23 ` Jagan Teki

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