From: Stefan Agner <stefan@agner.ch>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] mtd: nand: mxs: fix cache alignment for cache lines >32
Date: Mon, 1 Aug 2016 23:55:18 -0700 [thread overview]
Message-ID: <20160802065518.24140-1-stefan@agner.ch> (raw)
From: Stefan Agner <stefan.agner@toradex.com>
Currently the command buffer gets allocated with a size of 32 bytes.
This causes warning messages on systems with cache lines bigger than
32 bytes:
CACHE: Misaligned operation at range [9df17a00, 9df17a20]
Define command buffer to be at least 32 bytes, but more if cache
line is bigger.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
---
This appeared after Simon enable the message in check_cache_range
by default...
drivers/mtd/nand/mxs_nand.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index 94fc5c1..4bf564e 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -37,7 +37,12 @@
#endif
#define MXS_NAND_METADATA_SIZE 10
#define MXS_NAND_BITS_PER_ECC_LEVEL 13
+
+#if !defined(CONFIG_SYS_CACHELINE_SIZE) || CONFIG_SYS_CACHELINE_SIZE < 32
#define MXS_NAND_COMMAND_BUFFER_SIZE 32
+#else
+#define MXS_NAND_COMMAND_BUFFER_SIZE CONFIG_SYS_CACHELINE_SIZE
+#endif
#define MXS_NAND_BCH_TIMEOUT 10000
--
2.9.0
next reply other threads:[~2016-08-02 6:55 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-02 6:55 Stefan Agner [this message]
2016-08-02 8:17 ` [U-Boot] [PATCH] mtd: nand: mxs: fix cache alignment for cache lines >32 Stefano Babic
2016-08-03 7:57 ` Stefano Babic
2016-08-03 13:51 ` Fabio Estevam
2016-08-03 16:13 ` Stefan Agner
2016-08-03 17:39 ` Fabio Estevam
2016-08-03 18:09 ` Tom Rini
2016-08-03 18:29 ` Fabio Estevam
2016-08-03 18:35 ` Simon Glass
2016-08-03 18:44 ` Fabio Estevam
2016-08-03 19:08 ` Simon Glass
2016-08-03 19:43 ` Stefan Agner
2016-08-03 19:18 ` Stefan Agner
2016-08-03 20:05 ` Hannes Schmelzer
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