From: Tom Rini <trini@konsulko.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [U-Boot, v5, 2/2] arm: cache: always flush cache line size for page table
Date: Mon, 29 Aug 2016 08:00:44 -0400 [thread overview]
Message-ID: <20160829120044.GD8799@bill-the-cat> (raw)
In-Reply-To: <20160815043301.29276-2-stefan@agner.ch>
On Sun, Aug 14, 2016 at 09:33:01PM -0700, Stefan Agner wrote:
> From: Stefan Agner <stefan.agner@toradex.com>
>
> The page table is maintained by the CPU, hence it is safe to always
> align cache flush to a whole cache line size. This allows to use
> mmu_page_table_flush for a single page table, e.g. when configure
> only small regions through mmu_set_region_dcache_behaviour.
>
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Heiko Schocher <hs@denx.de>
Applied to u-boot/master, thanks!
--
Tom
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next prev parent reply other threads:[~2016-08-29 12:00 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-15 4:33 [U-Boot] [PATCH v5 1/2] arm: cache: add support for LPAE for region D$ behavior Stefan Agner
2016-08-15 4:33 ` [U-Boot] [PATCH v5 2/2] arm: cache: always flush cache line size for page table Stefan Agner
2016-08-29 12:00 ` Tom Rini [this message]
2016-08-29 12:00 ` [U-Boot] [U-Boot, v5, 1/2] arm: cache: add support for LPAE for region D$ behavior Tom Rini
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