From: Tom Rini <trini@konsulko.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 2/2] arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode
Date: Sat, 29 Oct 2016 13:41:45 -0400 [thread overview]
Message-ID: <20161029174145.GM18591@bill-the-cat> (raw)
In-Reply-To: <1477734550-17989-2-git-send-email-j-keerthy@ti.com>
On Sat, Oct 29, 2016 at 03:19:10PM +0530, Keerthy wrote:
> While we setup the mmu initially we mark set_section_dcache with
> DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
> is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
> 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with
> DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which
> keeps all the regions execute okay and this leads to random speculative
> fetches in random memory regions which was eventually caught by kernel
> omap-l3-noc driver.
>
> Fix this to mark the regions as XN by default.
>
> Signed-off-by: Keerthy <j-keerthy@ti.com>
> Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
--
Tom
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next prev parent reply other threads:[~2016-10-29 17:41 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-29 9:49 [U-Boot] [PATCH v2 1/2] arm: print the cache config option in hex instead of decimal Keerthy
2016-10-29 9:49 ` [U-Boot] [PATCH v2 2/2] arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode Keerthy
2016-10-29 17:41 ` Tom Rini [this message]
2016-10-29 17:44 ` Marek Vasut
2016-10-29 17:47 ` Tom Rini
2016-10-29 17:49 ` Marek Vasut
2016-10-30 1:59 ` Keerthy
2016-10-30 12:00 ` Marek Vasut
2016-11-07 4:07 ` Keerthy
2016-11-13 20:56 ` [U-Boot] [U-Boot, v2, " Tom Rini
2016-10-29 17:41 ` [U-Boot] [PATCH v2 1/2] arm: print the cache config option in hex instead of decimal Tom Rini
2016-11-13 20:56 ` [U-Boot] [U-Boot, v2, " Tom Rini
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