[U-Boot] [PATCH 02/13] sunxi: add basical memory map definitions of H6 SoC

[Maxime Ripard <maxime.ripard@bootlin.com>]

On Mon, Jun 25, 2018 at 08:50:08PM +0800, Icenowy Zheng wrote:
> 
> 
> 于 2018年6月25日 GMT+08:00 下午8:33:34, Maxime Ripard <maxime.ripard@bootlin.com> 写到:
> >On Mon, Jun 25, 2018 at 06:37:12PM +0800, Icenowy Zheng wrote:
> >> The Allwinner H6 SoC come with a totally new memory map.
> >> 
> >> Add basical definition of the new memory map into a header file, and
> >let
> >> the cpu.h header include it in the situation of H6.
> >> 
> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> >> ---
> >>  arch/arm/include/asm/arch-sunxi/cpu.h         |  2 +
> >>  .../include/asm/arch-sunxi/cpu_sun50i_h6.h    | 73
> >+++++++++++++++++++
> >>  2 files changed, 75 insertions(+)
> >>  create mode 100644 arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
> >> 
> >> diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h
> >b/arch/arm/include/asm/arch-sunxi/cpu.h
> >> index caec865264..08be963e8e 100644
> >> --- a/arch/arm/include/asm/arch-sunxi/cpu.h
> >> +++ b/arch/arm/include/asm/arch-sunxi/cpu.h
> >> @@ -9,6 +9,8 @@
> >>  
> >>  #if defined(CONFIG_MACH_SUN9I)
> >>  #include <asm/arch/cpu_sun9i.h>
> >> +#elif defined(CONFIG_MACH_SUN50I_H6)
> >> +#include <asm/arch/cpu_sun50i_h6.h>
> >>  #else
> >>  #include <asm/arch/cpu_sun4i.h>
> >>  #endif
> >> diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
> >b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
> >> new file mode 100644
> >> index 0000000000..b12f2dd1a2
> >> --- /dev/null
> >> +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
> >> @@ -0,0 +1,73 @@
> >> +/*
> >> + * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
> >> + *
> >> + * SPDX-License-Identifier:	GPL-2.0+
> >> + */
> >> +
> >> +#ifndef _SUNXI_CPU_SUN50I_H6_H
> >> +#define _SUNXI_CPU_SUN50I_H6_H
> >> +
> >> +#define SUNXI_SRAM_A1_BASE		0x00020000
> >
> >Isn't that the same thing than SUNXI_SRAM_ADDRESS? Having it defined
> >twice and expecting the value to be matching seems a bit weird.
> 
> This assumes SPL will be in SRAM A1, which may change.

Then let's deal with this when it will change.

Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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