[U-Boot] [PATCH v3 0/8] Get socfpga gen5 SPL working again.

[U-Boot] [PATCH v3 0/8] Get socfpga gen5 SPL working again.

[Simon Goldschmidt]

Socfpga gen5 SPL has been broken since moving to DM serial with
v2018.07. Also, U-Boot console output has been broken since then.
This series fixes this and makes some related small improvements.

Changes in v3:
- moved uart0's "u-boot,dm-pre-reloc;" from socfpga.dtsi to board
  specific dts files since this can change per board
- added patches 5-7 to boot SPL and U-Boot from fpga OnChip RAM
- dropped Patch 5/6 "serial: ns16550: fix debug uart putc called before
  init" (this needs a more generic fix)

Changes in v2:
- Improved comment on patch 1
- Removing gd->malloc_base assignment at the end of board_init_f()
  moved to an extra patch
- don't change printf() to debug() in reset_manager_gen5.c
  socfpga_bridges_reset() (instead make debug uart handle this)
- make ns16550 debug uart handle putc being called before init
- removed the assignment of gd->malloc_limit from board_init()

Simon Goldschmidt (8):
  arm: socfpga: fix SPL on gen5 after moving to DM serial
  arm: socfpga: fix device trees to work with DM serial
  arm: socfpga: spl_gen5: clean up malloc_base assignment
  arm: socfpga: cyclone5: handle debug uart
  arm: socfpga: fix U-Boot running from fpga OnChip RAM
  arm: socfpga: gen5: combine some init code for SPL and U-Boot
  arm: socfpga: fix SPL booting from fpga OnChip RAM
  malloc_simple: calloc: don't call memset if malloc failed

 arch/arm/dts/socfpga_arria5_socdk.dts         |  5 ++
 arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts    |  5 ++
 .../arm/dts/socfpga_cyclone5_de0_nano_soc.dts |  5 ++
 arch/arm/dts/socfpga_cyclone5_de10_nano.dts   |  5 ++
 arch/arm/dts/socfpga_cyclone5_de1_soc.dts     |  5 ++
 arch/arm/dts/socfpga_cyclone5_is1.dts         |  5 ++
 arch/arm/dts/socfpga_cyclone5_socdk.dts       |  5 ++
 arch/arm/dts/socfpga_cyclone5_sockit.dts      |  5 ++
 arch/arm/dts/socfpga_cyclone5_socrates.dts    |  5 ++
 arch/arm/dts/socfpga_cyclone5_sr1500.dts      |  2 +
 arch/arm/dts/socfpga_cyclone5_vining_fpga.dts |  5 ++
 arch/arm/mach-socfpga/Kconfig                 | 12 +++++
 arch/arm/mach-socfpga/include/mach/misc.h     |  4 ++
 arch/arm/mach-socfpga/misc_gen5.c             | 40 +++++++++------
 arch/arm/mach-socfpga/spl_gen5.c              | 49 ++++++-------------
 common/malloc_simple.c                        |  3 +-
 include/configs/socfpga_common.h              | 13 +++++
 17 files changed, 125 insertions(+), 48 deletions(-)

-- 
2.17.1

[U-Boot] [PATCH v3 1/8] arm: socfpga: fix SPL on gen5 after moving to DM serial

[Simon Goldschmidt]

There were NULL pointers dereferenced because DM was used
too early without correct initialization:
- malloc_simple returned NULL when called from preloader_console_init()
  because gd->malloc_limit was 0
- uclass_add dereferenced gd->uclass_root members which were NULL because
  dm_init (or one of its relatives) has not been called.

All this is fixed by calling spl_early_init before calling
preloader_console_init.

This fixes commit 73172753f4f3 ("ARM: socfpga: Convert to DM serial")

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v3: None
Changes in v2:
- Don't remove gd->malloc_base assignment at the end of board_init_f()
  (moved to an extra patch)

 arch/arm/mach-socfpga/spl_gen5.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index d6fe7d35af..9bdfaa3c1e 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -86,6 +86,7 @@ void board_init_f(ulong dummy)
 	const struct cm_config *cm_default_cfg = cm_get_default_config();
 	unsigned long sdram_size;
 	unsigned long reg;
+	int ret;
 
 	/*
 	 * First C code to run. Clear fake OCRAM ECC first as SBE
@@ -152,6 +153,12 @@ void board_init_f(ulong dummy)
 	/* unfreeze / thaw all IO banks */
 	sys_mgr_frzctrl_thaw_req();
 
+	ret = spl_early_init();
+	if (ret) {
+		debug("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+
 	/* enable console uart printing */
 	preloader_console_init();
 
-- 
2.17.1

[U-Boot] [PATCH v3 2/8] arm: socfpga: fix device trees to work with DM serial

[Simon Goldschmidt]

Device trees need to have the serial console device available
before relocation and require a stdout-path in chosen at least
for SPL to have a console.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v3:
- moved uart0's "u-boot,dm-pre-reloc;" from socfpga.dtsi to board
  specific dts files since this can change per board
Changes in v2: None

 arch/arm/dts/socfpga_arria5_socdk.dts          | 5 +++++
 arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts     | 5 +++++
 arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts | 5 +++++
 arch/arm/dts/socfpga_cyclone5_de10_nano.dts    | 5 +++++
 arch/arm/dts/socfpga_cyclone5_de1_soc.dts      | 5 +++++
 arch/arm/dts/socfpga_cyclone5_is1.dts          | 5 +++++
 arch/arm/dts/socfpga_cyclone5_socdk.dts        | 5 +++++
 arch/arm/dts/socfpga_cyclone5_sockit.dts       | 5 +++++
 arch/arm/dts/socfpga_cyclone5_socrates.dts     | 5 +++++
 arch/arm/dts/socfpga_cyclone5_sr1500.dts       | 2 ++
 arch/arm/dts/socfpga_cyclone5_vining_fpga.dts  | 5 +++++
 11 files changed, 52 insertions(+)

diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts
index 449ba9cbb9..6f4de2f563 100644
--- a/arch/arm/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/dts/socfpga_arria5_socdk.dts
@@ -11,6 +11,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200";
+		stdout-path = "serial0:115200n8";
 	};
 
 	memory {
@@ -99,3 +100,7 @@
 		cdns,tslch-ns = <4>;
 	};
 };
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
index aeb327dd5b..139a70f265 100644
--- a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
@@ -11,6 +11,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200";
+		stdout-path = "serial0:115200n8";
 	};
 
 	aliases {
@@ -56,3 +57,7 @@
 	disable-over-current;
 	status = "okay";
 };
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
index f4a98e4bb0..d504150edd 100644
--- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
@@ -11,6 +11,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200";
+		stdout-path = "serial0:115200n8";
 	};
 
 	aliases {
@@ -75,3 +76,7 @@
 &usb1 {
 	status = "okay";
 };
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
index 7da2d8b043..d4dd9e9bca 100644
--- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
@@ -13,6 +13,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200";
+		stdout-path = "serial0:115200n8";
 	};
 
 	aliases {
@@ -65,3 +66,7 @@
 &usb1 {
 	status = "okay";
 };
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
index e6fadb4fc9..f62292284d 100644
--- a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
@@ -11,6 +11,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200";
+		stdout-path = "serial0:115200n8";
 	};
 
 	aliases {
@@ -63,3 +64,7 @@
 &usb1 {
 	status = "okay";
 };
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts
index aa1ce2c3e2..4e94d86114 100644
--- a/arch/arm/dts/socfpga_cyclone5_is1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_is1.dts
@@ -11,6 +11,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200";
+		stdout-path = "serial0:115200n8";
 	};
 
 	memory {
@@ -102,3 +103,7 @@
 &usb1 {
 	status = "okay";
 };
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index 55c70abb02..c28be67bb9 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -11,6 +11,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200";
+		stdout-path = "serial0:115200n8";
 	};
 
 	memory {
@@ -113,3 +114,7 @@
 &usb1 {
 	status = "okay";
 };
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_sockit.dts b/arch/arm/dts/socfpga_cyclone5_sockit.dts
index 08d8356d80..c7a6cf2db8 100644
--- a/arch/arm/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/dts/socfpga_cyclone5_sockit.dts
@@ -11,6 +11,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200";
+		stdout-path = "serial0:115200n8";
 	};
 
 	aliases {
@@ -93,3 +94,7 @@
 &usb1 {
 	status = "okay";
 };
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index 0d452ae300..8cde9906a0 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -11,6 +11,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200";
+		stdout-path = "serial0:115200n8";
 	};
 
 	aliases {
@@ -84,3 +85,7 @@
 	disable-over-current;
 	status = "okay";
 };
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
index 341df7a3e7..86c61fe081 100644
--- a/arch/arm/dts/socfpga_cyclone5_sr1500.dts
+++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
@@ -11,6 +11,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200";
+		stdout-path = "serial0:115200n8";
 	};
 
 	aliases {
@@ -67,6 +68,7 @@
 
 &uart0 {
 	status = "okay";
+	u-boot,dm-pre-reloc;
 };
 
 &usb1 {
diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts
index 7a032af3a4..85ab56379f 100644
--- a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts
+++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts
@@ -11,6 +11,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200";
+		stdout-path = "serial0:115200n8";
 	};
 
 	aliases {
@@ -108,3 +109,7 @@
 &usb1 {
 	status = "okay";
 };
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+};
-- 
2.17.1

[U-Boot] [PATCH v3 2/8] arm: socfpga: fix device trees to work with DM serial

[Tom Rini]

On Mon, Aug 13, 2018 at 09:33:45AM +0200, Simon Goldschmidt wrote:

> Device trees need to have the serial console device available
> before relocation and require a stdout-path in chosen at least
> for SPL to have a console.
> 
> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> ---
> 
> Changes in v3:
> - moved uart0's "u-boot,dm-pre-reloc;" from socfpga.dtsi to board
>   specific dts files since this can change per board

Why are these not in socfpga-u-boot.dtsi ?  We have the mechanism to
grab CONFIG_SYS_CPU/CONFIG_SYS_SOC/CONFIG_SYS_VENDOR-u-boot.dtsi
automatically so that we don't have to modify the files we sync in from
upstream.

-- 
Tom
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[U-Boot] [PATCH v3 2/8] arm: socfpga: fix device trees to work with DM serial

[Simon Goldschmidt]

On Mon, Aug 13, 2018 at 3:17 PM Tom Rini <trini@konsulko.com> wrote:
>
> On Mon, Aug 13, 2018 at 09:33:45AM +0200, Simon Goldschmidt wrote:
>
> > Device trees need to have the serial console device available
> > before relocation and require a stdout-path in chosen at least
> > for SPL to have a console.
> >
> > Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> > ---
> >
> > Changes in v3:
> > - moved uart0's "u-boot,dm-pre-reloc;" from socfpga.dtsi to board
> >   specific dts files since this can change per board
>
> Why are these not in socfpga-u-boot.dtsi ?  We have the mechanism to
> grab CONFIG_SYS_CPU/CONFIG_SYS_SOC/CONFIG_SYS_VENDOR-u-boot.dtsi
> automatically so that we don't have to modify the files we sync in from
> upstream.

Ehrm, I don't know, really. The DTS files for socfpga already have
many U-Boot specifics and are quite different to Linux. It might make
sense to sync them, but do we really have to do this for 2018.09?

Keep in mind that this series exists to fix that 2018.07 broke on these boards.

Simon

[U-Boot] [PATCH v3 2/8] arm: socfpga: fix device trees to work with DM serial

[Tom Rini]

On Mon, Aug 13, 2018 at 03:25:19PM +0200, Simon Goldschmidt wrote:
> On Mon, Aug 13, 2018 at 3:17 PM Tom Rini <trini@konsulko.com> wrote:
> >
> > On Mon, Aug 13, 2018 at 09:33:45AM +0200, Simon Goldschmidt wrote:
> >
> > > Device trees need to have the serial console device available
> > > before relocation and require a stdout-path in chosen at least
> > > for SPL to have a console.
> > >
> > > Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> > > ---
> > >
> > > Changes in v3:
> > > - moved uart0's "u-boot,dm-pre-reloc;" from socfpga.dtsi to board
> > >   specific dts files since this can change per board
> >
> > Why are these not in socfpga-u-boot.dtsi ?  We have the mechanism to
> > grab CONFIG_SYS_CPU/CONFIG_SYS_SOC/CONFIG_SYS_VENDOR-u-boot.dtsi
> > automatically so that we don't have to modify the files we sync in from
> > upstream.
> 
> Ehrm, I don't know, really. The DTS files for socfpga already have
> many U-Boot specifics and are quite different to Linux. It might make
> sense to sync them, but do we really have to do this for 2018.09?
> 
> Keep in mind that this series exists to fix that 2018.07 broke on these boards.

Well, I think given that you're adding these changes right now, they
should be added to the correct file so that they aren't lost on re-sync
later.  It would be adding:
&uart0 {
       u-boot,dm-pre-reloc;
};

once to arch/arm/dts/socfpga-u-boot.dtsi rather than for every board.

-- 
Tom
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[U-Boot] [PATCH v3 2/8] arm: socfpga: fix device trees to work with DM serial

[Marek Vasut]

On 08/13/2018 03:28 PM, Tom Rini wrote:
> On Mon, Aug 13, 2018 at 03:25:19PM +0200, Simon Goldschmidt wrote:
>> On Mon, Aug 13, 2018 at 3:17 PM Tom Rini <trini@konsulko.com> wrote:
>>>
>>> On Mon, Aug 13, 2018 at 09:33:45AM +0200, Simon Goldschmidt wrote:
>>>
>>>> Device trees need to have the serial console device available
>>>> before relocation and require a stdout-path in chosen at least
>>>> for SPL to have a console.
>>>>
>>>> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
>>>> ---
>>>>
>>>> Changes in v3:
>>>> - moved uart0's "u-boot,dm-pre-reloc;" from socfpga.dtsi to board
>>>>   specific dts files since this can change per board
>>>
>>> Why are these not in socfpga-u-boot.dtsi ?  We have the mechanism to
>>> grab CONFIG_SYS_CPU/CONFIG_SYS_SOC/CONFIG_SYS_VENDOR-u-boot.dtsi
>>> automatically so that we don't have to modify the files we sync in from
>>> upstream.
>>
>> Ehrm, I don't know, really. The DTS files for socfpga already have
>> many U-Boot specifics and are quite different to Linux. It might make
>> sense to sync them, but do we really have to do this for 2018.09?
>>
>> Keep in mind that this series exists to fix that 2018.07 broke on these boards.
> 
> Well, I think given that you're adding these changes right now, they
> should be added to the correct file so that they aren't lost on re-sync
> later.  It would be adding:
> &uart0 {
>        u-boot,dm-pre-reloc;
> };
> 
> once to arch/arm/dts/socfpga-u-boot.dtsi rather than for every board.

Pulling the U-Boot specific crap would be most welcome, but it could be
a separate patch.

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v3 2/8] arm: socfpga: fix device trees to work with DM serial

[Tom Rini]

On Mon, Aug 13, 2018 at 03:29:30PM +0200, Marek Vasut wrote:
> On 08/13/2018 03:28 PM, Tom Rini wrote:
> > On Mon, Aug 13, 2018 at 03:25:19PM +0200, Simon Goldschmidt wrote:
> >> On Mon, Aug 13, 2018 at 3:17 PM Tom Rini <trini@konsulko.com> wrote:
> >>>
> >>> On Mon, Aug 13, 2018 at 09:33:45AM +0200, Simon Goldschmidt wrote:
> >>>
> >>>> Device trees need to have the serial console device available
> >>>> before relocation and require a stdout-path in chosen at least
> >>>> for SPL to have a console.
> >>>>
> >>>> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> >>>> ---
> >>>>
> >>>> Changes in v3:
> >>>> - moved uart0's "u-boot,dm-pre-reloc;" from socfpga.dtsi to board
> >>>>   specific dts files since this can change per board
> >>>
> >>> Why are these not in socfpga-u-boot.dtsi ?  We have the mechanism to
> >>> grab CONFIG_SYS_CPU/CONFIG_SYS_SOC/CONFIG_SYS_VENDOR-u-boot.dtsi
> >>> automatically so that we don't have to modify the files we sync in from
> >>> upstream.
> >>
> >> Ehrm, I don't know, really. The DTS files for socfpga already have
> >> many U-Boot specifics and are quite different to Linux. It might make
> >> sense to sync them, but do we really have to do this for 2018.09?
> >>
> >> Keep in mind that this series exists to fix that 2018.07 broke on these boards.
> > 
> > Well, I think given that you're adding these changes right now, they
> > should be added to the correct file so that they aren't lost on re-sync
> > later.  It would be adding:
> > &uart0 {
> >        u-boot,dm-pre-reloc;
> > };
> > 
> > once to arch/arm/dts/socfpga-u-boot.dtsi rather than for every board.
> 
> Pulling the U-Boot specific crap would be most welcome, but it could be
> a separate patch.

So you want to add stuff now and pull it out later?  That seems counter
intuitive, but sure, you're the custodian here.  When do you plan to do
the clean-up, for v2018.11?

-- 
Tom
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[U-Boot] [PATCH v3 2/8] arm: socfpga: fix device trees to work with DM serial

[Simon Goldschmidt]

Tom Rini <trini@konsulko.com> schrieb am Mo., 13. Aug. 2018, 15:33:

> On Mon, Aug 13, 2018 at 03:29:30PM +0200, Marek Vasut wrote:
> > On 08/13/2018 03:28 PM, Tom Rini wrote:
> > > On Mon, Aug 13, 2018 at 03:25:19PM +0200, Simon Goldschmidt wrote:
> > >> On Mon, Aug 13, 2018 at 3:17 PM Tom Rini <trini@konsulko.com> wrote:
> > >>>
> > >>> On Mon, Aug 13, 2018 at 09:33:45AM +0200, Simon Goldschmidt wrote:
> > >>>
> > >>>> Device trees need to have the serial console device available
> > >>>> before relocation and require a stdout-path in chosen at least
> > >>>> for SPL to have a console.
> > >>>>
> > >>>> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> > >>>> ---
> > >>>>
> > >>>> Changes in v3:
> > >>>> - moved uart0's "u-boot,dm-pre-reloc;" from socfpga.dtsi to board
> > >>>>   specific dts files since this can change per board
> > >>>
> > >>> Why are these not in socfpga-u-boot.dtsi ?  We have the mechanism to
> > >>> grab CONFIG_SYS_CPU/CONFIG_SYS_SOC/CONFIG_SYS_VENDOR-u-boot.dtsi
> > >>> automatically so that we don't have to modify the files we sync in
> from
> > >>> upstream.
> > >>
> > >> Ehrm, I don't know, really. The DTS files for socfpga already have
> > >> many U-Boot specifics and are quite different to Linux. It might make
> > >> sense to sync them, but do we really have to do this for 2018.09?
> > >>
> > >> Keep in mind that this series exists to fix that 2018.07 broke on
> these boards.
> > >
> > > Well, I think given that you're adding these changes right now, they
> > > should be added to the correct file so that they aren't lost on re-sync
> > > later.  It would be adding:
> > > &uart0 {
> > >        u-boot,dm-pre-reloc;
> > > };
> > >
> > > once to arch/arm/dts/socfpga-u-boot.dtsi rather than for every board.
> >
> > Pulling the U-Boot specific crap would be most welcome, but it could be
> > a separate patch.
>
> So you want to add stuff now and pull it out later?  That seems counter
> intuitive, but sure, you're the custodian here.  When do you plan to do
> the clean-up, for v2018.11?
>

Can we do this in one step with syncing up to the latest Linux device trees?

Simon

[U-Boot] [PATCH v3 2/8] arm: socfpga: fix device trees to work with DM serial

[Tom Rini]

On Mon, Aug 13, 2018 at 03:36:35PM +0200, Simon Goldschmidt wrote:
> Tom Rini <trini@konsulko.com> schrieb am Mo., 13. Aug. 2018, 15:33:
> 
> > On Mon, Aug 13, 2018 at 03:29:30PM +0200, Marek Vasut wrote:
> > > On 08/13/2018 03:28 PM, Tom Rini wrote:
> > > > On Mon, Aug 13, 2018 at 03:25:19PM +0200, Simon Goldschmidt wrote:
> > > >> On Mon, Aug 13, 2018 at 3:17 PM Tom Rini <trini@konsulko.com> wrote:
> > > >>>
> > > >>> On Mon, Aug 13, 2018 at 09:33:45AM +0200, Simon Goldschmidt wrote:
> > > >>>
> > > >>>> Device trees need to have the serial console device available
> > > >>>> before relocation and require a stdout-path in chosen at least
> > > >>>> for SPL to have a console.
> > > >>>>
> > > >>>> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> > > >>>> ---
> > > >>>>
> > > >>>> Changes in v3:
> > > >>>> - moved uart0's "u-boot,dm-pre-reloc;" from socfpga.dtsi to board
> > > >>>>   specific dts files since this can change per board
> > > >>>
> > > >>> Why are these not in socfpga-u-boot.dtsi ?  We have the mechanism to
> > > >>> grab CONFIG_SYS_CPU/CONFIG_SYS_SOC/CONFIG_SYS_VENDOR-u-boot.dtsi
> > > >>> automatically so that we don't have to modify the files we sync in
> > from
> > > >>> upstream.
> > > >>
> > > >> Ehrm, I don't know, really. The DTS files for socfpga already have
> > > >> many U-Boot specifics and are quite different to Linux. It might make
> > > >> sense to sync them, but do we really have to do this for 2018.09?
> > > >>
> > > >> Keep in mind that this series exists to fix that 2018.07 broke on
> > these boards.
> > > >
> > > > Well, I think given that you're adding these changes right now, they
> > > > should be added to the correct file so that they aren't lost on re-sync
> > > > later.  It would be adding:
> > > > &uart0 {
> > > >        u-boot,dm-pre-reloc;
> > > > };
> > > >
> > > > once to arch/arm/dts/socfpga-u-boot.dtsi rather than for every board.
> > >
> > > Pulling the U-Boot specific crap would be most welcome, but it could be
> > > a separate patch.
> >
> > So you want to add stuff now and pull it out later?  That seems counter
> > intuitive, but sure, you're the custodian here.  When do you plan to do
> > the clean-up, for v2018.11?
> >
> 
> Can we do this in one step with syncing up to the latest Linux device trees?

I honestly don't understand the hesitation to not introduce more change
than is required now.  But, I will defer.  I do want to know when people
plan to fix this however, as that feels like a reasonable compromise to
me.

-- 
Tom
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[U-Boot] [PATCH v3 2/8] arm: socfpga: fix device trees to work with DM serial

[Marek Vasut]

On 08/13/2018 03:41 PM, Tom Rini wrote:
> On Mon, Aug 13, 2018 at 03:36:35PM +0200, Simon Goldschmidt wrote:
>> Tom Rini <trini@konsulko.com> schrieb am Mo., 13. Aug. 2018, 15:33:
>>
>>> On Mon, Aug 13, 2018 at 03:29:30PM +0200, Marek Vasut wrote:
>>>> On 08/13/2018 03:28 PM, Tom Rini wrote:
>>>>> On Mon, Aug 13, 2018 at 03:25:19PM +0200, Simon Goldschmidt wrote:
>>>>>> On Mon, Aug 13, 2018 at 3:17 PM Tom Rini <trini@konsulko.com> wrote:
>>>>>>>
>>>>>>> On Mon, Aug 13, 2018 at 09:33:45AM +0200, Simon Goldschmidt wrote:
>>>>>>>
>>>>>>>> Device trees need to have the serial console device available
>>>>>>>> before relocation and require a stdout-path in chosen at least
>>>>>>>> for SPL to have a console.
>>>>>>>>
>>>>>>>> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
>>>>>>>> ---
>>>>>>>>
>>>>>>>> Changes in v3:
>>>>>>>> - moved uart0's "u-boot,dm-pre-reloc;" from socfpga.dtsi to board
>>>>>>>>   specific dts files since this can change per board
>>>>>>>
>>>>>>> Why are these not in socfpga-u-boot.dtsi ?  We have the mechanism to
>>>>>>> grab CONFIG_SYS_CPU/CONFIG_SYS_SOC/CONFIG_SYS_VENDOR-u-boot.dtsi
>>>>>>> automatically so that we don't have to modify the files we sync in
>>> from
>>>>>>> upstream.
>>>>>>
>>>>>> Ehrm, I don't know, really. The DTS files for socfpga already have
>>>>>> many U-Boot specifics and are quite different to Linux. It might make
>>>>>> sense to sync them, but do we really have to do this for 2018.09?
>>>>>>
>>>>>> Keep in mind that this series exists to fix that 2018.07 broke on
>>> these boards.
>>>>>
>>>>> Well, I think given that you're adding these changes right now, they
>>>>> should be added to the correct file so that they aren't lost on re-sync
>>>>> later.  It would be adding:
>>>>> &uart0 {
>>>>>        u-boot,dm-pre-reloc;
>>>>> };
>>>>>
>>>>> once to arch/arm/dts/socfpga-u-boot.dtsi rather than for every board.
>>>>
>>>> Pulling the U-Boot specific crap would be most welcome, but it could be
>>>> a separate patch.
>>>
>>> So you want to add stuff now and pull it out later?  That seems counter
>>> intuitive, but sure, you're the custodian here.  When do you plan to do
>>> the clean-up, for v2018.11?
>>>
>>
>> Can we do this in one step with syncing up to the latest Linux device trees?
> 
> I honestly don't understand the hesitation to not introduce more change
> than is required now.  But, I will defer.  I do want to know when people
> plan to fix this however, as that feels like a reasonable compromise to
> me.

I presume Simon will stick around, so I'm happy to cut him some slack ...

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v3 2/8] arm: socfpga: fix device trees to work with DM serial

[Simon Goldschmidt]

Tom Rini <trini@konsulko.com> schrieb am Mo., 13. Aug. 2018, 15:41:

> On Mon, Aug 13, 2018 at 03:36:35PM +0200, Simon Goldschmidt wrote:
> > Tom Rini <trini@konsulko.com> schrieb am Mo., 13. Aug. 2018, 15:33:
> >
> > > On Mon, Aug 13, 2018 at 03:29:30PM +0200, Marek Vasut wrote:
> > > > On 08/13/2018 03:28 PM, Tom Rini wrote:
> > > > > On Mon, Aug 13, 2018 at 03:25:19PM +0200, Simon Goldschmidt wrote:
> > > > >> On Mon, Aug 13, 2018 at 3:17 PM Tom Rini <trini@konsulko.com>
> wrote:
> > > > >>>
> > > > >>> On Mon, Aug 13, 2018 at 09:33:45AM +0200, Simon Goldschmidt
> wrote:
> > > > >>>
> > > > >>>> Device trees need to have the serial console device available
> > > > >>>> before relocation and require a stdout-path in chosen at least
> > > > >>>> for SPL to have a console.
> > > > >>>>
> > > > >>>> Signed-off-by: Simon Goldschmidt <
> simon.k.r.goldschmidt at gmail.com>
> > > > >>>> ---
> > > > >>>>
> > > > >>>> Changes in v3:
> > > > >>>> - moved uart0's "u-boot,dm-pre-reloc;" from socfpga.dtsi to
> board
> > > > >>>>   specific dts files since this can change per board
> > > > >>>
> > > > >>> Why are these not in socfpga-u-boot.dtsi ?  We have the
> mechanism to
> > > > >>> grab CONFIG_SYS_CPU/CONFIG_SYS_SOC/CONFIG_SYS_VENDOR-u-boot.dtsi
> > > > >>> automatically so that we don't have to modify the files we sync
> in
> > > from
> > > > >>> upstream.
> > > > >>
> > > > >> Ehrm, I don't know, really. The DTS files for socfpga already have
> > > > >> many U-Boot specifics and are quite different to Linux. It might
> make
> > > > >> sense to sync them, but do we really have to do this for 2018.09?
> > > > >>
> > > > >> Keep in mind that this series exists to fix that 2018.07 broke on
> > > these boards.
> > > > >
> > > > > Well, I think given that you're adding these changes right now,
> they
> > > > > should be added to the correct file so that they aren't lost on
> re-sync
> > > > > later.  It would be adding:
> > > > > &uart0 {
> > > > >        u-boot,dm-pre-reloc;
> > > > > };
> > > > >
> > > > > once to arch/arm/dts/socfpga-u-boot.dtsi rather than for every
> board.
> > > >
> > > > Pulling the U-Boot specific crap would be most welcome, but it could
> be
> > > > a separate patch.
> > >
> > > So you want to add stuff now and pull it out later?  That seems counter
> > > intuitive, but sure, you're the custodian here.  When do you plan to do
> > > the clean-up, for v2018.11?
> > >
> >
> > Can we do this in one step with syncing up to the latest Linux device
> trees?
>
> I honestly don't understand the hesitation to not introduce more change
> than is required now.  But, I will defer.  I do want to know when people
> plan to fix this however, as that feels like a reasonable compromise to
> me.
>

It's holiday season here so I can't say I'll be available all the time
until the 2018.09 release. That's why I don't want to do changes I can't
thoroughly test right now.

I might try the sync in September. It should not be too much work, but I
can only test one of the boards (the SoCrates).

Simom

[U-Boot] [PATCH v3 3/8] arm: socfpga: spl_gen5: clean up malloc_base assignment

[Simon Goldschmidt]

From: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>

In spl_gen5's board_init_f(), gd->malloc_base is manually assigned
at the end of the function to point to sdram.  This code is outdated
as by now, the heap is switched to sdram by the common function
spl_relocate_stack_gd() if the appropriate defines are set.

As it was, the value assigned manually was directly overwritten by
this common code, so remove the manual assignment.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v3: None
Changes in v2:
- this patch is new in v2 of the series (extracted from PATCH v1 1/6)

 arch/arm/mach-socfpga/spl_gen5.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 9bdfaa3c1e..0d5526656d 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -184,7 +184,4 @@ void board_init_f(ulong dummy)
 	}
 
 	socfpga_bridges_reset(1);
-
-	/* Configure simple malloc base pointer into RAM. */
-	gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
 }
-- 
2.17.1

[U-Boot] [PATCH v3 4/8] arm: socfpga: cyclone5: handle debug uart

[Simon Goldschmidt]

If CONFIG_DEBUG_UART is enabled, correctly initialize
the debug uart before console is initialized to debug
early boot problems in SPL.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v3: None
Changes in v2:
- don't change printf() to debug() in reset_manager_gen5.c
  socfpga_bridges_reset()

 arch/arm/mach-socfpga/spl_gen5.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 0d5526656d..0e685f6ee5 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -20,6 +20,7 @@
 #include <asm/arch/scu.h>
 #include <asm/arch/nic301.h>
 #include <asm/sections.h>
+#include <debug_uart.h>
 #include <fdtdec.h>
 #include <watchdog.h>
 
@@ -153,6 +154,11 @@ void board_init_f(ulong dummy)
 	/* unfreeze / thaw all IO banks */
 	sys_mgr_frzctrl_thaw_req();
 
+#ifdef CONFIG_DEBUG_UART
+	socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
+	debug_uart_init();
+#endif
+
 	ret = spl_early_init();
 	if (ret) {
 		debug("spl_early_init() failed: %d\n", ret);
-- 
2.17.1

[U-Boot] [PATCH v3 5/8] arm: socfpga: fix U-Boot running from fpga OnChip RAM

[Simon Goldschmidt]

gd->env_addr points to pre-relocation address even after
relocation. This leads to an abort in env_callback_init
when loading the environment.

Fix this by enabling CONFIG_SYS_EXTRA_ENV_RELOC.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v3: this patch is new in v3
Changes in v2: None

 include/configs/socfpga_common.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 8ebf6b85fe..2fb207c86a 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -284,6 +284,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SPL_STACK		CONFIG_SYS_SPL_MALLOC_START
 #endif
 
+#ifdef CONFIG_TARGET_SOCFPGA_GEN5
+/* When U-Boot is started from FPGA, prevent gd->env_addr to point into
+ * FPGA OnChip RAM after relocation
+ */
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
 /* Extra Environment */
 #ifndef CONFIG_SPL_BUILD
 
-- 
2.17.1

[U-Boot] [PATCH v3 5/8] arm: socfpga: fix U-Boot running from fpga OnChip RAM

[Marek Vasut]

On 08/13/2018 09:33 AM, Simon Goldschmidt wrote:
> gd->env_addr points to pre-relocation address even after
> relocation. This leads to an abort in env_callback_init
> when loading the environment.
> 
> Fix this by enabling CONFIG_SYS_EXTRA_ENV_RELOC.

Doesn't this apply to gen10 too ?

> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> ---
> 
> Changes in v3: this patch is new in v3
> Changes in v2: None
> 
>  include/configs/socfpga_common.h | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
> index 8ebf6b85fe..2fb207c86a 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -284,6 +284,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>  #define CONFIG_SPL_STACK		CONFIG_SYS_SPL_MALLOC_START
>  #endif
>  
> +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
> +/* When U-Boot is started from FPGA, prevent gd->env_addr to point into
> + * FPGA OnChip RAM after relocation
> + */
> +#define CONFIG_SYS_EXTRA_ENV_RELOC
> +#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
> +#endif
> +
>  /* Extra Environment */
>  #ifndef CONFIG_SPL_BUILD
>  
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v3 5/8] arm: socfpga: fix U-Boot running from fpga OnChip RAM

[Simon Goldschmidt]

Marek Vasut <marex@denx.de> schrieb am Mo., 13. Aug. 2018, 15:29:

> On 08/13/2018 09:33 AM, Simon Goldschmidt wrote:
> > gd->env_addr points to pre-relocation address even after
> > relocation. This leads to an abort in env_callback_init
> > when loading the environment.
> >
> > Fix this by enabling CONFIG_SYS_EXTRA_ENV_RELOC.
>
> Doesn't this apply to gen10 too ?
>

Ehrm, I really don't know. As I don't know gen10, I didn't want to break it.

I could try to check the sources, but without knowing the architecture
details and having a board to test, I might break things...


> > Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> > ---
> >
> > Changes in v3: this patch is new in v3
> > Changes in v2: None
> >
> >  include/configs/socfpga_common.h | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> >
> > diff --git a/include/configs/socfpga_common.h
> b/include/configs/socfpga_common.h
> > index 8ebf6b85fe..2fb207c86a 100644
> > --- a/include/configs/socfpga_common.h
> > +++ b/include/configs/socfpga_common.h
> > @@ -284,6 +284,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
> >  #define CONFIG_SPL_STACK             CONFIG_SYS_SPL_MALLOC_START
> >  #endif
> >
> > +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
> > +/* When U-Boot is started from FPGA, prevent gd->env_addr to point into
> > + * FPGA OnChip RAM after relocation
> > + */
> > +#define CONFIG_SYS_EXTRA_ENV_RELOC
> > +#define CONFIG_SYS_MONITOR_BASE      CONFIG_SYS_TEXT_BASE    /* start
> of monitor */
> > +#endif
> > +
> >  /* Extra Environment */
> >  #ifndef CONFIG_SPL_BUILD
> >
> >
>
>
> --
> Best regards,
> Marek Vasut
>

[U-Boot] [PATCH v3 5/8] arm: socfpga: fix U-Boot running from fpga OnChip RAM

[Marek Vasut]

On 08/13/2018 03:33 PM, Simon Goldschmidt wrote:
> 
> 
> Marek Vasut <marex at denx.de <mailto:marex@denx.de>> schrieb am Mo., 13.
> Aug. 2018, 15:29:
> 
>     On 08/13/2018 09:33 AM, Simon Goldschmidt wrote:
>     > gd->env_addr points to pre-relocation address even after
>     > relocation. This leads to an abort in env_callback_init
>     > when loading the environment.
>     >
>     > Fix this by enabling CONFIG_SYS_EXTRA_ENV_RELOC.
> 
>     Doesn't this apply to gen10 too ?
> 
> 
> Ehrm, I really don't know. As I don't know gen10, I didn't want to break it.
> 
> I could try to check the sources, but without knowing the architecture
> details and having a board to test, I might break things...

I'll probably be able to intercept that breakage, so just send a V4 with
that ifdef removed.

>     > Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com
>     <mailto:simon.k.r.goldschmidt@gmail.com>>
>     > ---
>     >
>     > Changes in v3: this patch is new in v3
>     > Changes in v2: None
>     >
>     >  include/configs/socfpga_common.h | 8 ++++++++
>     >  1 file changed, 8 insertions(+)
>     >
>     > diff --git a/include/configs/socfpga_common.h
>     b/include/configs/socfpga_common.h
>     > index 8ebf6b85fe..2fb207c86a 100644
>     > --- a/include/configs/socfpga_common.h
>     > +++ b/include/configs/socfpga_common.h
>     > @@ -284,6 +284,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>     >  #define CONFIG_SPL_STACK             CONFIG_SYS_SPL_MALLOC_START
>     >  #endif
>     > 
>     > +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
>     > +/* When U-Boot is started from FPGA, prevent gd->env_addr to
>     point into
>     > + * FPGA OnChip RAM after relocation
>     > + */
>     > +#define CONFIG_SYS_EXTRA_ENV_RELOC
>     > +#define CONFIG_SYS_MONITOR_BASE      CONFIG_SYS_TEXT_BASE    /*
>     start of monitor */
>     > +#endif
>     > +
>     >  /* Extra Environment */
>     >  #ifndef CONFIG_SPL_BUILD
>     > 
>     >
> 
> 
>     -- 
>     Best regards,
>     Marek Vasut
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v3 6/8] arm: socfpga: gen5: combine some init code for SPL and U-Boot

[Simon Goldschmidt]

Some of the code for low level system initialization in SPL's
board_init_f() and U-Boot's arch_early_init_r() is the same,
so let's combine it into a single function called from both.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v3: this patch is new in v3
Changes in v2: None

 arch/arm/mach-socfpga/include/mach/misc.h |  4 +++
 arch/arm/mach-socfpga/misc_gen5.c         | 33 +++++++++++++----------
 arch/arm/mach-socfpga/spl_gen5.c          | 30 +--------------------
 3 files changed, 24 insertions(+), 43 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
index 7fe77ac8d8..aa7f38d4ea 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -27,6 +27,10 @@ unsigned int shared_uart_com_port(const void *blob);
 unsigned int uart_com_port(const void *blob);
 #endif
 
+#ifdef CONFIG_TARGET_SOCFPGA_GEN5
+void socfpga_init_bus_mapping(void);
+#endif
+
 void do_bridge_reset(int enable);
 
 #endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 848551c73f..32af1a9084 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -175,6 +175,24 @@ static void socfpga_nic301_slave_ns(void)
 	writel(0x1, &nic301_regs->sdrdata);
 }
 
+void socfpga_init_bus_mapping(void)
+{
+	socfpga_bridges_reset(1);
+
+	socfpga_nic301_slave_ns();
+
+	/*
+	 * Private components security:
+	 * U-Boot : configure private timer, global timer and cpu component
+	 * access as non secure for kernel stage (as required by Linux)
+	 */
+	setbits_le32(&scu_regs->sacr, 0xfff);
+
+	/* Configure the L2 controller to make SDRAM start at 0 */
+	writel(0x1, &nic301_regs->remap);	/* remap.mpuzero */
+	writel(0x1, &pl310->pl310_addr_filter_start);
+}
+
 static u32 iswgrp_handoff[8];
 
 int arch_early_init_r(void)
@@ -193,20 +211,7 @@ int arch_early_init_r(void)
 	for (i = 0; i < 8; i++)	/* Cache initial SW setting regs */
 		iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
 
-	socfpga_bridges_reset(1);
-
-	socfpga_nic301_slave_ns();
-
-	/*
-	 * Private components security:
-	 * U-Boot : configure private timer, global timer and cpu component
-	 * access as non secure for kernel stage (as required by Linux)
-	 */
-	setbits_le32(&scu_regs->sacr, 0xfff);
-
-	/* Configure the L2 controller to make SDRAM start at 0 */
-	writel(0x1, &nic301_regs->remap);	/* remap.mpuzero */
-	writel(0x1, &pl310->pl310_addr_filter_start);
+	socfpga_init_bus_mapping();
 
 	/* Add device descriptor to FPGA device table */
 	socfpga_fpga_add();
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 0e685f6ee5..631905fbee 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -5,7 +5,6 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/pl310.h>
 #include <asm/u-boot.h>
 #include <asm/utils.h>
 #include <image.h>
@@ -17,8 +16,6 @@
 #include <asm/arch/misc.h>
 #include <asm/arch/scan_manager.h>
 #include <asm/arch/sdram.h>
-#include <asm/arch/scu.h>
-#include <asm/arch/nic301.h>
 #include <asm/sections.h>
 #include <debug_uart.h>
 #include <fdtdec.h>
@@ -26,12 +23,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct pl310_regs *const pl310 =
-	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-static struct scu_registers *scu_regs =
-	(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
-static struct nic301_registers *nic301_regs =
-	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
 static const struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
@@ -72,16 +63,6 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
-static void socfpga_nic301_slave_ns(void)
-{
-	writel(0x1, &nic301_regs->lwhps2fpgaregs);
-	writel(0x1, &nic301_regs->hps2fpgaregs);
-	writel(0x1, &nic301_regs->acp);
-	writel(0x1, &nic301_regs->rom);
-	writel(0x1, &nic301_regs->ocram);
-	writel(0x1, &nic301_regs->sdrdata);
-}
-
 void board_init_f(ulong dummy)
 {
 	const struct cm_config *cm_default_cfg = cm_get_default_config();
@@ -103,14 +84,7 @@ void board_init_f(ulong dummy)
 
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
-	socfpga_nic301_slave_ns();
-
-	/* Configure ARM MPU SNSAC register. */
-	setbits_le32(&scu_regs->sacr, 0xfff);
-
-	/* Remap SDRAM to 0x0 */
-	writel(0x1, &nic301_regs->remap);	/* remap.mpuzero */
-	writel(0x1, &pl310->pl310_addr_filter_start);
+	socfpga_init_bus_mapping();
 
 	debug("Freezing all I/O banks\n");
 	/* freeze all IO banks */
@@ -118,8 +92,6 @@ void board_init_f(ulong dummy)
 
 	/* Put everything into reset but L4WD0. */
 	socfpga_per_reset_all();
-	/* Put FPGA bridges into reset too. */
-	socfpga_bridges_reset(1);
 
 	socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
 	socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
-- 
2.17.1

[U-Boot] [PATCH v3 6/8] arm: socfpga: gen5: combine some init code for SPL and U-Boot

[Marek Vasut]

On 08/13/2018 09:33 AM, Simon Goldschmidt wrote:
> Some of the code for low level system initialization in SPL's
> board_init_f() and U-Boot's arch_early_init_r() is the same,
> so let's combine it into a single function called from both.
> 
> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> ---
> 
> Changes in v3: this patch is new in v3
> Changes in v2: None
> 
>  arch/arm/mach-socfpga/include/mach/misc.h |  4 +++
>  arch/arm/mach-socfpga/misc_gen5.c         | 33 +++++++++++++----------
>  arch/arm/mach-socfpga/spl_gen5.c          | 30 +--------------------
>  3 files changed, 24 insertions(+), 43 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
> index 7fe77ac8d8..aa7f38d4ea 100644
> --- a/arch/arm/mach-socfpga/include/mach/misc.h
> +++ b/arch/arm/mach-socfpga/include/mach/misc.h
> @@ -27,6 +27,10 @@ unsigned int shared_uart_com_port(const void *blob);
>  unsigned int uart_com_port(const void *blob);
>  #endif
>  
> +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
> +void socfpga_init_bus_mapping(void);
> +#endif
> +
>  void do_bridge_reset(int enable);
>  
>  #endif /* _MISC_H_ */
> diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
> index 848551c73f..32af1a9084 100644
> --- a/arch/arm/mach-socfpga/misc_gen5.c
> +++ b/arch/arm/mach-socfpga/misc_gen5.c
> @@ -175,6 +175,24 @@ static void socfpga_nic301_slave_ns(void)
>  	writel(0x1, &nic301_regs->sdrdata);
>  }
>  
> +void socfpga_init_bus_mapping(void)

Should be called something like socfpga_something_remap_something(),
since it configures the mapping of the first 1 MiB of RAM . otherwise OK

> +{
> +	socfpga_bridges_reset(1);

Drop this from the function, this has nothing to do with the remap settings.

> +	socfpga_nic301_slave_ns();
> +
> +	/*
> +	 * Private components security:
> +	 * U-Boot : configure private timer, global timer and cpu component
> +	 * access as non secure for kernel stage (as required by Linux)
> +	 */
> +	setbits_le32(&scu_regs->sacr, 0xfff);
> +
> +	/* Configure the L2 controller to make SDRAM start at 0 */
> +	writel(0x1, &nic301_regs->remap);	/* remap.mpuzero */
> +	writel(0x1, &pl310->pl310_addr_filter_start);
> +}
> +
>  static u32 iswgrp_handoff[8];
>  
>  int arch_early_init_r(void)
> @@ -193,20 +211,7 @@ int arch_early_init_r(void)
>  	for (i = 0; i < 8; i++)	/* Cache initial SW setting regs */
>  		iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
>  
> -	socfpga_bridges_reset(1);
> -
> -	socfpga_nic301_slave_ns();
> -
> -	/*
> -	 * Private components security:
> -	 * U-Boot : configure private timer, global timer and cpu component
> -	 * access as non secure for kernel stage (as required by Linux)
> -	 */
> -	setbits_le32(&scu_regs->sacr, 0xfff);
> -
> -	/* Configure the L2 controller to make SDRAM start at 0 */
> -	writel(0x1, &nic301_regs->remap);	/* remap.mpuzero */
> -	writel(0x1, &pl310->pl310_addr_filter_start);
> +	socfpga_init_bus_mapping();
>  
>  	/* Add device descriptor to FPGA device table */
>  	socfpga_fpga_add();
> diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
> index 0e685f6ee5..631905fbee 100644
> --- a/arch/arm/mach-socfpga/spl_gen5.c
> +++ b/arch/arm/mach-socfpga/spl_gen5.c
> @@ -5,7 +5,6 @@
>  
>  #include <common.h>
>  #include <asm/io.h>
> -#include <asm/pl310.h>
>  #include <asm/u-boot.h>
>  #include <asm/utils.h>
>  #include <image.h>
> @@ -17,8 +16,6 @@
>  #include <asm/arch/misc.h>
>  #include <asm/arch/scan_manager.h>
>  #include <asm/arch/sdram.h>
> -#include <asm/arch/scu.h>
> -#include <asm/arch/nic301.h>
>  #include <asm/sections.h>
>  #include <debug_uart.h>
>  #include <fdtdec.h>
> @@ -26,12 +23,6 @@
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> -static struct pl310_regs *const pl310 =
> -	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> -static struct scu_registers *scu_regs =
> -	(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
> -static struct nic301_registers *nic301_regs =
> -	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
>  static const struct socfpga_system_manager *sysmgr_regs =
>  	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>  
> @@ -72,16 +63,6 @@ u32 spl_boot_mode(const u32 boot_device)
>  }
>  #endif
>  
> -static void socfpga_nic301_slave_ns(void)
> -{
> -	writel(0x1, &nic301_regs->lwhps2fpgaregs);
> -	writel(0x1, &nic301_regs->hps2fpgaregs);
> -	writel(0x1, &nic301_regs->acp);
> -	writel(0x1, &nic301_regs->rom);
> -	writel(0x1, &nic301_regs->ocram);
> -	writel(0x1, &nic301_regs->sdrdata);
> -}
> -
>  void board_init_f(ulong dummy)
>  {
>  	const struct cm_config *cm_default_cfg = cm_get_default_config();
> @@ -103,14 +84,7 @@ void board_init_f(ulong dummy)
>  
>  	memset(__bss_start, 0, __bss_end - __bss_start);
>  
> -	socfpga_nic301_slave_ns();
> -
> -	/* Configure ARM MPU SNSAC register. */
> -	setbits_le32(&scu_regs->sacr, 0xfff);
> -
> -	/* Remap SDRAM to 0x0 */
> -	writel(0x1, &nic301_regs->remap);	/* remap.mpuzero */
> -	writel(0x1, &pl310->pl310_addr_filter_start);
> +	socfpga_init_bus_mapping();
>  
>  	debug("Freezing all I/O banks\n");
>  	/* freeze all IO banks */
> @@ -118,8 +92,6 @@ void board_init_f(ulong dummy)
>  
>  	/* Put everything into reset but L4WD0. */
>  	socfpga_per_reset_all();
> -	/* Put FPGA bridges into reset too. */
> -	socfpga_bridges_reset(1);
>  
>  	socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
>  	socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v3 7/8] arm: socfpga: fix SPL booting from fpga OnChip RAM

[Simon Goldschmidt]

To boot from fpga OnChip RAM, some changes are required in SPL
to ensure the code is linked to the correct address (in contrast
to QSPI and MMC boot, FPGA boot executes SPL in place instead of
copying it to SRAM) and that fpga OnChip RAM stays accessible while
SPL runs (don't disable fpga bridges).

This adds a new config option (CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA)
for socfpga gen5 boards.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v3: this patch is new in v3
Changes in v2: None

 arch/arm/mach-socfpga/Kconfig     | 12 ++++++++++++
 arch/arm/mach-socfpga/misc_gen5.c | 11 +++++++++--
 arch/arm/mach-socfpga/spl_gen5.c  |  3 ++-
 include/configs/socfpga_common.h  |  5 +++++
 4 files changed, 28 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 5c1df2cf1f..a909395aac 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -132,3 +132,15 @@ config SYS_CONFIG_NAME
 	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 endif
+
+if TARGET_SOCFPGA_GEN5
+
+config SPL_SOCFPGA_BOOT_FROM_FPGA
+	bool "Allow booting SPL from FPGA OnChip RAM"
+	default n
+	help
+	  Boot from FPGA: this changes the linker address for SPL code to run
+	  from FPGA OnChip memory instead of SRAM and ensures FPGA OnChip RAM
+	  stays accessible while SPL runs.
+
+endif
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 32af1a9084..00df16d0b1 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -177,7 +177,8 @@ static void socfpga_nic301_slave_ns(void)
 
 void socfpga_init_bus_mapping(void)
 {
-	socfpga_bridges_reset(1);
+	if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
+		socfpga_bridges_reset(1);
 
 	socfpga_nic301_slave_ns();
 
@@ -189,7 +190,13 @@ void socfpga_init_bus_mapping(void)
 	setbits_le32(&scu_regs->sacr, 0xfff);
 
 	/* Configure the L2 controller to make SDRAM start at 0 */
-	writel(0x1, &nic301_regs->remap);	/* remap.mpuzero */
+	if (CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) {
+		/* remap.mpuzero, keep fpga bridge enabled */
+		writel(0x9, &nic301_regs->remap);
+	} else {
+		/* remap.mpuzero */
+		writel(0x1, &nic301_regs->remap);
+	}
 	writel(0x1, &pl310->pl310_addr_filter_start);
 }
 
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 631905fbee..1a16c46915 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -161,5 +161,6 @@ void board_init_f(ulong dummy)
 		hang();
 	}
 
-	socfpga_bridges_reset(1);
+	if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
+		socfpga_bridges_reset(1);
 }
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 2fb207c86a..3cdde0f926 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -239,7 +239,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  * 0xFFEz_zzzz ...... Malloc area (grows up to top)
  * 0xFFE3_FFFF ...... End of SRAM (top)
  */
+#if CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA
+/* SPL executed from FPGA */
+#define CONFIG_SPL_TEXT_BASE		0xC0000000
+#else
 #define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_ADDR
+#endif
 #define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM_SIZE
 
 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-- 
2.17.1

[U-Boot] [PATCH v3 7/8] arm: socfpga: fix SPL booting from fpga OnChip RAM

[Marek Vasut]

On 08/13/2018 09:33 AM, Simon Goldschmidt wrote:
> To boot from fpga OnChip RAM, some changes are required in SPL
> to ensure the code is linked to the correct address (in contrast
> to QSPI and MMC boot, FPGA boot executes SPL in place instead of
> copying it to SRAM) and that fpga OnChip RAM stays accessible while
> SPL runs (don't disable fpga bridges).
> 
> This adds a new config option (CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA)
> for socfpga gen5 boards.
> 
> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

I wonder if you can somehow detect that you're booting from FPGA , using
BSEL readout maybe, but then I guess you have a problem with the link
address ... hrm.

> ---
> 
> Changes in v3: this patch is new in v3
> Changes in v2: None
> 
>  arch/arm/mach-socfpga/Kconfig     | 12 ++++++++++++
>  arch/arm/mach-socfpga/misc_gen5.c | 11 +++++++++--
>  arch/arm/mach-socfpga/spl_gen5.c  |  3 ++-
>  include/configs/socfpga_common.h  |  5 +++++
>  4 files changed, 28 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
> index 5c1df2cf1f..a909395aac 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -132,3 +132,15 @@ config SYS_CONFIG_NAME
>  	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
>  
>  endif
> +
> +if TARGET_SOCFPGA_GEN5
> +
> +config SPL_SOCFPGA_BOOT_FROM_FPGA
> +	bool "Allow booting SPL from FPGA OnChip RAM"

If you converted SPL_TEXT_BASE to Kconfig , then selecting this could
flip it to correct value. Can you do that ?

> +	default n
> +	help
> +	  Boot from FPGA: this changes the linker address for SPL code to run
> +	  from FPGA OnChip memory instead of SRAM and ensures FPGA OnChip RAM
> +	  stays accessible while SPL runs.
> +
> +endif
> diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
> index 32af1a9084..00df16d0b1 100644
> --- a/arch/arm/mach-socfpga/misc_gen5.c
> +++ b/arch/arm/mach-socfpga/misc_gen5.c
> @@ -177,7 +177,8 @@ static void socfpga_nic301_slave_ns(void)
>  
>  void socfpga_init_bus_mapping(void)
>  {
> -	socfpga_bridges_reset(1);
> +	if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
> +		socfpga_bridges_reset(1);
>  
>  	socfpga_nic301_slave_ns();
>  
> @@ -189,7 +190,13 @@ void socfpga_init_bus_mapping(void)
>  	setbits_le32(&scu_regs->sacr, 0xfff);
>  
>  	/* Configure the L2 controller to make SDRAM start at 0 */
> -	writel(0x1, &nic301_regs->remap);	/* remap.mpuzero */
> +	if (CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) {
> +		/* remap.mpuzero, keep fpga bridge enabled */
> +		writel(0x9, &nic301_regs->remap);
> +	} else {
> +		/* remap.mpuzero */
> +		writel(0x1, &nic301_regs->remap);
> +	}
>  	writel(0x1, &pl310->pl310_addr_filter_start);
>  }
>  
> diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
> index 631905fbee..1a16c46915 100644
> --- a/arch/arm/mach-socfpga/spl_gen5.c
> +++ b/arch/arm/mach-socfpga/spl_gen5.c
> @@ -161,5 +161,6 @@ void board_init_f(ulong dummy)
>  		hang();
>  	}
>  
> -	socfpga_bridges_reset(1);
> +	if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
> +		socfpga_bridges_reset(1);
>  }
> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
> index 2fb207c86a..3cdde0f926 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -239,7 +239,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>   * 0xFFEz_zzzz ...... Malloc area (grows up to top)
>   * 0xFFE3_FFFF ...... End of SRAM (top)
>   */
> +#if CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA
> +/* SPL executed from FPGA */
> +#define CONFIG_SPL_TEXT_BASE		0xC0000000
> +#else
>  #define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_ADDR
> +#endif
>  #define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM_SIZE
>  
>  #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v3 7/8] arm: socfpga: fix SPL booting from fpga OnChip RAM

[Simon Goldschmidt]

Marek Vasut <marex@denx.de> schrieb am Mo., 13. Aug. 2018, 15:29:

> On 08/13/2018 09:33 AM, Simon Goldschmidt wrote:
> > To boot from fpga OnChip RAM, some changes are required in SPL
> > to ensure the code is linked to the correct address (in contrast
> > to QSPI and MMC boot, FPGA boot executes SPL in place instead of
> > copying it to SRAM) and that fpga OnChip RAM stays accessible while
> > SPL runs (don't disable fpga bridges).
> >
> > This adds a new config option (CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA)
> > for socfpga gen5 boards.
> >
> > Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
>
> I wonder if you can somehow detect that you're booting from FPGA , using
> BSEL readout maybe, but then I guess you have a problem with the link
> address ... hrm.
>

I was trying that, but we need to fix the linker address anyway, so...


> > ---
> >
> > Changes in v3: this patch is new in v3
> > Changes in v2: None
> >
> >  arch/arm/mach-socfpga/Kconfig     | 12 ++++++++++++
> >  arch/arm/mach-socfpga/misc_gen5.c | 11 +++++++++--
> >  arch/arm/mach-socfpga/spl_gen5.c  |  3 ++-
> >  include/configs/socfpga_common.h  |  5 +++++
> >  4 files changed, 28 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/mach-socfpga/Kconfig
> b/arch/arm/mach-socfpga/Kconfig
> > index 5c1df2cf1f..a909395aac 100644
> > --- a/arch/arm/mach-socfpga/Kconfig
> > +++ b/arch/arm/mach-socfpga/Kconfig
> > @@ -132,3 +132,15 @@ config SYS_CONFIG_NAME
> >       default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
> >
> >  endif
> > +
> > +if TARGET_SOCFPGA_GEN5
> > +
> > +config SPL_SOCFPGA_BOOT_FROM_FPGA
> > +     bool "Allow booting SPL from FPGA OnChip RAM"
>
> If you converted SPL_TEXT_BASE to Kconfig , then selecting this could
> flip it to correct value. Can you do that ?
>

Sure, I'll try that.


> > +     default n
> > +     help
> > +       Boot from FPGA: this changes the linker address for SPL code to
> run
> > +       from FPGA OnChip memory instead of SRAM and ensures FPGA OnChip
> RAM
> > +       stays accessible while SPL runs.
> > +
> > +endif
> > diff --git a/arch/arm/mach-socfpga/misc_gen5.c
> b/arch/arm/mach-socfpga/misc_gen5.c
> > index 32af1a9084..00df16d0b1 100644
> > --- a/arch/arm/mach-socfpga/misc_gen5.c
> > +++ b/arch/arm/mach-socfpga/misc_gen5.c
> > @@ -177,7 +177,8 @@ static void socfpga_nic301_slave_ns(void)
> >
> >  void socfpga_init_bus_mapping(void)
> >  {
> > -     socfpga_bridges_reset(1);
> > +     if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
> > +             socfpga_bridges_reset(1);
> >
> >       socfpga_nic301_slave_ns();
> >
> > @@ -189,7 +190,13 @@ void socfpga_init_bus_mapping(void)
> >       setbits_le32(&scu_regs->sacr, 0xfff);
> >
> >       /* Configure the L2 controller to make SDRAM start at 0 */
> > -     writel(0x1, &nic301_regs->remap);       /* remap.mpuzero */
> > +     if (CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) {
> > +             /* remap.mpuzero, keep fpga bridge enabled */
> > +             writel(0x9, &nic301_regs->remap);
> > +     } else {
> > +             /* remap.mpuzero */
> > +             writel(0x1, &nic301_regs->remap);
> > +     }
> >       writel(0x1, &pl310->pl310_addr_filter_start);
> >  }
> >
> > diff --git a/arch/arm/mach-socfpga/spl_gen5.c
> b/arch/arm/mach-socfpga/spl_gen5.c
> > index 631905fbee..1a16c46915 100644
> > --- a/arch/arm/mach-socfpga/spl_gen5.c
> > +++ b/arch/arm/mach-socfpga/spl_gen5.c
> > @@ -161,5 +161,6 @@ void board_init_f(ulong dummy)
> >               hang();
> >       }
> >
> > -     socfpga_bridges_reset(1);
> > +     if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
> > +             socfpga_bridges_reset(1);
> >  }
> > diff --git a/include/configs/socfpga_common.h
> b/include/configs/socfpga_common.h
> > index 2fb207c86a..3cdde0f926 100644
> > --- a/include/configs/socfpga_common.h
> > +++ b/include/configs/socfpga_common.h
> > @@ -239,7 +239,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
> >   * 0xFFEz_zzzz ...... Malloc area (grows up to top)
> >   * 0xFFE3_FFFF ...... End of SRAM (top)
> >   */
> > +#if CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA
> > +/* SPL executed from FPGA */
> > +#define CONFIG_SPL_TEXT_BASE         0xC0000000
> > +#else
> >  #define CONFIG_SPL_TEXT_BASE         CONFIG_SYS_INIT_RAM_ADDR
> > +#endif
> >  #define CONFIG_SPL_MAX_SIZE          CONFIG_SYS_INIT_RAM_SIZE
> >
> >  #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> >
>
>
> --
> Best regards,
> Marek Vasut
>

[U-Boot] [PATCH v3 7/8] arm: socfpga: fix SPL booting from fpga OnChip RAM

[Marek Vasut]

On 08/13/2018 03:32 PM, Simon Goldschmidt wrote:
> 
> 
> Marek Vasut <marex at denx.de <mailto:marex@denx.de>> schrieb am Mo., 13.
> Aug. 2018, 15:29:
> 
>     On 08/13/2018 09:33 AM, Simon Goldschmidt wrote:
>     > To boot from fpga OnChip RAM, some changes are required in SPL
>     > to ensure the code is linked to the correct address (in contrast
>     > to QSPI and MMC boot, FPGA boot executes SPL in place instead of
>     > copying it to SRAM) and that fpga OnChip RAM stays accessible while
>     > SPL runs (don't disable fpga bridges).
>     >
>     > This adds a new config option (CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA)
>     > for socfpga gen5 boards.
>     >
>     > Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com
>     <mailto:simon.k.r.goldschmidt@gmail.com>>
> 
>     I wonder if you can somehow detect that you're booting from FPGA , using
>     BSEL readout maybe, but then I guess you have a problem with the link
>     address ... hrm.
> 
> 
> I was trying that, but we need to fix the linker address anyway, so...

Right

>     > ---
>     >
>     > Changes in v3: this patch is new in v3
>     > Changes in v2: None
>     >
>     >  arch/arm/mach-socfpga/Kconfig     | 12 ++++++++++++
>     >  arch/arm/mach-socfpga/misc_gen5.c | 11 +++++++++--
>     >  arch/arm/mach-socfpga/spl_gen5.c  |  3 ++-
>     >  include/configs/socfpga_common.h  |  5 +++++
>     >  4 files changed, 28 insertions(+), 3 deletions(-)
>     >
>     > diff --git a/arch/arm/mach-socfpga/Kconfig
>     b/arch/arm/mach-socfpga/Kconfig
>     > index 5c1df2cf1f..a909395aac 100644
>     > --- a/arch/arm/mach-socfpga/Kconfig
>     > +++ b/arch/arm/mach-socfpga/Kconfig
>     > @@ -132,3 +132,15 @@ config SYS_CONFIG_NAME
>     >       default "socfpga_vining_fpga" if
>     TARGET_SOCFPGA_SAMTEC_VINING_FPGA
>     > 
>     >  endif
>     > +
>     > +if TARGET_SOCFPGA_GEN5
>     > +
>     > +config SPL_SOCFPGA_BOOT_FROM_FPGA
>     > +     bool "Allow booting SPL from FPGA OnChip RAM"
> 
>     If you converted SPL_TEXT_BASE to Kconfig , then selecting this could
>     flip it to correct value. Can you do that ?
> 
> 
> Sure, I'll try that.

Look at tools/moveconfig.py

>     > +     default n
>     > +     help
>     > +       Boot from FPGA: this changes the linker address for SPL
>     code to run
>     > +       from FPGA OnChip memory instead of SRAM and ensures FPGA
>     OnChip RAM
>     > +       stays accessible while SPL runs.
>     > +
>     > +endif
>     > diff --git a/arch/arm/mach-socfpga/misc_gen5.c
>     b/arch/arm/mach-socfpga/misc_gen5.c
>     > index 32af1a9084..00df16d0b1 100644
>     > --- a/arch/arm/mach-socfpga/misc_gen5.c
>     > +++ b/arch/arm/mach-socfpga/misc_gen5.c
>     > @@ -177,7 +177,8 @@ static void socfpga_nic301_slave_ns(void)
>     > 
>     >  void socfpga_init_bus_mapping(void)
>     >  {
>     > -     socfpga_bridges_reset(1);
>     > +     if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
>     > +             socfpga_bridges_reset(1);
>     > 
>     >       socfpga_nic301_slave_ns();
>     > 
>     > @@ -189,7 +190,13 @@ void socfpga_init_bus_mapping(void)
>     >       setbits_le32(&scu_regs->sacr, 0xfff);
>     > 
>     >       /* Configure the L2 controller to make SDRAM start at 0 */
>     > -     writel(0x1, &nic301_regs->remap);       /* remap.mpuzero */
>     > +     if (CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) {
>     > +             /* remap.mpuzero, keep fpga bridge enabled */
>     > +             writel(0x9, &nic301_regs->remap);
>     > +     } else {
>     > +             /* remap.mpuzero */
>     > +             writel(0x1, &nic301_regs->remap);
>     > +     }
>     >       writel(0x1, &pl310->pl310_addr_filter_start);
>     >  }
>     > 
>     > diff --git a/arch/arm/mach-socfpga/spl_gen5.c
>     b/arch/arm/mach-socfpga/spl_gen5.c
>     > index 631905fbee..1a16c46915 100644
>     > --- a/arch/arm/mach-socfpga/spl_gen5.c
>     > +++ b/arch/arm/mach-socfpga/spl_gen5.c
>     > @@ -161,5 +161,6 @@ void board_init_f(ulong dummy)
>     >               hang();
>     >       }
>     > 
>     > -     socfpga_bridges_reset(1);
>     > +     if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
>     > +             socfpga_bridges_reset(1);
>     >  }
>     > diff --git a/include/configs/socfpga_common.h
>     b/include/configs/socfpga_common.h
>     > index 2fb207c86a..3cdde0f926 100644
>     > --- a/include/configs/socfpga_common.h
>     > +++ b/include/configs/socfpga_common.h
>     > @@ -239,7 +239,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>     >   * 0xFFEz_zzzz ...... Malloc area (grows up to top)
>     >   * 0xFFE3_FFFF ...... End of SRAM (top)
>     >   */
>     > +#if CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA
>     > +/* SPL executed from FPGA */
>     > +#define CONFIG_SPL_TEXT_BASE         0xC0000000
>     > +#else
>     >  #define CONFIG_SPL_TEXT_BASE         CONFIG_SYS_INIT_RAM_ADDR
>     > +#endif
>     >  #define CONFIG_SPL_MAX_SIZE          CONFIG_SYS_INIT_RAM_SIZE
>     > 
>     >  #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>     >
> 
> 
>     -- 
>     Best regards,
>     Marek Vasut
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v3 8/8] malloc_simple: calloc: don't call memset if malloc failed

[Simon Goldschmidt]

malloc_simple() can return 0 if out of memory. Don't call memset
from calloc() in this case but rely on the caller checking
the return value.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>

---

Changes in v3: None
Changes in v2: None

 common/malloc_simple.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/common/malloc_simple.c b/common/malloc_simple.c
index c14f8b59c1..871b5444bd 100644
--- a/common/malloc_simple.c
+++ b/common/malloc_simple.c
@@ -57,7 +57,8 @@ void *calloc(size_t nmemb, size_t elem_size)
 	void *ptr;
 
 	ptr = malloc(size);
-	memset(ptr, '\0', size);
+	if (ptr)
+		memset(ptr, '\0', size);
 
 	return ptr;
 }
-- 
2.17.1

[U-Boot] [PATCH v3 0/8] Get socfpga gen5 SPL working again.

[Marek Vasut]

On 08/13/2018 09:33 AM, Simon Goldschmidt wrote:
> Socfpga gen5 SPL has been broken since moving to DM serial with
> v2018.07. Also, U-Boot console output has been broken since then.
> This series fixes this and makes some related small improvements.
> 
> Changes in v3:
> - moved uart0's "u-boot,dm-pre-reloc;" from socfpga.dtsi to board
>   specific dts files since this can change per board
> - added patches 5-7 to boot SPL and U-Boot from fpga OnChip RAM
> - dropped Patch 5/6 "serial: ns16550: fix debug uart putc called before
>   init" (this needs a more generic fix)
> 
> Changes in v2:
> - Improved comment on patch 1
> - Removing gd->malloc_base assignment at the end of board_init_f()
>   moved to an extra patch
> - don't change printf() to debug() in reset_manager_gen5.c
>   socfpga_bridges_reset() (instead make debug uart handle this)
> - make ns16550 debug uart handle putc being called before init
> - removed the assignment of gd->malloc_limit from board_init()
> 
> Simon Goldschmidt (8):
>   arm: socfpga: fix SPL on gen5 after moving to DM serial
>   arm: socfpga: fix device trees to work with DM serial
>   arm: socfpga: spl_gen5: clean up malloc_base assignment
>   arm: socfpga: cyclone5: handle debug uart
>   arm: socfpga: fix U-Boot running from fpga OnChip RAM
>   arm: socfpga: gen5: combine some init code for SPL and U-Boot
>   arm: socfpga: fix SPL booting from fpga OnChip RAM
>   malloc_simple: calloc: don't call memset if malloc failed
> 
>  arch/arm/dts/socfpga_arria5_socdk.dts         |  5 ++
>  arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts    |  5 ++
>  .../arm/dts/socfpga_cyclone5_de0_nano_soc.dts |  5 ++
>  arch/arm/dts/socfpga_cyclone5_de10_nano.dts   |  5 ++
>  arch/arm/dts/socfpga_cyclone5_de1_soc.dts     |  5 ++
>  arch/arm/dts/socfpga_cyclone5_is1.dts         |  5 ++
>  arch/arm/dts/socfpga_cyclone5_socdk.dts       |  5 ++
>  arch/arm/dts/socfpga_cyclone5_sockit.dts      |  5 ++
>  arch/arm/dts/socfpga_cyclone5_socrates.dts    |  5 ++
>  arch/arm/dts/socfpga_cyclone5_sr1500.dts      |  2 +
>  arch/arm/dts/socfpga_cyclone5_vining_fpga.dts |  5 ++
>  arch/arm/mach-socfpga/Kconfig                 | 12 +++++
>  arch/arm/mach-socfpga/include/mach/misc.h     |  4 ++
>  arch/arm/mach-socfpga/misc_gen5.c             | 40 +++++++++------
>  arch/arm/mach-socfpga/spl_gen5.c              | 49 ++++++-------------
>  common/malloc_simple.c                        |  3 +-
>  include/configs/socfpga_common.h              | 13 +++++
>  17 files changed, 125 insertions(+), 48 deletions(-)
> 
I applied some of this to u-boot-socfpga/master , so you dont have to
repost those.

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v3 0/8] Get socfpga gen5 SPL working again.

[Simon Goldschmidt]

Marek Vasut <marex@denx.de> schrieb am Mo., 13. Aug. 2018, 15:29:

> On 08/13/2018 09:33 AM, Simon Goldschmidt wrote:
> > Socfpga gen5 SPL has been broken since moving to DM serial with
> > v2018.07. Also, U-Boot console output has been broken since then.
> > This series fixes this and makes some related small improvements.
> >
> > Changes in v3:
> > - moved uart0's "u-boot,dm-pre-reloc;" from socfpga.dtsi to board
> >   specific dts files since this can change per board
> > - added patches 5-7 to boot SPL and U-Boot from fpga OnChip RAM
> > - dropped Patch 5/6 "serial: ns16550: fix debug uart putc called before
> >   init" (this needs a more generic fix)
> >
> > Changes in v2:
> > - Improved comment on patch 1
> > - Removing gd->malloc_base assignment at the end of board_init_f()
> >   moved to an extra patch
> > - don't change printf() to debug() in reset_manager_gen5.c
> >   socfpga_bridges_reset() (instead make debug uart handle this)
> > - make ns16550 debug uart handle putc being called before init
> > - removed the assignment of gd->malloc_limit from board_init()
> >
> > Simon Goldschmidt (8):
> >   arm: socfpga: fix SPL on gen5 after moving to DM serial
> >   arm: socfpga: fix device trees to work with DM serial
> >   arm: socfpga: spl_gen5: clean up malloc_base assignment
> >   arm: socfpga: cyclone5: handle debug uart
> >   arm: socfpga: fix U-Boot running from fpga OnChip RAM
> >   arm: socfpga: gen5: combine some init code for SPL and U-Boot
> >   arm: socfpga: fix SPL booting from fpga OnChip RAM
> >   malloc_simple: calloc: don't call memset if malloc failed
> >
> >  arch/arm/dts/socfpga_arria5_socdk.dts         |  5 ++
> >  arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts    |  5 ++
> >  .../arm/dts/socfpga_cyclone5_de0_nano_soc.dts |  5 ++
> >  arch/arm/dts/socfpga_cyclone5_de10_nano.dts   |  5 ++
> >  arch/arm/dts/socfpga_cyclone5_de1_soc.dts     |  5 ++
> >  arch/arm/dts/socfpga_cyclone5_is1.dts         |  5 ++
> >  arch/arm/dts/socfpga_cyclone5_socdk.dts       |  5 ++
> >  arch/arm/dts/socfpga_cyclone5_sockit.dts      |  5 ++
> >  arch/arm/dts/socfpga_cyclone5_socrates.dts    |  5 ++
> >  arch/arm/dts/socfpga_cyclone5_sr1500.dts      |  2 +
> >  arch/arm/dts/socfpga_cyclone5_vining_fpga.dts |  5 ++
> >  arch/arm/mach-socfpga/Kconfig                 | 12 +++++
> >  arch/arm/mach-socfpga/include/mach/misc.h     |  4 ++
> >  arch/arm/mach-socfpga/misc_gen5.c             | 40 +++++++++------
> >  arch/arm/mach-socfpga/spl_gen5.c              | 49 ++++++-------------
> >  common/malloc_simple.c                        |  3 +-
> >  include/configs/socfpga_common.h              | 13 +++++
> >  17 files changed, 125 insertions(+), 48 deletions(-)
> >
> I applied some of this to u-boot-socfpga/master , so you dont have to
> repost those.
>

Ok, thanks!

Simon