[U-Boot] [PATCH] mtd: nand: denali: fix unaligned cache operation warnings on ARMv7 SoCs

[U-Boot] [PATCH] mtd: nand: denali: fix unaligned cache operation warnings on ARMv7 SoCs

[Masahiro Yamada]

If the OOB size is not multiple of the cache line size, the ARMv7
cache operation still warns "Misaligned operation at range".

The real cache coherency problem was fixed by commit e3332e1a1a04
("Make kmalloc'ed memory really DMA-safe").  Now it is the matter
of the warning messages.

=> nand info

Device 0: nand0, sector size 256 KiB
  Page size       4096 b
  OOB size         224 b
  Erase size    262144 b
  subpagesize     4096 b
  options     0x00104200
  bbt options 0x00060000
=> nand dump 0
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
  ...

Reported-by: Marek Vasut <marex@denx.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

 drivers/mtd/nand/denali.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index 7302c37..d1cac06 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -21,6 +21,8 @@ static dma_addr_t dma_map_single(void *dev, void *ptr, size_t size,
 {
 	unsigned long addr = (unsigned long)ptr;
 
+	size = ALIGN(size, ARCH_DMA_MINALIGN);
+
 	if (dir == DMA_FROM_DEVICE)
 		invalidate_dcache_range(addr, addr + size);
 	else
@@ -32,6 +34,8 @@ static dma_addr_t dma_map_single(void *dev, void *ptr, size_t size,
 static void dma_unmap_single(void *dev, dma_addr_t addr, size_t size,
 			     enum dma_data_direction dir)
 {
+	size = ALIGN(size, ARCH_DMA_MINALIGN);
+
 	if (dir != DMA_TO_DEVICE)
 		invalidate_dcache_range(addr, addr + size);
 }
-- 
2.7.4

[U-Boot] [PATCH] mtd: nand: denali: fix unaligned cache operation warnings on ARMv7 SoCs

[Marek Vasut]

On 09/10/2018 04:17 AM, Masahiro Yamada wrote:
> If the OOB size is not multiple of the cache line size, the ARMv7
> cache operation still warns "Misaligned operation at range".
> 
> The real cache coherency problem was fixed by commit e3332e1a1a04
> ("Make kmalloc'ed memory really DMA-safe").  Now it is the matter
> of the warning messages.

The cache ops won't happen if the address isn't aligned, so this is
needed on armv7a anyway. It's not just about silencing the messages,
this patch is actually required.

> => nand info
> 
> Device 0: nand0, sector size 256 KiB
>   Page size       4096 b
>   OOB size         224 b
>   Erase size    262144 b
>   subpagesize     4096 b
>   options     0x00104200
>   bbt options 0x00060000
> => nand dump 0
> CACHE: Misaligned operation at range [9fb15280, 9fb16360]
> CACHE: Misaligned operation at range [9fb15280, 9fb16360]
> CACHE: Misaligned operation at range [9fb15280, 9fb16360]
> CACHE: Misaligned operation at range [9fb15280, 9fb16360]
>   ...
> 
> Reported-by: Marek Vasut <marex@denx.de>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> ---
> 
>  drivers/mtd/nand/denali.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
> index 7302c37..d1cac06 100644
> --- a/drivers/mtd/nand/denali.c
> +++ b/drivers/mtd/nand/denali.c
> @@ -21,6 +21,8 @@ static dma_addr_t dma_map_single(void *dev, void *ptr, size_t size,
>  {
>  	unsigned long addr = (unsigned long)ptr;
>  
> +	size = ALIGN(size, ARCH_DMA_MINALIGN);
> +
>  	if (dir == DMA_FROM_DEVICE)
>  		invalidate_dcache_range(addr, addr + size);
>  	else
> @@ -32,6 +34,8 @@ static dma_addr_t dma_map_single(void *dev, void *ptr, size_t size,
>  static void dma_unmap_single(void *dev, dma_addr_t addr, size_t size,
>  			     enum dma_data_direction dir)
>  {
> +	size = ALIGN(size, ARCH_DMA_MINALIGN);
> +
>  	if (dir != DMA_TO_DEVICE)
>  		invalidate_dcache_range(addr, addr + size);
>  }
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH] mtd: nand: denali: fix unaligned cache operation warnings on ARMv7 SoCs

[Masahiro Yamada]

2018-09-10 22:26 GMT+09:00 Marek Vasut <marek.vasut@gmail.com>:
> On 09/10/2018 04:17 AM, Masahiro Yamada wrote:
>> If the OOB size is not multiple of the cache line size, the ARMv7
>> cache operation still warns "Misaligned operation at range".
>>
>> The real cache coherency problem was fixed by commit e3332e1a1a04
>> ("Make kmalloc'ed memory really DMA-safe").  Now it is the matter
>> of the warning messages.
>
> The cache ops won't happen if the address isn't aligned, so this is
> needed on armv7a anyway. It's not just about silencing the messages,
> this patch is actually required.


You are right.
I was misunderstanding.

I will reword the patch description.  Thanks!


-- 
Best Regards
Masahiro Yamada

[U-Boot] [PATCH] mtd: nand: denali: fix unaligned cache operation warnings on ARMv7 SoCs

[Tom Rini]

On Mon, Sep 10, 2018 at 11:17:30AM +0900, Masahiro Yamada wrote:

> If the OOB size is not multiple of the cache line size, the ARMv7
> cache operation still warns "Misaligned operation at range".
> 
> The real cache coherency problem was fixed by commit e3332e1a1a04
> ("Make kmalloc'ed memory really DMA-safe").  Now it is the matter
> of the warning messages.
> 
> => nand info
> 
> Device 0: nand0, sector size 256 KiB
>   Page size       4096 b
>   OOB size         224 b
>   Erase size    262144 b
>   subpagesize     4096 b
>   options     0x00104200
>   bbt options 0x00060000
> => nand dump 0
> CACHE: Misaligned operation at range [9fb15280, 9fb16360]
> CACHE: Misaligned operation at range [9fb15280, 9fb16360]
> CACHE: Misaligned operation at range [9fb15280, 9fb16360]
> CACHE: Misaligned operation at range [9fb15280, 9fb16360]
>   ...
> 
> Reported-by: Marek Vasut <marex@denx.de>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

After re-wording the commit message based on Marek's email, applied to
u-boot/master, thanks!

-- 
Tom
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