* [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support
@ 2018-05-28 12:24 Peng Fan
2018-05-28 12:24 ` [U-Boot] [PATCH 01/41] imx: import SCFW API Peng Fan
` (42 more replies)
0 siblings, 43 replies; 69+ messages in thread
From: Peng Fan @ 2018-05-28 12:24 UTC (permalink / raw)
To: u-boot
This patchset is to upstream i.MX8QXP and mek board support, with some
drivers update to support i.MX8QXP. The information about the processor
could be found
https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-8-processors/i.mx-8x-family-arm-cortex-a35-3d-graphics-4k-video-dsp-error-correcting-code-on-ddr:i.MX8X
The architecture of i.MX8QXP is different from i.MX6/7/8M, inside i.MX8QXP,
there is a dedicated processor(SCU) used for power/clock/pin/
pad/resource management/thermal and etc. The ACore need to communicate
with SCU using SCFW API. The SCFW API is exported by SCFW, so we directly
import it into U-Boot source code.
Gao Pan (1):
imx: lpi2c: fix clock issue when NACK detected
Peng Fan (32):
imx: import SCFW API
imx: add Kconfig entry for i.MX8
arm: build mach-imx for i.MX8
imx8: add IPC communication support between ACore and SCU
arm: global_data: introduce ipc_channel_handle
imx: boot_mode: Add FLEXSPI boot entry
imx8: add imx-regs header file
imx8: pins: include i.MX8QXP pin header when CONFIG_IMX8QXP defined
imx: add i.MX8 cpu type
imx8: add basic cpu support
imx8: add boot device detection
imx8: implement mmc_get_env_dev
imx8: implement imx_get_mac_from_fuse
imx8: implement get_board_serial
imx8: add mmu and dram related functiions
imx8: add bootaux support
imx8: add arch_cpu_init
imx8: add clock driver
imx8: add iomux configuration code
serial_lpuart: Update lpuart driver to support i.MX8
net: fec: do not access reserved register for i.MX8
gpio: mxc_gpio: add support for i.MX8
pinctrl: Add pinctrl driver for i.MX8
power: Add power domain driver for i.MX8
power: Add PD device lookup interface to power domain uclass
power-domain: add dummy functions when CONFIG_POWER_DOMAIN not defined
dm: core: device: enable power domain in probe
drivers: regulator: fixed: add off-on-delay-us
log: include command header file
i2c-mux: pca954x: support pca9646 i2c switch
dts: imx8qxp: Add DTS and binding header files
imx: 8qxp_mek: Add i.MX8QXP MEK board support
Ye Li (8):
fsl_esdhc: Update usdhc driver to support i.MX8
serial: lpuart: Enable RX and TX FIFO
imx_lpi2c: Update lpi2c driver to support imx8
lpi2c: Fix bus stop problem in xfer
lpi2c: Add bus busy error handling
net: fec_mxc: Add the init_clk_fec function
sata: Add i.MX8 SATA support
mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue
arch/arm/Kconfig | 8 +
arch/arm/Makefile | 2 +-
arch/arm/dts/Makefile | 2 +
arch/arm/dts/fsl-imx8qxp-mek.dts | 416 +++++
arch/arm/dts/fsl-imx8qxp.dtsi | 1593 ++++++++++++++++++++
arch/arm/include/asm/arch-imx/cpu.h | 5 +
arch/arm/include/asm/arch-imx8/clock.h | 36 +
arch/arm/include/asm/arch-imx8/cpu.h | 26 +
arch/arm/include/asm/arch-imx8/fsl_mu_hal.h | 54 +
arch/arm/include/asm/arch-imx8/gpio.h | 22 +
arch/arm/include/asm/arch-imx8/i2c.h | 34 +
arch/arm/include/asm/arch-imx8/imx-regs.h | 119 ++
arch/arm/include/asm/arch-imx8/imx8-pins.h | 15 +
arch/arm/include/asm/arch-imx8/imx8qm_pads.h | 295 ++++
arch/arm/include/asm/arch-imx8/imx8qxp_pads.h | 200 +++
arch/arm/include/asm/arch-imx8/iomux.h | 40 +
arch/arm/include/asm/arch-imx8/power-domain.h | 15 +
arch/arm/include/asm/arch-imx8/sci/ipc.h | 67 +
arch/arm/include/asm/arch-imx8/sci/rpc.h | 131 ++
arch/arm/include/asm/arch-imx8/sci/sci.h | 39 +
arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h | 160 ++
arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h | 523 +++++++
arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h | 568 +++++++
arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h | 686 +++++++++
arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h | 759 ++++++++++
arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h | 306 ++++
arch/arm/include/asm/arch-imx8/sci/types.h | 862 +++++++++++
arch/arm/include/asm/arch-imx8/sys_proto.h | 19 +
arch/arm/include/asm/global_data.h | 4 +
arch/arm/include/asm/mach-imx/boot_mode.h | 1 +
arch/arm/include/asm/mach-imx/sys_proto.h | 3 +
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/imx8/Kconfig | 26 +
arch/arm/mach-imx/imx8/Makefile | 13 +
arch/arm/mach-imx/imx8/clock.c | 361 +++++
arch/arm/mach-imx/imx8/cpu.c | 783 ++++++++++
arch/arm/mach-imx/imx8/fsl_mu_hal.c | 28 +
arch/arm/mach-imx/imx8/iomux.c | 47 +
arch/arm/mach-imx/imx8/sci/ipc.c | 100 ++
arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h | 54 +
arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c | 76 +
arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h | 76 +
arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c | 515 +++++++
arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h | 68 +
arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c | 475 ++++++
arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h | 73 +
arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c | 460 ++++++
arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h | 83 +
arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c | 645 ++++++++
arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h | 67 +
arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c | 365 +++++
board/freescale/imx8qxp_mek/Kconfig | 14 +
board/freescale/imx8qxp_mek/MAINTAINERS | 6 +
board/freescale/imx8qxp_mek/Makefile | 7 +
board/freescale/imx8qxp_mek/imx8qxp_mek.c | 159 ++
configs/imx8qxp_mek_defconfig | 47 +
drivers/ata/Kconfig | 6 +
drivers/ata/Makefile | 1 +
drivers/ata/ahci.c | 25 +
drivers/ata/sata_imx.c | 64 +
drivers/core/device.c | 7 +
drivers/gpio/mxc_gpio.c | 30 +-
drivers/i2c/imx_lpi2c.c | 82 +-
drivers/i2c/muxes/pca954x.c | 9 +-
drivers/mmc/fsl_esdhc.c | 32 +-
drivers/net/fec_mxc.c | 9 +-
drivers/pinctrl/nxp/Kconfig | 18 +
drivers/pinctrl/nxp/Makefile | 2 +
drivers/pinctrl/nxp/pinctrl-imx.c | 209 +--
drivers/pinctrl/nxp/pinctrl-imx.h | 16 +
drivers/pinctrl/nxp/pinctrl-imx8.c | 42 +
drivers/pinctrl/nxp/pinctrl-scu.c | 72 +
drivers/power/domain/Kconfig | 6 +
drivers/power/domain/Makefile | 1 +
drivers/power/domain/imx8-power-domain.c | 315 ++++
drivers/power/domain/power-domain-uclass.c | 42 +
drivers/power/regulator/fixed.c | 6 +
drivers/serial/serial_lpuart.c | 48 +-
include/configs/imx8qxp_mek.h | 157 ++
include/dt-bindings/clock/imx8qxp-clock.h | 533 +++++++
include/dt-bindings/pinctrl/pads-imx8qm.h | 975 ++++++++++++
include/dt-bindings/pinctrl/pads-imx8qxp.h | 770 ++++++++++
include/dt-bindings/soc/imx8_pd.h | 197 +++
include/dt-bindings/soc/imx_rsrc.h | 560 +++++++
include/fsl_lpuart.h | 2 +-
.../asm/arch-mx7ulp => include}/imx_lpi2c.h | 0
include/log.h | 1 +
include/power-domain.h | 52 +
88 files changed, 15691 insertions(+), 157 deletions(-)
create mode 100644 arch/arm/dts/fsl-imx8qxp-mek.dts
create mode 100644 arch/arm/dts/fsl-imx8qxp.dtsi
create mode 100644 arch/arm/include/asm/arch-imx8/clock.h
create mode 100644 arch/arm/include/asm/arch-imx8/cpu.h
create mode 100644 arch/arm/include/asm/arch-imx8/fsl_mu_hal.h
create mode 100644 arch/arm/include/asm/arch-imx8/gpio.h
create mode 100644 arch/arm/include/asm/arch-imx8/i2c.h
create mode 100644 arch/arm/include/asm/arch-imx8/imx-regs.h
create mode 100644 arch/arm/include/asm/arch-imx8/imx8-pins.h
create mode 100644 arch/arm/include/asm/arch-imx8/imx8qm_pads.h
create mode 100644 arch/arm/include/asm/arch-imx8/imx8qxp_pads.h
create mode 100644 arch/arm/include/asm/arch-imx8/iomux.h
create mode 100644 arch/arm/include/asm/arch-imx8/power-domain.h
create mode 100755 arch/arm/include/asm/arch-imx8/sci/ipc.h
create mode 100755 arch/arm/include/asm/arch-imx8/sci/rpc.h
create mode 100644 arch/arm/include/asm/arch-imx8/sci/sci.h
create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h
create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h
create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h
create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h
create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h
create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h
create mode 100755 arch/arm/include/asm/arch-imx8/sci/types.h
create mode 100644 arch/arm/include/asm/arch-imx8/sys_proto.h
create mode 100644 arch/arm/mach-imx/imx8/Kconfig
create mode 100644 arch/arm/mach-imx/imx8/Makefile
create mode 100644 arch/arm/mach-imx/imx8/clock.c
create mode 100644 arch/arm/mach-imx/imx8/cpu.c
create mode 100644 arch/arm/mach-imx/imx8/fsl_mu_hal.c
create mode 100644 arch/arm/mach-imx/imx8/iomux.c
create mode 100644 arch/arm/mach-imx/imx8/sci/ipc.c
create mode 100644 arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h
create mode 100644 arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c
create mode 100644 arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h
create mode 100644 arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c
create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h
create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c
create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h
create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c
create mode 100644 arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h
create mode 100644 arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c
create mode 100644 arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h
create mode 100644 arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c
create mode 100644 board/freescale/imx8qxp_mek/Kconfig
create mode 100644 board/freescale/imx8qxp_mek/MAINTAINERS
create mode 100644 board/freescale/imx8qxp_mek/Makefile
create mode 100644 board/freescale/imx8qxp_mek/imx8qxp_mek.c
create mode 100644 configs/imx8qxp_mek_defconfig
create mode 100644 drivers/ata/sata_imx.c
create mode 100644 drivers/pinctrl/nxp/pinctrl-imx8.c
create mode 100644 drivers/pinctrl/nxp/pinctrl-scu.c
create mode 100644 drivers/power/domain/imx8-power-domain.c
create mode 100644 include/configs/imx8qxp_mek.h
create mode 100644 include/dt-bindings/clock/imx8qxp-clock.h
create mode 100644 include/dt-bindings/pinctrl/pads-imx8qm.h
create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h
create mode 100644 include/dt-bindings/soc/imx8_pd.h
create mode 100644 include/dt-bindings/soc/imx_rsrc.h
rename {arch/arm/include/asm/arch-mx7ulp => include}/imx_lpi2c.h (100%)
--
2.14.1
^ permalink raw reply [flat|nested] 69+ messages in thread* [U-Boot] [PATCH 01/41] imx: import SCFW API 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan @ 2018-05-28 12:24 ` Peng Fan 2018-06-12 9:41 ` Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 02/41] imx: add Kconfig entry for i.MX8 Peng Fan ` (41 subsequent siblings) 42 siblings, 1 reply; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:24 UTC (permalink / raw) To: u-boot The SCFW API files are generated from scfw source code and imported to U-Boot source code withou code changes. The commit in SCFW is commit a5759de95691("SCF-69 Fix the voltage for 1.06GHz setpoint on A72.") Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/include/asm/arch-imx8/imx8qm_pads.h | 295 +++++++ arch/arm/include/asm/arch-imx8/imx8qxp_pads.h | 200 +++++ arch/arm/include/asm/arch-imx8/sci/ipc.h | 67 ++ arch/arm/include/asm/arch-imx8/sci/rpc.h | 131 +++ arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h | 160 ++++ arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h | 523 +++++++++++ arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h | 568 ++++++++++++ arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h | 686 +++++++++++++++ arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h | 759 ++++++++++++++++ arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h | 306 +++++++ arch/arm/include/asm/arch-imx8/sci/types.h | 862 ++++++++++++++++++ arch/arm/mach-imx/imx8/Makefile | 11 + arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h | 54 ++ arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c | 76 ++ arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h | 76 ++ arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c | 515 +++++++++++ arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h | 68 ++ arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c | 475 ++++++++++ arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h | 73 ++ arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c | 460 ++++++++++ arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h | 83 ++ arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c | 645 ++++++++++++++ arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h | 67 ++ arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c | 365 ++++++++ include/dt-bindings/pinctrl/pads-imx8qm.h | 975 +++++++++++++++++++++ include/dt-bindings/pinctrl/pads-imx8qxp.h | 770 ++++++++++++++++ include/dt-bindings/soc/imx_rsrc.h | 560 ++++++++++++ 27 files changed, 9830 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8/imx8qm_pads.h create mode 100644 arch/arm/include/asm/arch-imx8/imx8qxp_pads.h create mode 100755 arch/arm/include/asm/arch-imx8/sci/ipc.h create mode 100755 arch/arm/include/asm/arch-imx8/sci/rpc.h create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h create mode 100755 arch/arm/include/asm/arch-imx8/sci/types.h create mode 100644 arch/arm/mach-imx/imx8/Makefile create mode 100644 arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h create mode 100644 arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c create mode 100644 arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h create mode 100644 arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c create mode 100644 arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h create mode 100644 arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c create mode 100644 arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h create mode 100644 arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c create mode 100644 include/dt-bindings/pinctrl/pads-imx8qm.h create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h create mode 100644 include/dt-bindings/soc/imx_rsrc.h diff --git a/arch/arm/include/asm/arch-imx8/imx8qm_pads.h b/arch/arm/include/asm/arch-imx8/imx8qm_pads.h new file mode 100644 index 0000000000..5cd2b76759 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx8qm_pads.h @@ -0,0 +1,295 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file used to configure SoC pad list. + */ + +#ifndef SC_PADS_H +#define SC_PADS_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Pad Definitions + */ +/*@{*/ +#define SC_P_SIM0_CLK 0 /*!< DMA.SIM0.CLK, LSIO.GPIO0.IO00 */ +#define SC_P_SIM0_RST 1 /*!< DMA.SIM0.RST, LSIO.GPIO0.IO01 */ +#define SC_P_SIM0_IO 2 /*!< DMA.SIM0.IO, LSIO.GPIO0.IO02 */ +#define SC_P_SIM0_PD 3 /*!< DMA.SIM0.PD, DMA.I2C3.SCL, LSIO.GPIO0.IO03 */ +#define SC_P_SIM0_POWER_EN 4 /*!< DMA.SIM0.POWER_EN, DMA.I2C3.SDA, LSIO.GPIO0.IO04 */ +#define SC_P_SIM0_GPIO0_00 5 /*!< DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM 6 /*!< */ +#define SC_P_M40_I2C0_SCL 7 /*!< M40.I2C0.SCL, M40.UART0.RX, M40.GPIO0.IO02, LSIO.GPIO0.IO06 */ +#define SC_P_M40_I2C0_SDA 8 /*!< M40.I2C0.SDA, M40.UART0.TX, M40.GPIO0.IO03, LSIO.GPIO0.IO07 */ +#define SC_P_M40_GPIO0_00 9 /*!< M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */ +#define SC_P_M40_GPIO0_01 10 /*!< M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */ +#define SC_P_M41_I2C0_SCL 11 /*!< M41.I2C0.SCL, M41.UART0.RX, M41.GPIO0.IO02, LSIO.GPIO0.IO10 */ +#define SC_P_M41_I2C0_SDA 12 /*!< M41.I2C0.SDA, M41.UART0.TX, M41.GPIO0.IO03, LSIO.GPIO0.IO11 */ +#define SC_P_M41_GPIO0_00 13 /*!< M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */ +#define SC_P_M41_GPIO0_01 14 /*!< M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */ +#define SC_P_GPT0_CLK 15 /*!< LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */ +#define SC_P_GPT0_CAPTURE 16 /*!< LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */ +#define SC_P_GPT0_COMPARE 17 /*!< LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */ +#define SC_P_GPT1_CLK 18 /*!< LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */ +#define SC_P_GPT1_CAPTURE 19 /*!< LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */ +#define SC_P_GPT1_COMPARE 20 /*!< LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */ +#define SC_P_UART0_RX 21 /*!< DMA.UART0.RX, SCU.UART0.RX, LSIO.GPIO0.IO20 */ +#define SC_P_UART0_TX 22 /*!< DMA.UART0.TX, SCU.UART0.TX, LSIO.GPIO0.IO21 */ +#define SC_P_UART0_RTS_B 23 /*!< DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */ +#define SC_P_UART0_CTS_B 24 /*!< DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */ +#define SC_P_UART1_TX 25 /*!< DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */ +#define SC_P_UART1_RX 26 /*!< DMA.UART1.RX, DMA.SPI3.SDO, LSIO.GPIO0.IO25 */ +#define SC_P_UART1_RTS_B 27 /*!< DMA.UART1.RTS_B, DMA.SPI3.SDI, DMA.UART1.CTS_B, LSIO.GPIO0.IO26 */ +#define SC_P_UART1_CTS_B 28 /*!< DMA.UART1.CTS_B, DMA.SPI3.CS0, DMA.UART1.RTS_B, LSIO.GPIO0.IO27 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 29 /*!< */ +#define SC_P_SCU_PMIC_MEMC_ON 30 /*!< SCU.GPIO0.IOXX_PMIC_MEMC_ON */ +#define SC_P_SCU_WDOG_OUT 31 /*!< SCU.WDOG0.WDOG_OUT */ +#define SC_P_PMIC_I2C_SDA 32 /*!< SCU.PMIC_I2C.SDA */ +#define SC_P_PMIC_I2C_SCL 33 /*!< SCU.PMIC_I2C.SCL */ +#define SC_P_PMIC_EARLY_WARNING 34 /*!< SCU.PMIC_EARLY_WARNING */ +#define SC_P_PMIC_INT_B 35 /*!< SCU.DSC.PMIC_INT_B */ +#define SC_P_SCU_GPIO0_00 36 /*!< SCU.GPIO0.IO00, SCU.UART0.RX, LSIO.GPIO0.IO28 */ +#define SC_P_SCU_GPIO0_01 37 /*!< SCU.GPIO0.IO01, SCU.UART0.TX, LSIO.GPIO0.IO29 */ +#define SC_P_SCU_GPIO0_02 38 /*!< SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */ +#define SC_P_SCU_GPIO0_03 39 /*!< SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */ +#define SC_P_SCU_GPIO0_04 40 /*!< SCU.GPIO0.IO04, SCU.GPIO0.IOXX_PMIC_A72_ON, LSIO.GPIO1.IO00 */ +#define SC_P_SCU_GPIO0_05 41 /*!< SCU.GPIO0.IO05, SCU.GPIO0.IOXX_PMIC_A53_ON, LSIO.GPIO1.IO01 */ +#define SC_P_SCU_GPIO0_06 42 /*!< SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */ +#define SC_P_SCU_GPIO0_07 43 /*!< SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, LSIO.GPIO1.IO03 */ +#define SC_P_SCU_BOOT_MODE0 44 /*!< SCU.DSC.BOOT_MODE0 */ +#define SC_P_SCU_BOOT_MODE1 45 /*!< SCU.DSC.BOOT_MODE1 */ +#define SC_P_SCU_BOOT_MODE2 46 /*!< SCU.DSC.BOOT_MODE2 */ +#define SC_P_SCU_BOOT_MODE3 47 /*!< SCU.DSC.BOOT_MODE3 */ +#define SC_P_SCU_BOOT_MODE4 48 /*!< SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */ +#define SC_P_SCU_BOOT_MODE5 49 /*!< SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */ +#define SC_P_LVDS0_GPIO00 50 /*!< LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */ +#define SC_P_LVDS0_GPIO01 51 /*!< LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */ +#define SC_P_LVDS0_I2C0_SCL 52 /*!< LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */ +#define SC_P_LVDS0_I2C0_SDA 53 /*!< LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */ +#define SC_P_LVDS0_I2C1_SCL 54 /*!< LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */ +#define SC_P_LVDS0_I2C1_SDA 55 /*!< LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */ +#define SC_P_LVDS1_GPIO00 56 /*!< LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */ +#define SC_P_LVDS1_GPIO01 57 /*!< LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */ +#define SC_P_LVDS1_I2C0_SCL 58 /*!< LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */ +#define SC_P_LVDS1_I2C0_SDA 59 /*!< LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */ +#define SC_P_LVDS1_I2C1_SCL 60 /*!< LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */ +#define SC_P_LVDS1_I2C1_SDA 61 /*!< LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62 /*!< */ +#define SC_P_MIPI_DSI0_I2C0_SCL 63 /*!< MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */ +#define SC_P_MIPI_DSI0_I2C0_SDA 64 /*!< MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */ +#define SC_P_MIPI_DSI0_GPIO0_00 65 /*!< MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 */ +#define SC_P_MIPI_DSI0_GPIO0_01 66 /*!< MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */ +#define SC_P_MIPI_DSI1_I2C0_SCL 67 /*!< MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */ +#define SC_P_MIPI_DSI1_I2C0_SDA 68 /*!< MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */ +#define SC_P_MIPI_DSI1_GPIO0_00 69 /*!< MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 */ +#define SC_P_MIPI_DSI1_GPIO0_01 70 /*!< MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 71 /*!< */ +#define SC_P_MIPI_CSI0_MCLK_OUT 72 /*!< MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */ +#define SC_P_MIPI_CSI0_I2C0_SCL 73 /*!< MIPI_CSI0.I2C0.SCL, LSIO.GPIO1.IO25 */ +#define SC_P_MIPI_CSI0_I2C0_SDA 74 /*!< MIPI_CSI0.I2C0.SDA, LSIO.GPIO1.IO26 */ +#define SC_P_MIPI_CSI0_GPIO0_00 75 /*!< MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, MIPI_CSI1.I2C0.SCL, LSIO.GPIO1.IO27 */ +#define SC_P_MIPI_CSI0_GPIO0_01 76 /*!< MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, MIPI_CSI1.I2C0.SDA, LSIO.GPIO1.IO28 */ +#define SC_P_MIPI_CSI1_MCLK_OUT 77 /*!< MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */ +#define SC_P_MIPI_CSI1_GPIO0_00 78 /*!< MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */ +#define SC_P_MIPI_CSI1_GPIO0_01 79 /*!< MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */ +#define SC_P_MIPI_CSI1_I2C0_SCL 80 /*!< MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */ +#define SC_P_MIPI_CSI1_I2C0_SDA 81 /*!< MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */ +#define SC_P_HDMI_TX0_TS_SCL 82 /*!< HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */ +#define SC_P_HDMI_TX0_TS_SDA 83 /*!< HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */ +#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 84 /*!< */ +#define SC_P_ESAI1_FSR 85 /*!< AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */ +#define SC_P_ESAI1_FST 86 /*!< AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */ +#define SC_P_ESAI1_SCKR 87 /*!< AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */ +#define SC_P_ESAI1_SCKT 88 /*!< AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 */ +#define SC_P_ESAI1_TX0 89 /*!< AUD.ESAI1.TX0, AUD.SAI2.RXD, AUD.SPDIF0.RX, LSIO.GPIO2.IO08 */ +#define SC_P_ESAI1_TX1 90 /*!< AUD.ESAI1.TX1, AUD.SAI2.RXFS, AUD.SPDIF0.TX, LSIO.GPIO2.IO09 */ +#define SC_P_ESAI1_TX2_RX3 91 /*!< AUD.ESAI1.TX2_RX3, AUD.SPDIF0.RX, LSIO.GPIO2.IO10 */ +#define SC_P_ESAI1_TX3_RX2 92 /*!< AUD.ESAI1.TX3_RX2, AUD.SPDIF0.TX, LSIO.GPIO2.IO11 */ +#define SC_P_ESAI1_TX4_RX1 93 /*!< AUD.ESAI1.TX4_RX1, LSIO.GPIO2.IO12 */ +#define SC_P_ESAI1_TX5_RX0 94 /*!< AUD.ESAI1.TX5_RX0, LSIO.GPIO2.IO13 */ +#define SC_P_SPDIF0_RX 95 /*!< AUD.SPDIF0.RX, AUD.MQS.R, AUD.ACM.MCLK_IN1, LSIO.GPIO2.IO14 */ +#define SC_P_SPDIF0_TX 96 /*!< AUD.SPDIF0.TX, AUD.MQS.L, AUD.ACM.MCLK_OUT1, LSIO.GPIO2.IO15 */ +#define SC_P_SPDIF0_EXT_CLK 97 /*!< AUD.SPDIF0.EXT_CLK, DMA.DMA0.REQ_IN0, LSIO.GPIO2.IO16 */ +#define SC_P_SPI3_SCK 98 /*!< DMA.SPI3.SCK, LSIO.GPIO2.IO17 */ +#define SC_P_SPI3_SDO 99 /*!< DMA.SPI3.SDO, DMA.FTM.CH0, LSIO.GPIO2.IO18 */ +#define SC_P_SPI3_SDI 100 /*!< DMA.SPI3.SDI, DMA.FTM.CH1, LSIO.GPIO2.IO19 */ +#define SC_P_SPI3_CS0 101 /*!< DMA.SPI3.CS0, DMA.FTM.CH2, LSIO.GPIO2.IO20 */ +#define SC_P_SPI3_CS1 102 /*!< DMA.SPI3.CS1, LSIO.GPIO2.IO21 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 103 /*!< */ +#define SC_P_ESAI0_FSR 104 /*!< AUD.ESAI0.FSR, LSIO.GPIO2.IO22 */ +#define SC_P_ESAI0_FST 105 /*!< AUD.ESAI0.FST, LSIO.GPIO2.IO23 */ +#define SC_P_ESAI0_SCKR 106 /*!< AUD.ESAI0.SCKR, LSIO.GPIO2.IO24 */ +#define SC_P_ESAI0_SCKT 107 /*!< AUD.ESAI0.SCKT, LSIO.GPIO2.IO25 */ +#define SC_P_ESAI0_TX0 108 /*!< AUD.ESAI0.TX0, LSIO.GPIO2.IO26 */ +#define SC_P_ESAI0_TX1 109 /*!< AUD.ESAI0.TX1, LSIO.GPIO2.IO27 */ +#define SC_P_ESAI0_TX2_RX3 110 /*!< AUD.ESAI0.TX2_RX3, LSIO.GPIO2.IO28 */ +#define SC_P_ESAI0_TX3_RX2 111 /*!< AUD.ESAI0.TX3_RX2, LSIO.GPIO2.IO29 */ +#define SC_P_ESAI0_TX4_RX1 112 /*!< AUD.ESAI0.TX4_RX1, LSIO.GPIO2.IO30 */ +#define SC_P_ESAI0_TX5_RX0 113 /*!< AUD.ESAI0.TX5_RX0, LSIO.GPIO2.IO31 */ +#define SC_P_MCLK_IN0 114 /*!< AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, AUD.ESAI1.RX_HF_CLK, LSIO.GPIO3.IO00 */ +#define SC_P_MCLK_OUT0 115 /*!< AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, AUD.ESAI1.TX_HF_CLK, LSIO.GPIO3.IO01 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC 116 /*!< */ +#define SC_P_SPI0_SCK 117 /*!< DMA.SPI0.SCK, AUD.SAI0.RXC, LSIO.GPIO3.IO02 */ +#define SC_P_SPI0_SDO 118 /*!< DMA.SPI0.SDO, AUD.SAI0.TXD, LSIO.GPIO3.IO03 */ +#define SC_P_SPI0_SDI 119 /*!< DMA.SPI0.SDI, AUD.SAI0.RXD, LSIO.GPIO3.IO04 */ +#define SC_P_SPI0_CS0 120 /*!< DMA.SPI0.CS0, AUD.SAI0.RXFS, LSIO.GPIO3.IO05 */ +#define SC_P_SPI0_CS1 121 /*!< DMA.SPI0.CS1, AUD.SAI0.TXC, LSIO.GPIO3.IO06 */ +#define SC_P_SPI2_SCK 122 /*!< DMA.SPI2.SCK, LSIO.GPIO3.IO07 */ +#define SC_P_SPI2_SDO 123 /*!< DMA.SPI2.SDO, LSIO.GPIO3.IO08 */ +#define SC_P_SPI2_SDI 124 /*!< DMA.SPI2.SDI, LSIO.GPIO3.IO09 */ +#define SC_P_SPI2_CS0 125 /*!< DMA.SPI2.CS0, LSIO.GPIO3.IO10 */ +#define SC_P_SPI2_CS1 126 /*!< DMA.SPI2.CS1, AUD.SAI0.TXFS, LSIO.GPIO3.IO11 */ +#define SC_P_SAI1_RXC 127 /*!< AUD.SAI1.RXC, AUD.SAI0.TXD, LSIO.GPIO3.IO12 */ +#define SC_P_SAI1_RXD 128 /*!< AUD.SAI1.RXD, AUD.SAI0.TXFS, LSIO.GPIO3.IO13 */ +#define SC_P_SAI1_RXFS 129 /*!< AUD.SAI1.RXFS, AUD.SAI0.RXD, LSIO.GPIO3.IO14 */ +#define SC_P_SAI1_TXC 130 /*!< AUD.SAI1.TXC, AUD.SAI0.TXC, LSIO.GPIO3.IO15 */ +#define SC_P_SAI1_TXD 131 /*!< AUD.SAI1.TXD, AUD.SAI1.RXC, LSIO.GPIO3.IO16 */ +#define SC_P_SAI1_TXFS 132 /*!< AUD.SAI1.TXFS, AUD.SAI1.RXFS, LSIO.GPIO3.IO17 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 133 /*!< */ +#define SC_P_ADC_IN7 134 /*!< DMA.ADC1.IN3, DMA.SPI1.CS1, LSIO.KPP0.ROW3, LSIO.GPIO3.IO25 */ +#define SC_P_ADC_IN6 135 /*!< DMA.ADC1.IN2, DMA.SPI1.CS0, LSIO.KPP0.ROW2, LSIO.GPIO3.IO24 */ +#define SC_P_ADC_IN5 136 /*!< DMA.ADC1.IN1, DMA.SPI1.SDI, LSIO.KPP0.ROW1, LSIO.GPIO3.IO23 */ +#define SC_P_ADC_IN4 137 /*!< DMA.ADC1.IN0, DMA.SPI1.SDO, LSIO.KPP0.ROW0, LSIO.GPIO3.IO22 */ +#define SC_P_ADC_IN3 138 /*!< DMA.ADC0.IN3, DMA.SPI1.SCK, LSIO.KPP0.COL3, LSIO.GPIO3.IO21 */ +#define SC_P_ADC_IN2 139 /*!< DMA.ADC0.IN2, LSIO.KPP0.COL2, LSIO.GPIO3.IO20 */ +#define SC_P_ADC_IN1 140 /*!< DMA.ADC0.IN1, LSIO.KPP0.COL1, LSIO.GPIO3.IO19 */ +#define SC_P_ADC_IN0 141 /*!< DMA.ADC0.IN0, LSIO.KPP0.COL0, LSIO.GPIO3.IO18 */ +#define SC_P_MLB_SIG 142 /*!< CONN.MLB.SIG, AUD.SAI3.RXC, LSIO.GPIO3.IO26 */ +#define SC_P_MLB_CLK 143 /*!< CONN.MLB.CLK, AUD.SAI3.RXFS, LSIO.GPIO3.IO27 */ +#define SC_P_MLB_DATA 144 /*!< CONN.MLB.DATA, AUD.SAI3.RXD, LSIO.GPIO3.IO28 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 145 /*!< */ +#define SC_P_FLEXCAN0_RX 146 /*!< DMA.FLEXCAN0.RX, LSIO.GPIO3.IO29 */ +#define SC_P_FLEXCAN0_TX 147 /*!< DMA.FLEXCAN0.TX, LSIO.GPIO3.IO30 */ +#define SC_P_FLEXCAN1_RX 148 /*!< DMA.FLEXCAN1.RX, LSIO.GPIO3.IO31 */ +#define SC_P_FLEXCAN1_TX 149 /*!< DMA.FLEXCAN1.TX, LSIO.GPIO4.IO00 */ +#define SC_P_FLEXCAN2_RX 150 /*!< DMA.FLEXCAN2.RX, LSIO.GPIO4.IO01 */ +#define SC_P_FLEXCAN2_TX 151 /*!< DMA.FLEXCAN2.TX, LSIO.GPIO4.IO02 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 152 /*!< */ +#define SC_P_USB_SS3_TC0 153 /*!< DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO4.IO03 */ +#define SC_P_USB_SS3_TC1 154 /*!< DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */ +#define SC_P_USB_SS3_TC2 155 /*!< DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO05 */ +#define SC_P_USB_SS3_TC3 156 /*!< DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */ +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 157 /*!< */ +#define SC_P_USDHC1_RESET_B 158 /*!< CONN.USDHC1.RESET_B, LSIO.GPIO4.IO07 */ +#define SC_P_USDHC1_VSELECT 159 /*!< CONN.USDHC1.VSELECT, LSIO.GPIO4.IO08 */ +#define SC_P_USDHC2_RESET_B 160 /*!< CONN.USDHC2.RESET_B, LSIO.GPIO4.IO09 */ +#define SC_P_USDHC2_VSELECT 161 /*!< CONN.USDHC2.VSELECT, LSIO.GPIO4.IO10 */ +#define SC_P_USDHC2_WP 162 /*!< CONN.USDHC2.WP, LSIO.GPIO4.IO11 */ +#define SC_P_USDHC2_CD_B 163 /*!< CONN.USDHC2.CD_B, LSIO.GPIO4.IO12 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 164 /*!< */ +#define SC_P_ENET0_MDIO 165 /*!< CONN.ENET0.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO13 */ +#define SC_P_ENET0_MDC 166 /*!< CONN.ENET0.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO14 */ +#define SC_P_ENET0_REFCLK_125M_25M 167 /*!< CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, LSIO.GPIO4.IO15 */ +#define SC_P_ENET1_REFCLK_125M_25M 168 /*!< CONN.ENET1.REFCLK_125M_25M, CONN.ENET1.PPS, LSIO.GPIO4.IO16 */ +#define SC_P_ENET1_MDIO 169 /*!< CONN.ENET1.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO17 */ +#define SC_P_ENET1_MDC 170 /*!< CONN.ENET1.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO18 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 171 /*!< */ +#define SC_P_QSPI1A_SS0_B 172 /*!< LSIO.QSPI1A.SS0_B, LSIO.GPIO4.IO19 */ +#define SC_P_QSPI1A_SS1_B 173 /*!< LSIO.QSPI1A.SS1_B, LSIO.QSPI1A.SCLK2, LSIO.GPIO4.IO20 */ +#define SC_P_QSPI1A_SCLK 174 /*!< LSIO.QSPI1A.SCLK, LSIO.GPIO4.IO21 */ +#define SC_P_QSPI1A_DQS 175 /*!< LSIO.QSPI1A.DQS, LSIO.GPIO4.IO22 */ +#define SC_P_QSPI1A_DATA3 176 /*!< LSIO.QSPI1A.DATA3, DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO23 */ +#define SC_P_QSPI1A_DATA2 177 /*!< LSIO.QSPI1A.DATA2, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO24 */ +#define SC_P_QSPI1A_DATA1 178 /*!< LSIO.QSPI1A.DATA1, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO25 */ +#define SC_P_QSPI1A_DATA0 179 /*!< LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1 180 /*!< */ +#define SC_P_QSPI0A_DATA0 181 /*!< LSIO.QSPI0A.DATA0 */ +#define SC_P_QSPI0A_DATA1 182 /*!< LSIO.QSPI0A.DATA1 */ +#define SC_P_QSPI0A_DATA2 183 /*!< LSIO.QSPI0A.DATA2 */ +#define SC_P_QSPI0A_DATA3 184 /*!< LSIO.QSPI0A.DATA3 */ +#define SC_P_QSPI0A_DQS 185 /*!< LSIO.QSPI0A.DQS */ +#define SC_P_QSPI0A_SS0_B 186 /*!< LSIO.QSPI0A.SS0_B */ +#define SC_P_QSPI0A_SS1_B 187 /*!< LSIO.QSPI0A.SS1_B, LSIO.QSPI0A.SCLK2 */ +#define SC_P_QSPI0A_SCLK 188 /*!< LSIO.QSPI0A.SCLK */ +#define SC_P_QSPI0B_SCLK 189 /*!< LSIO.QSPI0B.SCLK */ +#define SC_P_QSPI0B_DATA0 190 /*!< LSIO.QSPI0B.DATA0 */ +#define SC_P_QSPI0B_DATA1 191 /*!< LSIO.QSPI0B.DATA1 */ +#define SC_P_QSPI0B_DATA2 192 /*!< LSIO.QSPI0B.DATA2 */ +#define SC_P_QSPI0B_DATA3 193 /*!< LSIO.QSPI0B.DATA3 */ +#define SC_P_QSPI0B_DQS 194 /*!< LSIO.QSPI0B.DQS */ +#define SC_P_QSPI0B_SS0_B 195 /*!< LSIO.QSPI0B.SS0_B */ +#define SC_P_QSPI0B_SS1_B 196 /*!< LSIO.QSPI0B.SS1_B, LSIO.QSPI0B.SCLK2 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 197 /*!< */ +#define SC_P_PCIE_CTRL0_CLKREQ_B 198 /*!< HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO27 */ +#define SC_P_PCIE_CTRL0_WAKE_B 199 /*!< HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO28 */ +#define SC_P_PCIE_CTRL0_PERST_B 200 /*!< HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO29 */ +#define SC_P_PCIE_CTRL1_CLKREQ_B 201 /*!< HSIO.PCIE1.CLKREQ_B, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO30 */ +#define SC_P_PCIE_CTRL1_WAKE_B 202 /*!< HSIO.PCIE1.WAKE_B, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO31 */ +#define SC_P_PCIE_CTRL1_PERST_B 203 /*!< HSIO.PCIE1.PERST_B, DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO5.IO00 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 204 /*!< */ +#define SC_P_USB_HSIC0_DATA 205 /*!< CONN.USB_HSIC0.DATA, DMA.I2C1.SDA, LSIO.GPIO5.IO01 */ +#define SC_P_USB_HSIC0_STROBE 206 /*!< CONN.USB_HSIC0.STROBE, DMA.I2C1.SCL, LSIO.GPIO5.IO02 */ +#define SC_P_CALIBRATION_0_HSIC 207 /*!< */ +#define SC_P_CALIBRATION_1_HSIC 208 /*!< */ +#define SC_P_EMMC0_CLK 209 /*!< CONN.EMMC0.CLK, CONN.NAND.READY_B */ +#define SC_P_EMMC0_CMD 210 /*!< CONN.EMMC0.CMD, CONN.NAND.DQS, AUD.MQS.R, LSIO.GPIO5.IO03 */ +#define SC_P_EMMC0_DATA0 211 /*!< CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO5.IO04 */ +#define SC_P_EMMC0_DATA1 212 /*!< CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO5.IO05 */ +#define SC_P_EMMC0_DATA2 213 /*!< CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO5.IO06 */ +#define SC_P_EMMC0_DATA3 214 /*!< CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO5.IO07 */ +#define SC_P_EMMC0_DATA4 215 /*!< CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO5.IO08 */ +#define SC_P_EMMC0_DATA5 216 /*!< CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO5.IO09 */ +#define SC_P_EMMC0_DATA6 217 /*!< CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO5.IO10 */ +#define SC_P_EMMC0_DATA7 218 /*!< CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO5.IO11 */ +#define SC_P_EMMC0_STROBE 219 /*!< CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO5.IO12 */ +#define SC_P_EMMC0_RESET_B 220 /*!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, CONN.USDHC1.VSELECT, LSIO.GPIO5.IO13 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 221 /*!< */ +#define SC_P_USDHC1_CLK 222 /*!< CONN.USDHC1.CLK, AUD.MQS.R */ +#define SC_P_USDHC1_CMD 223 /*!< CONN.USDHC1.CMD, AUD.MQS.L, LSIO.GPIO5.IO14 */ +#define SC_P_USDHC1_DATA0 224 /*!< CONN.USDHC1.DATA0, CONN.NAND.RE_N, LSIO.GPIO5.IO15 */ +#define SC_P_USDHC1_DATA1 225 /*!< CONN.USDHC1.DATA1, CONN.NAND.RE_P, LSIO.GPIO5.IO16 */ +#define SC_P_CTL_NAND_RE_P_N 226 /*!< */ +#define SC_P_USDHC1_DATA2 227 /*!< CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */ +#define SC_P_USDHC1_DATA3 228 /*!< CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */ +#define SC_P_CTL_NAND_DQS_P_N 229 /*!< */ +#define SC_P_USDHC1_DATA4 230 /*!< CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 */ +#define SC_P_USDHC1_DATA5 231 /*!< CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */ +#define SC_P_USDHC1_DATA6 232 /*!< CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 */ +#define SC_P_USDHC1_DATA7 233 /*!< CONN.USDHC1.DATA7, CONN.NAND.ALE, CONN.USDHC1.CD_B, LSIO.GPIO5.IO22 */ +#define SC_P_USDHC1_STROBE 234 /*!< CONN.USDHC1.STROBE, CONN.NAND.CE1_B, CONN.USDHC1.RESET_B, LSIO.GPIO5.IO23 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2 235 /*!< */ +#define SC_P_USDHC2_CLK 236 /*!< CONN.USDHC2.CLK, AUD.MQS.R, LSIO.GPIO5.IO24 */ +#define SC_P_USDHC2_CMD 237 /*!< CONN.USDHC2.CMD, AUD.MQS.L, LSIO.GPIO5.IO25 */ +#define SC_P_USDHC2_DATA0 238 /*!< CONN.USDHC2.DATA0, DMA.UART4.RX, LSIO.GPIO5.IO26 */ +#define SC_P_USDHC2_DATA1 239 /*!< CONN.USDHC2.DATA1, DMA.UART4.TX, LSIO.GPIO5.IO27 */ +#define SC_P_USDHC2_DATA2 240 /*!< CONN.USDHC2.DATA2, DMA.UART4.CTS_B, LSIO.GPIO5.IO28 */ +#define SC_P_USDHC2_DATA3 241 /*!< CONN.USDHC2.DATA3, DMA.UART4.RTS_B, LSIO.GPIO5.IO29 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 242 /*!< */ +#define SC_P_ENET0_RGMII_TXC 243 /*!< CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, LSIO.GPIO5.IO30 */ +#define SC_P_ENET0_RGMII_TX_CTL 244 /*!< CONN.ENET0.RGMII_TX_CTL, LSIO.GPIO5.IO31 */ +#define SC_P_ENET0_RGMII_TXD0 245 /*!< CONN.ENET0.RGMII_TXD0, LSIO.GPIO6.IO00 */ +#define SC_P_ENET0_RGMII_TXD1 246 /*!< CONN.ENET0.RGMII_TXD1, LSIO.GPIO6.IO01 */ +#define SC_P_ENET0_RGMII_TXD2 247 /*!< CONN.ENET0.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO02 */ +#define SC_P_ENET0_RGMII_TXD3 248 /*!< CONN.ENET0.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO03 */ +#define SC_P_ENET0_RGMII_RXC 249 /*!< CONN.ENET0.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO04 */ +#define SC_P_ENET0_RGMII_RX_CTL 250 /*!< CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 */ +#define SC_P_ENET0_RGMII_RXD0 251 /*!< CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */ +#define SC_P_ENET0_RGMII_RXD1 252 /*!< CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */ +#define SC_P_ENET0_RGMII_RXD2 253 /*!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO08 */ +#define SC_P_ENET0_RGMII_RXD3 254 /*!< CONN.ENET0.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO09 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 255 /*!< */ +#define SC_P_ENET1_RGMII_TXC 256 /*!< CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_OUT, CONN.ENET1.RCLK50M_IN, LSIO.GPIO6.IO10 */ +#define SC_P_ENET1_RGMII_TX_CTL 257 /*!< CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO6.IO11 */ +#define SC_P_ENET1_RGMII_TXD0 258 /*!< CONN.ENET1.RGMII_TXD0, LSIO.GPIO6.IO12 */ +#define SC_P_ENET1_RGMII_TXD1 259 /*!< CONN.ENET1.RGMII_TXD1, LSIO.GPIO6.IO13 */ +#define SC_P_ENET1_RGMII_TXD2 260 /*!< CONN.ENET1.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO14 */ +#define SC_P_ENET1_RGMII_TXD3 261 /*!< CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO15 */ +#define SC_P_ENET1_RGMII_RXC 262 /*!< CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO16 */ +#define SC_P_ENET1_RGMII_RX_CTL 263 /*!< CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 */ +#define SC_P_ENET1_RGMII_RXD0 264 /*!< CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */ +#define SC_P_ENET1_RGMII_RXD1 265 /*!< CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */ +#define SC_P_ENET1_RGMII_RXD2 266 /*!< CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */ +#define SC_P_ENET1_RGMII_RXD3 267 /*!< CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 268 /*!< */ +/*@}*/ + +#endif /* SC_PADS_H */ + diff --git a/arch/arm/include/asm/arch-imx8/imx8qxp_pads.h b/arch/arm/include/asm/arch-imx8/imx8qxp_pads.h new file mode 100644 index 0000000000..8db40c549a --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx8qxp_pads.h @@ -0,0 +1,200 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file used to configure SoC pad list. + */ + +#ifndef SC_PADS_H +#define SC_PADS_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Pad Definitions + */ +/*@{*/ +#define SC_P_PCIE_CTRL0_PERST_B 0 /*!< HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */ +#define SC_P_PCIE_CTRL0_CLKREQ_B 1 /*!< HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */ +#define SC_P_PCIE_CTRL0_WAKE_B 2 /*!< HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 /*!< */ +#define SC_P_USB_SS3_TC0 4 /*!< ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */ +#define SC_P_USB_SS3_TC1 5 /*!< ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */ +#define SC_P_USB_SS3_TC2 6 /*!< ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 */ +#define SC_P_USB_SS3_TC3 7 /*!< ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */ +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8 /*!< */ +#define SC_P_EMMC0_CLK 9 /*!< CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */ +#define SC_P_EMMC0_CMD 10 /*!< CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */ +#define SC_P_EMMC0_DATA0 11 /*!< CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */ +#define SC_P_EMMC0_DATA1 12 /*!< CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */ +#define SC_P_EMMC0_DATA2 13 /*!< CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */ +#define SC_P_EMMC0_DATA3 14 /*!< CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15 /*!< */ +#define SC_P_EMMC0_DATA4 16 /*!< CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */ +#define SC_P_EMMC0_DATA5 17 /*!< CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */ +#define SC_P_EMMC0_DATA6 18 /*!< CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */ +#define SC_P_EMMC0_DATA7 19 /*!< CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 */ +#define SC_P_EMMC0_STROBE 20 /*!< CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 */ +#define SC_P_EMMC0_RESET_B 21 /*!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22 /*!< */ +#define SC_P_USDHC1_RESET_B 23 /*!< CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 */ +#define SC_P_USDHC1_VSELECT 24 /*!< CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20 */ +#define SC_P_CTL_NAND_RE_P_N 25 /*!< */ +#define SC_P_USDHC1_WP 26 /*!< CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */ +#define SC_P_USDHC1_CD_B 27 /*!< CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22 */ +#define SC_P_CTL_NAND_DQS_P_N 28 /*!< */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29 /*!< */ +#define SC_P_USDHC1_CLK 30 /*!< CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */ +#define SC_P_USDHC1_CMD 31 /*!< CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */ +#define SC_P_USDHC1_DATA0 32 /*!< CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */ +#define SC_P_USDHC1_DATA1 33 /*!< CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */ +#define SC_P_USDHC1_DATA2 34 /*!< CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, LSIO.GPIO4.IO27 */ +#define SC_P_USDHC1_DATA3 35 /*!< CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, LSIO.GPIO4.IO28 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36 /*!< */ +#define SC_P_ENET0_RGMII_TXC 37 /*!< CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */ +#define SC_P_ENET0_RGMII_TX_CTL 38 /*!< CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */ +#define SC_P_ENET0_RGMII_TXD0 39 /*!< CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 */ +#define SC_P_ENET0_RGMII_TXD1 40 /*!< CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */ +#define SC_P_ENET0_RGMII_TXD2 41 /*!< CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 */ +#define SC_P_ENET0_RGMII_TXD3 42 /*!< CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, LSIO.GPIO5.IO02 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43 /*!< */ +#define SC_P_ENET0_RGMII_RXC 44 /*!< CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */ +#define SC_P_ENET0_RGMII_RX_CTL 45 /*!< CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */ +#define SC_P_ENET0_RGMII_RXD0 46 /*!< CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */ +#define SC_P_ENET0_RGMII_RXD1 47 /*!< CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */ +#define SC_P_ENET0_RGMII_RXD2 48 /*!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */ +#define SC_P_ENET0_RGMII_RXD3 49 /*!< CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO5.IO08 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50 /*!< */ +#define SC_P_ENET0_REFCLK_125M_25M 51 /*!< CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO5.IO09 */ +#define SC_P_ENET0_MDIO 52 /*!< CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO5.IO10 */ +#define SC_P_ENET0_MDC 53 /*!< CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO5.IO11 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54 /*!< */ +#define SC_P_ESAI0_FSR 55 /*!< ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN */ +#define SC_P_ESAI0_FST 56 /*!< ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01, CONN.ENET1.RGMII_TXD2, LSIO.GPIO0.IO01 */ +#define SC_P_ESAI0_SCKR 57 /*!< ADMA.ESAI0.SCKR, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO0.IO02 */ +#define SC_P_ESAI0_SCKT 58 /*!< ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D03, CONN.ENET1.RGMII_TXD3, LSIO.GPIO0.IO03 */ +#define SC_P_ESAI0_TX0 59 /*!< ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D04, CONN.ENET1.RGMII_RXC, LSIO.GPIO0.IO04 */ +#define SC_P_ESAI0_TX1 60 /*!< ADMA.ESAI0.TX1, ADMA.LCDIF.D05, CONN.ENET1.RGMII_RXD3, LSIO.GPIO0.IO05 */ +#define SC_P_ESAI0_TX2_RX3 61 /*!< ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D06, CONN.ENET1.RGMII_RXD2, LSIO.GPIO0.IO06 */ +#define SC_P_ESAI0_TX3_RX2 62 /*!< ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD1, LSIO.GPIO0.IO07 */ +#define SC_P_ESAI0_TX4_RX1 63 /*!< ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D08, CONN.ENET1.RGMII_TXD0, LSIO.GPIO0.IO08 */ +#define SC_P_ESAI0_TX5_RX0 64 /*!< ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D09, CONN.ENET1.RGMII_TXD1, LSIO.GPIO0.IO09 */ +#define SC_P_SPDIF0_RX 65 /*!< ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, LSIO.GPIO0.IO10 */ +#define SC_P_SPDIF0_TX 66 /*!< ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO0.IO11 */ +#define SC_P_SPDIF0_EXT_CLK 67 /*!< ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, LSIO.GPIO0.IO12 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68 /*!< */ +#define SC_P_SPI3_SCK 69 /*!< ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */ +#define SC_P_SPI3_SDO 70 /*!< ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */ +#define SC_P_SPI3_SDI 71 /*!< ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */ +#define SC_P_SPI3_CS0 72 /*!< ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16 */ +#define SC_P_SPI3_CS1 73 /*!< ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16 */ +#define SC_P_MCLK_IN1 74 /*!< ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17 */ +#define SC_P_MCLK_IN0 75 /*!< ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO0.IO19 */ +#define SC_P_MCLK_OUT0 76 /*!< ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO0.IO20 */ +#define SC_P_UART1_TX 77 /*!< ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21 */ +#define SC_P_UART1_RX 78 /*!< ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22 */ +#define SC_P_UART1_RTS_B 79 /*!< ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK */ +#define SC_P_UART1_CTS_B 80 /*!< ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO24 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81 /*!< */ +#define SC_P_SAI0_TXD 82 /*!< ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, LSIO.GPIO0.IO25 */ +#define SC_P_SAI0_TXC 83 /*!< ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, LSIO.GPIO0.IO26 */ +#define SC_P_SAI0_RXD 84 /*!< ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, LSIO.GPIO0.IO27 */ +#define SC_P_SAI0_TXFS 85 /*!< ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO0.IO28 */ +#define SC_P_SAI1_RXD 86 /*!< ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D21, LSIO.GPIO0.IO29 */ +#define SC_P_SAI1_RXC 87 /*!< ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22, LSIO.GPIO0.IO30 */ +#define SC_P_SAI1_RXFS 88 /*!< ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO0.IO31 */ +#define SC_P_SPI2_CS0 89 /*!< ADMA.SPI2.CS0, LSIO.GPIO1.IO00 */ +#define SC_P_SPI2_SDO 90 /*!< ADMA.SPI2.SDO, LSIO.GPIO1.IO01 */ +#define SC_P_SPI2_SDI 91 /*!< ADMA.SPI2.SDI, LSIO.GPIO1.IO02 */ +#define SC_P_SPI2_SCK 92 /*!< ADMA.SPI2.SCK, LSIO.GPIO1.IO03 */ +#define SC_P_SPI0_SCK 93 /*!< ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO04 */ +#define SC_P_SPI0_SDI 94 /*!< ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO1.IO05 */ +#define SC_P_SPI0_SDO 95 /*!< ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO06 */ +#define SC_P_SPI0_CS1 96 /*!< ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO1.IO07 */ +#define SC_P_SPI0_CS0 97 /*!< ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO1.IO08 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98 /*!< */ +#define SC_P_ADC_IN1 99 /*!< ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO09 */ +#define SC_P_ADC_IN0 100 /*!< ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO10 */ +#define SC_P_ADC_IN3 101 /*!< ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO1.IO11 */ +#define SC_P_ADC_IN2 102 /*!< ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO1.IO12 */ +#define SC_P_ADC_IN5 103 /*!< ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO1.IO13 */ +#define SC_P_ADC_IN4 104 /*!< ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO1.IO14 */ +#define SC_P_FLEXCAN0_RX 105 /*!< ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO1.IO15 */ +#define SC_P_FLEXCAN0_TX 106 /*!< ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO1.IO16 */ +#define SC_P_FLEXCAN1_RX 107 /*!< ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, LSIO.GPIO1.IO17 */ +#define SC_P_FLEXCAN1_TX 108 /*!< ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18 */ +#define SC_P_FLEXCAN2_RX 109 /*!< ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19 */ +#define SC_P_FLEXCAN2_TX 110 /*!< ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20 */ +#define SC_P_UART0_RX 111 /*!< ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, SCU.UART0.RX, LSIO.GPIO1.IO21 */ +#define SC_P_UART0_TX 112 /*!< ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, SCU.UART0.TX, LSIO.GPIO1.IO22 */ +#define SC_P_UART2_TX 113 /*!< ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */ +#define SC_P_UART2_RX 114 /*!< ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115 /*!< */ +#define SC_P_MIPI_DSI0_I2C0_SCL 116 /*!< MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 */ +#define SC_P_MIPI_DSI0_I2C0_SDA 117 /*!< MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 */ +#define SC_P_MIPI_DSI0_GPIO0_00 118 /*!< MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO27 */ +#define SC_P_MIPI_DSI0_GPIO0_01 119 /*!< MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */ +#define SC_P_MIPI_DSI1_I2C0_SCL 120 /*!< MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 */ +#define SC_P_MIPI_DSI1_I2C0_SDA 121 /*!< MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 */ +#define SC_P_MIPI_DSI1_GPIO0_00 122 /*!< MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO31 */ +#define SC_P_MIPI_DSI1_GPIO0_01 123 /*!< MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124 /*!< */ +#define SC_P_JTAG_TRST_B 125 /*!< SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */ +#define SC_P_PMIC_I2C_SCL 126 /*!< SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */ +#define SC_P_PMIC_I2C_SDA 127 /*!< SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */ +#define SC_P_PMIC_INT_B 128 /*!< SCU.DSC.PMIC_INT_B */ +#define SC_P_SCU_GPIO0_00 129 /*!< SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, LSIO.GPIO2.IO03 */ +#define SC_P_SCU_GPIO0_01 130 /*!< SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, SCU.WDOG0.WDOG_OUT */ +#define SC_P_SCU_PMIC_STANDBY 131 /*!< SCU.DSC.PMIC_STANDBY */ +#define SC_P_SCU_BOOT_MODE0 132 /*!< SCU.DSC.BOOT_MODE0 */ +#define SC_P_SCU_BOOT_MODE1 133 /*!< SCU.DSC.BOOT_MODE1 */ +#define SC_P_SCU_BOOT_MODE2 134 /*!< SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA */ +#define SC_P_SCU_BOOT_MODE3 135 /*!< SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, SCU.DSC.RTC_CLOCK_OUTPUT_32K */ +#define SC_P_CSI_D00 136 /*!< CI_PI.D02, ADMA.SAI0.RXC */ +#define SC_P_CSI_D01 137 /*!< CI_PI.D03, ADMA.SAI0.RXD */ +#define SC_P_CSI_D02 138 /*!< CI_PI.D04, ADMA.SAI0.RXFS */ +#define SC_P_CSI_D03 139 /*!< CI_PI.D05, ADMA.SAI2.RXC */ +#define SC_P_CSI_D04 140 /*!< CI_PI.D06, ADMA.SAI2.RXD */ +#define SC_P_CSI_D05 141 /*!< CI_PI.D07, ADMA.SAI2.RXFS */ +#define SC_P_CSI_D06 142 /*!< CI_PI.D08, ADMA.SAI3.RXC */ +#define SC_P_CSI_D07 143 /*!< CI_PI.D09, ADMA.SAI3.RXD */ +#define SC_P_CSI_HSYNC 144 /*!< CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS */ +#define SC_P_CSI_VSYNC 145 /*!< CI_PI.VSYNC, CI_PI.D01 */ +#define SC_P_CSI_PCLK 146 /*!< CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */ +#define SC_P_CSI_MCLK 147 /*!< CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */ +#define SC_P_CSI_EN 148 /*!< CI_PI.EN, CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */ +#define SC_P_CSI_RESET 149 /*!< CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150 /*!< */ +#define SC_P_MIPI_CSI0_MCLK_OUT 151 /*!< MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */ +#define SC_P_MIPI_CSI0_I2C0_SCL 152 /*!< MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 */ +#define SC_P_MIPI_CSI0_I2C0_SDA 153 /*!< MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 */ +#define SC_P_MIPI_CSI0_GPIO0_01 154 /*!< MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */ +#define SC_P_MIPI_CSI0_GPIO0_00 155 /*!< MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */ +#define SC_P_QSPI0A_DATA0 156 /*!< LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */ +#define SC_P_QSPI0A_DATA1 157 /*!< LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */ +#define SC_P_QSPI0A_DATA2 158 /*!< LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */ +#define SC_P_QSPI0A_DATA3 159 /*!< LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */ +#define SC_P_QSPI0A_DQS 160 /*!< LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */ +#define SC_P_QSPI0A_SS0_B 161 /*!< LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */ +#define SC_P_QSPI0A_SS1_B 162 /*!< LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */ +#define SC_P_QSPI0A_SCLK 163 /*!< LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164 /*!< */ +#define SC_P_QSPI0B_SCLK 165 /*!< LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */ +#define SC_P_QSPI0B_DATA0 166 /*!< LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO3.IO18 */ +#define SC_P_QSPI0B_DATA1 167 /*!< LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO3.IO19 */ +#define SC_P_QSPI0B_DATA2 168 /*!< LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */ +#define SC_P_QSPI0B_DATA3 169 /*!< LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */ +#define SC_P_QSPI0B_DQS 170 /*!< LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 */ +#define SC_P_QSPI0B_SS0_B 171 /*!< LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */ +#define SC_P_QSPI0B_SS1_B 172 /*!< LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO3.IO24 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173 /*!< */ +/*@}*/ + +#endif /* SC_PADS_H */ + diff --git a/arch/arm/include/asm/arch-imx8/sci/ipc.h b/arch/arm/include/asm/arch-imx8/sci/ipc.h new file mode 100755 index 0000000000..3759ac4c45 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/ipc.h @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file for the IPC implementation. + */ + +#ifndef SC_IPC_H +#define SC_IPC_H + +/* Includes */ + +#include <asm/arch/sci/types.h> + +/* Defines */ + +/* Types */ + +/* Functions */ + +/*! + * This function opens an IPC channel. + * + * @param[out] ipc return pointer for ipc handle + * @param[in] id id of channel to open + * + * @return Returns an error code (SC_ERR_NONE = success, SC_ERR_IPC + * otherwise). + * + * The \a id parameter is implementation specific. Could be an MU + * address, pointer to a driver path, channel index, etc. + */ +sc_err_t sc_ipc_open(sc_ipc_t *ipc, sc_ipc_id_t id); + +/*! + * This function closes an IPC channel. + * + * @param[in] ipc id of channel to close + */ +void sc_ipc_close(sc_ipc_t ipc); + +/*! + * This function reads a message from an IPC channel. + * + * @param[in] ipc id of channel read from + * @param[out] data pointer to message buffer to read + * + * This function will block if no message is available to be read. + */ +void sc_ipc_read(sc_ipc_t ipc, void *data); + +/*! + * This function writes a message to an IPC channel. + * + * @param[in] ipc id of channel to write to + * @param[in] data pointer to message buffer to write + * + * This function will block if the outgoing buffer is full. + */ +void sc_ipc_write(sc_ipc_t ipc, void *data); + +#endif /* SC_IPC_H */ + diff --git a/arch/arm/include/asm/arch-imx8/sci/rpc.h b/arch/arm/include/asm/arch-imx8/sci/rpc.h new file mode 100755 index 0000000000..afb891e2c5 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/rpc.h @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file for the RPC implementation. + */ + +#ifndef SC_RPC_H +#define SC_RPC_H + +/* Includes */ + +#include <asm/arch/sci/types.h> +#include <asm/arch/sci/ipc.h> + +/* Defines */ + +#define SC_RPC_VERSION 1U + +#define SC_RPC_MAX_MSG 8U + +#define RPC_VER(MSG) ((MSG)->version) +#define RPC_SIZE(MSG) ((MSG)->size) +#define RPC_SVC(MSG) ((MSG)->svc) +#define RPC_FUNC(MSG) ((MSG)->func) +#define RPC_R8(MSG) ((MSG)->func) +#define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4U]) +#define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2U]) +#define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[(IDX)]) +#define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U]) +#define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2U]) +#define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[(IDX)]) + +#define SC_RPC_SVC_UNKNOWN 0U +#define SC_RPC_SVC_RETURN 1U +#define SC_RPC_SVC_PM 2U +#define SC_RPC_SVC_RM 3U +#define SC_RPC_SVC_TIMER 5U +#define SC_RPC_SVC_PAD 6U +#define SC_RPC_SVC_MISC 7U +#define SC_RPC_SVC_IRQ 8U +#define SC_RPC_SVC_ABORT 9U + +#define SC_RPC_ASYNC_STATE_RD_START 0U +#define SC_RPC_ASYNC_STATE_RD_ACTIVE 1U +#define SC_RPC_ASYNC_STATE_RD_DONE 2U +#define SC_RPC_ASYNC_STATE_WR_START 3U +#define SC_RPC_ASYNC_STATE_WR_ACTIVE 4U +#define SC_RPC_ASYNC_STATE_WR_DONE 5U + +#define SC_RPC_MU_GIR_SVC 0x1U +#define SC_RPC_MU_GIR_DBG 0x8U + +/* Types */ + +typedef uint8_t sc_rpc_svc_t; + +typedef struct sc_rpc_msg_s +{ + uint8_t version; + uint8_t size; + uint8_t svc; + uint8_t func; + union + { + int32_t i32[(SC_RPC_MAX_MSG - 1U)]; + int16_t i16[(SC_RPC_MAX_MSG - 1U) * 2U]; + int8_t i8[(SC_RPC_MAX_MSG - 1U) * 4U]; + uint32_t u32[(SC_RPC_MAX_MSG - 1U)]; + uint16_t u16[(SC_RPC_MAX_MSG - 1U) * 2U]; + uint8_t u8[(SC_RPC_MAX_MSG - 1U) * 4U]; + } DATA; +} sc_rpc_msg_t; + +typedef uint8_t sc_rpc_async_state_t; + +typedef struct sc_rpc_async_msg_s +{ + sc_rpc_async_state_t state; + uint8_t wordIdx; + sc_rpc_msg_t msg; + uint32_t timeStamp; +} sc_rpc_async_msg_t; + +/* Functions */ + +/*! + * This is an internal function to send an RPC message over an IPC + * channel. It is called by client-side SCFW API function shims. + * + * @param[in] ipc IPC handle + * @param[in,out] msg handle to a message + * @param[in] no_resp response flag + * + * If \a no_resp is SC_FALSE then this function waits for a response + * and returns the result in \a msg. + */ +void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, sc_bool_t no_resp); + +/*! + * This is an internal function to dispath an RPC call that has + * arrived via IPC over an MU. It is called by server-side SCFW. + * + * @param[in] mu MU message arrived on + * @param[in,out] msg handle to a message + * + * The function result is returned in \a msg. + */ +void sc_rpc_dispatch(sc_rsrc_t mu, sc_rpc_msg_t *msg); + +/*! + * This function translates an RPC message and forwards on to the + * normal RPC API. It is used only by hypervisors. + * + * @param[in] ipc IPC handle + * @param[in,out] msg handle to a message + * + * This function decodes a message, calls macros to translate the + * resources, pads, addresses, partitions, memory regions, etc. and + * then forwards on to the hypervisors SCFW API.Return results are + * translated back abd placed back into the message to be returned + * to the original API. + */ +void sc_rpc_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg); + +#endif /* SC_RPC_H */ + diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h new file mode 100755 index 0000000000..1e266c39b4 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file containing the public API for the System Controller (SC) + * Interrupt (IRQ) function. + * + * @addtogroup IRQ_SVC (SVC) Interrupt Service + * + * Module for the Interrupt (IRQ) service. + * + * @{ + */ + +#ifndef SC_IRQ_API_H +#define SC_IRQ_API_H + +/* Includes */ + +#include <asm/arch/sci/types.h> + +/* Defines */ + +#define SC_IRQ_NUM_GROUP 4U /*!< Number of groups */ + +/*! + * @name Defines for sc_irq_group_t + */ +/*@{*/ +#define SC_IRQ_GROUP_TEMP 0U /*!< Temp interrupts */ +#define SC_IRQ_GROUP_WDOG 1U /*!< Watchdog interrupts */ +#define SC_IRQ_GROUP_RTC 2U /*!< RTC interrupts */ +#define SC_IRQ_GROUP_WAKE 3U /*!< Wakeup interrupts */ +/*@}*/ + +/*! + * @name Defines for sc_irq_temp_t + */ +/*@{*/ +#define SC_IRQ_TEMP_HIGH (1U << 0U) /*!< Temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU0_HIGH (1U << 1U) /*!< CPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU1_HIGH (1U << 2U) /*!< CPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU0_HIGH (1U << 3U) /*!< GPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU1_HIGH (1U << 4U) /*!< GPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC0_HIGH (1U << 5U) /*!< DRC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC1_HIGH (1U << 6U) /*!< DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_VPU_HIGH (1U << 7U) /*!< DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC0_HIGH (1U << 8U) /*!< PMIC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC1_HIGH (1U << 9U) /*!< PMIC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_LOW (1U << 10U) /*!< Temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU0_LOW (1U << 11U) /*!< CPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU1_LOW (1U << 12U) /*!< CPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU0_LOW (1U << 13U) /*!< GPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU1_LOW (1U << 14U) /*!< GPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC0_LOW (1U << 15U) /*!< DRC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC1_LOW (1U << 16U) /*!< DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_VPU_LOW (1U << 17U) /*!< DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC0_LOW (1U << 18U) /*!< PMIC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC1_LOW (1U << 19U) /*!< PMIC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC2_HIGH (1U << 20U) /*!< PMIC2 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC2_LOW (1U << 21U) /*!< PMIC2 temp alarm interrupt */ +/*@}*/ + +/*! + * @name Defines for sc_irq_wdog_t + */ +/*@{*/ +#define SC_IRQ_WDOG (1U << 0U /*!< Watchdog interrupt */ +/*@}*/ + +/*! + * @name Defines for sc_irq_rtc_t + */ +/*@{*/ +#define SC_IRQ_RTC (1U << 0U) /*!< RTC interrupt */ +/*@}*/ + +/*! + * @name Defines for sc_irq_wake_t + */ +/*@{*/ +#define SC_IRQ_BUTTON (1U << 0U) /*!< Button interrupt */ +#define SC_IRQ_PAD (1U << 1U) /*!< Pad wakeup */ +/*@}*/ + +/* Types */ + +/*! + * This type is used to declare an interrupt group. + */ +typedef uint8_t sc_irq_group_t; + +/*! + * This type is used to declare a bit mask of temp interrupts. + */ +typedef uint8_t sc_irq_temp_t; + +/*! + * This type is used to declare a bit mask of watchdog interrupts. + */ +typedef uint8_t sc_irq_wdog_t; + +/*! + * This type is used to declare a bit mask of RTC interrupts. + */ +typedef uint8_t sc_irq_rtc_t; + +/*! + * This type is used to declare a bit mask of wakeup interrupts. + */ +typedef uint8_t sc_irq_wake_t; + +/* Functions */ + +/*! + * This function enables/disables interrupts. If pending interrupts + * are unmasked, an interrupt will be triggered. + * + * @param[in] ipc IPC handle + * @param[in] resource MU channel + * @param[in] group group the interrupts are in + * @param[in] mask mask of interrupts to affect + * @param[in] enable state to change interrupts to + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if group invalid + */ +sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, + sc_irq_group_t group, uint32_t mask, sc_bool_t enable); + +/*! + * This function returns the current interrupt status (regardless if + * masked). Automatically clears pending interrupts. + * + * @param[in] ipc IPC handle + * @param[in] resource MU channel + * @param[in] group groups the interrupts are in + * @param[in] status status of interrupts + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if group invalid + * + * The returned \a status may show interrupts pending that are + * currently masked. + */ +sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, + sc_irq_group_t group, uint32_t *status); + +#endif /* SC_IRQ_API_H */ + +/**@}*/ + diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h new file mode 100755 index 0000000000..210dd04c7c --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h @@ -0,0 +1,523 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file containing the public API for the System Controller (SC) + * Miscellaneous (MISC) function. + * + * @addtogroup MISC_SVC (SVC) Miscellaneous Service + * + * Module for the Miscellaneous (MISC) service. + * + * @{ + */ + +#ifndef SC_MISC_API_H +#define SC_MISC_API_H + +/* Includes */ + +#include <asm/arch/sci/types.h> +#include <asm/arch/sci/svc/rm/api.h> + +/* Defines */ + +/*! + * @name Defines for type widths + */ +/*@{*/ +#define SC_MISC_DMA_GRP_W 5U /*!< Width of sc_misc_dma_group_t */ +/*@}*/ + +/*! Max DMA channel priority group */ +#define SC_MISC_DMA_GRP_MAX 31U + +/*! + * @name Defines for sc_misc_boot_status_t + */ +/*@{*/ +#define SC_MISC_BOOT_STATUS_SUCCESS 0U /*!< Success */ +#define SC_MISC_BOOT_STATUS_SECURITY 1U /*!< Security violation */ +/*@}*/ + +/*! + * @name Defines for sc_misc_seco_auth_cmd_t + */ +/*@{*/ +#define SC_MISC_SECO_AUTH_SECO_FW 0U /*!< SECO Firmware */ +#define SC_MISC_SECO_AUTH_HDMI_TX_FW 1U /*!< HDMI TX Firmware */ +#define SC_MISC_SECO_AUTH_HDMI_RX_FW 2U /*!< HDMI RX Firmware */ +/*@}*/ + +/*! + * @name Defines for sc_misc_temp_t + */ +/*@{*/ +#define SC_MISC_TEMP 0U /*!< Temp sensor */ +#define SC_MISC_TEMP_HIGH 1U /*!< Temp high alarm */ +#define SC_MISC_TEMP_LOW 2U /*!< Temp low alarm */ +/*@}*/ + +/*! + * @name Defines for sc_misc_seco_auth_cmd_t + */ +/*@{*/ +#define SC_MISC_AUTH_CONTAINER 0U /*!< Authenticate container */ +#define SC_MISC_VERIFY_IMAGE 1U /*!< Verify image */ +#define SC_MISC_REL_CONTAINER 2U /*!< Release container */ +/*@}*/ + +/* Types */ + +/*! + * This type is used to store a DMA channel priority group. + */ +typedef uint8_t sc_misc_dma_group_t; + +/*! + * This type is used report boot status. + */ +typedef uint8_t sc_misc_boot_status_t; + +/*! + * This type is used to issue SECO authenticate commands. + */ +typedef uint8_t sc_misc_seco_auth_cmd_t; + +/*! + * This type is used report boot status. + */ +typedef uint8_t sc_misc_temp_t; + +/* Functions */ + +/*! + * @name Control Functions + * @{ + */ + +/*! + * This function sets a miscellaneous control value. + * + * @param[in] ipc IPC handle + * @param[in] resource resource the control is associated with + * @param[in] ctrl control to change + * @param[in] val value to apply to the control + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent + * of the owner + * + * Refer to the [Control List](@ref CONTROLS) for valid control values. + */ +sc_err_t sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource, + sc_ctrl_t ctrl, uint32_t val); + +/*! + * This function gets a miscellaneous control value. + * + * @param[in] ipc IPC handle + * @param[in] resource resource the control is associated with + * @param[in] ctrl control to get + * @param[out] val pointer to return the control value + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent + * of the owner + * + * Refer to the [Control List](@ref CONTROLS) for valid control values. + */ +sc_err_t sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, + sc_ctrl_t ctrl, uint32_t *val); + +/* @} */ + +/*! + * @name DMA Functions + * @{ + */ + +/*! + * This function configures the max DMA channel priority group for a + * partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to assign \a max + * @param[in] max max priority group (0-31) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the parent + * of the affected partition + * + * Valid \a max range is 0-31 with 0 being the lowest and 31 the highest. + * Default is the max priority group for the parent partition of \a pt. + */ +sc_err_t sc_misc_set_max_dma_group(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_misc_dma_group_t max); + +/*! + * This function configures the priority group for a DMA channel. + * + * @param[in] ipc IPC handle + * @param[in] resource DMA channel resource + * @param[in] group priority group (0-31) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the owner or parent + * of the owner of the DMA channel + * + * Valid \a group range is 0-31 with 0 being the lowest and 31 the highest. + * The max value of \a group is limited by the partition max set using + * sc_misc_set_max_dma_group(). + */ +sc_err_t sc_misc_set_dma_group(sc_ipc_t ipc, sc_rsrc_t resource, + sc_misc_dma_group_t group); + +/* @} */ + +/*! + * @name Security Functions + * @{ + */ + +/*! + * This function loads a SECO image. + * + * @param[in] ipc IPC handle + * @param[in] addr_src address of image source + * @param[in] addr_dst address of image destination + * @param[in] len lenth of image to load + * @param[in] fw SC_TRUE = firmware load + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_UNAVAILABLE if SECO not available + * + * This is used to load images via the SECO. Examples include SECO + * Firmware and IVT/CSF data used for authentication. These are usually + * loaded into SECO TCM. \a addr_src is in secure memory. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_misc_seco_image_load(sc_ipc_t ipc, sc_faddr_t addr_src, + sc_faddr_t addr_dst, uint32_t len, sc_bool_t fw); + +/*! + * This function is used to authenticate a SECO image or command. + * + * @param[in] ipc IPC handle + * @param[in] cmd authenticate command + * @param[in] addr address of/or metadata + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_UNAVAILABLE if SECO not available + * + * This is used to authenticate a SECO image or issue a security + * command. \a addr often points to an container. It is also + * just data (or even unused) for some commands. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_misc_seco_authenticate(sc_ipc_t ipc, + sc_misc_seco_auth_cmd_t cmd, sc_faddr_t addr); + +/*! + * This function securely writes a group of fuse words. + * + * @param[in] ipc IPC handle + * @param[in] addr address of message block + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available + * + * Note \a addr must be a pointer into secure RAM. The contents at + * this location are a signed fuse command message block. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_misc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function securely enables debug. + * + * @param[in] ipc IPC handle + * @param[in] addr address of message block + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available + * + * Note \a addr must be a pointer into secure RAM. The contents at + * this location are a signed fuse command message block. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_misc_seco_enable_debug(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function updates the lifecycle of the device. + * + * @param[in] ipc IPC handle + * @param[in] lifecycle new lifecycle + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_misc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t lifecycle); + +/*! + * This function securely reverses the lifecycle. + * + * @param[in] ipc IPC handle + * @param[in] addr address of message block + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available + * + * Note \a addr must be a pointer into secure RAM. The contents at + * this location are a signed fuse command message block. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_misc_seco_return_lifecycle(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function is used to return the SECO FW build info. + * + * @param[in] ipc IPC handle + * @param[out] version pointer to return build number + * @param[out] commit pointer to return commit ID (git SHA-1) + */ +void sc_misc_seco_build_info(sc_ipc_t ipc, uint32_t *version, + uint32_t *commit); + +/* @} */ + +/*! + * @name Debug Functions + * @{ + */ + +/*! + * This function is used output a debug character from the SCU UART. + * + * @param[in] ipc IPC handle + * @param[in] ch character to output + */ +void sc_misc_debug_out(sc_ipc_t ipc, uint8_t ch); + +/*! + * This function starts/stops emulation waveform capture. + * + * @param[in] ipc IPC handle + * @param[in] enable flag to enable/disable capture + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_UNAVAILABLE if not running on emulation + */ +sc_err_t sc_misc_waveform_capture(sc_ipc_t ipc, sc_bool_t enable); + +/*! + * This function is used to return the SCFW build info. + * + * @param[in] ipc IPC handle + * @param[out] build pointer to return build number + * @param[out] commit pointer to return commit ID (git SHA-1) + */ +void sc_misc_build_info(sc_ipc_t ipc, uint32_t *build, + uint32_t *commit); + +/*! + * This function is used to return the device's unique ID. + * + * @param[in] ipc IPC handle + * @param[out] id_l pointer to return lower 32-bit of ID [31:0] + * @param[out] id_h pointer to return upper 32-bits of ID [63:32] + */ +void sc_misc_unique_id(sc_ipc_t ipc, uint32_t *id_l, + uint32_t *id_h); + +/* @} */ + +/*! + * @name Other Functions + * @{ + */ + +/*! + * This function configures the ARI match value for PCIe/SATA resources. + * + * @param[in] ipc IPC handle + * @param[in] resource match resource + * @param[in] resource_mst PCIe/SATA master to match + * @param[in] ari ARI to match + * @param[in] enable enable match or not + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the owner or parent + * of the owner of the resource and translation + * + * For PCIe, the ARI is the 16-bit value that includes the bus number, + * device number, and function number. For SATA, this value includes the + * FISType and PM_Port. + */ +sc_err_t sc_misc_set_ari(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rsrc_t resource_mst, uint16_t ari, sc_bool_t enable); + +/*! + * This function reports boot status. + * + * @param[in] ipc IPC handle + * @param[in] status boot status + * + * This is used by SW partitions to report status of boot. This is + * normally used to report a boot failure. + */ +void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status); + +/*! + * This function tells the SCFW that a CPU is done booting. + * + * @param[in] ipc IPC handle + * @param[in] cpu CPU that is done booting + * + * This is called by early booting CPUs to report they are done with + * initialization. After starting early CPUs, the SCFW halts the + * booting process until they are done. During this time, early + * CPUs can call the SCFW with lower latency as the SCFW is idle. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the CPU owner + */ +sc_err_t sc_misc_boot_done(sc_ipc_t ipc, sc_rsrc_t cpu); + +/*! + * This function reads a given fuse word index. + * + * @param[in] ipc IPC handle + * @param[in] word fuse word index + * @param[out] val fuse read value + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_NOACCESS if read operation failed + * - SC_ERR_LOCKED if read operation is locked + */ +sc_err_t sc_misc_otp_fuse_read(sc_ipc_t ipc, uint32_t word, uint32_t *val); + +/*! + * This function writes a given fuse word index. + * + * @param[in] ipc IPC handle + * @param[in] word fuse word index + * @param[in] val fuse write value + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_NOACCESS if write operation failed + * - SC_ERR_LOCKED if write operation is locked + */ +sc_err_t sc_misc_otp_fuse_write(sc_ipc_t ipc, uint32_t word, uint32_t val); + +/*! + * This function sets a temp sensor alarm. + * + * @param[in] ipc IPC handle + * @param[in] resource resource with sensor + * @param[in] temp alarm to set + * @param[in] celsius whole part of temp to set + * @param[in] tenths fractional part of temp to set + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * This function will enable the alarm interrupt if the temp requested is + * not the min/max temp. This enable automatically clears when the alarm + * occurs and this function has to be called again to re-enable. + * + * Return errors codes: + * - SC_ERR_PARM if parameters invalid + */ +sc_err_t sc_misc_set_temp(sc_ipc_t ipc, sc_rsrc_t resource, + sc_misc_temp_t temp, int16_t celsius, int8_t tenths); + +/*! + * This function gets a temp sensor value. + * + * @param[in] ipc IPC handle + * @param[in] resource resource with sensor + * @param[in] temp value to get (sensor or alarm) + * @param[out] celsius whole part of temp to get + * @param[out] tenths fractional part of temp to get + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if parameters invalid + */ +sc_err_t sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, + sc_misc_temp_t temp, int16_t *celsius, int8_t *tenths); + +/*! + * This function returns the boot device. + * + * @param[in] ipc IPC handle + * @param[out] dev pointer to return boot device + */ +void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *dev); + +/*! + * This function returns the current status of the ON/OFF button. + * + * @param[in] ipc IPC handle + * @param[out] status pointer to return button status + */ +void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status); + +/* @} */ + +#endif /* SC_MISC_API_H */ + +/**@}*/ + diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h new file mode 100755 index 0000000000..76cb0dab9a --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h @@ -0,0 +1,568 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file containing the public API for the System Controller (SC) + * Pad Control (PAD) function. + * + * @addtogroup PAD_SVC (SVC) Pad Service + * + * Module for the Pad Control (PAD) service. + * + * @details + * + * Pad configuration is managed by SC firmware. The pad configuration + * features supported by the SC firmware include: + * + * - Configuring the mux, input/output connection, and low-power isolation + mode. + * - Configuring the technology-specific pad setting such as drive strength, + * pullup/pulldown, etc. + * - Configuring compensation for pad groups with dual voltage capability. + * + * Pad functions fall into one of three categories. Generic functions are + * common to all SoCs and all process technologies. SoC functions are raw + * low-level functions. Technology-specific functions are specific to the + * process technology. + * + * The list of pads is SoC specific. Refer to the SoC [Pad List](@ref PADS) + * for valid pad values. Note that all pads exist on a die but may or + * may not be brought out by the specific package. Mapping of pads to + * package pins/balls is documented in the associated Data Sheet. Some pads + * may not be brought out because the part (die+package) is defeatured and + * some pads may connect to the substrate in the package. + * + * Some pads (SC_P_COMP_*) that can be specified are not individual pads + * but are in fact pad groups. These groups have additional configuration + * that can be done using the sc_pad_set_gp_28fdsoi_comp() function. More + * info on these can be found in the associated Reference Manual. + * + * Pads are managed as a resource by the Resource Manager (RM). They have + * assigned owners and only the owners can configure the pads. Some of the + * pads are reserved for use by the SCFW itself and this can be overriden + * with the implementation of board_config_sc(). Additionally, pads may + * be assigned to various other partitions via the implementation of + * board_system_config(). + * + * Note muxing two input pads to the same IP functional signal will + * result in undefined behavior. + * @{ + */ + +#ifndef SC_PAD_API_H +#define SC_PAD_API_H + +/* Includes */ + +#include <asm/arch/sci/types.h> +#include <asm/arch/sci/svc/rm/api.h> + +/* Defines */ + +/*! + * @name Defines for type widths + */ +/*@{*/ +#define SC_PAD_MUX_W 3U /*!< Width of mux parameter */ +/*@}*/ + +/*! + * @name Defines for sc_pad_config_t + */ +/*@{*/ +#define SC_PAD_CONFIG_NORMAL 0U /*!< Normal */ +#define SC_PAD_CONFIG_OD 1U /*!< Open Drain */ +#define SC_PAD_CONFIG_OD_IN 2U /*!< Open Drain and input */ +#define SC_PAD_CONFIG_OUT_IN 3U /*!< Output and input */ +/*@}*/ + +/*! + * @name Defines for sc_pad_iso_t + */ +/*@{*/ +#define SC_PAD_ISO_OFF 0U /*!< ISO latch is transparent */ +#define SC_PAD_ISO_EARLY 1U /*!< Follow EARLY_ISO */ +#define SC_PAD_ISO_LATE 2U /*!< Follow LATE_ISO */ +#define SC_PAD_ISO_ON 3U /*!< ISO latched data is held */ +/*@}*/ + +/*! + * @name Defines for sc_pad_28fdsoi_dse_t + */ +/*@{*/ +#define SC_PAD_28FDSOI_DSE_18V_1MA 0U /*!< Drive strength of 1mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_2MA 1U /*!< Drive strength of 2mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_4MA 2U /*!< Drive strength of 4mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_6MA 3U /*!< Drive strength of 6mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_8MA 4U /*!< Drive strength of 8mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_10MA 5U /*!< Drive strength of 10mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_12MA 6U /*!< Drive strength of 12mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_HS 7U /*!< High-speed drive strength for 1.8v */ +#define SC_PAD_28FDSOI_DSE_33V_2MA 0U /*!< Drive strength of 2mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_4MA 1U /*!< Drive strength of 4mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_8MA 2U /*!< Drive strength of 8mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_12MA 3U /*!< Drive strength of 12mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_DV_HIGH 0U /*!< High drive strength for dual volt */ +#define SC_PAD_28FDSOI_DSE_DV_LOW 1U /*!< Low drive strength for dual volt */ +/*@}*/ + +/*! + * @name Defines for sc_pad_28fdsoi_ps_t + */ +/*@{*/ +#define SC_PAD_28FDSOI_PS_KEEPER 0U /*!< Bus-keeper (only valid for 1.8v) */ +#define SC_PAD_28FDSOI_PS_PU 1U /*!< Pull-up */ +#define SC_PAD_28FDSOI_PS_PD 2U /*!< Pull-down */ +#define SC_PAD_28FDSOI_PS_NONE 3U /*!< No pull (disabled) */ +/*@}*/ + +/*! + * @name Defines for sc_pad_28fdsoi_pus_t + */ +/*@{*/ +#define SC_PAD_28FDSOI_PUS_30K_PD 0U /*!< 30K pull-down */ +#define SC_PAD_28FDSOI_PUS_100K_PU 1U /*!< 100K pull-up */ +#define SC_PAD_28FDSOI_PUS_3K_PU 2U /*!< 3K pull-up */ +#define SC_PAD_28FDSOI_PUS_30K_PU 3U /*!< 30K pull-up */ +/*@}*/ + +/*! + * @name Defines for sc_pad_wakeup_t + */ +/*@{*/ +#define SC_PAD_WAKEUP_OFF 0U /*!< Off */ +#define SC_PAD_WAKEUP_CLEAR 1U /*!< Clears pending flag */ +#define SC_PAD_WAKEUP_LOW_LVL 4U /*!< Low level */ +#define SC_PAD_WAKEUP_FALL_EDGE 5U /*!< Falling edge */ +#define SC_PAD_WAKEUP_RISE_EDGE 6U /*!< Rising edge */ +#define SC_PAD_WAKEUP_HIGH_LVL 7U /*!< High-level */ +/*@}*/ + +/* Types */ + +/*! + * This type is used to declare a pad config. It determines how the + * output data is driven, pull-up is controlled, and input signal is + * connected. Normal and OD are typical and only connect the input + * when the output is not driven. The IN options are less common and + * force an input connection even when driving the output. + */ +typedef uint8_t sc_pad_config_t; + +/*! + * This type is used to declare a pad low-power isolation config. + * ISO_LATE is the most common setting. ISO_EARLY is only used when + * an output pad is directly determined by another input pad. The + * other two are only used when SW wants to directly contol isolation. + */ +typedef uint8_t sc_pad_iso_t; + +/*! + * This type is used to declare a drive strength. Note it is specific + * to 28FDSOI. Also note that valid values depend on the pad type. + */ +typedef uint8_t sc_pad_28fdsoi_dse_t; + +/*! + * This type is used to declare a pull select. Note it is specific + * to 28FDSOI. + */ +typedef uint8_t sc_pad_28fdsoi_ps_t; + +/*! + * This type is used to declare a pull-up select. Note it is specific + * to 28FDSOI HSIC pads. + */ +typedef uint8_t sc_pad_28fdsoi_pus_t; + +/*! + * This type is used to declare a wakeup mode of a pad. + */ +typedef uint8_t sc_pad_wakeup_t; + +/* Functions */ + +/*! + * @name Generic Functions + * @{ + */ + +/*! + * This function configures the mux settings for a pad. This includes + * the signal mux, pad config, and low-power isolation mode. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] mux mux setting + * @param[in] config pad config + * @param[in] iso low-power isolation mode + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Note muxing two input pads to the same IP functional signal will + * result in undefined behavior. + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad, + uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso); + +/*! + * This function gets the mux settings for a pad. This includes + * the signal mux, pad config, and low-power isolation mode. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] mux pointer to return mux setting + * @param[out] config pointer to return pad config + * @param[out] iso pointer to return low-power isolation mode + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pad_t pad, + uint8_t *mux, sc_pad_config_t *config, sc_pad_iso_t *iso); + +/*! + * This function configures the general purpose pad control. This + * is technology dependent and includes things like drive strength, + * slew rate, pull up/down, etc. Refer to the SoC Reference Manual + * for bit field details. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] ctrl control value to set + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t ctrl); + +/*! + * This function gets the general purpose pad control. This + * is technology dependent and includes things like drive strength, + * slew rate, pull up/down, etc. Refer to the SoC Reference Manual + * for bit field details. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] ctrl pointer to return control value + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl); + +/*! + * This function configures the wakeup mode of the pad. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] wakeup wakeup to set + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_wakeup_t wakeup); + +/*! + * This function gets the wakeup mode of a pad. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] wakeup pointer to return wakeup + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_wakeup_t *wakeup); + +/*! + * This function configures a pad. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] mux mux setting + * @param[in] config pad config + * @param[in] iso low-power isolation mode + * @param[in] ctrl control value + * @param[in] wakeup wakeup to set + * + * @see sc_pad_set_mux(). + * @see sc_pad_set_gp(). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Note muxing two input pads to the same IP functional signal will + * result in undefined behavior. + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux, + sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl, + sc_pad_wakeup_t wakeup); + +/*! + * This function gets a pad's config. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] mux pointer to return mux setting + * @param[out] config pointer to return pad config + * @param[out] iso pointer to return low-power isolation mode + * @param[out] ctrl pointer to return control value + * @param[out] wakeup pointer to return wakeup to set + * + * @see sc_pad_set_mux(). + * @see sc_pad_set_gp(). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t *mux, + sc_pad_config_t *config, sc_pad_iso_t *iso, uint32_t *ctrl, + sc_pad_wakeup_t *wakeup); + +/* @} */ + +/*! + * @name SoC Specific Functions + * @{ + */ + +/*! + * This function configures the settings for a pad. This setting is SoC + * specific. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] val value to set + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, uint32_t val); + +/*! + * This function gets the settings for a pad. This setting is SoC + * specific. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] val pointer to return setting + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val); + +/* @} */ + +/*! + * @name Technology Specific Functions + * @{ + */ + +/*! + * This function configures the pad control specific to 28FDSOI. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] dse drive strength + * @param[in] ps pull select + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, + * - SC_ERR_UNAVAILABLE if process not applicable + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps); + +/*! + * This function gets the pad control specific to 28FDSOI. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] dse pointer to return drive strength + * @param[out] ps pointer to return pull select + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, + * - SC_ERR_UNAVAILABLE if process not applicable + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t *dse, sc_pad_28fdsoi_ps_t *ps); + +/*! + * This function configures the pad control specific to 28FDSOI. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] dse drive strength + * @param[in] hys hysteresis + * @param[in] pus pull-up select + * @param[in] pke pull keeper enable + * @param[in] pue pull-up enable + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, + * - SC_ERR_UNAVAILABLE if process not applicable + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t dse, sc_bool_t hys, sc_pad_28fdsoi_pus_t pus, + sc_bool_t pke, sc_bool_t pue); + +/*! + * This function gets the pad control specific to 28FDSOI. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] dse pointer to return drive strength + * @param[out] hys pointer to return hysteresis + * @param[out] pus pointer to return pull-up select + * @param[out] pke pointer to return pull keeper enable + * @param[out] pue pointer to return pull-up enable + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, + * - SC_ERR_UNAVAILABLE if process not applicable + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys, sc_pad_28fdsoi_pus_t *pus, + sc_bool_t *pke, sc_bool_t *pue); + +/*! + * This function configures the compensation control specific to 28FDSOI. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] compen compensation/freeze mode + * @param[in] fastfrz fast freeze + * @param[in] rasrcp compensation code for PMOS + * @param[in] rasrcn compensation code for NMOS + * @param[in] nasrc_sel NASRC read select + * @param[in] psw_ovr 2.5v override + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, + * - SC_ERR_UNAVAILABLE if process not applicable + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + * + * Note \a psw_ovr is only applicable to pads supporting 2.5 volt + * operation (e.g. some Ethernet pads). + */ +sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad, + uint8_t compen, sc_bool_t fastfrz, uint8_t rasrcp, uint8_t rasrcn, + sc_bool_t nasrc_sel, sc_bool_t psw_ovr); + +/*! + * This function gets the compensation control specific to 28FDSOI. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] compen pointer to return compensation/freeze mode + * @param[out] fastfrz pointer to return fast freeze + * @param[out] rasrcp pointer to return compensation code for PMOS + * @param[out] rasrcn pointer to return compensation code for NMOS + * @param[out] nasrc_sel pointer to return NASRC read select + * @param[out] compok pointer to return compensation status + * @param[out] nasrc pointer to return NASRCP/NASRCN + * @param[out] psw_ovr pointer to return the 2.5v override + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, + * - SC_ERR_UNAVAILABLE if process not applicable + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad, + uint8_t *compen, sc_bool_t *fastfrz, uint8_t *rasrcp, uint8_t *rasrcn, + sc_bool_t *nasrc_sel, sc_bool_t *compok, uint8_t *nasrc, sc_bool_t *psw_ovr); + +/* @} */ + +#endif /* SC_PAD_API_H */ + +/**@}*/ + diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h new file mode 100755 index 0000000000..25d8f063e6 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h @@ -0,0 +1,686 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file containing the public API for the System Controller (SC) + * Power Management (PM) function. This includes functions for power state + * control, clock control, reset control, and wake-up event control. + * + * @addtogroup PM_SVC (SVC) Power Management Service + * + * Module for the Power Management (PM) service. + * + * @{ + */ + +#ifndef SC_PM_API_H +#define SC_PM_API_H + +/* Includes */ + +#include <asm/arch/sci/types.h> +#include <asm/arch/sci/svc/rm/api.h> + +/* Defines */ + +/*! + * @name Defines for type widths + */ +/*@{*/ +#define SC_PM_POWER_MODE_W 2U /*!< Width of sc_pm_power_mode_t */ +#define SC_PM_CLOCK_MODE_W 3U /*!< Width of sc_pm_clock_mode_t */ +#define SC_PM_RESET_TYPE_W 2U /*!< Width of sc_pm_reset_type_t */ +#define SC_PM_RESET_REASON_W 3U /*!< Width of sc_pm_reset_reason_t */ +/*@}*/ + +/*! + * @name Defines for clock indexes (sc_pm_clk_t) + */ +/*@{*/ +/*@}*/ + +/*! + * @name Defines for ALL parameters + */ +/*@{*/ +#define SC_PM_CLK_ALL UINT8_MAX /*!< All clocks */ +/*@}*/ + +/*! + * @name Defines for sc_pm_power_mode_t + */ +/*@{*/ +#define SC_PM_PW_MODE_OFF 0U /*!< Power off */ +#define SC_PM_PW_MODE_STBY 1U /*!< Power in standby */ +#define SC_PM_PW_MODE_LP 2U /*!< Power in low-power */ +#define SC_PM_PW_MODE_ON 3U /*!< Power on */ +/*@}*/ + +/*! + * @name Defines for sc_pm_clk_t + */ +/*@{*/ +#define SC_PM_CLK_SLV_BUS 0U /*!< Slave bus clock */ +#define SC_PM_CLK_MST_BUS 1U /*!< Master bus clock */ +#define SC_PM_CLK_PER 2U /*!< Peripheral clock */ +#define SC_PM_CLK_PHY 3U /*!< Phy clock */ +#define SC_PM_CLK_MISC 4U /*!< Misc clock */ +#define SC_PM_CLK_MISC0 0U /*!< Misc 0 clock */ +#define SC_PM_CLK_MISC1 1U /*!< Misc 1 clock */ +#define SC_PM_CLK_MISC2 2U /*!< Misc 2 clock */ +#define SC_PM_CLK_MISC3 3U /*!< Misc 3 clock */ +#define SC_PM_CLK_MISC4 4U /*!< Misc 4 clock */ +#define SC_PM_CLK_CPU 2U /*!< CPU clock */ +#define SC_PM_CLK_PLL 4U /*!< PLL */ +#define SC_PM_CLK_BYPASS 4U /*!< Bypass clock */ +/*@}*/ + +/*! + * @name Defines for sc_pm_clk_mode_t + */ +/*@{*/ +#define SC_PM_CLK_MODE_ROM_INIT 0U /*!< Clock is initialized by ROM. */ +#define SC_PM_CLK_MODE_OFF 1U /*!< Clock is disabled */ +#define SC_PM_CLK_MODE_ON 2U /*!< Clock is enabled. */ +#define SC_PM_CLK_MODE_AUTOGATE_SW 3U /*!< Clock is in SW autogate mode */ +#define SC_PM_CLK_MODE_AUTOGATE_HW 4U /*!< Clock is in HW autogate mode */ +#define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /*!< Clock is in SW-HW autogate mode */ +/*@}*/ + +/*! + * @name Defines for sc_pm_clk_parent_t + */ +/*@{*/ +#define SC_PM_PARENT_XTAL 0U /*!< Parent is XTAL. */ +#define SC_PM_PARENT_PLL0 1U /*!< Parent is PLL0 */ +#define SC_PM_PARENT_PLL1 2U /*!< Parent is PLL1 or PLL0/2 */ +#define SC_PM_PARENT_PLL2 3U /*!< Parent in PLL2 or PLL0/4 */ +#define SC_PM_PARENT_BYPS 4U /*!< Parent is a bypass clock. */ +/*@}*/ + +/*! + * @name Defines for sc_pm_reset_type_t + */ +/*@{*/ +#define SC_PM_RESET_TYPE_COLD 0U /*!< Cold reset */ +#define SC_PM_RESET_TYPE_WARM 1U /*!< Warm reset */ +#define SC_PM_RESET_TYPE_BOARD 2U /*!< Board reset */ +/*@}*/ + +/*! + * @name Defines for sc_pm_reset_cause_t + */ +/*@{*/ +#define SC_PM_RESET_CAUSE_TEMP 0U /*!< Reset due to temp panic alarm */ +#define SC_PM_RESET_CAUSE_FAULT 1U /*!< Reset due to fault exception */ +#define SC_PM_RESET_CAUSE_IRQ 2U /*!< Reset due to SCU reset IRQ */ +#define SC_PM_RESET_CAUSE_WDOG 3U /*!< Reset due to SW WDOG */ +#define SC_PM_RESET_CAUSE_API 4U /*!< Reset due to pm_reset() or monitor */ +/*@}*/ + +/*! + * @name Defines for sc_pm_reset_reason_t + */ +/*@{*/ +#define SC_PM_RESET_REASON_POR 0U /*!< Power on reset */ +#define SC_PM_RESET_REASON_WARM 1U /*!< Warm reset */ +#define SC_PM_RESET_REASON_SW 2U /*!< Software reset */ +#define SC_PM_RESET_REASON_WDOG 3U /*!< Watchdog reset */ +#define SC_PM_RESET_REASON_LOCKUP 4U /*!< Lockup reset */ +#define SC_PM_RESET_REASON_TAMPER 5U /*!< Tamper reset */ +#define SC_PM_RESET_REASON_TEMP 6U /*!< Temp reset */ +#define SC_PM_RESET_REASON_LOW_VOLT 7U /*!< Low voltage reset */ +/*@}*/ + +/*! + * @name Defines for sc_pm_sys_if_t + */ +/*@{*/ +#define SC_PM_SYS_IF_INTERCONNECT 0U /*!< System interconnect */ +#define SC_PM_SYS_IF_MU 1U /*!< AP -> SCU message units */ +#define SC_PM_SYS_IF_OCMEM 2U /*!< On-chip memory (ROM/OCRAM) */ +#define SC_PM_SYS_IF_DDR 3U /*!< DDR memory */ +/*@}*/ + +/*! + * @name Defines for sc_pm_wake_src_t + */ +/*@{*/ +#define SC_PM_WAKE_SRC_NONE 0U /*!< No wake source, used for self-kill */ +#define SC_PM_WAKE_SRC_SCU 1U /*!< Wakeup from SCU to resume CPU (IRQSTEER & GIC powered down) */ +#define SC_PM_WAKE_SRC_IRQSTEER 2U /*!< Wakeup from IRQSTEER to resume CPU (GIC powered down) */ +#define SC_PM_WAKE_SRC_IRQSTEER_GIC 3U /*!< Wakeup from IRQSTEER+GIC to wake CPU (GIC clock gated) */ +#define SC_PM_WAKE_SRC_GIC 4U /*!< Wakeup from GIC to wake CPU */ +/*@}*/ + +/* Types */ + +/*! + * This type is used to declare a power mode. Note resources only use + * SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON. The other modes are used only + * as system power modes. + */ +typedef uint8_t sc_pm_power_mode_t; + +/*! + * This type is used to declare a clock. + */ +typedef uint8_t sc_pm_clk_t; + +/*! + * This type is used to declare a clock mode. + */ +typedef uint8_t sc_pm_clk_mode_t; + +/*! + * This type is used to declare the clock parent. + */ +typedef uint8_t sc_pm_clk_parent_t; + +/*! + * This type is used to declare clock rates. + */ +typedef uint32_t sc_pm_clock_rate_t; + +/*! + * This type is used to declare a desired reset type. + */ +typedef uint8_t sc_pm_reset_type_t; + +/*! + * This type is used to declare a desired reset type. + */ +typedef uint8_t sc_pm_reset_cause; + +/*! + * This type is used to declare a reason for a reset. + */ +typedef uint8_t sc_pm_reset_reason_t; + +/*! + * This type is used to specify a system-level interface to be power managed. + */ +typedef uint8_t sc_pm_sys_if_t; + +/*! + * This type is used to specify a wake source for CPU resources. + */ +typedef uint8_t sc_pm_wake_src_t; + +/* Functions */ + +/*! + * @name Power Functions + * @{ + */ + +/*! + * This function sets the system power mode. Only the owner of the + * SC_R_SYSTEM resource can do this. + * + * @param[in] ipc IPC handle + * @param[in] mode power mode to apply + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid mode, + * - SC_ERR_NOACCESS if caller not the owner of SC_R_SYSTEM + * + * @see sc_pm_set_sys_power_mode(). + */ +sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_pm_power_mode_t mode); + +/*! + * This function sets the power mode of a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition + * @param[in] mode power mode to apply + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid partition or mode, + * - SC_ERR_NOACCESS if caller's partition is not the owner or + * parent of \a pt + * + * The power mode of the partitions is a max power any resource will + * be set to. Calling this will result in all resources owned + * by \a pt to have their power changed to the lower of \a mode or the + * individual resource mode set using sc_pm_set_resource_power_mode(). + */ +sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_pm_power_mode_t mode); + +/*! + * This function gets the power mode of a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition + * @param[out] mode pointer to return power mode + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid partition + */ +sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_pm_power_mode_t *mode); + +/*! + * This function sets the power mode of a resource. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] mode power mode to apply + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or mode, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent of the owner + * + * Resources must be@SC_PM_PW_MODE_LP mode or higher to access them, + * otherwise the master will get a bus error or hang. + * + * This function will record the individual resource power mode + * and change it if the requested mode is lower than or equal to the + * partition power mode set with sc_pm_set_partition_power_mode(). + * In other words, the power mode of the resource will be the minimum + * of the resource power mode and the partition power mode. + * + * Note some resources are still not accessible even when powered up if bus + * transactions go through a fabric not powered up. Examples of this are + * resources in display and capture subsystems which require the display + * controller or the imaging subsytem to be powered up first. + * + * Not that resources are grouped into power domains by the underlying + * hardware. If any resource in the domain is on, the entire power domain + * will be on. Other power domains required to access the resource will + * also be turned on. Clocks required to access the peripheral will be + * turned on. Refer to the SoC RM for more info on power domains and access + * infrastructure (bus fabrics, clock domains, etc.). + */ +sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode); + +/*! + * This function gets the power mode of a resource. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[out] mode pointer to return power mode + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Note only SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON are valid. The value + * returned does not reflect the power mode of the partition.. + */ +sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t *mode); + +/*! + * This function requests the low power mode some of the resources + * can enter based on their state. This API is only valid for the + * following resources : SC_R_A53, SC_R_A53_0, SC_R_A53_1, SC_A53_2, + * SC_A53_3, SC_R_A72, SC_R_A72_0, SC_R_A72_1, SC_R_CC1, SC_R_A35, + * SC_R_A35_0, SC_R_A35_1, SC_R_A35_2, SC_R_A35_3. + * For all other resources it will return SC_ERR_PARAM. + * This function will set the low power mode the cores, cluster + * and cluster associated resources will enter when all the cores + * in a given cluster execute WFI + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] mode power mode to apply + * + * @return Returns an error code (SC_ERR_NONE = success). + * + */ +sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode); + +/*! + * This function requests low-power mode entry for CPU/cluster + * resources. This API is only valid for the following resources: + * SC_R_A53, SC_R_A53_x, SC_R_A72, SC_R_A72_x, SC_R_A35, SC_R_A35_x, + * SC_R_CCI. For all other resources it will return SC_ERR_PARAM. + * For individual core resources, the specified power mode + * and wake source will be applied after the core has entered + * WFI. For cluster resources, the specified power mode is + * applied after all cores in the cluster have entered low-power mode. + * For multicluster resources, the specified power mode is applied + * after all clusters have reached low-power mode. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] mode power mode to apply + * @param[in] wake_src wake source for low-power exit + * + * @return Returns an error code (SC_ERR_NONE = success). + * + */ +sc_err_t sc_pm_req_cpu_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode, sc_pm_wake_src_t wake_src); + +/*! + * This function is used to set the resume address of a CPU. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the CPU resource + * @param[in] address 64-bit resume address + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or address, + * - SC_ERR_NOACCESS if caller's partition is not the parent of the + * resource (CPU) owner + */ +sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource, + sc_faddr_t address); + +/*! + * This function is used to set parameters for CPU resume from + * low-power mode. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the CPU resource + * @param[in] isPrimary set SC_TRUE if primary wake CPU + * @param[in] address 64-bit resume address + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or address, + * - SC_ERR_NOACCESS if caller's partition is not the parent of the + * resource (CPU) owner + */ +sc_err_t sc_pm_set_cpu_resume(sc_ipc_t ipc, sc_rsrc_t resource, + sc_bool_t isPrimary, sc_faddr_t address); + +/*! + * This function requests the power mode configuration for system-level + * interfaces including messaging units, interconnect, and memories. This API + * is only valid for the following resources : SC_R_A53, SC_R_A72, and + * SC_R_M4_x_PID_y. For all other resources, it will return SC_ERR_PARAM. + * The requested power mode will be captured and applied to system-level + * resources as system conditions allow. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] sys_if system-level interface to be configured + * @param[in] hpm high-power mode for the system interface + * @param[in] lpm low-power mode for the system interface + * + * @return Returns an error code (SC_ERR_NONE = success). + * + */ +sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, sc_pm_power_mode_t lpm); + +/* @} */ + +/*! + * @name Clock/PLL Functions + * @{ + */ + +/*! + * This function sets the rate of a resource's clock/PLL. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] clk clock/PLL to affect + * @param[in,out] rate pointer to rate to set, + * return actual rate + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or clock/PLL, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent of the owner, + * - SC_ERR_UNAVAILABLE if clock/PLL not applicable to this resource, + * - SC_ERR_LOCKED if rate locked (usually because shared clock/PLL) + * + * Refer to the [Clock List](@ref CLOCKS) for valid clock/PLL values. + */ +sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); + +/*! + * This function gets the rate of a resource's clock/PLL. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] clk clock/PLL to affect + * @param[out] rate pointer to return rate + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or clock/PLL, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent of the owner, + * - SC_ERR_UNAVAILABLE if clock/PLL not applicable to this resource + * + * Refer to the [Clock List](@ref CLOCKS) for valid clock/PLL values. + */ +sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); + +/*! + * This function enables/disables a resource's clock. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] clk clock to affect + * @param[in] enable enable if SC_TRUE; otherwise disabled + * @param[in] autog HW auto clock gating + * + * If \a resource is SC_R_ALL then all resources owned will be affected. + * No error will be returned. + * + * If \a clk is SC_PM_CLK_ALL, then an error will be returned if any + * of the available clocks returns an error. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or clock, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent of the owner, + * - SC_ERR_UNAVAILABLE if clock not applicable to this resource + * + * Refer to the [Clock List](@ref CLOCKS) for valid clock values. + */ +sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog); + +/*! + * This function sets the parent of a resource's clock. + * This function should only be called when the clock is disabled. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] clk clock to affect + * @param[in] parent New parent of the clock. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or clock, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent of the owner, + * - SC_ERR_UNAVAILABLE if clock not applicable to this resource + * - SC_ERR_BUSY if clock is currently enabled. + * - SC_ERR_NOPOWER if resource not powered + * + * Refer to the [Clock List](@ref CLOCKS) for valid clock values. + */ +sc_err_t sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clk_parent_t parent); + +/*! + * This function gets the parent of a resource's clock. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] clk clock to affect + * @param[out] parent pointer to return parent of clock. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or clock, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent of the owner, + * - SC_ERR_UNAVAILABLE if clock not applicable to this resource + * + * Refer to the [Clock List](@ref CLOCKS) for valid clock values. + */ +sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clk_parent_t *parent); + +/* @} */ + +/*! + * @name Reset Functions + * @{ + */ + +/*! + * This function is used to reset the system. Only the owner of the + * SC_R_SYSTEM resource can do this. + * + * @param[in] ipc IPC handle + * @param[in] type reset type + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid type, + * - SC_ERR_NOACCESS if caller not the owner of SC_R_SYSTEM + * + * If this function returns, then the reset did not occur due to an + * invalid parameter. + */ +sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type); + +/*! + * This function gets a caller's reset reason. + * + * @param[in] ipc IPC handle + * @param[out] reason pointer to return reset reason + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason); + +/*! + * This function is used to boot a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to boot + * @param[in] resource_cpu ID of the CPU resource to start + * @param[in] boot_addr 64-bit boot address + * @param[in] resource_mu ID of the MU that must be powered + * @param[in] resource_dev ID of the boot device that must be powered + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid partition, resource, or addr, + * - SC_ERR_NOACCESS if caller's partition is not the parent of the + * partition to boot + */ +sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_rsrc_t resource_cpu, sc_faddr_t boot_addr, + sc_rsrc_t resource_mu, sc_rsrc_t resource_dev); + +/*! + * This function is used to reboot the caller's partition. + * + * @param[in] ipc IPC handle + * @param[in] type reset type + * + * If \a type is SC_PM_RESET_TYPE_COLD, then most peripherals owned by + * the calling partition will be reset if possible. SC state (partitions, + * power, clocks, etc.) is reset. The boot SW of the booting CPU must be + * able to handle peripherals that that are not reset. + * + * If \a type is SC_PM_RESET_TYPE_WARM, then only the boot CPU is reset. + * SC state (partitions, power, clocks, etc.) are NOT reset. The boot SW + * of the booting CPU must be able to handle peripherals and SC state that + * that are not reset. + * + * If \a type is SC_PM_RESET_TYPE_BOARD, then return with no action. + * + * If this function returns, then the reset did not occur due to an + * invalid parameter. + */ +void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type); + +/*! + * This function is used to reboot a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to reboot + * @param[in] type reset type + * + * If \a type is SC_PM_RESET_TYPE_COLD, then most peripherals owned by + * the calling partition will be reset if possible. SC state (partitions, + * power, clocks, etc.) is reset. The boot SW of the booting CPU must be + * able to handle peripherals that that are not reset. + * + * If \a type is SC_PM_RESET_TYPE_WARM, then only the boot CPU is reset. + * SC state (partitions, power, clocks, etc.) are NOT reset. The boot SW + * of the booting CPU must be able to handle peripherals and SC state that + * that are not reset. + * + * If \a type is SC_PM_RESET_TYPE_BOARD, then return with no action. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid partition or type + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt, + * + * Most peripherals owned by the partition will be reset if + * possible. SC state (partitions, power, clocks, etc.) is reset. The + * boot SW of the booting CPU must be able to handle peripherals that + * that are not reset. + */ +sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_pm_reset_type_t type); + +/*! + * This function is used to start/stop a CPU. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the CPU resource + * @param[in] enable start if SC_TRUE; otherwise stop + * @param[in] address 64-bit boot address + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or address, + * - SC_ERR_NOACCESS if caller's partition is not the parent of the + * resource (CPU) owner + */ +sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, + sc_faddr_t address); + +/* @} */ + +#endif /* SC_PM_API_H */ + +/**@}*/ + diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h new file mode 100755 index 0000000000..0de009a00e --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h @@ -0,0 +1,759 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file containing the public API for the System Controller (SC) + * Resource Management (RM) function. This includes functions for + * partitioning resources, pads, and memory regions. + * + * @addtogroup RM_SVC (SVC) Resource Management Service + * + * Module for the Resource Management (RM) service. + * + * @includedoc rm/details.dox + * + * @{ + */ + +#ifndef SC_RM_API_H +#define SC_RM_API_H + +/* Includes */ + +#include <asm/arch/sci/types.h> + +/* Defines */ + +/*! + * @name Defines for type widths + */ +/*@{*/ +#define SC_RM_PARTITION_W 5U /*!< Width of sc_rm_pt_t */ +#define SC_RM_MEMREG_W 6U /*!< Width of sc_rm_mr_t */ +#define SC_RM_DID_W 4U /*!< Width of sc_rm_did_t */ +#define SC_RM_SID_W 6U /*!< Width of sc_rm_sid_t */ +#define SC_RM_SPA_W 2U /*!< Width of sc_rm_spa_t */ +#define SC_RM_PERM_W 3U /*!< Width of sc_rm_perm_t */ +/*@}*/ + +/*! + * @name Defines for ALL parameters + */ +/*@{*/ +#define SC_RM_PT_ALL ((sc_rm_pt_t) UINT8_MAX) /*!< All partitions */ +#define SC_RM_MR_ALL ((sc_rm_mr_t) UINT8_MAX) /*!< All memory regions */ +/*@}*/ + +/*! + * @name Defines for sc_rm_spa_t + */ +/*@{*/ +#define SC_RM_SPA_PASSTHRU 0U /*!< Pass through (attribute driven by master) */ +#define SC_RM_SPA_PASSSID 1U /*!< Pass through and output on SID */ +#define SC_RM_SPA_ASSERT 2U /*!< Assert (force to be secure/privileged) */ +#define SC_RM_SPA_NEGATE 3U /*!< Negate (force to be non-secure/user) */ +/*@}*/ + +/*! + * @name Defines for sc_rm_perm_t + */ +/*@{*/ +#define SC_RM_PERM_NONE 0U /*!< No access */ +#define SC_RM_PERM_SEC_R 1U /*!< Secure RO */ +#define SC_RM_PERM_SECPRIV_RW 2U /*!< Secure privilege R/W */ +#define SC_RM_PERM_SEC_RW 3U /*!< Secure R/W */ +#define SC_RM_PERM_NSPRIV_R 4U /*!< Secure R/W, non-secure privilege RO */ +#define SC_RM_PERM_NS_R 5U /*!< Secure R/W, non-secure RO */ +#define SC_RM_PERM_NSPRIV_RW 6U /*!< Secure R/W, non-secure privilege R/W */ +#define SC_RM_PERM_FULL 7U /*!< Full access */ +/*@}*/ + +/* Types */ + +/*! + * This type is used to declare a resource partition. + */ +typedef uint8_t sc_rm_pt_t; + +/*! + * This type is used to declare a memory region. + */ +typedef uint8_t sc_rm_mr_t; + +/*! + * This type is used to declare a resource domain ID used by the + * isolation HW. + */ +typedef uint8_t sc_rm_did_t; + +/*! + * This type is used to declare an SMMU StreamID. + */ +typedef uint16_t sc_rm_sid_t; + +/*! + * This type is a used to declare master transaction attributes. + */ +typedef uint8_t sc_rm_spa_t; + +/*! + * This type is used to declare a resource/memory region access permission. + * Refer to the XRDC2 Block Guide for more information. + */ +typedef uint8_t sc_rm_perm_t; + +/* Functions */ + +/*! + * @name Partition Functions + * @{ + */ + +/*! + * This function requests that the SC create a new resource partition. + * + * @param[in] ipc IPC handle + * @param[out] pt return handle for partition; used for subsequent function + * calls associated with this partition + * @param[in] secure boolean indicating if this partition should be secure; only + * valid if caller is secure + * @param[in] isolated boolean indicating if this partition should be HW isolated + * via XRDC; set SC_TRUE if new DID is desired + * @param[in] restricted boolean indicating if this partition should be restricted; set + * SC_TRUE if masters in this partition cannot create new partitions + * @param[in] grant boolean indicating if this partition should always grant + * access and control to the parent + * @param[in] coherent boolean indicating if this partition is coherent; + * set SC_TRUE if only this partition will contain both AP clusters + * and they will be coherent via the CCI + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_ERR_PARM if caller's partition is not secure but a new secure partition is requested, + * - SC_ERR_LOCKED if caller's partition is locked, + * - SC_ERR_UNAVAILABLE if partition table is full (no more allocation space) + * + * Marking as non-secure prevents subsequent functions from configuring masters in this + * partition to assert the secure signal. If restricted then the new partition is limited + * in what functions it can call, especially those associated with managing partitions. + * + * The grant option is usually used to isolate a bus master's traffic to specific + * memory without isolating the peripheral interface of the master or the API + * controls of that master. + */ +sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure, + sc_bool_t isolated, sc_bool_t restricted, sc_bool_t grant, sc_bool_t coherent); + +/*! + * This function makes a partition confidential. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition that is granting + * @param[in] retro retroactive + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if \a pt out of range, + * - SC_ERR_NOACCESS if caller's not allowed to change \a pt + * - SC_ERR_LOCKED if partition \a pt is locked + * + * Call to make a partition confidential. Confidential means only this + * partition should be able to grant access permissions to this partition. + * + * If retroactive, then all resources owned by other partitions will have + * access rights for this partition removed, even if locked. + */ +sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t retro); + +/*! + * This function frees a partition and assigns all resources to the caller. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to free + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if \a pt out of range or invalid, + * - SC_ERR_NOACCESS if \a pt is the SC partition, + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt, + * - SC_ERR_LOCKED if \a pt or caller's partition is locked + * + * All resources, memory regions, and pads are assigned to the caller/parent. + * The partition watchdog is disabled (even if locked). DID is freed. + */ +sc_err_t sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt); + +/*! + * This function returns the DID of a partition. + * + * @param[in] ipc IPC handle + * + * @return Returns the domain ID (DID) of the caller's partition. + * + * The DID is a SoC-specific internal ID used by the HW resource + * protection mechanism. It is only required by clients when using the + * SEMA42 module as the DID is sometimes connected to the master ID. + */ +sc_rm_did_t sc_rm_get_did(sc_ipc_t ipc); + +/*! + * This function forces a partition to use a specific static DID. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to assign \a did + * @param[in] did static DID to assign + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if \a pt or \a did out of range, + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt, + * - SC_ERR_LOCKED if \a pt is locked + * + * Assumes no assigned resources or memory regions yet! The number of static + * DID is fixed by the SC@boot. + */ +sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_rm_did_t did); + +/*! + * This function locks a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to lock + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if \a pt out of range, + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt + * + * If a partition is locked it cannot be freed, have resources/pads assigned + * to/from it, memory regions created/assigned, DID changed, or parent changed. + */ +sc_err_t sc_rm_partition_lock(sc_ipc_t ipc, sc_rm_pt_t pt); + +/*! + * This function gets the partition handle of the caller. + * + * @param[in] ipc IPC handle + * @param[out] pt return handle for caller's partition + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt); + +/*! + * This function sets a new parent for a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition for which parent is to be + * changed + * @param[in] pt_parent handle of partition to set as parent + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt, + * - SC_ERR_LOCKED if either partition is locked + */ +sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_rm_pt_t pt_parent); + +/*! + * This function moves all movable resources/pads owned by a source partition + * to a destination partition. It can be used to more quickly set up a new + * partition if a majority of the caller's resources are to be moved to a + * new partition. + * + * @param[in] ipc IPC handle + * @param[in] pt_src handle of partition from which resources should + * be moved from + * @param[in] pt_dst handle of partition to which resources should be + * moved to + * @param[in] move_rsrc boolean to indicate if resources should be moved + * @param[in] move_pads boolean to indicate if pads should be moved + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * By default, all resources are movable. This can be changed using the + * sc_rm_set_resource_movable() function. Note all masters defaulted to SMMU + * bypass. + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not \a pt_src or the + * parent of \a pt_src, + * - SC_ERR_LOCKED if either partition is locked + */ +sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst, + sc_bool_t move_rsrc, sc_bool_t move_pads); + +/* @} */ + +/*! + * @name Resource Functions + * @{ + */ + +/*! + * This function assigns ownership of a resource to a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to which resource should be + * assigned + * @param[in] resource resource to assign + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * This action resets the resource's master and peripheral attributes. + * Privilege attribute will be PASSTHRU, security attribute will be + * ASSERT if the partition si secure and NEGATE if it is not, and + * masters will defaulted to SMMU bypass. Access permissions will reset + * to SEC_RW for the owning partition only for secure partitions, FULL for + * non-secure. DEfault is no access by other partitions. + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent + * of the owner, + * - SC_ERR_LOCKED if the owning partition or \a pt is locked + */ +sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_rsrc_t resource); + +/*! + * This function flags resources as movable or not. + * + * @param[in] ipc IPC handle + * @param[in] resource_fst first resource for which flag should be set + * @param[in] resource_lst last resource for which flag should be set + * @param[in] movable movable flag (SC_TRUE is movable) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if resources are out of range, + * - SC_ERR_NOACCESS if caller's partition is not a parent of a resource owner, + * - SC_ERR_LOCKED if the owning partition is locked + * + * This function is used to determine the set of resources that will be + * moved using the sc_rm_move_all() function. All resources are movable + * by default so this function is normally used to prevent a set of + * resources from moving. + */ +sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst, + sc_rsrc_t resource_lst, sc_bool_t movable); + +/*! + * This function flags all of a subsystem's resources as movable + * or not. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to use to identify subsystem + * @param[in] movable movable flag (SC_TRUE is movable) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if a function argument is out of range + * + * Note \a resource is used to find the associated subsystem. Only + * resources owned by the caller are set. + */ +sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource, + sc_bool_t movable); + +/*! + * This function sets attributes for a resource which is a bus master (i.e. + * capable of DMA). + * + * @param[in] ipc IPC handle + * @param[in] resource master resource for which attributes should apply + * @param[in] sa security attribute + * @param[in] pa privilege attribute + * @param[in] smmu_bypass SMMU bypass mode + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not a parent of the resource owner, + * - SC_ERR_LOCKED if the owning partition is locked + * + * This function configures how the HW isolation will see bus transactions + * from the specified master. Note the security attribute will only be + * changed if the caller's partition is secure. + */ +sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_spa_t sa, sc_rm_spa_t pa, sc_bool_t smmu_bypass); + +/*! + * This function sets the StreamID for a resource which is a bus master (i.e. + * capable of DMA). + * + * @param[in] ipc IPC handle + * @param[in] resource master resource for which attributes should apply + * @param[in] sid StreamID + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent + * of the owner, + * - SC_ERR_LOCKED if the owning partition is locked + * + * This function configures the SID attribute associated with all bus transactions + * from this master. Note 0 is not a valid SID as it is reserved to indicate + * bypass. + */ +sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_sid_t sid); + +/*! + * This function sets access permissions for a peripheral resource. + * + * @param[in] ipc IPC handle + * @param[in] resource peripheral resource for which permissions should apply + * @param[in] pt handle of partition \a perm should by applied for + * @param[in] perm permissions to apply to \a resource for \a pt + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent + * of the owner, + * - SC_ERR_LOCKED if the owning partition is locked + * - SC_ERR_LOCKED if the \a pt is confidential and the caller isn't \a pt + * + * This function configures how the HW isolation will restrict access to a + * peripheral based on the attributes of a transaction from bus master. + */ +sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_pt_t pt, sc_rm_perm_t perm); + +/*! + * This function gets ownership status of a resource. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to check + * + * @return Returns a boolean (SC_TRUE if caller's partition owns the resource). + * + * If \a resource is out of range then SC_FALSE is returned. + */ +sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource); + +/*! + * This function is used to test if a resource is a bus master. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to check + * + * @return Returns a boolean (SC_TRUE if the resource is a bus master). + * + * If \a resource is out of range then SC_FALSE is returned. + */ +sc_bool_t sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource); + +/*! + * This function is used to test if a resource is a peripheral. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to check + * + * @return Returns a boolean (SC_TRUE if the resource is a peripheral). + * + * If \a resource is out of range then SC_FALSE is returned. + */ +sc_bool_t sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource); + +/*! + * This function is used to obtain info about a resource. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to inquire about + * @param[out] sid pointer to return StreamID + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if \a resource is out of range + */ +sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_sid_t *sid); + +/* @} */ + +/*! + * @name Memory Region Functions + * @{ + */ + +/*! + * This function requests that the SC create a new memory region. + * + * @param[in] ipc IPC handle + * @param[out] mr return handle for region; used for + * subsequent function calls + * associated with this region + * @param[in] addr_start start address of region (physical) + * @param[in] addr_end end address of region (physical) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if the new memory region is misaligned, + * - SC_ERR_LOCKED if caller's partition is locked, + * - SC_ERR_PARM if the new memory region spans multiple existing regions, + * - SC_ERR_NOACCESS if caller's partition does not own the memory containing + * the new region, + * - SC_ERR_UNAVAILABLE if memory region table is full (no more allocation + * space) + * + * The area covered by the memory region must currently be owned by the caller. + * By default, the new region will have access permission set to allow the + * caller to access. + */ +sc_err_t sc_rm_memreg_alloc(sc_ipc_t ipc, sc_rm_mr_t *mr, + sc_faddr_t addr_start, sc_faddr_t addr_end); + +/*! + * This function requests that the SC split a memory region. + * + * @param[in] ipc IPC handle + * @param[in] mr handle of memory region to split + * @param[out] mr_ret return handle for new region; used for + * subsequent function calls + * associated with this region + * @param[in] addr_start start address of region (physical) + * @param[in] addr_end end address of region (physical) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if the new memory region is not start/end part of mr, + * - SC_ERR_LOCKED if caller's partition is locked, + * - SC_ERR_PARM if the new memory region spans multiple existing regions, + * - SC_ERR_NOACCESS if caller's partition does not own the memory containing + * the new region, + * - SC_ERR_UNAVAILABLE if memory region table is full (no more allocation + * space) + * + * Note the new region must start or end on the split region. + */ +sc_err_t sc_rm_memreg_split(sc_ipc_t ipc, sc_rm_mr_t mr, + sc_rm_mr_t *mr_ret, sc_faddr_t addr_start, sc_faddr_t addr_end); + +/*! + * This function frees a memory region. + * + * @param[in] ipc IPC handle + * @param[in] mr handle of memory region to free + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if \a mr out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not a parent of \a mr, + * - SC_ERR_LOCKED if the owning partition of \a mr is locked + */ +sc_err_t sc_rm_memreg_free(sc_ipc_t ipc, sc_rm_mr_t mr); + +/*! + * Internal SC function to find a memory region. + * + * @see sc_rm_find_memreg(). + */ +/*! + * This function finds a memory region. + * + * @param[in] ipc IPC handle + * @param[out] mr return handle for region; used for + * subsequent function calls + * associated with this region + * @param[in] addr_start start address of region to search for + * @param[in] addr_end end address of region to search for + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOTFOUND if region not found, + * + * Searches only for regions owned by the caller. Finds first + * region containing the range specified. + */ +sc_err_t sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, + sc_faddr_t addr_start, sc_faddr_t addr_end); + +/*! + * This function assigns ownership of a memory region. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to which memory region + * should be assigned + * @param[in] mr handle of memory region to assign + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the \a mr owner or parent + * of the owner, + * - SC_ERR_LOCKED if the owning partition or \a pt is locked + */ +sc_err_t sc_rm_assign_memreg(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_mr_t mr); + +/*! + * This function sets access permissions for a memory region. + * + * @param[in] ipc IPC handle + * @param[in] mr handle of memory region for which permissions + * should apply + * @param[in] pt handle of partition \a perm should by + * applied for + * @param[in] perm permissions to apply to \a mr for \a pt + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the region owner or parent + * of the owner, + * - SC_ERR_LOCKED if the owning partition is locked + * - SC_ERR_LOCKED if the \a pt is confidential and the caller isn't \a pt + * + * This function configures how the HW isolation will restrict access to a + * memory region based on the attributes of a transaction from bus master. + */ +sc_err_t sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr, + sc_rm_pt_t pt, sc_rm_perm_t perm); + +/*! + * This function gets ownership status of a memory region. + * + * @param[in] ipc IPC handle + * @param[in] mr handle of memory region to check + * + * @return Returns a boolean (SC_TRUE if caller's partition owns the + * memory region). + * + * If \a mr is out of range then SC_FALSE is returned. + */ +sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr); + +/*! + * This function is used to obtain info about a memory region. + * + * @param[in] ipc IPC handle + * @param[in] mr handle of memory region to inquire about + * @param[out] addr_start pointer to return start address + * @param[out] addr_end pointer to return end address + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if \a mr is out of range + */ +sc_err_t sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, + sc_faddr_t *addr_start, sc_faddr_t *addr_end); + +/* @} */ + +/*! + * @name Pad Functions + * @{ + */ + +/*! + * This function assigns ownership of a pad to a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to which pad should + * be assigned + * @param[in] pad pad to assign + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner or parent + * of the owner, + * - SC_ERR_LOCKED if the owning partition or \a pt is locked + */ +sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad); + +/*! + * This function flags pads as movable or not. + * + * @param[in] ipc IPC handle + * @param[in] pad_fst first pad for which flag should be set + * @param[in] pad_lst last pad for which flag should be set + * @param[in] movable movable flag (SC_TRUE is movable) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if pads are out of range, + * - SC_ERR_NOACCESS if caller's partition is not a parent of a pad owner, + * - SC_ERR_LOCKED if the owning partition is locked + * + * This function is used to determine the set of pads that will be + * moved using the sc_rm_move_all() function. All pads are movable + * by default so this function is normally used to prevent a set of + * pads from moving. + */ +sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst, + sc_pad_t pad_lst, sc_bool_t movable); + +/*! + * This function gets ownership status of a pad. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to check + * + * @return Returns a boolean (SC_TRUE if caller's partition owns the pad). + * + * If \a pad is out of range then SC_FALSE is returned. + */ +sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad); + +/* @} */ + +/*! + * @name Debug Functions + * @{ + */ + +/*! + * This function dumps the RM state for debug. + * + * @param[in] ipc IPC handle + */ +void sc_rm_dump(sc_ipc_t ipc); + +/* @} */ + +#endif /* SC_RM_API_H */ + +/**@}*/ + diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h new file mode 100755 index 0000000000..631dab1531 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h @@ -0,0 +1,306 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file containing the public API for the System Controller (SC) + * Timer function. + * + * @addtogroup TIMER_SVC (SVC) Timer Service + * + * Module for the Timer service. This includes support for the watchdog, RTC, + * and system counter. Note every resource partition has a watchdog it can + * use. + * + * @{ + */ + +#ifndef SC_TIMER_API_H +#define SC_TIMER_API_H + +/* Includes */ + +#include <asm/arch/sci/types.h> +#include <asm/arch/sci/svc/rm/api.h> + +/* Defines */ + +/*! + * @name Defines for type widths + */ +/*@{*/ +#define SC_TIMER_ACTION_W 3U /*!< Width of sc_timer_wdog_action_t */ +/*@}*/ + +/*! + * @name Defines for sc_timer_wdog_action_t + */ +/*@{*/ +#define SC_TIMER_WDOG_ACTION_PARTITION 0U /*!< Reset partition */ +#define SC_TIMER_WDOG_ACTION_WARM 1U /*!< Warm reset system */ +#define SC_TIMER_WDOG_ACTION_COLD 2U /*!< Cold reset system */ +#define SC_TIMER_WDOG_ACTION_BOARD 3U /*!< Reset board */ +#define SC_TIMER_WDOG_ACTION_IRQ 4U /*!< Only generate IRQs */ +/*@}*/ + +/* Types */ + +/*! + * This type is used to configure the watchdog action. + */ +typedef uint8_t sc_timer_wdog_action_t; + +/*! + * This type is used to declare a watchdog time value in milliseconds. + */ +typedef uint32_t sc_timer_wdog_time_t; + +/* Functions */ + +/*! + * @name Wathdog Functions + * @{ + */ + +/*! + * This function sets the watchdog timeout in milliseconds. If not + * set then the timeout defaults to the max. Once locked this value + * cannot be changed. + * + * @param[in] ipc IPC handle + * @param[in] timeout timeout period for the watchdog + * + * @return Returns an error code (SC_ERR_NONE = success, SC_ERR_LOCKED + * = locked). + */ +sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc, + sc_timer_wdog_time_t timeout); + +/*! + * This function sets the watchdog pre-timeout in milliseconds. If not + * set then the pre-timeout defaults to the max. Once locked this value + * cannot be changed. + * + * @param[in] ipc IPC handle + * @param[in] pre_timeout pre-timeout period for the watchdog + * + * When the pre-timout expires an IRQ will be generated. Note this timeout + * clears when the IRQ is triggered. An IRQ is generated for the failing + * partition and all of its child partitions. + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_timer_set_wdog_pre_timeout(sc_ipc_t ipc, + sc_timer_wdog_time_t pre_timeout); + +/*! + * This function starts the watchdog. + * + * @param[in] ipc IPC handle + * @param[in] lock boolean indicating the lock status + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * If \a lock is set then the watchdog cannot be stopped or the timeout + * period changed. + */ +sc_err_t sc_timer_start_wdog(sc_ipc_t ipc, sc_bool_t lock); + +/*! + * This function stops the watchdog if it is not locked. + * + * @param[in] ipc IPC handle + * + * @return Returns an error code (SC_ERR_NONE = success, SC_ERR_LOCKED + * = locked). + */ +sc_err_t sc_timer_stop_wdog(sc_ipc_t ipc); + +/*! + * This function pings (services, kicks) the watchdog resetting the time + * before expiration back to the timeout. + * + * @param[in] ipc IPC handle + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_timer_ping_wdog(sc_ipc_t ipc); + +/*! + * This function gets the status of the watchdog. All arguments are + * in milliseconds. + * + * @param[in] ipc IPC handle + * @param[out] timeout pointer to return the timeout + * @param[out] max_timeout pointer to return the max timeout + * @param[out] remaining_time pointer to return the time remaining + * until trigger + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_timer_get_wdog_status(sc_ipc_t ipc, + sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *max_timeout, + sc_timer_wdog_time_t *remaining_time); + +/*! + * This function gets the status of the watchdog of a partition. All + * arguments are in milliseconds. + * + * @param[in] ipc IPC handle + * @param[in] pt partition to query + * @param[out] enb pointer to return enable status + * @param[out] timeout pointer to return the timeout + * @param[out] remaining_time pointer to return the time remaining + * until trigger + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t *enb, + sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *remaining_time); + +/*! + * This function configures the action to be taken when a watchdog + * expires. + * + * @param[in] ipc IPC handle + * @param[in] pt partition to affect + * @param[in] action action to take + * + * Default action is inherited from the parent. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid parameters, + * - SC_ERR_NOACCESS if caller's partition is not the SYSTEM owner, + * - SC_ERR_LOCKED if the watchdog is locked + */ +sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc, + sc_rm_pt_t pt, sc_timer_wdog_action_t action); + +/* @} */ + +/*! + * @name Real-Time Clock (RTC) Functions + * @{ + */ + +/*! + * This function sets the RTC time. Only the owner of the SC_R_SYSTEM + * resource can set the time. + * + * @param[in] ipc IPC handle + * @param[in] year year (min 1970) + * @param[in] mon month (1-12) + * @param[in] day day of the month (1-31) + * @param[in] hour hour (0-23) + * @param[in] min minute (0-59) + * @param[in] sec second (0-59) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters, + * - SC_ERR_NOACCESS if caller's partition is not the SYSTEM owner + */ +sc_err_t sc_timer_set_rtc_time(sc_ipc_t ipc, uint16_t year, uint8_t mon, + uint8_t day, uint8_t hour, uint8_t min, uint8_t sec); + +/*! + * This function gets the RTC time. + * + * @param[in] ipc IPC handle + * @param[out] year pointer to return year (min 1970) + * @param[out] mon pointer to return month (1-12) + * @param[out] day pointer to return day of the month (1-31) + * @param[out] hour pointer to return hour (0-23) + * @param[out] min pointer to return minute (0-59) + * @param[out] sec pointer to return second (0-59) + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_timer_get_rtc_time(sc_ipc_t ipc, uint16_t *year, uint8_t *mon, + uint8_t *day, uint8_t *hour, uint8_t *min, uint8_t *sec); + +/*! + * This function gets the RTC time in seconds since 1/1/1970. + * + * @param[in] ipc IPC handle + * @param[out] sec pointer to return second + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_timer_get_rtc_sec1970(sc_ipc_t ipc, uint32_t *sec); + +/*! + * This function sets the RTC alarm. + * + * @param[in] ipc IPC handle + * @param[in] year year (min 1970) + * @param[in] mon month (1-12) + * @param[in] day day of the month (1-31) + * @param[in] hour hour (0-23) + * @param[in] min minute (0-59) + * @param[in] sec second (0-59) + * + * Note this alarm setting clears when the alarm is triggered. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters + */ +sc_err_t sc_timer_set_rtc_alarm(sc_ipc_t ipc, uint16_t year, uint8_t mon, + uint8_t day, uint8_t hour, uint8_t min, uint8_t sec); + +/*! + * This function sets the RTC alarm. + * + * @param[in] ipc IPC handle + * @param[in] sec period in seconds + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters + */ +sc_err_t sc_timer_set_rtc_periodic_alarm(sc_ipc_t ipc, uint32_t sec); + +/*! + * This function sets the RTC alarm. + * + * @param[in] ipc IPC handle + * + * Note this alarm setting clears when the alarm is triggered. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters + */ +sc_err_t sc_timer_cancel_rtc_alarm(sc_ipc_t ipc); + +/*! + * This function sets the RTC calibration value. Only the owner of the SC_R_SYSTEM + * resource can set the calibration. + * + * @param[in] ipc IPC handle + * @param[in] count calbration count (-16 to 15) + * + * The calibration value is a 5-bit value including the sign bit, which is + * implemented in 2's complement. It is added or subtracted from the RTC on + * a perdiodic basis, once per 32768 cycles of the RTC clock. + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_timer_set_rtc_calb(sc_ipc_t ipc, int8_t count); + +/* @} */ + +#endif /* SC_TIMER_API_H */ + +/**@}*/ + diff --git a/arch/arm/include/asm/arch-imx8/sci/types.h b/arch/arm/include/asm/arch-imx8/sci/types.h new file mode 100755 index 0000000000..e4c37a0480 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/types.h @@ -0,0 +1,862 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file containing types used across multiple service APIs. + */ + +#ifndef SC_TYPES_H +#define SC_TYPES_H + +/* Includes */ +#include <linux/types.h> + +/* Defines */ +/*! + * This type is used to declare a handle for an IPC communication + * channel. Its meaning is specific to the IPC implementation. + */ +typedef uint64_t sc_ipc_t; + +/*! + * This type is used to declare an ID for an IPC communication + * channel. Its meaning is specific to the IPC implementation. + */ +typedef uint64_t sc_ipc_id_t; + +/*! + * @name Defines for common frequencies + */ +/*@{*/ +#define SC_32KHZ 32768U /*!< 32KHz */ +#define SC_10MHZ 10000000U /*!< 10MHz */ +#define SC_20MHZ 20000000U /*!< 20MHz */ +#define SC_25MHZ 25000000U /*!< 25MHz */ +#define SC_27MHZ 27000000U /*!< 27MHz */ +#define SC_40MHZ 40000000U /*!< 40MHz */ +#define SC_45MHZ 45000000U /*!< 45MHz */ +#define SC_50MHZ 50000000U /*!< 50MHz */ +#define SC_60MHZ 60000000U /*!< 60MHz */ +#define SC_66MHZ 66666666U /*!< 66MHz */ +#define SC_74MHZ 74250000U /*!< 74.25MHz */ +#define SC_80MHZ 80000000U /*!< 80MHz */ +#define SC_83MHZ 83333333U /*!< 83MHz */ +#define SC_84MHZ 84375000U /*!< 84.37MHz */ +#define SC_100MHZ 100000000U /*!< 100MHz */ +#define SC_125MHZ 125000000U /*!< 125MHz */ +#define SC_133MHZ 133333333U /*!< 133MHz */ +#define SC_135MHZ 135000000U /*!< 135MHz */ +#define SC_150MHZ 150000000U /*!< 150MHz */ +#define SC_160MHZ 160000000U /*!< 160MHz */ +#define SC_166MHZ 166666666U /*!< 166MHz */ +#define SC_175MHZ 175000000U /*!< 175MHz */ +#define SC_180MHZ 180000000U /*!< 180MHz */ +#define SC_200MHZ 200000000U /*!< 200MHz */ +#define SC_250MHZ 250000000U /*!< 250MHz */ +#define SC_266MHZ 266666666U /*!< 266MHz */ +#define SC_300MHZ 300000000U /*!< 300MHz */ +#define SC_312MHZ 312500000U /*!< 312.5MHZ */ +#define SC_320MHZ 320000000U /*!< 320MHz */ +#define SC_325MHZ 325000000U /*!< 325MHz */ +#define SC_333MHZ 333333333U /*!< 333MHz */ +#define SC_350MHZ 350000000U /*!< 350MHz */ +#define SC_372MHZ 372000000U /*!< 372MHz */ +#define SC_375MHZ 375000000U /*!< 375MHz */ +#define SC_400MHZ 400000000U /*!< 400MHz */ +#define SC_500MHZ 500000000U /*!< 500MHz */ +#define SC_594MHZ 594000000U /*!< 594MHz */ +#define SC_625MHZ 625000000U /*!< 625MHz */ +#define SC_640MHZ 640000000U /*!< 640MHz */ +#define SC_650MHZ 650000000U /*!< 650MHz */ +#define SC_667MHZ 666666667U /*!< 667MHz */ +#define SC_675MHZ 675000000U /*!< 675MHz */ +#define SC_700MHZ 700000000U /*!< 700MHz */ +#define SC_720MHZ 720000000U /*!< 720MHz */ +#define SC_750MHZ 750000000U /*!< 750MHz */ +#define SC_800MHZ 800000000U /*!< 800MHz */ +#define SC_850MHZ 850000000U /*!< 850MHz */ +#define SC_900MHZ 900000000U /*!< 900MHz */ +#define SC_1000MHZ 1000000000U /*!< 1GHz */ +#define SC_1060MHZ 1060000000U /*!< 1.06GHz */ +#define SC_1188MHZ 1188000000U /*!< 1.188GHz */ +#define SC_1260MHZ 1260000000U /*!< 1.26GHz */ +#define SC_1280MHZ 1280000000U /*!< 1.28GHz */ +#define SC_1300MHZ 1300000000U /*!< 1.3GHz */ +#define SC_1400MHZ 1400000000U /*!< 1.4GHz */ +#define SC_1500MHZ 1500000000U /*!< 1.5GHz */ +#define SC_1600MHZ 1600000000U /*!< 1.6GHz */ +#define SC_1800MHZ 1800000000U /*!< 1.8GHz */ +#define SC_2000MHZ 2000000000U /*!< 2.0GHz */ +#define SC_2112MHZ 2112000000U /*!< 2.12GHz */ +/*@}*/ + +/*! + * @name Defines for 24M related frequencies + */ +/*@{*/ +#define SC_8MHZ 8000000U /*!< 8MHz */ +#define SC_12MHZ 12000000U /*!< 12MHz */ +#define SC_19MHZ 19800000U /*!< 19.8MHz */ +#define SC_24MHZ 24000000U /*!< 24MHz */ +#define SC_48MHZ 48000000U /*!< 48MHz */ +#define SC_120MHZ 120000000U /*!< 120MHz */ +#define SC_132MHZ 132000000U /*!< 132MHz */ +#define SC_144MHZ 144000000U /*!< 144MHz */ +#define SC_192MHZ 192000000U /*!< 192MHz */ +#define SC_211MHZ 211200000U /*!< 211.2MHz */ +#define SC_240MHZ 240000000U /*!< 240MHz */ +#define SC_264MHZ 264000000U /*!< 264MHz */ +#define SC_352MHZ 352000000U /*!< 352MHz */ +#define SC_360MHZ 360000000U /*!< 360MHz */ +#define SC_384MHZ 384000000U /*!< 384MHz */ +#define SC_396MHZ 396000000U /*!< 396MHz */ +#define SC_432MHZ 432000000U /*!< 432MHz */ +#define SC_480MHZ 480000000U /*!< 480MHz */ +#define SC_600MHZ 600000000U /*!< 600MHz */ +#define SC_744MHZ 744000000U /*!< 744MHz */ +#define SC_792MHZ 792000000U /*!< 792MHz */ +#define SC_864MHZ 864000000U /*!< 864MHz */ +#define SC_960MHZ 960000000U /*!< 960MHz */ +#define SC_1056MHZ 1056000000U /*!< 1056MHz */ +#define SC_1104MHZ 1104000000U /*!< 1104MHz */ +#define SC_1200MHZ 1200000000U /*!< 1.2GHz */ +#define SC_1464MHZ 1464000000U /*!< 1.464GHz */ +#define SC_2400MHZ 2400000000U /*!< 2.4GHz */ +/*@}*/ + +/*! + * @name Defines for A/V related frequencies + */ +/*@{*/ +#define SC_62MHZ 62937500U /*!< 62.9375MHz */ +#define SC_755MHZ 755250000U /*!< 755.25MHz */ +/*@}*/ + +/*! + * @name Defines for type widths + */ +/*@{*/ +#define SC_FADDR_W 36U /*!< Width of sc_faddr_t */ +#define SC_BOOL_W 1U /*!< Width of sc_bool_t */ +#define SC_ERR_W 4U /*!< Width of sc_err_t */ +#define SC_RSRC_W 10U /*!< Width of sc_rsrc_t */ +#define SC_CTRL_W 6U /*!< Width of sc_ctrl_t */ +/*@}*/ + +/*! + * @name Defines for sc_bool_t + */ +/*@{*/ +#define SC_FALSE ((sc_bool_t) 0U) /*!< True */ +#define SC_TRUE ((sc_bool_t) 1U) /*!< False */ +/*@}*/ + +/*! + * @name Defines for sc_err_t. + */ +/*@{*/ +#define SC_ERR_NONE 0U /*!< Success */ +#define SC_ERR_VERSION 1U /*!< Incompatible API version */ +#define SC_ERR_CONFIG 2U /*!< Configuration error */ +#define SC_ERR_PARM 3U /*!< Bad parameter */ +#define SC_ERR_NOACCESS 4U /*!< Permission error (no access) */ +#define SC_ERR_LOCKED 5U /*!< Permission error (locked) */ +#define SC_ERR_UNAVAILABLE 6U /*!< Unavailable (out of resources) */ +#define SC_ERR_NOTFOUND 7U /*!< Not found */ +#define SC_ERR_NOPOWER 8U /*!< No power */ +#define SC_ERR_IPC 9U /*!< Generic IPC error */ +#define SC_ERR_BUSY 10U /*!< Resource is currently busy/active */ +#define SC_ERR_FAIL 11U /*!< General I/O failure */ +#define SC_ERR_LAST 12U +/*@}*/ + +/*! + * @name Defines for sc_rsrc_t. + */ +/*@{*/ +#define SC_R_A53 0U +#define SC_R_A53_0 1U +#define SC_R_A53_1 2U +#define SC_R_A53_2 3U +#define SC_R_A53_3 4U +#define SC_R_A72 5U +#define SC_R_A72_0 6U +#define SC_R_A72_1 7U +#define SC_R_A72_2 8U +#define SC_R_A72_3 9U +#define SC_R_CCI 10U +#define SC_R_DB 11U +#define SC_R_DRC_0 12U +#define SC_R_DRC_1 13U +#define SC_R_GIC_SMMU 14U +#define SC_R_IRQSTR_M4_0 15U +#define SC_R_IRQSTR_M4_1 16U +#define SC_R_SMMU 17U +#define SC_R_GIC 18U +#define SC_R_DC_0_BLIT0 19U +#define SC_R_DC_0_BLIT1 20U +#define SC_R_DC_0_BLIT2 21U +#define SC_R_DC_0_BLIT_OUT 22U +#define SC_R_DC_0_CAPTURE0 23U +#define SC_R_DC_0_CAPTURE1 24U +#define SC_R_DC_0_WARP 25U +#define SC_R_DC_0_INTEGRAL0 26U +#define SC_R_DC_0_INTEGRAL1 27U +#define SC_R_DC_0_VIDEO0 28U +#define SC_R_DC_0_VIDEO1 29U +#define SC_R_DC_0_FRAC0 30U +#define SC_R_DC_0_FRAC1 31U +#define SC_R_DC_0 32U +#define SC_R_GPU_2_PID0 33U +#define SC_R_DC_0_PLL_0 34U +#define SC_R_DC_0_PLL_1 35U +#define SC_R_DC_1_BLIT0 36U +#define SC_R_DC_1_BLIT1 37U +#define SC_R_DC_1_BLIT2 38U +#define SC_R_DC_1_BLIT_OUT 39U +#define SC_R_DC_1_CAPTURE0 40U +#define SC_R_DC_1_CAPTURE1 41U +#define SC_R_DC_1_WARP 42U +#define SC_R_DC_1_INTEGRAL0 43U +#define SC_R_DC_1_INTEGRAL1 44U +#define SC_R_DC_1_VIDEO0 45U +#define SC_R_DC_1_VIDEO1 46U +#define SC_R_DC_1_FRAC0 47U +#define SC_R_DC_1_FRAC1 48U +#define SC_R_DC_1 49U +#define SC_R_GPU_3_PID0 50U +#define SC_R_DC_1_PLL_0 51U +#define SC_R_DC_1_PLL_1 52U +#define SC_R_SPI_0 53U +#define SC_R_SPI_1 54U +#define SC_R_SPI_2 55U +#define SC_R_SPI_3 56U +#define SC_R_UART_0 57U +#define SC_R_UART_1 58U +#define SC_R_UART_2 59U +#define SC_R_UART_3 60U +#define SC_R_UART_4 61U +#define SC_R_EMVSIM_0 62U +#define SC_R_EMVSIM_1 63U +#define SC_R_DMA_0_CH0 64U +#define SC_R_DMA_0_CH1 65U +#define SC_R_DMA_0_CH2 66U +#define SC_R_DMA_0_CH3 67U +#define SC_R_DMA_0_CH4 68U +#define SC_R_DMA_0_CH5 69U +#define SC_R_DMA_0_CH6 70U +#define SC_R_DMA_0_CH7 71U +#define SC_R_DMA_0_CH8 72U +#define SC_R_DMA_0_CH9 73U +#define SC_R_DMA_0_CH10 74U +#define SC_R_DMA_0_CH11 75U +#define SC_R_DMA_0_CH12 76U +#define SC_R_DMA_0_CH13 77U +#define SC_R_DMA_0_CH14 78U +#define SC_R_DMA_0_CH15 79U +#define SC_R_DMA_0_CH16 80U +#define SC_R_DMA_0_CH17 81U +#define SC_R_DMA_0_CH18 82U +#define SC_R_DMA_0_CH19 83U +#define SC_R_DMA_0_CH20 84U +#define SC_R_DMA_0_CH21 85U +#define SC_R_DMA_0_CH22 86U +#define SC_R_DMA_0_CH23 87U +#define SC_R_DMA_0_CH24 88U +#define SC_R_DMA_0_CH25 89U +#define SC_R_DMA_0_CH26 90U +#define SC_R_DMA_0_CH27 91U +#define SC_R_DMA_0_CH28 92U +#define SC_R_DMA_0_CH29 93U +#define SC_R_DMA_0_CH30 94U +#define SC_R_DMA_0_CH31 95U +#define SC_R_I2C_0 96U +#define SC_R_I2C_1 97U +#define SC_R_I2C_2 98U +#define SC_R_I2C_3 99U +#define SC_R_I2C_4 100U +#define SC_R_ADC_0 101U +#define SC_R_ADC_1 102U +#define SC_R_FTM_0 103U +#define SC_R_FTM_1 104U +#define SC_R_CAN_0 105U +#define SC_R_CAN_1 106U +#define SC_R_CAN_2 107U +#define SC_R_DMA_1_CH0 108U +#define SC_R_DMA_1_CH1 109U +#define SC_R_DMA_1_CH2 110U +#define SC_R_DMA_1_CH3 111U +#define SC_R_DMA_1_CH4 112U +#define SC_R_DMA_1_CH5 113U +#define SC_R_DMA_1_CH6 114U +#define SC_R_DMA_1_CH7 115U +#define SC_R_DMA_1_CH8 116U +#define SC_R_DMA_1_CH9 117U +#define SC_R_DMA_1_CH10 118U +#define SC_R_DMA_1_CH11 119U +#define SC_R_DMA_1_CH12 120U +#define SC_R_DMA_1_CH13 121U +#define SC_R_DMA_1_CH14 122U +#define SC_R_DMA_1_CH15 123U +#define SC_R_DMA_1_CH16 124U +#define SC_R_DMA_1_CH17 125U +#define SC_R_DMA_1_CH18 126U +#define SC_R_DMA_1_CH19 127U +#define SC_R_DMA_1_CH20 128U +#define SC_R_DMA_1_CH21 129U +#define SC_R_DMA_1_CH22 130U +#define SC_R_DMA_1_CH23 131U +#define SC_R_DMA_1_CH24 132U +#define SC_R_DMA_1_CH25 133U +#define SC_R_DMA_1_CH26 134U +#define SC_R_DMA_1_CH27 135U +#define SC_R_DMA_1_CH28 136U +#define SC_R_DMA_1_CH29 137U +#define SC_R_DMA_1_CH30 138U +#define SC_R_DMA_1_CH31 139U +#define SC_R_UNUSED1 140U +#define SC_R_UNUSED2 141U +#define SC_R_UNUSED3 142U +#define SC_R_UNUSED4 143U +#define SC_R_GPU_0_PID0 144U +#define SC_R_GPU_0_PID1 145U +#define SC_R_GPU_0_PID2 146U +#define SC_R_GPU_0_PID3 147U +#define SC_R_GPU_1_PID0 148U +#define SC_R_GPU_1_PID1 149U +#define SC_R_GPU_1_PID2 150U +#define SC_R_GPU_1_PID3 151U +#define SC_R_PCIE_A 152U +#define SC_R_SERDES_0 153U +#define SC_R_MATCH_0 154U +#define SC_R_MATCH_1 155U +#define SC_R_MATCH_2 156U +#define SC_R_MATCH_3 157U +#define SC_R_MATCH_4 158U +#define SC_R_MATCH_5 159U +#define SC_R_MATCH_6 160U +#define SC_R_MATCH_7 161U +#define SC_R_MATCH_8 162U +#define SC_R_MATCH_9 163U +#define SC_R_MATCH_10 164U +#define SC_R_MATCH_11 165U +#define SC_R_MATCH_12 166U +#define SC_R_MATCH_13 167U +#define SC_R_MATCH_14 168U +#define SC_R_PCIE_B 169U +#define SC_R_SATA_0 170U +#define SC_R_SERDES_1 171U +#define SC_R_HSIO_GPIO 172U +#define SC_R_MATCH_15 173U +#define SC_R_MATCH_16 174U +#define SC_R_MATCH_17 175U +#define SC_R_MATCH_18 176U +#define SC_R_MATCH_19 177U +#define SC_R_MATCH_20 178U +#define SC_R_MATCH_21 179U +#define SC_R_MATCH_22 180U +#define SC_R_MATCH_23 181U +#define SC_R_MATCH_24 182U +#define SC_R_MATCH_25 183U +#define SC_R_MATCH_26 184U +#define SC_R_MATCH_27 185U +#define SC_R_MATCH_28 186U +#define SC_R_LCD_0 187U +#define SC_R_LCD_0_PWM_0 188U +#define SC_R_LCD_0_I2C_0 189U +#define SC_R_LCD_0_I2C_1 190U +#define SC_R_PWM_0 191U +#define SC_R_PWM_1 192U +#define SC_R_PWM_2 193U +#define SC_R_PWM_3 194U +#define SC_R_PWM_4 195U +#define SC_R_PWM_5 196U +#define SC_R_PWM_6 197U +#define SC_R_PWM_7 198U +#define SC_R_GPIO_0 199U +#define SC_R_GPIO_1 200U +#define SC_R_GPIO_2 201U +#define SC_R_GPIO_3 202U +#define SC_R_GPIO_4 203U +#define SC_R_GPIO_5 204U +#define SC_R_GPIO_6 205U +#define SC_R_GPIO_7 206U +#define SC_R_GPT_0 207U +#define SC_R_GPT_1 208U +#define SC_R_GPT_2 209U +#define SC_R_GPT_3 210U +#define SC_R_GPT_4 211U +#define SC_R_KPP 212U +#define SC_R_MU_0A 213U +#define SC_R_MU_1A 214U +#define SC_R_MU_2A 215U +#define SC_R_MU_3A 216U +#define SC_R_MU_4A 217U +#define SC_R_MU_5A 218U +#define SC_R_MU_6A 219U +#define SC_R_MU_7A 220U +#define SC_R_MU_8A 221U +#define SC_R_MU_9A 222U +#define SC_R_MU_10A 223U +#define SC_R_MU_11A 224U +#define SC_R_MU_12A 225U +#define SC_R_MU_13A 226U +#define SC_R_MU_5B 227U +#define SC_R_MU_6B 228U +#define SC_R_MU_7B 229U +#define SC_R_MU_8B 230U +#define SC_R_MU_9B 231U +#define SC_R_MU_10B 232U +#define SC_R_MU_11B 233U +#define SC_R_MU_12B 234U +#define SC_R_MU_13B 235U +#define SC_R_ROM_0 236U +#define SC_R_FSPI_0 237U +#define SC_R_FSPI_1 238U +#define SC_R_IEE 239U +#define SC_R_IEE_R0 240U +#define SC_R_IEE_R1 241U +#define SC_R_IEE_R2 242U +#define SC_R_IEE_R3 243U +#define SC_R_IEE_R4 244U +#define SC_R_IEE_R5 245U +#define SC_R_IEE_R6 246U +#define SC_R_IEE_R7 247U +#define SC_R_SDHC_0 248U +#define SC_R_SDHC_1 249U +#define SC_R_SDHC_2 250U +#define SC_R_ENET_0 251U +#define SC_R_ENET_1 252U +#define SC_R_MLB_0 253U +#define SC_R_DMA_2_CH0 254U +#define SC_R_DMA_2_CH1 255U +#define SC_R_DMA_2_CH2 256U +#define SC_R_DMA_2_CH3 257U +#define SC_R_DMA_2_CH4 258U +#define SC_R_USB_0 259U +#define SC_R_USB_1 260U +#define SC_R_USB_0_PHY 261U +#define SC_R_USB_2 262U +#define SC_R_USB_2_PHY 263U +#define SC_R_DTCP 264U +#define SC_R_NAND 265U +#define SC_R_LVDS_0 266U +#define SC_R_LVDS_0_PWM_0 267U +#define SC_R_LVDS_0_I2C_0 268U +#define SC_R_LVDS_0_I2C_1 269U +#define SC_R_LVDS_1 270U +#define SC_R_LVDS_1_PWM_0 271U +#define SC_R_LVDS_1_I2C_0 272U +#define SC_R_LVDS_1_I2C_1 273U +#define SC_R_LVDS_2 274U +#define SC_R_LVDS_2_PWM_0 275U +#define SC_R_LVDS_2_I2C_0 276U +#define SC_R_LVDS_2_I2C_1 277U +#define SC_R_M4_0_PID0 278U +#define SC_R_M4_0_PID1 279U +#define SC_R_M4_0_PID2 280U +#define SC_R_M4_0_PID3 281U +#define SC_R_M4_0_PID4 282U +#define SC_R_M4_0_RGPIO 283U +#define SC_R_M4_0_SEMA42 284U +#define SC_R_M4_0_TPM 285U +#define SC_R_M4_0_PIT 286U +#define SC_R_M4_0_UART 287U +#define SC_R_M4_0_I2C 288U +#define SC_R_M4_0_INTMUX 289U +#define SC_R_M4_0_SIM 290U +#define SC_R_M4_0_WDOG 291U +#define SC_R_M4_0_MU_0B 292U +#define SC_R_M4_0_MU_0A0 293U +#define SC_R_M4_0_MU_0A1 294U +#define SC_R_M4_0_MU_0A2 295U +#define SC_R_M4_0_MU_0A3 296U +#define SC_R_M4_0_MU_1A 297U +#define SC_R_M4_1_PID0 298U +#define SC_R_M4_1_PID1 299U +#define SC_R_M4_1_PID2 300U +#define SC_R_M4_1_PID3 301U +#define SC_R_M4_1_PID4 302U +#define SC_R_M4_1_RGPIO 303U +#define SC_R_M4_1_SEMA42 304U +#define SC_R_M4_1_TPM 305U +#define SC_R_M4_1_PIT 306U +#define SC_R_M4_1_UART 307U +#define SC_R_M4_1_I2C 308U +#define SC_R_M4_1_INTMUX 309U +#define SC_R_M4_1_SIM 310U +#define SC_R_M4_1_WDOG 311U +#define SC_R_M4_1_MU_0B 312U +#define SC_R_M4_1_MU_0A0 313U +#define SC_R_M4_1_MU_0A1 314U +#define SC_R_M4_1_MU_0A2 315U +#define SC_R_M4_1_MU_0A3 316U +#define SC_R_M4_1_MU_1A 317U +#define SC_R_SAI_0 318U +#define SC_R_SAI_1 319U +#define SC_R_SAI_2 320U +#define SC_R_IRQSTR_SCU2 321U +#define SC_R_IRQSTR_DSP 322U +#define SC_R_UNUSED5 323U +#define SC_R_OCRAM 324U +#define SC_R_AUDIO_PLL_0 325U +#define SC_R_PI_0 326U +#define SC_R_PI_0_PWM_0 327U +#define SC_R_PI_0_PWM_1 328U +#define SC_R_PI_0_I2C_0 329U +#define SC_R_PI_0_PLL 330U +#define SC_R_PI_1 331U +#define SC_R_PI_1_PWM_0 332U +#define SC_R_PI_1_PWM_1 333U +#define SC_R_PI_1_I2C_0 334U +#define SC_R_PI_1_PLL 335U +#define SC_R_SC_PID0 336U +#define SC_R_SC_PID1 337U +#define SC_R_SC_PID2 338U +#define SC_R_SC_PID3 339U +#define SC_R_SC_PID4 340U +#define SC_R_SC_SEMA42 341U +#define SC_R_SC_TPM 342U +#define SC_R_SC_PIT 343U +#define SC_R_SC_UART 344U +#define SC_R_SC_I2C 345U +#define SC_R_SC_MU_0B 346U +#define SC_R_SC_MU_0A0 347U +#define SC_R_SC_MU_0A1 348U +#define SC_R_SC_MU_0A2 349U +#define SC_R_SC_MU_0A3 350U +#define SC_R_SC_MU_1A 351U +#define SC_R_SYSCNT_RD 352U +#define SC_R_SYSCNT_CMP 353U +#define SC_R_DEBUG 354U +#define SC_R_SYSTEM 355U +#define SC_R_SNVS 356U +#define SC_R_OTP 357U +#define SC_R_VPU_PID0 358U +#define SC_R_VPU_PID1 359U +#define SC_R_VPU_PID2 360U +#define SC_R_VPU_PID3 361U +#define SC_R_VPU_PID4 362U +#define SC_R_VPU_PID5 363U +#define SC_R_VPU_PID6 364U +#define SC_R_VPU_PID7 365U +#define SC_R_VPU_UART 366U +#define SC_R_VPUCORE 367U +#define SC_R_VPUCORE_0 368U +#define SC_R_VPUCORE_1 369U +#define SC_R_VPUCORE_2 370U +#define SC_R_VPUCORE_3 371U +#define SC_R_DMA_4_CH0 372U +#define SC_R_DMA_4_CH1 373U +#define SC_R_DMA_4_CH2 374U +#define SC_R_DMA_4_CH3 375U +#define SC_R_DMA_4_CH4 376U +#define SC_R_ISI_CH0 377U +#define SC_R_ISI_CH1 378U +#define SC_R_ISI_CH2 379U +#define SC_R_ISI_CH3 380U +#define SC_R_ISI_CH4 381U +#define SC_R_ISI_CH5 382U +#define SC_R_ISI_CH6 383U +#define SC_R_ISI_CH7 384U +#define SC_R_MJPEG_DEC_S0 385U +#define SC_R_MJPEG_DEC_S1 386U +#define SC_R_MJPEG_DEC_S2 387U +#define SC_R_MJPEG_DEC_S3 388U +#define SC_R_MJPEG_ENC_S0 389U +#define SC_R_MJPEG_ENC_S1 390U +#define SC_R_MJPEG_ENC_S2 391U +#define SC_R_MJPEG_ENC_S3 392U +#define SC_R_MIPI_0 393U +#define SC_R_MIPI_0_PWM_0 394U +#define SC_R_MIPI_0_I2C_0 395U +#define SC_R_MIPI_0_I2C_1 396U +#define SC_R_MIPI_1 397U +#define SC_R_MIPI_1_PWM_0 398U +#define SC_R_MIPI_1_I2C_0 399U +#define SC_R_MIPI_1_I2C_1 400U +#define SC_R_CSI_0 401U +#define SC_R_CSI_0_PWM_0 402U +#define SC_R_CSI_0_I2C_0 403U +#define SC_R_CSI_1 404U +#define SC_R_CSI_1_PWM_0 405U +#define SC_R_CSI_1_I2C_0 406U +#define SC_R_HDMI 407U +#define SC_R_HDMI_I2S 408U +#define SC_R_HDMI_I2C_0 409U +#define SC_R_HDMI_PLL_0 410U +#define SC_R_HDMI_RX 411U +#define SC_R_HDMI_RX_BYPASS 412U +#define SC_R_HDMI_RX_I2C_0 413U +#define SC_R_ASRC_0 414U +#define SC_R_ESAI_0 415U +#define SC_R_SPDIF_0 416U +#define SC_R_SPDIF_1 417U +#define SC_R_SAI_3 418U +#define SC_R_SAI_4 419U +#define SC_R_SAI_5 420U +#define SC_R_GPT_5 421U +#define SC_R_GPT_6 422U +#define SC_R_GPT_7 423U +#define SC_R_GPT_8 424U +#define SC_R_GPT_9 425U +#define SC_R_GPT_10 426U +#define SC_R_DMA_2_CH5 427U +#define SC_R_DMA_2_CH6 428U +#define SC_R_DMA_2_CH7 429U +#define SC_R_DMA_2_CH8 430U +#define SC_R_DMA_2_CH9 431U +#define SC_R_DMA_2_CH10 432U +#define SC_R_DMA_2_CH11 433U +#define SC_R_DMA_2_CH12 434U +#define SC_R_DMA_2_CH13 435U +#define SC_R_DMA_2_CH14 436U +#define SC_R_DMA_2_CH15 437U +#define SC_R_DMA_2_CH16 438U +#define SC_R_DMA_2_CH17 439U +#define SC_R_DMA_2_CH18 440U +#define SC_R_DMA_2_CH19 441U +#define SC_R_DMA_2_CH20 442U +#define SC_R_DMA_2_CH21 443U +#define SC_R_DMA_2_CH22 444U +#define SC_R_DMA_2_CH23 445U +#define SC_R_DMA_2_CH24 446U +#define SC_R_DMA_2_CH25 447U +#define SC_R_DMA_2_CH26 448U +#define SC_R_DMA_2_CH27 449U +#define SC_R_DMA_2_CH28 450U +#define SC_R_DMA_2_CH29 451U +#define SC_R_DMA_2_CH30 452U +#define SC_R_DMA_2_CH31 453U +#define SC_R_ASRC_1 454U +#define SC_R_ESAI_1 455U +#define SC_R_SAI_6 456U +#define SC_R_SAI_7 457U +#define SC_R_AMIX 458U +#define SC_R_MQS_0 459U +#define SC_R_DMA_3_CH0 460U +#define SC_R_DMA_3_CH1 461U +#define SC_R_DMA_3_CH2 462U +#define SC_R_DMA_3_CH3 463U +#define SC_R_DMA_3_CH4 464U +#define SC_R_DMA_3_CH5 465U +#define SC_R_DMA_3_CH6 466U +#define SC_R_DMA_3_CH7 467U +#define SC_R_DMA_3_CH8 468U +#define SC_R_DMA_3_CH9 469U +#define SC_R_DMA_3_CH10 470U +#define SC_R_DMA_3_CH11 471U +#define SC_R_DMA_3_CH12 472U +#define SC_R_DMA_3_CH13 473U +#define SC_R_DMA_3_CH14 474U +#define SC_R_DMA_3_CH15 475U +#define SC_R_DMA_3_CH16 476U +#define SC_R_DMA_3_CH17 477U +#define SC_R_DMA_3_CH18 478U +#define SC_R_DMA_3_CH19 479U +#define SC_R_DMA_3_CH20 480U +#define SC_R_DMA_3_CH21 481U +#define SC_R_DMA_3_CH22 482U +#define SC_R_DMA_3_CH23 483U +#define SC_R_DMA_3_CH24 484U +#define SC_R_DMA_3_CH25 485U +#define SC_R_DMA_3_CH26 486U +#define SC_R_DMA_3_CH27 487U +#define SC_R_DMA_3_CH28 488U +#define SC_R_DMA_3_CH29 489U +#define SC_R_DMA_3_CH30 490U +#define SC_R_DMA_3_CH31 491U +#define SC_R_AUDIO_PLL_1 492U +#define SC_R_AUDIO_CLK_0 493U +#define SC_R_AUDIO_CLK_1 494U +#define SC_R_MCLK_OUT_0 495U +#define SC_R_MCLK_OUT_1 496U +#define SC_R_PMIC_0 497U +#define SC_R_PMIC_1 498U +#define SC_R_SECO 499U +#define SC_R_CAAM_JR1 500U +#define SC_R_CAAM_JR2 501U +#define SC_R_CAAM_JR3 502U +#define SC_R_SECO_MU_2 503U +#define SC_R_SECO_MU_3 504U +#define SC_R_SECO_MU_4 505U +#define SC_R_HDMI_RX_PWM_0 506U +#define SC_R_A35 507U +#define SC_R_A35_0 508U +#define SC_R_A35_1 509U +#define SC_R_A35_2 510U +#define SC_R_A35_3 511U +#define SC_R_DSP 512U +#define SC_R_DSP_RAM 513U +#define SC_R_CAAM_JR1_OUT 514U +#define SC_R_CAAM_JR2_OUT 515U +#define SC_R_CAAM_JR3_OUT 516U +#define SC_R_VPU_DEC_0 517U +#define SC_R_VPU_ENC_0 518U +#define SC_R_CAAM_JR0 519U +#define SC_R_CAAM_JR0_OUT 520U +#define SC_R_PMIC_2 521U +#define SC_R_DBLOGIC 522U +#define SC_R_HDMI_PLL_1 523U +#define SC_R_BOARD_R0 524U +#define SC_R_BOARD_R1 525U +#define SC_R_BOARD_R2 526U +#define SC_R_BOARD_R3 527U +#define SC_R_BOARD_R4 528U +#define SC_R_BOARD_R5 529U +#define SC_R_BOARD_R6 530U +#define SC_R_BOARD_R7 531U +#define SC_R_MJPEG_DEC_MP 532U +#define SC_R_MJPEG_ENC_MP 533U +#define SC_R_VPU_TS_0 534U +#define SC_R_VPU_MU_0 535U +#define SC_R_VPU_MU_1 536U +#define SC_R_VPU_MU_2 537U +#define SC_R_VPU_MU_3 538U +#define SC_R_VPU_ENC_1 539U +#define SC_R_VPU 540U +#define SC_R_LAST 541U +#define SC_R_ALL ((sc_rsrc_t) UINT16_MAX) /*!< All resources */ +/*@}*/ + +/* NOTE - please add by replacing some of the UNUSED from above! */ + +/*! + * Defnes for sc_ctrl_t. + */ +#define SC_C_TEMP 0U +#define SC_C_TEMP_HI 1U +#define SC_C_TEMP_LOW 2U +#define SC_C_PXL_LINK_MST1_ADDR 3U +#define SC_C_PXL_LINK_MST2_ADDR 4U +#define SC_C_PXL_LINK_MST_ENB 5U +#define SC_C_PXL_LINK_MST1_ENB 6U +#define SC_C_PXL_LINK_MST2_ENB 7U +#define SC_C_PXL_LINK_SLV1_ADDR 8U +#define SC_C_PXL_LINK_SLV2_ADDR 9U +#define SC_C_PXL_LINK_MST_VLD 10U +#define SC_C_PXL_LINK_MST1_VLD 11U +#define SC_C_PXL_LINK_MST2_VLD 12U +#define SC_C_SINGLE_MODE 13U +#define SC_C_ID 14U +#define SC_C_PXL_CLK_POLARITY 15U +#define SC_C_LINESTATE 16U +#define SC_C_PCIE_G_RST 17U +#define SC_C_PCIE_BUTTON_RST 18U +#define SC_C_PCIE_PERST 19U +#define SC_C_PHY_RESET 20U +#define SC_C_PXL_LINK_RATE_CORRECTION 21U +#define SC_C_PANIC 22U +#define SC_C_PRIORITY_GROUP 23U +#define SC_C_TXCLK 24U +#define SC_C_CLKDIV 25U +#define SC_C_DISABLE_50 26U +#define SC_C_DISABLE_125 27U +#define SC_C_SEL_125 28U +#define SC_C_MODE 29U +#define SC_C_SYNC_CTRL0 30U +#define SC_C_KACHUNK_CNT 31U +#define SC_C_KACHUNK_SEL 32U +#define SC_C_SYNC_CTRL1 33U +#define SC_C_DPI_RESET 34U +#define SC_C_MIPI_RESET 35U +#define SC_C_DUAL_MODE 36U +#define SC_C_VOLTAGE 37U +#define SC_C_PXL_LINK_SEL 38U +#define SC_C_OFS_SEL 39U +#define SC_C_OFS_AUDIO 40U +#define SC_C_OFS_PERIPH 41U +#define SC_C_OFS_IRQ 42U +#define SC_C_RST0 43U +#define SC_C_RST1 44U +#define SC_C_SEL0 45U +#define SC_C_LAST 46U + +#define SC_P_ALL ((sc_pad_t) UINT16_MAX) /*!< All pads */ + +/* Types */ + +/*! + * This type is used to store a boolean + */ +typedef uint8_t sc_bool_t; + +/*! + * This type is used to store a system (full-size) address. + */ +typedef uint64_t sc_faddr_t; + +/*! + * This type is used to indicate error response for most functions. + */ +typedef uint8_t sc_err_t; + +/*! + * This type is used to indicate a resource. Resources include peripherals + * and bus masters (but not memory regions). Note items from list should + * never be changed or removed (only added to@the end of the list). + */ +typedef uint16_t sc_rsrc_t; + +/*! + * This type is used to indicate a control. + */ +typedef uint8_t sc_ctrl_t; + +/*! + * This type is used to indicate a pad. Valid values are SoC specific. + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +typedef uint16_t sc_pad_t; + +/* Extra documentation of standard types */ + +#ifdef DOXYGEN + /*! + * Type used to declare an 8-bit integer. + */ + typedef __INT8_TYPE__ int8_t; + + /*! + * Type used to declare a 16-bit integer. + */ + typedef __INT16_TYPE__ int16_t; + + /*! + * Type used to declare a 32-bit integer. + */ + typedef __INT32_TYPE__ int32_t; + + /*! + * Type used to declare a 64-bit integer. + */ + typedef __INT64_TYPE__ int64_t; + + /*! + * Type used to declare an 8-bit unsigned integer. + */ + typedef __UINT8_TYPE__ uint8_t; + + /*! + * Type used to declare a 16-bit unsigned integer. + */ + typedef __UINT16_TYPE__ uint16_t; + + /*! + * Type used to declare a 32-bit unsigned integer. + */ + typedef __UINT32_TYPE__ uint32_t; + + /*! + * Type used to declare a 64-bit unsigned integer. + */ + typedef __UINT64_TYPE__ uint64_t; +#endif + +#endif /* SC_TYPES_H */ + diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile new file mode 100644 index 0000000000..cfb7e34653 --- /dev/null +++ b/arch/arm/mach-imx/imx8/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += sci/svc/misc/rpc_clnt.o +obj-y += sci/svc/pad/rpc_clnt.o +obj-y += sci/svc/pm/rpc_clnt.o +obj-y += sci/svc/rm/rpc_clnt.o +obj-y += sci/svc/timer/rpc_clnt.o diff --git a/arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h b/arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h new file mode 100644 index 0000000000..ca0653d4da --- /dev/null +++ b/arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file for the IRQ RPC implementation. + * + * @addtogroup IRQ_SVC + * @{ + */ + +#ifndef SC_IRQ_RPC_H +#define SC_IRQ_RPC_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Defines for RPC IRQ function calls + */ +/*@{*/ +#define IRQ_FUNC_UNKNOWN 0 /*!< Unknown function */ +#define IRQ_FUNC_ENABLE 1U /*!< Index for irq_enable() RPC call */ +#define IRQ_FUNC_STATUS 2U /*!< Index for irq_status() RPC call */ +/*@}*/ + +/* Types */ + +/* Functions */ + +/*! + * This function dispatches an incoming IRQ RPC request. + * + * @param[in] caller_pt caller partition + * @param[in] msg pointer to RPC message + */ +void irq_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg); + +/*! + * This function translates and dispatches an IRQ RPC request. + * + * @param[in] ipc IPC handle + * @param[in] msg pointer to RPC message + */ +void irq_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg); + +#endif /* SC_IRQ_RPC_H */ + +/**@}*/ + diff --git a/arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c b/arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c new file mode 100644 index 0000000000..8ecff72e21 --- /dev/null +++ b/arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * File containing client-side RPC functions for the IRQ service. These + * functions are ported to clients that communicate to the SC. + * + * @addtogroup IRQ_SVC + * @{ + */ + +/* Includes */ + +#include <asm/arch/sci/types.h> +#include <asm/arch/sci/svc/rm/api.h> +#include <asm/arch/sci/svc/irq/api.h> +#include <asm/arch/sci/rpc.h> +#include "rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/* Local Functions */ + +sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, + sc_irq_group_t group, uint32_t mask, sc_bool_t enable) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_IRQ; + RPC_FUNC(&msg) = (uint8_t) IRQ_FUNC_ENABLE; + RPC_U32(&msg, 0U) = (uint32_t) mask; + RPC_U16(&msg, 4U) = (uint16_t) resource; + RPC_U8(&msg, 6U) = (uint8_t) group; + RPC_U8(&msg, 7U) = (uint8_t) enable; + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, + sc_irq_group_t group, uint32_t *status) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_IRQ; + RPC_FUNC(&msg) = (uint8_t) IRQ_FUNC_STATUS; + RPC_U16(&msg, 0U) = (uint16_t) resource; + RPC_U8(&msg, 2U) = (uint8_t) group; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (status != NULL) + { + *status = RPC_U32(&msg, 0U); + } + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +/**@}*/ + diff --git a/arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h b/arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h new file mode 100644 index 0000000000..fee681d889 --- /dev/null +++ b/arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file for the MISC RPC implementation. + * + * @addtogroup MISC_SVC + * @{ + */ + +#ifndef SC_MISC_RPC_H +#define SC_MISC_RPC_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Defines for RPC MISC function calls + */ +/*@{*/ +#define MISC_FUNC_UNKNOWN 0 /*!< Unknown function */ +#define MISC_FUNC_SET_CONTROL 1U /*!< Index for misc_set_control() RPC call */ +#define MISC_FUNC_GET_CONTROL 2U /*!< Index for misc_get_control() RPC call */ +#define MISC_FUNC_SET_MAX_DMA_GROUP 4U /*!< Index for misc_set_max_dma_group() RPC call */ +#define MISC_FUNC_SET_DMA_GROUP 5U /*!< Index for misc_set_dma_group() RPC call */ +#define MISC_FUNC_SECO_IMAGE_LOAD 8U /*!< Index for misc_seco_image_load() RPC call */ +#define MISC_FUNC_SECO_AUTHENTICATE 9U /*!< Index for misc_seco_authenticate() RPC call */ +#define MISC_FUNC_SECO_FUSE_WRITE 20U /*!< Index for misc_seco_fuse_write() RPC call */ +#define MISC_FUNC_SECO_ENABLE_DEBUG 21U /*!< Index for misc_seco_enable_debug() RPC call */ +#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U /*!< Index for misc_seco_forward_lifecycle() RPC call */ +#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U /*!< Index for misc_seco_return_lifecycle() RPC call */ +#define MISC_FUNC_SECO_BUILD_INFO 24U /*!< Index for misc_seco_build_info() RPC call */ +#define MISC_FUNC_DEBUG_OUT 10U /*!< Index for misc_debug_out() RPC call */ +#define MISC_FUNC_WAVEFORM_CAPTURE 6U /*!< Index for misc_waveform_capture() RPC call */ +#define MISC_FUNC_BUILD_INFO 15U /*!< Index for misc_build_info() RPC call */ +#define MISC_FUNC_UNIQUE_ID 19U /*!< Index for misc_unique_id() RPC call */ +#define MISC_FUNC_SET_ARI 3U /*!< Index for misc_set_ari() RPC call */ +#define MISC_FUNC_BOOT_STATUS 7U /*!< Index for misc_boot_status() RPC call */ +#define MISC_FUNC_BOOT_DONE 14U /*!< Index for misc_boot_done() RPC call */ +#define MISC_FUNC_OTP_FUSE_READ 11U /*!< Index for misc_otp_fuse_read() RPC call */ +#define MISC_FUNC_OTP_FUSE_WRITE 17U /*!< Index for misc_otp_fuse_write() RPC call */ +#define MISC_FUNC_SET_TEMP 12U /*!< Index for misc_set_temp() RPC call */ +#define MISC_FUNC_GET_TEMP 13U /*!< Index for misc_get_temp() RPC call */ +#define MISC_FUNC_GET_BOOT_DEV 16U /*!< Index for misc_get_boot_dev() RPC call */ +#define MISC_FUNC_GET_BUTTON_STATUS 18U /*!< Index for misc_get_button_status() RPC call */ +/*@}*/ + +/* Types */ + +/* Functions */ + +/*! + * This function dispatches an incoming MISC RPC request. + * + * @param[in] caller_pt caller partition + * @param[in] msg pointer to RPC message + */ +void misc_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg); + +/*! + * This function translates and dispatches an MISC RPC request. + * + * @param[in] ipc IPC handle + * @param[in] msg pointer to RPC message + */ +void misc_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg); + +#endif /* SC_MISC_RPC_H */ + +/**@}*/ + diff --git a/arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c b/arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c new file mode 100644 index 0000000000..b4a9741986 --- /dev/null +++ b/arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c @@ -0,0 +1,515 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * File containing client-side RPC functions for the MISC service. These + * functions are ported to clients that communicate to the SC. + * + * @addtogroup MISC_SVC + * @{ + */ + +/* Includes */ + +#include <asm/arch/sci/types.h> +#include <asm/arch/sci/svc/rm/api.h> +#include <asm/arch/sci/svc/misc/api.h> +#include <asm/arch/sci/rpc.h> +#include "rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/* Local Functions */ + +sc_err_t sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource, + sc_ctrl_t ctrl, uint32_t val) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SET_CONTROL; + RPC_U32(&msg, 0U) = (uint32_t) ctrl; + RPC_U32(&msg, 4U) = (uint32_t) val; + RPC_U16(&msg, 8U) = (uint16_t) resource; + RPC_SIZE(&msg) = 4U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, + sc_ctrl_t ctrl, uint32_t *val) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_GET_CONTROL; + RPC_U32(&msg, 0U) = (uint32_t) ctrl; + RPC_U16(&msg, 4U) = (uint16_t) resource; + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (val != NULL) + { + *val = RPC_U32(&msg, 0U); + } + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_set_max_dma_group(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_misc_dma_group_t max) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SET_MAX_DMA_GROUP; + RPC_U8(&msg, 0U) = (uint8_t) pt; + RPC_U8(&msg, 1U) = (uint8_t) max; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_set_dma_group(sc_ipc_t ipc, sc_rsrc_t resource, + sc_misc_dma_group_t group) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SET_DMA_GROUP; + RPC_U16(&msg, 0U) = (uint16_t) resource; + RPC_U8(&msg, 2U) = (uint8_t) group; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_seco_image_load(sc_ipc_t ipc, sc_faddr_t addr_src, + sc_faddr_t addr_dst, uint32_t len, sc_bool_t fw) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SECO_IMAGE_LOAD; + RPC_U32(&msg, 0U) = (uint32_t) (addr_src >> 32U); + RPC_U32(&msg, 4U) = (uint32_t) addr_src; + RPC_U32(&msg, 8U) = (uint32_t) (addr_dst >> 32U); + RPC_U32(&msg, 12U) = (uint32_t) addr_dst; + RPC_U32(&msg, 16U) = (uint32_t) len; + RPC_U8(&msg, 20U) = (uint8_t) fw; + RPC_SIZE(&msg) = 7U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_seco_authenticate(sc_ipc_t ipc, + sc_misc_seco_auth_cmd_t cmd, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SECO_AUTHENTICATE; + RPC_U32(&msg, 0U) = (uint32_t) (addr >> 32U); + RPC_U32(&msg, 4U) = (uint32_t) addr; + RPC_U8(&msg, 8U) = (uint8_t) cmd; + RPC_SIZE(&msg) = 4U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SECO_FUSE_WRITE; + RPC_U32(&msg, 0U) = (uint32_t) (addr >> 32U); + RPC_U32(&msg, 4U) = (uint32_t) addr; + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_seco_enable_debug(sc_ipc_t ipc, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SECO_ENABLE_DEBUG; + RPC_U32(&msg, 0U) = (uint32_t) (addr >> 32U); + RPC_U32(&msg, 4U) = (uint32_t) addr; + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t lifecycle) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SECO_FORWARD_LIFECYCLE; + RPC_U32(&msg, 0U) = (uint32_t) lifecycle; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_seco_return_lifecycle(sc_ipc_t ipc, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SECO_RETURN_LIFECYCLE; + RPC_U32(&msg, 0U) = (uint32_t) (addr >> 32U); + RPC_U32(&msg, 4U) = (uint32_t) addr; + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +void sc_misc_seco_build_info(sc_ipc_t ipc, uint32_t *version, + uint32_t *commit) +{ + sc_rpc_msg_t msg; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SECO_BUILD_INFO; + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (version != NULL) + { + *version = RPC_U32(&msg, 0U); + } + + if (commit != NULL) + { + *commit = RPC_U32(&msg, 4U); + } + + return; +} + +void sc_misc_debug_out(sc_ipc_t ipc, uint8_t ch) +{ + sc_rpc_msg_t msg; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_DEBUG_OUT; + RPC_U8(&msg, 0U) = (uint8_t) ch; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + return; +} + +sc_err_t sc_misc_waveform_capture(sc_ipc_t ipc, sc_bool_t enable) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_WAVEFORM_CAPTURE; + RPC_U8(&msg, 0U) = (uint8_t) enable; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +void sc_misc_build_info(sc_ipc_t ipc, uint32_t *build, + uint32_t *commit) +{ + sc_rpc_msg_t msg; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_BUILD_INFO; + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (build != NULL) + { + *build = RPC_U32(&msg, 0U); + } + + if (commit != NULL) + { + *commit = RPC_U32(&msg, 4U); + } + + return; +} + +void sc_misc_unique_id(sc_ipc_t ipc, uint32_t *id_l, + uint32_t *id_h) +{ + sc_rpc_msg_t msg; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_UNIQUE_ID; + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (id_l != NULL) + { + *id_l = RPC_U32(&msg, 0U); + } + + if (id_h != NULL) + { + *id_h = RPC_U32(&msg, 4U); + } + + return; +} + +sc_err_t sc_misc_set_ari(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rsrc_t resource_mst, uint16_t ari, sc_bool_t enable) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SET_ARI; + RPC_U16(&msg, 0U) = (uint16_t) resource; + RPC_U16(&msg, 2U) = (uint16_t) resource_mst; + RPC_U16(&msg, 4U) = (uint16_t) ari; + RPC_U8(&msg, 6U) = (uint8_t) enable; + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status) +{ + sc_rpc_msg_t msg; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_BOOT_STATUS; + RPC_U8(&msg, 0U) = (uint8_t) status; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_TRUE); + + return; +} + +sc_err_t sc_misc_boot_done(sc_ipc_t ipc, sc_rsrc_t cpu) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_BOOT_DONE; + RPC_U16(&msg, 0U) = (uint16_t) cpu; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_otp_fuse_read(sc_ipc_t ipc, uint32_t word, uint32_t *val) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_OTP_FUSE_READ; + RPC_U32(&msg, 0U) = (uint32_t) word; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (val != NULL) + { + *val = RPC_U32(&msg, 0U); + } + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_otp_fuse_write(sc_ipc_t ipc, uint32_t word, uint32_t val) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_OTP_FUSE_WRITE; + RPC_U32(&msg, 0U) = (uint32_t) word; + RPC_U32(&msg, 4U) = (uint32_t) val; + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_set_temp(sc_ipc_t ipc, sc_rsrc_t resource, + sc_misc_temp_t temp, int16_t celsius, int8_t tenths) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SET_TEMP; + RPC_U16(&msg, 0U) = (uint16_t) resource; + RPC_I16(&msg, 2U) = (int16_t) celsius; + RPC_U8(&msg, 4U) = (uint8_t) temp; + RPC_I8(&msg, 5U) = (int8_t) tenths; + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, + sc_misc_temp_t temp, int16_t *celsius, int8_t *tenths) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_GET_TEMP; + RPC_U16(&msg, 0U) = (uint16_t) resource; + RPC_U8(&msg, 2U) = (uint8_t) temp; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (celsius != NULL) + { + *celsius = RPC_I16(&msg, 0U); + } + + result = RPC_R8(&msg); + if (tenths != NULL) + { + *tenths = RPC_I8(&msg, 2U); + } + + return (sc_err_t) result; +} + +void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *dev) +{ + sc_rpc_msg_t msg; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_GET_BOOT_DEV; + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (dev != NULL) + { + *dev = RPC_U16(&msg, 0U); + } + + return; +} + +void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status) +{ + sc_rpc_msg_t msg; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_GET_BUTTON_STATUS; + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (status != NULL) + { + *status = RPC_U8(&msg, 0U); + } + + return; +} + +/**@}*/ + diff --git a/arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h b/arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h new file mode 100644 index 0000000000..b658dcc23d --- /dev/null +++ b/arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file for the PAD RPC implementation. + * + * @addtogroup PAD_SVC + * @{ + */ + +#ifndef SC_PAD_RPC_H +#define SC_PAD_RPC_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Defines for RPC PAD function calls + */ +/*@{*/ +#define PAD_FUNC_UNKNOWN 0 /*!< Unknown function */ +#define PAD_FUNC_SET_MUX 1U /*!< Index for pad_set_mux() RPC call */ +#define PAD_FUNC_GET_MUX 6U /*!< Index for pad_get_mux() RPC call */ +#define PAD_FUNC_SET_GP 2U /*!< Index for pad_set_gp() RPC call */ +#define PAD_FUNC_GET_GP 7U /*!< Index for pad_get_gp() RPC call */ +#define PAD_FUNC_SET_WAKEUP 4U /*!< Index for pad_set_wakeup() RPC call */ +#define PAD_FUNC_GET_WAKEUP 9U /*!< Index for pad_get_wakeup() RPC call */ +#define PAD_FUNC_SET_ALL 5U /*!< Index for pad_set_all() RPC call */ +#define PAD_FUNC_GET_ALL 10U /*!< Index for pad_get_all() RPC call */ +#define PAD_FUNC_SET 15U /*!< Index for pad_set() RPC call */ +#define PAD_FUNC_GET 16U /*!< Index for pad_get() RPC call */ +#define PAD_FUNC_SET_GP_28FDSOI 11U /*!< Index for pad_set_gp_28fdsoi() RPC call */ +#define PAD_FUNC_GET_GP_28FDSOI 12U /*!< Index for pad_get_gp_28fdsoi() RPC call */ +#define PAD_FUNC_SET_GP_28FDSOI_HSIC 3U /*!< Index for pad_set_gp_28fdsoi_hsic() RPC call */ +#define PAD_FUNC_GET_GP_28FDSOI_HSIC 8U /*!< Index for pad_get_gp_28fdsoi_hsic() RPC call */ +#define PAD_FUNC_SET_GP_28FDSOI_COMP 13U /*!< Index for pad_set_gp_28fdsoi_comp() RPC call */ +#define PAD_FUNC_GET_GP_28FDSOI_COMP 14U /*!< Index for pad_get_gp_28fdsoi_comp() RPC call */ +/*@}*/ + +/* Types */ + +/* Functions */ + +/*! + * This function dispatches an incoming PAD RPC request. + * + * @param[in] caller_pt caller partition + * @param[in] msg pointer to RPC message + */ +void pad_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg); + +/*! + * This function translates and dispatches an PAD RPC request. + * + * @param[in] ipc IPC handle + * @param[in] msg pointer to RPC message + */ +void pad_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg); + +#endif /* SC_PAD_RPC_H */ + +/**@}*/ + diff --git a/arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c b/arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c new file mode 100644 index 0000000000..4a93c1a48e --- /dev/null +++ b/arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c @@ -0,0 +1,475 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * File containing client-side RPC functions for the PAD service. These + * functions are ported to clients that communicate to the SC. + * + * @addtogroup PAD_SVC + * @{ + */ + +/* Includes */ + +#include <asm/arch/sci/types.h> +#include <asm/arch/sci/svc/rm/api.h> +#include <asm/arch/sci/svc/pad/api.h> +#include <asm/arch/sci/rpc.h> +#include "rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/* Local Functions */ + +sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad, + uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_MUX; + RPC_U16(&msg, 0U) = (uint16_t) pad; + RPC_U8(&msg, 2U) = (uint8_t) mux; + RPC_U8(&msg, 3U) = (uint8_t) config; + RPC_U8(&msg, 4U) = (uint8_t) iso; + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pad_t pad, + uint8_t *mux, sc_pad_config_t *config, sc_pad_iso_t *iso) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_MUX; + RPC_U16(&msg, 0U) = (uint16_t) pad; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (mux != NULL) + { + *mux = RPC_U8(&msg, 0U); + } + + if (config != NULL) + { + *config = RPC_U8(&msg, 1U); + } + + if (iso != NULL) + { + *iso = RPC_U8(&msg, 2U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t ctrl) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_GP; + RPC_U32(&msg, 0U) = (uint32_t) ctrl; + RPC_U16(&msg, 4U) = (uint16_t) pad; + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_GP; + RPC_U16(&msg, 0U) = (uint16_t) pad; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (ctrl != NULL) + { + *ctrl = RPC_U32(&msg, 0U); + } + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_wakeup_t wakeup) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_WAKEUP; + RPC_U16(&msg, 0U) = (uint16_t) pad; + RPC_U8(&msg, 2U) = (uint8_t) wakeup; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_wakeup_t *wakeup) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_WAKEUP; + RPC_U16(&msg, 0U) = (uint16_t) pad; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (wakeup != NULL) + { + *wakeup = RPC_U8(&msg, 0U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux, + sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl, + sc_pad_wakeup_t wakeup) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_ALL; + RPC_U32(&msg, 0U) = (uint32_t) ctrl; + RPC_U16(&msg, 4U) = (uint16_t) pad; + RPC_U8(&msg, 6U) = (uint8_t) mux; + RPC_U8(&msg, 7U) = (uint8_t) config; + RPC_U8(&msg, 8U) = (uint8_t) iso; + RPC_U8(&msg, 9U) = (uint8_t) wakeup; + RPC_SIZE(&msg) = 4U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t *mux, + sc_pad_config_t *config, sc_pad_iso_t *iso, uint32_t *ctrl, + sc_pad_wakeup_t *wakeup) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_ALL; + RPC_U16(&msg, 0U) = (uint16_t) pad; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (ctrl != NULL) + { + *ctrl = RPC_U32(&msg, 0U); + } + + result = RPC_R8(&msg); + if (mux != NULL) + { + *mux = RPC_U8(&msg, 4U); + } + + if (config != NULL) + { + *config = RPC_U8(&msg, 5U); + } + + if (iso != NULL) + { + *iso = RPC_U8(&msg, 6U); + } + + if (wakeup != NULL) + { + *wakeup = RPC_U8(&msg, 7U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, uint32_t val) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET; + RPC_U32(&msg, 0U) = (uint32_t) val; + RPC_U16(&msg, 4U) = (uint16_t) pad; + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET; + RPC_U16(&msg, 0U) = (uint16_t) pad; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (val != NULL) + { + *val = RPC_U32(&msg, 0U); + } + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_GP_28FDSOI; + RPC_U16(&msg, 0U) = (uint16_t) pad; + RPC_U8(&msg, 2U) = (uint8_t) dse; + RPC_U8(&msg, 3U) = (uint8_t) ps; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t *dse, sc_pad_28fdsoi_ps_t *ps) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_GP_28FDSOI; + RPC_U16(&msg, 0U) = (uint16_t) pad; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (dse != NULL) + { + *dse = RPC_U8(&msg, 0U); + } + + if (ps != NULL) + { + *ps = RPC_U8(&msg, 1U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t dse, sc_bool_t hys, sc_pad_28fdsoi_pus_t pus, + sc_bool_t pke, sc_bool_t pue) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_GP_28FDSOI_HSIC; + RPC_U16(&msg, 0U) = (uint16_t) pad; + RPC_U8(&msg, 2U) = (uint8_t) dse; + RPC_U8(&msg, 3U) = (uint8_t) pus; + RPC_U8(&msg, 4U) = (uint8_t) hys; + RPC_U8(&msg, 5U) = (uint8_t) pke; + RPC_U8(&msg, 6U) = (uint8_t) pue; + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys, sc_pad_28fdsoi_pus_t *pus, + sc_bool_t *pke, sc_bool_t *pue) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_GP_28FDSOI_HSIC; + RPC_U16(&msg, 0U) = (uint16_t) pad; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (dse != NULL) + { + *dse = RPC_U8(&msg, 0U); + } + + if (pus != NULL) + { + *pus = RPC_U8(&msg, 1U); + } + + if (hys != NULL) + { + *hys = RPC_U8(&msg, 2U); + } + + if (pke != NULL) + { + *pke = RPC_U8(&msg, 3U); + } + + if (pue != NULL) + { + *pue = RPC_U8(&msg, 4U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad, + uint8_t compen, sc_bool_t fastfrz, uint8_t rasrcp, uint8_t rasrcn, + sc_bool_t nasrc_sel, sc_bool_t psw_ovr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_GP_28FDSOI_COMP; + RPC_U16(&msg, 0U) = (uint16_t) pad; + RPC_U8(&msg, 2U) = (uint8_t) compen; + RPC_U8(&msg, 3U) = (uint8_t) rasrcp; + RPC_U8(&msg, 4U) = (uint8_t) rasrcn; + RPC_U8(&msg, 5U) = (uint8_t) fastfrz; + RPC_U8(&msg, 6U) = (uint8_t) nasrc_sel; + RPC_U8(&msg, 7U) = (uint8_t) psw_ovr; + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad, + uint8_t *compen, sc_bool_t *fastfrz, uint8_t *rasrcp, uint8_t *rasrcn, + sc_bool_t *nasrc_sel, sc_bool_t *compok, uint8_t *nasrc, sc_bool_t *psw_ovr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_GP_28FDSOI_COMP; + RPC_U16(&msg, 0U) = (uint16_t) pad; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (compen != NULL) + { + *compen = RPC_U8(&msg, 0U); + } + + if (rasrcp != NULL) + { + *rasrcp = RPC_U8(&msg, 1U); + } + + if (rasrcn != NULL) + { + *rasrcn = RPC_U8(&msg, 2U); + } + + if (nasrc != NULL) + { + *nasrc = RPC_U8(&msg, 3U); + } + + if (fastfrz != NULL) + { + *fastfrz = RPC_U8(&msg, 4U); + } + + if (nasrc_sel != NULL) + { + *nasrc_sel = RPC_U8(&msg, 5U); + } + + if (compok != NULL) + { + *compok = RPC_U8(&msg, 6U); + } + + if (psw_ovr != NULL) + { + *psw_ovr = RPC_U8(&msg, 7U); + } + + return (sc_err_t) result; +} + +/**@}*/ + diff --git a/arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h b/arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h new file mode 100644 index 0000000000..49046c2ca7 --- /dev/null +++ b/arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file for the PM RPC implementation. + * + * @addtogroup PM_SVC + * @{ + */ + +#ifndef SC_PM_RPC_H +#define SC_PM_RPC_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Defines for RPC PM function calls + */ +/*@{*/ +#define PM_FUNC_UNKNOWN 0 /*!< Unknown function */ +#define PM_FUNC_SET_SYS_POWER_MODE 19U /*!< Index for pm_set_sys_power_mode() RPC call */ +#define PM_FUNC_SET_PARTITION_POWER_MODE 1U /*!< Index for pm_set_partition_power_mode() RPC call */ +#define PM_FUNC_GET_SYS_POWER_MODE 2U /*!< Index for pm_get_sys_power_mode() RPC call */ +#define PM_FUNC_SET_RESOURCE_POWER_MODE 3U /*!< Index for pm_set_resource_power_mode() RPC call */ +#define PM_FUNC_GET_RESOURCE_POWER_MODE 4U /*!< Index for pm_get_resource_power_mode() RPC call */ +#define PM_FUNC_REQ_LOW_POWER_MODE 16U /*!< Index for pm_req_low_power_mode() RPC call */ +#define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U /*!< Index for pm_req_cpu_low_power_mode() RPC call */ +#define PM_FUNC_SET_CPU_RESUME_ADDR 17U /*!< Index for pm_set_cpu_resume_addr() RPC call */ +#define PM_FUNC_SET_CPU_RESUME 21U /*!< Index for pm_set_cpu_resume() RPC call */ +#define PM_FUNC_REQ_SYS_IF_POWER_MODE 18U /*!< Index for pm_req_sys_if_power_mode() RPC call */ +#define PM_FUNC_SET_CLOCK_RATE 5U /*!< Index for pm_set_clock_rate() RPC call */ +#define PM_FUNC_GET_CLOCK_RATE 6U /*!< Index for pm_get_clock_rate() RPC call */ +#define PM_FUNC_CLOCK_ENABLE 7U /*!< Index for pm_clock_enable() RPC call */ +#define PM_FUNC_SET_CLOCK_PARENT 14U /*!< Index for pm_set_clock_parent() RPC call */ +#define PM_FUNC_GET_CLOCK_PARENT 15U /*!< Index for pm_get_clock_parent() RPC call */ +#define PM_FUNC_RESET 13U /*!< Index for pm_reset() RPC call */ +#define PM_FUNC_RESET_REASON 10U /*!< Index for pm_reset_reason() RPC call */ +#define PM_FUNC_BOOT 8U /*!< Index for pm_boot() RPC call */ +#define PM_FUNC_REBOOT 9U /*!< Index for pm_reboot() RPC call */ +#define PM_FUNC_REBOOT_PARTITION 12U /*!< Index for pm_reboot_partition() RPC call */ +#define PM_FUNC_CPU_START 11U /*!< Index for pm_cpu_start() RPC call */ +/*@}*/ + +/* Types */ + +/* Functions */ + +/*! + * This function dispatches an incoming PM RPC request. + * + * @param[in] caller_pt caller partition + * @param[in] msg pointer to RPC message + */ +void pm_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg); + +/*! + * This function translates and dispatches an PM RPC request. + * + * @param[in] ipc IPC handle + * @param[in] msg pointer to RPC message + */ +void pm_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg); + +#endif /* SC_PM_RPC_H */ + +/**@}*/ + diff --git a/arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c b/arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c new file mode 100644 index 0000000000..6cad000354 --- /dev/null +++ b/arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c @@ -0,0 +1,460 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * File containing client-side RPC functions for the PM service. These + * functions are ported to clients that communicate to the SC. + * + * @addtogroup PM_SVC + * @{ + */ + +/* Includes */ + +#include <asm/arch/sci/types.h> +#include <asm/arch/sci/svc/rm/api.h> +#include <asm/arch/sci/svc/pm/api.h> +#include <asm/arch/sci/rpc.h> +#include "rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/* Local Functions */ + +sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_pm_power_mode_t mode) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_SYS_POWER_MODE; + RPC_U8(&msg, 0U) = (uint8_t) mode; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_pm_power_mode_t mode) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_PARTITION_POWER_MODE; + RPC_U8(&msg, 0U) = (uint8_t) pt; + RPC_U8(&msg, 1U) = (uint8_t) mode; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_pm_power_mode_t *mode) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_GET_SYS_POWER_MODE; + RPC_U8(&msg, 0U) = (uint8_t) pt; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (mode != NULL) + { + *mode = RPC_U8(&msg, 0U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_RESOURCE_POWER_MODE; + RPC_U16(&msg, 0U) = (uint16_t) resource; + RPC_U8(&msg, 2U) = (uint8_t) mode; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t *mode) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_GET_RESOURCE_POWER_MODE; + RPC_U16(&msg, 0U) = (uint16_t) resource; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (mode != NULL) + { + *mode = RPC_U8(&msg, 0U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_REQ_LOW_POWER_MODE; + RPC_U16(&msg, 0U) = (uint16_t) resource; + RPC_U8(&msg, 2U) = (uint8_t) mode; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_req_cpu_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode, sc_pm_wake_src_t wake_src) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_REQ_CPU_LOW_POWER_MODE; + RPC_U16(&msg, 0U) = (uint16_t) resource; + RPC_U8(&msg, 2U) = (uint8_t) mode; + RPC_U8(&msg, 3U) = (uint8_t) wake_src; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource, + sc_faddr_t address) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_CPU_RESUME_ADDR; + RPC_U32(&msg, 0U) = (uint32_t) (address >> 32U); + RPC_U32(&msg, 4U) = (uint32_t) address; + RPC_U16(&msg, 8U) = (uint16_t) resource; + RPC_SIZE(&msg) = 4U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_set_cpu_resume(sc_ipc_t ipc, sc_rsrc_t resource, + sc_bool_t isPrimary, sc_faddr_t address) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_CPU_RESUME; + RPC_U32(&msg, 0U) = (uint32_t) (address >> 32U); + RPC_U32(&msg, 4U) = (uint32_t) address; + RPC_U16(&msg, 8U) = (uint16_t) resource; + RPC_U8(&msg, 10U) = (uint8_t) isPrimary; + RPC_SIZE(&msg) = 4U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, sc_pm_power_mode_t lpm) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_REQ_SYS_IF_POWER_MODE; + RPC_U16(&msg, 0U) = (uint16_t) resource; + RPC_U8(&msg, 2U) = (uint8_t) sys_if; + RPC_U8(&msg, 3U) = (uint8_t) hpm; + RPC_U8(&msg, 4U) = (uint8_t) lpm; + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clock_rate_t *rate) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_CLOCK_RATE; + RPC_U32(&msg, 0U) = *(uint32_t*) rate; + RPC_U16(&msg, 4U) = (uint16_t) resource; + RPC_U8(&msg, 6U) = (uint8_t) clk; + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + *rate = RPC_U32(&msg, 0U); + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clock_rate_t *rate) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_GET_CLOCK_RATE; + RPC_U16(&msg, 0U) = (uint16_t) resource; + RPC_U8(&msg, 2U) = (uint8_t) clk; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (rate != NULL) + { + *rate = RPC_U32(&msg, 0U); + } + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_CLOCK_ENABLE; + RPC_U16(&msg, 0U) = (uint16_t) resource; + RPC_U8(&msg, 2U) = (uint8_t) clk; + RPC_U8(&msg, 3U) = (uint8_t) enable; + RPC_U8(&msg, 4U) = (uint8_t) autog; + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clk_parent_t parent) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_CLOCK_PARENT; + RPC_U16(&msg, 0U) = (uint16_t) resource; + RPC_U8(&msg, 2U) = (uint8_t) clk; + RPC_U8(&msg, 3U) = (uint8_t) parent; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clk_parent_t *parent) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_GET_CLOCK_PARENT; + RPC_U16(&msg, 0U) = (uint16_t) resource; + RPC_U8(&msg, 2U) = (uint8_t) clk; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (parent != NULL) + { + *parent = RPC_U8(&msg, 0U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_RESET; + RPC_U8(&msg, 0U) = (uint8_t) type; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_RESET_REASON; + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (reason != NULL) + { + *reason = RPC_U8(&msg, 0U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_rsrc_t resource_cpu, sc_faddr_t boot_addr, + sc_rsrc_t resource_mu, sc_rsrc_t resource_dev) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_BOOT; + RPC_U32(&msg, 0U) = (uint32_t) (boot_addr >> 32U); + RPC_U32(&msg, 4U) = (uint32_t) boot_addr; + RPC_U16(&msg, 8U) = (uint16_t) resource_cpu; + RPC_U16(&msg, 10U) = (uint16_t) resource_mu; + RPC_U16(&msg, 12U) = (uint16_t) resource_dev; + RPC_U8(&msg, 14U) = (uint8_t) pt; + RPC_SIZE(&msg) = 5U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type) +{ + sc_rpc_msg_t msg; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_REBOOT; + RPC_U8(&msg, 0U) = (uint8_t) type; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_TRUE); + + return; +} + +sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_pm_reset_type_t type) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_REBOOT_PARTITION; + RPC_U8(&msg, 0U) = (uint8_t) pt; + RPC_U8(&msg, 1U) = (uint8_t) type; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, + sc_faddr_t address) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_CPU_START; + RPC_U32(&msg, 0U) = (uint32_t) (address >> 32U); + RPC_U32(&msg, 4U) = (uint32_t) address; + RPC_U16(&msg, 8U) = (uint16_t) resource; + RPC_U8(&msg, 10U) = (uint8_t) enable; + RPC_SIZE(&msg) = 4U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +/**@}*/ + diff --git a/arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h b/arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h new file mode 100644 index 0000000000..196615e937 --- /dev/null +++ b/arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file for the RM RPC implementation. + * + * @addtogroup RM_SVC + * @{ + */ + +#ifndef SC_RM_RPC_H +#define SC_RM_RPC_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Defines for RPC RM function calls + */ +/*@{*/ +#define RM_FUNC_UNKNOWN 0 /*!< Unknown function */ +#define RM_FUNC_PARTITION_ALLOC 1U /*!< Index for rm_partition_alloc() RPC call */ +#define RM_FUNC_SET_CONFIDENTIAL 31U /*!< Index for rm_set_confidential() RPC call */ +#define RM_FUNC_PARTITION_FREE 2U /*!< Index for rm_partition_free() RPC call */ +#define RM_FUNC_GET_DID 26U /*!< Index for rm_get_did() RPC call */ +#define RM_FUNC_PARTITION_STATIC 3U /*!< Index for rm_partition_static() RPC call */ +#define RM_FUNC_PARTITION_LOCK 4U /*!< Index for rm_partition_lock() RPC call */ +#define RM_FUNC_GET_PARTITION 5U /*!< Index for rm_get_partition() RPC call */ +#define RM_FUNC_SET_PARENT 6U /*!< Index for rm_set_parent() RPC call */ +#define RM_FUNC_MOVE_ALL 7U /*!< Index for rm_move_all() RPC call */ +#define RM_FUNC_ASSIGN_RESOURCE 8U /*!< Index for rm_assign_resource() RPC call */ +#define RM_FUNC_SET_RESOURCE_MOVABLE 9U /*!< Index for rm_set_resource_movable() RPC call */ +#define RM_FUNC_SET_SUBSYS_RSRC_MOVABLE 28U /*!< Index for rm_set_subsys_rsrc_movable() RPC call */ +#define RM_FUNC_SET_MASTER_ATTRIBUTES 10U /*!< Index for rm_set_master_attributes() RPC call */ +#define RM_FUNC_SET_MASTER_SID 11U /*!< Index for rm_set_master_sid() RPC call */ +#define RM_FUNC_SET_PERIPHERAL_PERMISSIONS 12U /*!< Index for rm_set_peripheral_permissions() RPC call */ +#define RM_FUNC_IS_RESOURCE_OWNED 13U /*!< Index for rm_is_resource_owned() RPC call */ +#define RM_FUNC_IS_RESOURCE_MASTER 14U /*!< Index for rm_is_resource_master() RPC call */ +#define RM_FUNC_IS_RESOURCE_PERIPHERAL 15U /*!< Index for rm_is_resource_peripheral() RPC call */ +#define RM_FUNC_GET_RESOURCE_INFO 16U /*!< Index for rm_get_resource_info() RPC call */ +#define RM_FUNC_MEMREG_ALLOC 17U /*!< Index for rm_memreg_alloc() RPC call */ +#define RM_FUNC_MEMREG_SPLIT 29U /*!< Index for rm_memreg_split() RPC call */ +#define RM_FUNC_MEMREG_FREE 18U /*!< Index for rm_memreg_free() RPC call */ +#define RM_FUNC_FIND_MEMREG 30U /*!< Index for rm_find_memreg() RPC call */ +#define RM_FUNC_ASSIGN_MEMREG 19U /*!< Index for rm_assign_memreg() RPC call */ +#define RM_FUNC_SET_MEMREG_PERMISSIONS 20U /*!< Index for rm_set_memreg_permissions() RPC call */ +#define RM_FUNC_IS_MEMREG_OWNED 21U /*!< Index for rm_is_memreg_owned() RPC call */ +#define RM_FUNC_GET_MEMREG_INFO 22U /*!< Index for rm_get_memreg_info() RPC call */ +#define RM_FUNC_ASSIGN_PAD 23U /*!< Index for rm_assign_pad() RPC call */ +#define RM_FUNC_SET_PAD_MOVABLE 24U /*!< Index for rm_set_pad_movable() RPC call */ +#define RM_FUNC_IS_PAD_OWNED 25U /*!< Index for rm_is_pad_owned() RPC call */ +#define RM_FUNC_DUMP 27U /*!< Index for rm_dump() RPC call */ +/*@}*/ + +/* Types */ + +/* Functions */ + +/*! + * This function dispatches an incoming RM RPC request. + * + * @param[in] caller_pt caller partition + * @param[in] msg pointer to RPC message + */ +void rm_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg); + +/*! + * This function translates and dispatches an RM RPC request. + * + * @param[in] ipc IPC handle + * @param[in] msg pointer to RPC message + */ +void rm_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg); + +#endif /* SC_RM_RPC_H */ + +/**@}*/ + diff --git a/arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c b/arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c new file mode 100644 index 0000000000..d1475cf643 --- /dev/null +++ b/arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c @@ -0,0 +1,645 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * File containing client-side RPC functions for the RM service. These + * functions are ported to clients that communicate to the SC. + * + * @addtogroup RM_SVC + * @{ + */ + +/* Includes */ + +#include <asm/arch/sci/types.h> +#include <asm/arch/sci/svc/rm/api.h> +#include <asm/arch/sci/rpc.h> +#include "rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/* Local Functions */ + +sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure, + sc_bool_t isolated, sc_bool_t restricted, sc_bool_t grant, sc_bool_t coherent) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_PARTITION_ALLOC; + RPC_U8(&msg, 0U) = (uint8_t) secure; + RPC_U8(&msg, 1U) = (uint8_t) isolated; + RPC_U8(&msg, 2U) = (uint8_t) restricted; + RPC_U8(&msg, 3U) = (uint8_t) grant; + RPC_U8(&msg, 4U) = (uint8_t) coherent; + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (pt != NULL) + { + *pt = RPC_U8(&msg, 0U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t retro) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_CONFIDENTIAL; + RPC_U8(&msg, 0U) = (uint8_t) pt; + RPC_U8(&msg, 1U) = (uint8_t) retro; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_PARTITION_FREE; + RPC_U8(&msg, 0U) = (uint8_t) pt; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_rm_did_t sc_rm_get_did(sc_ipc_t ipc) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_GET_DID; + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_rm_did_t) result; +} + +sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_rm_did_t did) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_PARTITION_STATIC; + RPC_U8(&msg, 0U) = (uint8_t) pt; + RPC_U8(&msg, 1U) = (uint8_t) did; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_partition_lock(sc_ipc_t ipc, sc_rm_pt_t pt) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_PARTITION_LOCK; + RPC_U8(&msg, 0U) = (uint8_t) pt; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_GET_PARTITION; + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (pt != NULL) + { + *pt = RPC_U8(&msg, 0U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_rm_pt_t pt_parent) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_PARENT; + RPC_U8(&msg, 0U) = (uint8_t) pt; + RPC_U8(&msg, 1U) = (uint8_t) pt_parent; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst, + sc_bool_t move_rsrc, sc_bool_t move_pads) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_MOVE_ALL; + RPC_U8(&msg, 0U) = (uint8_t) pt_src; + RPC_U8(&msg, 1U) = (uint8_t) pt_dst; + RPC_U8(&msg, 2U) = (uint8_t) move_rsrc; + RPC_U8(&msg, 3U) = (uint8_t) move_pads; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_rsrc_t resource) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_ASSIGN_RESOURCE; + RPC_U16(&msg, 0U) = (uint16_t) resource; + RPC_U8(&msg, 2U) = (uint8_t) pt; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst, + sc_rsrc_t resource_lst, sc_bool_t movable) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_RESOURCE_MOVABLE; + RPC_U16(&msg, 0U) = (uint16_t) resource_fst; + RPC_U16(&msg, 2U) = (uint16_t) resource_lst; + RPC_U8(&msg, 4U) = (uint8_t) movable; + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource, + sc_bool_t movable) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_SUBSYS_RSRC_MOVABLE; + RPC_U16(&msg, 0U) = (uint16_t) resource; + RPC_U8(&msg, 2U) = (uint8_t) movable; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_spa_t sa, sc_rm_spa_t pa, sc_bool_t smmu_bypass) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_MASTER_ATTRIBUTES; + RPC_U16(&msg, 0U) = (uint16_t) resource; + RPC_U8(&msg, 2U) = (uint8_t) sa; + RPC_U8(&msg, 3U) = (uint8_t) pa; + RPC_U8(&msg, 4U) = (uint8_t) smmu_bypass; + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_sid_t sid) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_MASTER_SID; + RPC_U16(&msg, 0U) = (uint16_t) resource; + RPC_U16(&msg, 2U) = (uint16_t) sid; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_pt_t pt, sc_rm_perm_t perm) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_PERIPHERAL_PERMISSIONS; + RPC_U16(&msg, 0U) = (uint16_t) resource; + RPC_U8(&msg, 2U) = (uint8_t) pt; + RPC_U8(&msg, 3U) = (uint8_t) perm; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_IS_RESOURCE_OWNED; + RPC_U16(&msg, 0U) = (uint16_t) resource; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_bool_t) result; +} + +sc_bool_t sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_IS_RESOURCE_MASTER; + RPC_U16(&msg, 0U) = (uint16_t) resource; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_bool_t) result; +} + +sc_bool_t sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_IS_RESOURCE_PERIPHERAL; + RPC_U16(&msg, 0U) = (uint16_t) resource; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_bool_t) result; +} + +sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_sid_t *sid) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_GET_RESOURCE_INFO; + RPC_U16(&msg, 0U) = (uint16_t) resource; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (sid != NULL) + { + *sid = RPC_U16(&msg, 0U); + } + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_memreg_alloc(sc_ipc_t ipc, sc_rm_mr_t *mr, + sc_faddr_t addr_start, sc_faddr_t addr_end) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_MEMREG_ALLOC; + RPC_U32(&msg, 0U) = (uint32_t) (addr_start >> 32U); + RPC_U32(&msg, 4U) = (uint32_t) addr_start; + RPC_U32(&msg, 8U) = (uint32_t) (addr_end >> 32U); + RPC_U32(&msg, 12U) = (uint32_t) addr_end; + RPC_SIZE(&msg) = 5U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (mr != NULL) + { + *mr = RPC_U8(&msg, 0U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_rm_memreg_split(sc_ipc_t ipc, sc_rm_mr_t mr, + sc_rm_mr_t *mr_ret, sc_faddr_t addr_start, sc_faddr_t addr_end) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_MEMREG_SPLIT; + RPC_U32(&msg, 0U) = (uint32_t) (addr_start >> 32U); + RPC_U32(&msg, 4U) = (uint32_t) addr_start; + RPC_U32(&msg, 8U) = (uint32_t) (addr_end >> 32U); + RPC_U32(&msg, 12U) = (uint32_t) addr_end; + RPC_U8(&msg, 16U) = (uint8_t) mr; + RPC_SIZE(&msg) = 6U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (mr_ret != NULL) + { + *mr_ret = RPC_U8(&msg, 0U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_rm_memreg_free(sc_ipc_t ipc, sc_rm_mr_t mr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_MEMREG_FREE; + RPC_U8(&msg, 0U) = (uint8_t) mr; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, + sc_faddr_t addr_start, sc_faddr_t addr_end) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_FIND_MEMREG; + RPC_U32(&msg, 0U) = (uint32_t) (addr_start >> 32U); + RPC_U32(&msg, 4U) = (uint32_t) addr_start; + RPC_U32(&msg, 8U) = (uint32_t) (addr_end >> 32U); + RPC_U32(&msg, 12U) = (uint32_t) addr_end; + RPC_SIZE(&msg) = 5U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + if (mr != NULL) + { + *mr = RPC_U8(&msg, 0U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_rm_assign_memreg(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_mr_t mr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_ASSIGN_MEMREG; + RPC_U8(&msg, 0U) = (uint8_t) pt; + RPC_U8(&msg, 1U) = (uint8_t) mr; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr, + sc_rm_pt_t pt, sc_rm_perm_t perm) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_MEMREG_PERMISSIONS; + RPC_U8(&msg, 0U) = (uint8_t) mr; + RPC_U8(&msg, 1U) = (uint8_t) pt; + RPC_U8(&msg, 2U) = (uint8_t) perm; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_IS_MEMREG_OWNED; + RPC_U8(&msg, 0U) = (uint8_t) mr; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_bool_t) result; +} + +sc_err_t sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, + sc_faddr_t *addr_start, sc_faddr_t *addr_end) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_GET_MEMREG_INFO; + RPC_U8(&msg, 0U) = (uint8_t) mr; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (addr_start != NULL) + { + *addr_start = ((uint64_t) RPC_U32(&msg, 0U) << 32U) | RPC_U32(&msg, 4U); + } + + if (addr_end != NULL) + { + *addr_end = ((uint64_t) RPC_U32(&msg, 8U) << 32U) | RPC_U32(&msg, 12U); + } + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_ASSIGN_PAD; + RPC_U16(&msg, 0U) = (uint16_t) pad; + RPC_U8(&msg, 2U) = (uint8_t) pt; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst, + sc_pad_t pad_lst, sc_bool_t movable) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_PAD_MOVABLE; + RPC_U16(&msg, 0U) = (uint16_t) pad_fst; + RPC_U16(&msg, 2U) = (uint16_t) pad_lst; + RPC_U8(&msg, 4U) = (uint8_t) movable; + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_IS_PAD_OWNED; + RPC_U8(&msg, 0U) = (uint8_t) pad; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_bool_t) result; +} + +void sc_rm_dump(sc_ipc_t ipc) +{ + sc_rpc_msg_t msg; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_DUMP; + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + return; +} + +/**@}*/ + diff --git a/arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h b/arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h new file mode 100644 index 0000000000..0c498e97f0 --- /dev/null +++ b/arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file for the TIMER RPC implementation. + * + * @addtogroup TIMER_SVC + * @{ + */ + +#ifndef SC_TIMER_RPC_H +#define SC_TIMER_RPC_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Defines for RPC TIMER function calls + */ +/*@{*/ +#define TIMER_FUNC_UNKNOWN 0 /*!< Unknown function */ +#define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /*!< Index for timer_set_wdog_timeout() RPC call */ +#define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /*!< Index for timer_set_wdog_pre_timeout() RPC call */ +#define TIMER_FUNC_START_WDOG 2U /*!< Index for timer_start_wdog() RPC call */ +#define TIMER_FUNC_STOP_WDOG 3U /*!< Index for timer_stop_wdog() RPC call */ +#define TIMER_FUNC_PING_WDOG 4U /*!< Index for timer_ping_wdog() RPC call */ +#define TIMER_FUNC_GET_WDOG_STATUS 5U /*!< Index for timer_get_wdog_status() RPC call */ +#define TIMER_FUNC_PT_GET_WDOG_STATUS 13U /*!< Index for timer_pt_get_wdog_status() RPC call */ +#define TIMER_FUNC_SET_WDOG_ACTION 10U /*!< Index for timer_set_wdog_action() RPC call */ +#define TIMER_FUNC_SET_RTC_TIME 6U /*!< Index for timer_set_rtc_time() RPC call */ +#define TIMER_FUNC_GET_RTC_TIME 7U /*!< Index for timer_get_rtc_time() RPC call */ +#define TIMER_FUNC_GET_RTC_SEC1970 9U /*!< Index for timer_get_rtc_sec1970() RPC call */ +#define TIMER_FUNC_SET_RTC_ALARM 8U /*!< Index for timer_set_rtc_alarm() RPC call */ +#define TIMER_FUNC_SET_RTC_PERIODIC_ALARM 14U /*!< Index for timer_set_rtc_periodic_alarm() RPC call */ +#define TIMER_FUNC_CANCEL_RTC_ALARM 15U /*!< Index for timer_cancel_rtc_alarm() RPC call */ +#define TIMER_FUNC_SET_RTC_CALB 11U /*!< Index for timer_set_rtc_calb() RPC call */ +/*@}*/ + +/* Types */ + +/* Functions */ + +/*! + * This function dispatches an incoming TIMER RPC request. + * + * @param[in] caller_pt caller partition + * @param[in] msg pointer to RPC message + */ +void timer_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg); + +/*! + * This function translates and dispatches an TIMER RPC request. + * + * @param[in] ipc IPC handle + * @param[in] msg pointer to RPC message + */ +void timer_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg); + +#endif /* SC_TIMER_RPC_H */ + +/**@}*/ + diff --git a/arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c b/arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c new file mode 100644 index 0000000000..abdf433b5c --- /dev/null +++ b/arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c @@ -0,0 +1,365 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * File containing client-side RPC functions for the TIMER service. These + * functions are ported to clients that communicate to the SC. + * + * @addtogroup TIMER_SVC + * @{ + */ + +/* Includes */ + +#include <asm/arch/sci/types.h> +#include <asm/arch/sci/svc/rm/api.h> +#include <asm/arch/sci/svc/timer/api.h> +#include <asm/arch/sci/rpc.h> +#include "rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/* Local Functions */ + +sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc, + sc_timer_wdog_time_t timeout) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_WDOG_TIMEOUT; + RPC_U32(&msg, 0U) = (uint32_t) timeout; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_set_wdog_pre_timeout(sc_ipc_t ipc, + sc_timer_wdog_time_t pre_timeout) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_WDOG_PRE_TIMEOUT; + RPC_U32(&msg, 0U) = (uint32_t) pre_timeout; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_start_wdog(sc_ipc_t ipc, sc_bool_t lock) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_START_WDOG; + RPC_U8(&msg, 0U) = (uint8_t) lock; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_stop_wdog(sc_ipc_t ipc) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_STOP_WDOG; + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_ping_wdog(sc_ipc_t ipc) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_PING_WDOG; + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_get_wdog_status(sc_ipc_t ipc, + sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *max_timeout, + sc_timer_wdog_time_t *remaining_time) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_GET_WDOG_STATUS; + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (timeout != NULL) + { + *timeout = RPC_U32(&msg, 0U); + } + + if (max_timeout != NULL) + { + *max_timeout = RPC_U32(&msg, 4U); + } + + if (remaining_time != NULL) + { + *remaining_time = RPC_U32(&msg, 8U); + } + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t *enb, + sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *remaining_time) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_PT_GET_WDOG_STATUS; + RPC_U8(&msg, 0U) = (uint8_t) pt; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (timeout != NULL) + { + *timeout = RPC_U32(&msg, 0U); + } + + if (remaining_time != NULL) + { + *remaining_time = RPC_U32(&msg, 4U); + } + + result = RPC_R8(&msg); + if (enb != NULL) + { + *enb = RPC_U8(&msg, 8U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc, + sc_rm_pt_t pt, sc_timer_wdog_action_t action) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_WDOG_ACTION; + RPC_U8(&msg, 0U) = (uint8_t) pt; + RPC_U8(&msg, 1U) = (uint8_t) action; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_set_rtc_time(sc_ipc_t ipc, uint16_t year, uint8_t mon, + uint8_t day, uint8_t hour, uint8_t min, uint8_t sec) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_RTC_TIME; + RPC_U16(&msg, 0U) = (uint16_t) year; + RPC_U8(&msg, 2U) = (uint8_t) mon; + RPC_U8(&msg, 3U) = (uint8_t) day; + RPC_U8(&msg, 4U) = (uint8_t) hour; + RPC_U8(&msg, 5U) = (uint8_t) min; + RPC_U8(&msg, 6U) = (uint8_t) sec; + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_get_rtc_time(sc_ipc_t ipc, uint16_t *year, uint8_t *mon, + uint8_t *day, uint8_t *hour, uint8_t *min, uint8_t *sec) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_GET_RTC_TIME; + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (year != NULL) + { + *year = RPC_U16(&msg, 0U); + } + + result = RPC_R8(&msg); + if (mon != NULL) + { + *mon = RPC_U8(&msg, 2U); + } + + if (day != NULL) + { + *day = RPC_U8(&msg, 3U); + } + + if (hour != NULL) + { + *hour = RPC_U8(&msg, 4U); + } + + if (min != NULL) + { + *min = RPC_U8(&msg, 5U); + } + + if (sec != NULL) + { + *sec = RPC_U8(&msg, 6U); + } + + return (sc_err_t) result; +} + +sc_err_t sc_timer_get_rtc_sec1970(sc_ipc_t ipc, uint32_t *sec) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_GET_RTC_SEC1970; + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + if (sec != NULL) + { + *sec = RPC_U32(&msg, 0U); + } + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_set_rtc_alarm(sc_ipc_t ipc, uint16_t year, uint8_t mon, + uint8_t day, uint8_t hour, uint8_t min, uint8_t sec) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_RTC_ALARM; + RPC_U16(&msg, 0U) = (uint16_t) year; + RPC_U8(&msg, 2U) = (uint8_t) mon; + RPC_U8(&msg, 3U) = (uint8_t) day; + RPC_U8(&msg, 4U) = (uint8_t) hour; + RPC_U8(&msg, 5U) = (uint8_t) min; + RPC_U8(&msg, 6U) = (uint8_t) sec; + RPC_SIZE(&msg) = 3U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_set_rtc_periodic_alarm(sc_ipc_t ipc, uint32_t sec) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_RTC_PERIODIC_ALARM; + RPC_U32(&msg, 0U) = (uint32_t) sec; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_cancel_rtc_alarm(sc_ipc_t ipc) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_CANCEL_RTC_ALARM; + RPC_SIZE(&msg) = 1U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +sc_err_t sc_timer_set_rtc_calb(sc_ipc_t ipc, int8_t count) +{ + sc_rpc_msg_t msg; + uint8_t result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_RTC_CALB; + RPC_I8(&msg, 0U) = (int8_t) count; + RPC_SIZE(&msg) = 2U; + + sc_call_rpc(ipc, &msg, SC_FALSE); + + result = RPC_R8(&msg); + return (sc_err_t) result; +} + +/**@}*/ + diff --git a/include/dt-bindings/pinctrl/pads-imx8qm.h b/include/dt-bindings/pinctrl/pads-imx8qm.h new file mode 100644 index 0000000000..ba75ecb7a5 --- /dev/null +++ b/include/dt-bindings/pinctrl/pads-imx8qm.h @@ -0,0 +1,975 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file used to configure SoC pad list. + */ + +#ifndef SC_PADS_H +#define SC_PADS_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Pad Definitions + */ +/*@{*/ +#define SC_P_SIM0_CLK 0 /*!< DMA.SIM0.CLK, LSIO.GPIO0.IO00 */ +#define SC_P_SIM0_RST 1 /*!< DMA.SIM0.RST, LSIO.GPIO0.IO01 */ +#define SC_P_SIM0_IO 2 /*!< DMA.SIM0.IO, LSIO.GPIO0.IO02 */ +#define SC_P_SIM0_PD 3 /*!< DMA.SIM0.PD, DMA.I2C3.SCL, LSIO.GPIO0.IO03 */ +#define SC_P_SIM0_POWER_EN 4 /*!< DMA.SIM0.POWER_EN, DMA.I2C3.SDA, LSIO.GPIO0.IO04 */ +#define SC_P_SIM0_GPIO0_00 5 /*!< DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM 6 /*!< */ +#define SC_P_M40_I2C0_SCL 7 /*!< M40.I2C0.SCL, M40.UART0.RX, M40.GPIO0.IO02, LSIO.GPIO0.IO06 */ +#define SC_P_M40_I2C0_SDA 8 /*!< M40.I2C0.SDA, M40.UART0.TX, M40.GPIO0.IO03, LSIO.GPIO0.IO07 */ +#define SC_P_M40_GPIO0_00 9 /*!< M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */ +#define SC_P_M40_GPIO0_01 10 /*!< M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */ +#define SC_P_M41_I2C0_SCL 11 /*!< M41.I2C0.SCL, M41.UART0.RX, M41.GPIO0.IO02, LSIO.GPIO0.IO10 */ +#define SC_P_M41_I2C0_SDA 12 /*!< M41.I2C0.SDA, M41.UART0.TX, M41.GPIO0.IO03, LSIO.GPIO0.IO11 */ +#define SC_P_M41_GPIO0_00 13 /*!< M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */ +#define SC_P_M41_GPIO0_01 14 /*!< M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */ +#define SC_P_GPT0_CLK 15 /*!< LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */ +#define SC_P_GPT0_CAPTURE 16 /*!< LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */ +#define SC_P_GPT0_COMPARE 17 /*!< LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */ +#define SC_P_GPT1_CLK 18 /*!< LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */ +#define SC_P_GPT1_CAPTURE 19 /*!< LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */ +#define SC_P_GPT1_COMPARE 20 /*!< LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */ +#define SC_P_UART0_RX 21 /*!< DMA.UART0.RX, SCU.UART0.RX, LSIO.GPIO0.IO20 */ +#define SC_P_UART0_TX 22 /*!< DMA.UART0.TX, SCU.UART0.TX, LSIO.GPIO0.IO21 */ +#define SC_P_UART0_RTS_B 23 /*!< DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */ +#define SC_P_UART0_CTS_B 24 /*!< DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */ +#define SC_P_UART1_TX 25 /*!< DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */ +#define SC_P_UART1_RX 26 /*!< DMA.UART1.RX, DMA.SPI3.SDO, LSIO.GPIO0.IO25 */ +#define SC_P_UART1_RTS_B 27 /*!< DMA.UART1.RTS_B, DMA.SPI3.SDI, DMA.UART1.CTS_B, LSIO.GPIO0.IO26 */ +#define SC_P_UART1_CTS_B 28 /*!< DMA.UART1.CTS_B, DMA.SPI3.CS0, DMA.UART1.RTS_B, LSIO.GPIO0.IO27 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 29 /*!< */ +#define SC_P_SCU_PMIC_MEMC_ON 30 /*!< SCU.GPIO0.IOXX_PMIC_MEMC_ON */ +#define SC_P_SCU_WDOG_OUT 31 /*!< SCU.WDOG0.WDOG_OUT */ +#define SC_P_PMIC_I2C_SDA 32 /*!< SCU.PMIC_I2C.SDA */ +#define SC_P_PMIC_I2C_SCL 33 /*!< SCU.PMIC_I2C.SCL */ +#define SC_P_PMIC_EARLY_WARNING 34 /*!< SCU.PMIC_EARLY_WARNING */ +#define SC_P_PMIC_INT_B 35 /*!< SCU.DSC.PMIC_INT_B */ +#define SC_P_SCU_GPIO0_00 36 /*!< SCU.GPIO0.IO00, SCU.UART0.RX, LSIO.GPIO0.IO28 */ +#define SC_P_SCU_GPIO0_01 37 /*!< SCU.GPIO0.IO01, SCU.UART0.TX, LSIO.GPIO0.IO29 */ +#define SC_P_SCU_GPIO0_02 38 /*!< SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */ +#define SC_P_SCU_GPIO0_03 39 /*!< SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */ +#define SC_P_SCU_GPIO0_04 40 /*!< SCU.GPIO0.IO04, SCU.GPIO0.IOXX_PMIC_A72_ON, LSIO.GPIO1.IO00 */ +#define SC_P_SCU_GPIO0_05 41 /*!< SCU.GPIO0.IO05, SCU.GPIO0.IOXX_PMIC_A53_ON, LSIO.GPIO1.IO01 */ +#define SC_P_SCU_GPIO0_06 42 /*!< SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */ +#define SC_P_SCU_GPIO0_07 43 /*!< SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, LSIO.GPIO1.IO03 */ +#define SC_P_SCU_BOOT_MODE0 44 /*!< SCU.DSC.BOOT_MODE0 */ +#define SC_P_SCU_BOOT_MODE1 45 /*!< SCU.DSC.BOOT_MODE1 */ +#define SC_P_SCU_BOOT_MODE2 46 /*!< SCU.DSC.BOOT_MODE2 */ +#define SC_P_SCU_BOOT_MODE3 47 /*!< SCU.DSC.BOOT_MODE3 */ +#define SC_P_SCU_BOOT_MODE4 48 /*!< SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */ +#define SC_P_SCU_BOOT_MODE5 49 /*!< SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */ +#define SC_P_LVDS0_GPIO00 50 /*!< LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */ +#define SC_P_LVDS0_GPIO01 51 /*!< LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */ +#define SC_P_LVDS0_I2C0_SCL 52 /*!< LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */ +#define SC_P_LVDS0_I2C0_SDA 53 /*!< LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */ +#define SC_P_LVDS0_I2C1_SCL 54 /*!< LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */ +#define SC_P_LVDS0_I2C1_SDA 55 /*!< LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */ +#define SC_P_LVDS1_GPIO00 56 /*!< LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */ +#define SC_P_LVDS1_GPIO01 57 /*!< LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */ +#define SC_P_LVDS1_I2C0_SCL 58 /*!< LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */ +#define SC_P_LVDS1_I2C0_SDA 59 /*!< LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */ +#define SC_P_LVDS1_I2C1_SCL 60 /*!< LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */ +#define SC_P_LVDS1_I2C1_SDA 61 /*!< LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62 /*!< */ +#define SC_P_MIPI_DSI0_I2C0_SCL 63 /*!< MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */ +#define SC_P_MIPI_DSI0_I2C0_SDA 64 /*!< MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */ +#define SC_P_MIPI_DSI0_GPIO0_00 65 /*!< MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 */ +#define SC_P_MIPI_DSI0_GPIO0_01 66 /*!< MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */ +#define SC_P_MIPI_DSI1_I2C0_SCL 67 /*!< MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */ +#define SC_P_MIPI_DSI1_I2C0_SDA 68 /*!< MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */ +#define SC_P_MIPI_DSI1_GPIO0_00 69 /*!< MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 */ +#define SC_P_MIPI_DSI1_GPIO0_01 70 /*!< MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 71 /*!< */ +#define SC_P_MIPI_CSI0_MCLK_OUT 72 /*!< MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */ +#define SC_P_MIPI_CSI0_I2C0_SCL 73 /*!< MIPI_CSI0.I2C0.SCL, LSIO.GPIO1.IO25 */ +#define SC_P_MIPI_CSI0_I2C0_SDA 74 /*!< MIPI_CSI0.I2C0.SDA, LSIO.GPIO1.IO26 */ +#define SC_P_MIPI_CSI0_GPIO0_00 75 /*!< MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, MIPI_CSI1.I2C0.SCL, LSIO.GPIO1.IO27 */ +#define SC_P_MIPI_CSI0_GPIO0_01 76 /*!< MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, MIPI_CSI1.I2C0.SDA, LSIO.GPIO1.IO28 */ +#define SC_P_MIPI_CSI1_MCLK_OUT 77 /*!< MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */ +#define SC_P_MIPI_CSI1_GPIO0_00 78 /*!< MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */ +#define SC_P_MIPI_CSI1_GPIO0_01 79 /*!< MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */ +#define SC_P_MIPI_CSI1_I2C0_SCL 80 /*!< MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */ +#define SC_P_MIPI_CSI1_I2C0_SDA 81 /*!< MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */ +#define SC_P_HDMI_TX0_TS_SCL 82 /*!< HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */ +#define SC_P_HDMI_TX0_TS_SDA 83 /*!< HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */ +#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 84 /*!< */ +#define SC_P_ESAI1_FSR 85 /*!< AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */ +#define SC_P_ESAI1_FST 86 /*!< AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */ +#define SC_P_ESAI1_SCKR 87 /*!< AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */ +#define SC_P_ESAI1_SCKT 88 /*!< AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 */ +#define SC_P_ESAI1_TX0 89 /*!< AUD.ESAI1.TX0, AUD.SAI2.RXD, AUD.SPDIF0.RX, LSIO.GPIO2.IO08 */ +#define SC_P_ESAI1_TX1 90 /*!< AUD.ESAI1.TX1, AUD.SAI2.RXFS, AUD.SPDIF0.TX, LSIO.GPIO2.IO09 */ +#define SC_P_ESAI1_TX2_RX3 91 /*!< AUD.ESAI1.TX2_RX3, AUD.SPDIF0.RX, LSIO.GPIO2.IO10 */ +#define SC_P_ESAI1_TX3_RX2 92 /*!< AUD.ESAI1.TX3_RX2, AUD.SPDIF0.TX, LSIO.GPIO2.IO11 */ +#define SC_P_ESAI1_TX4_RX1 93 /*!< AUD.ESAI1.TX4_RX1, LSIO.GPIO2.IO12 */ +#define SC_P_ESAI1_TX5_RX0 94 /*!< AUD.ESAI1.TX5_RX0, LSIO.GPIO2.IO13 */ +#define SC_P_SPDIF0_RX 95 /*!< AUD.SPDIF0.RX, AUD.MQS.R, AUD.ACM.MCLK_IN1, LSIO.GPIO2.IO14 */ +#define SC_P_SPDIF0_TX 96 /*!< AUD.SPDIF0.TX, AUD.MQS.L, AUD.ACM.MCLK_OUT1, LSIO.GPIO2.IO15 */ +#define SC_P_SPDIF0_EXT_CLK 97 /*!< AUD.SPDIF0.EXT_CLK, DMA.DMA0.REQ_IN0, LSIO.GPIO2.IO16 */ +#define SC_P_SPI3_SCK 98 /*!< DMA.SPI3.SCK, LSIO.GPIO2.IO17 */ +#define SC_P_SPI3_SDO 99 /*!< DMA.SPI3.SDO, DMA.FTM.CH0, LSIO.GPIO2.IO18 */ +#define SC_P_SPI3_SDI 100 /*!< DMA.SPI3.SDI, DMA.FTM.CH1, LSIO.GPIO2.IO19 */ +#define SC_P_SPI3_CS0 101 /*!< DMA.SPI3.CS0, DMA.FTM.CH2, LSIO.GPIO2.IO20 */ +#define SC_P_SPI3_CS1 102 /*!< DMA.SPI3.CS1, LSIO.GPIO2.IO21 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 103 /*!< */ +#define SC_P_ESAI0_FSR 104 /*!< AUD.ESAI0.FSR, LSIO.GPIO2.IO22 */ +#define SC_P_ESAI0_FST 105 /*!< AUD.ESAI0.FST, LSIO.GPIO2.IO23 */ +#define SC_P_ESAI0_SCKR 106 /*!< AUD.ESAI0.SCKR, LSIO.GPIO2.IO24 */ +#define SC_P_ESAI0_SCKT 107 /*!< AUD.ESAI0.SCKT, LSIO.GPIO2.IO25 */ +#define SC_P_ESAI0_TX0 108 /*!< AUD.ESAI0.TX0, LSIO.GPIO2.IO26 */ +#define SC_P_ESAI0_TX1 109 /*!< AUD.ESAI0.TX1, LSIO.GPIO2.IO27 */ +#define SC_P_ESAI0_TX2_RX3 110 /*!< AUD.ESAI0.TX2_RX3, LSIO.GPIO2.IO28 */ +#define SC_P_ESAI0_TX3_RX2 111 /*!< AUD.ESAI0.TX3_RX2, LSIO.GPIO2.IO29 */ +#define SC_P_ESAI0_TX4_RX1 112 /*!< AUD.ESAI0.TX4_RX1, LSIO.GPIO2.IO30 */ +#define SC_P_ESAI0_TX5_RX0 113 /*!< AUD.ESAI0.TX5_RX0, LSIO.GPIO2.IO31 */ +#define SC_P_MCLK_IN0 114 /*!< AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, AUD.ESAI1.RX_HF_CLK, LSIO.GPIO3.IO00 */ +#define SC_P_MCLK_OUT0 115 /*!< AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, AUD.ESAI1.TX_HF_CLK, LSIO.GPIO3.IO01 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC 116 /*!< */ +#define SC_P_SPI0_SCK 117 /*!< DMA.SPI0.SCK, AUD.SAI0.RXC, LSIO.GPIO3.IO02 */ +#define SC_P_SPI0_SDO 118 /*!< DMA.SPI0.SDO, AUD.SAI0.TXD, LSIO.GPIO3.IO03 */ +#define SC_P_SPI0_SDI 119 /*!< DMA.SPI0.SDI, AUD.SAI0.RXD, LSIO.GPIO3.IO04 */ +#define SC_P_SPI0_CS0 120 /*!< DMA.SPI0.CS0, AUD.SAI0.RXFS, LSIO.GPIO3.IO05 */ +#define SC_P_SPI0_CS1 121 /*!< DMA.SPI0.CS1, AUD.SAI0.TXC, LSIO.GPIO3.IO06 */ +#define SC_P_SPI2_SCK 122 /*!< DMA.SPI2.SCK, LSIO.GPIO3.IO07 */ +#define SC_P_SPI2_SDO 123 /*!< DMA.SPI2.SDO, LSIO.GPIO3.IO08 */ +#define SC_P_SPI2_SDI 124 /*!< DMA.SPI2.SDI, LSIO.GPIO3.IO09 */ +#define SC_P_SPI2_CS0 125 /*!< DMA.SPI2.CS0, LSIO.GPIO3.IO10 */ +#define SC_P_SPI2_CS1 126 /*!< DMA.SPI2.CS1, AUD.SAI0.TXFS, LSIO.GPIO3.IO11 */ +#define SC_P_SAI1_RXC 127 /*!< AUD.SAI1.RXC, AUD.SAI0.TXD, LSIO.GPIO3.IO12 */ +#define SC_P_SAI1_RXD 128 /*!< AUD.SAI1.RXD, AUD.SAI0.TXFS, LSIO.GPIO3.IO13 */ +#define SC_P_SAI1_RXFS 129 /*!< AUD.SAI1.RXFS, AUD.SAI0.RXD, LSIO.GPIO3.IO14 */ +#define SC_P_SAI1_TXC 130 /*!< AUD.SAI1.TXC, AUD.SAI0.TXC, LSIO.GPIO3.IO15 */ +#define SC_P_SAI1_TXD 131 /*!< AUD.SAI1.TXD, AUD.SAI1.RXC, LSIO.GPIO3.IO16 */ +#define SC_P_SAI1_TXFS 132 /*!< AUD.SAI1.TXFS, AUD.SAI1.RXFS, LSIO.GPIO3.IO17 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 133 /*!< */ +#define SC_P_ADC_IN7 134 /*!< DMA.ADC1.IN3, DMA.SPI1.CS1, LSIO.KPP0.ROW3, LSIO.GPIO3.IO25 */ +#define SC_P_ADC_IN6 135 /*!< DMA.ADC1.IN2, DMA.SPI1.CS0, LSIO.KPP0.ROW2, LSIO.GPIO3.IO24 */ +#define SC_P_ADC_IN5 136 /*!< DMA.ADC1.IN1, DMA.SPI1.SDI, LSIO.KPP0.ROW1, LSIO.GPIO3.IO23 */ +#define SC_P_ADC_IN4 137 /*!< DMA.ADC1.IN0, DMA.SPI1.SDO, LSIO.KPP0.ROW0, LSIO.GPIO3.IO22 */ +#define SC_P_ADC_IN3 138 /*!< DMA.ADC0.IN3, DMA.SPI1.SCK, LSIO.KPP0.COL3, LSIO.GPIO3.IO21 */ +#define SC_P_ADC_IN2 139 /*!< DMA.ADC0.IN2, LSIO.KPP0.COL2, LSIO.GPIO3.IO20 */ +#define SC_P_ADC_IN1 140 /*!< DMA.ADC0.IN1, LSIO.KPP0.COL1, LSIO.GPIO3.IO19 */ +#define SC_P_ADC_IN0 141 /*!< DMA.ADC0.IN0, LSIO.KPP0.COL0, LSIO.GPIO3.IO18 */ +#define SC_P_MLB_SIG 142 /*!< CONN.MLB.SIG, AUD.SAI3.RXC, LSIO.GPIO3.IO26 */ +#define SC_P_MLB_CLK 143 /*!< CONN.MLB.CLK, AUD.SAI3.RXFS, LSIO.GPIO3.IO27 */ +#define SC_P_MLB_DATA 144 /*!< CONN.MLB.DATA, AUD.SAI3.RXD, LSIO.GPIO3.IO28 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 145 /*!< */ +#define SC_P_FLEXCAN0_RX 146 /*!< DMA.FLEXCAN0.RX, LSIO.GPIO3.IO29 */ +#define SC_P_FLEXCAN0_TX 147 /*!< DMA.FLEXCAN0.TX, LSIO.GPIO3.IO30 */ +#define SC_P_FLEXCAN1_RX 148 /*!< DMA.FLEXCAN1.RX, LSIO.GPIO3.IO31 */ +#define SC_P_FLEXCAN1_TX 149 /*!< DMA.FLEXCAN1.TX, LSIO.GPIO4.IO00 */ +#define SC_P_FLEXCAN2_RX 150 /*!< DMA.FLEXCAN2.RX, LSIO.GPIO4.IO01 */ +#define SC_P_FLEXCAN2_TX 151 /*!< DMA.FLEXCAN2.TX, LSIO.GPIO4.IO02 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 152 /*!< */ +#define SC_P_USB_SS3_TC0 153 /*!< DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO4.IO03 */ +#define SC_P_USB_SS3_TC1 154 /*!< DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */ +#define SC_P_USB_SS3_TC2 155 /*!< DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO05 */ +#define SC_P_USB_SS3_TC3 156 /*!< DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */ +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 157 /*!< */ +#define SC_P_USDHC1_RESET_B 158 /*!< CONN.USDHC1.RESET_B, LSIO.GPIO4.IO07 */ +#define SC_P_USDHC1_VSELECT 159 /*!< CONN.USDHC1.VSELECT, LSIO.GPIO4.IO08 */ +#define SC_P_USDHC2_RESET_B 160 /*!< CONN.USDHC2.RESET_B, LSIO.GPIO4.IO09 */ +#define SC_P_USDHC2_VSELECT 161 /*!< CONN.USDHC2.VSELECT, LSIO.GPIO4.IO10 */ +#define SC_P_USDHC2_WP 162 /*!< CONN.USDHC2.WP, LSIO.GPIO4.IO11 */ +#define SC_P_USDHC2_CD_B 163 /*!< CONN.USDHC2.CD_B, LSIO.GPIO4.IO12 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 164 /*!< */ +#define SC_P_ENET0_MDIO 165 /*!< CONN.ENET0.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO13 */ +#define SC_P_ENET0_MDC 166 /*!< CONN.ENET0.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO14 */ +#define SC_P_ENET0_REFCLK_125M_25M 167 /*!< CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, LSIO.GPIO4.IO15 */ +#define SC_P_ENET1_REFCLK_125M_25M 168 /*!< CONN.ENET1.REFCLK_125M_25M, CONN.ENET1.PPS, LSIO.GPIO4.IO16 */ +#define SC_P_ENET1_MDIO 169 /*!< CONN.ENET1.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO17 */ +#define SC_P_ENET1_MDC 170 /*!< CONN.ENET1.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO18 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 171 /*!< */ +#define SC_P_QSPI1A_SS0_B 172 /*!< LSIO.QSPI1A.SS0_B, LSIO.GPIO4.IO19 */ +#define SC_P_QSPI1A_SS1_B 173 /*!< LSIO.QSPI1A.SS1_B, LSIO.QSPI1A.SCLK2, LSIO.GPIO4.IO20 */ +#define SC_P_QSPI1A_SCLK 174 /*!< LSIO.QSPI1A.SCLK, LSIO.GPIO4.IO21 */ +#define SC_P_QSPI1A_DQS 175 /*!< LSIO.QSPI1A.DQS, LSIO.GPIO4.IO22 */ +#define SC_P_QSPI1A_DATA3 176 /*!< LSIO.QSPI1A.DATA3, DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO23 */ +#define SC_P_QSPI1A_DATA2 177 /*!< LSIO.QSPI1A.DATA2, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO24 */ +#define SC_P_QSPI1A_DATA1 178 /*!< LSIO.QSPI1A.DATA1, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO25 */ +#define SC_P_QSPI1A_DATA0 179 /*!< LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1 180 /*!< */ +#define SC_P_QSPI0A_DATA0 181 /*!< LSIO.QSPI0A.DATA0 */ +#define SC_P_QSPI0A_DATA1 182 /*!< LSIO.QSPI0A.DATA1 */ +#define SC_P_QSPI0A_DATA2 183 /*!< LSIO.QSPI0A.DATA2 */ +#define SC_P_QSPI0A_DATA3 184 /*!< LSIO.QSPI0A.DATA3 */ +#define SC_P_QSPI0A_DQS 185 /*!< LSIO.QSPI0A.DQS */ +#define SC_P_QSPI0A_SS0_B 186 /*!< LSIO.QSPI0A.SS0_B */ +#define SC_P_QSPI0A_SS1_B 187 /*!< LSIO.QSPI0A.SS1_B, LSIO.QSPI0A.SCLK2 */ +#define SC_P_QSPI0A_SCLK 188 /*!< LSIO.QSPI0A.SCLK */ +#define SC_P_QSPI0B_SCLK 189 /*!< LSIO.QSPI0B.SCLK */ +#define SC_P_QSPI0B_DATA0 190 /*!< LSIO.QSPI0B.DATA0 */ +#define SC_P_QSPI0B_DATA1 191 /*!< LSIO.QSPI0B.DATA1 */ +#define SC_P_QSPI0B_DATA2 192 /*!< LSIO.QSPI0B.DATA2 */ +#define SC_P_QSPI0B_DATA3 193 /*!< LSIO.QSPI0B.DATA3 */ +#define SC_P_QSPI0B_DQS 194 /*!< LSIO.QSPI0B.DQS */ +#define SC_P_QSPI0B_SS0_B 195 /*!< LSIO.QSPI0B.SS0_B */ +#define SC_P_QSPI0B_SS1_B 196 /*!< LSIO.QSPI0B.SS1_B, LSIO.QSPI0B.SCLK2 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 197 /*!< */ +#define SC_P_PCIE_CTRL0_CLKREQ_B 198 /*!< HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO27 */ +#define SC_P_PCIE_CTRL0_WAKE_B 199 /*!< HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO28 */ +#define SC_P_PCIE_CTRL0_PERST_B 200 /*!< HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO29 */ +#define SC_P_PCIE_CTRL1_CLKREQ_B 201 /*!< HSIO.PCIE1.CLKREQ_B, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO30 */ +#define SC_P_PCIE_CTRL1_WAKE_B 202 /*!< HSIO.PCIE1.WAKE_B, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO31 */ +#define SC_P_PCIE_CTRL1_PERST_B 203 /*!< HSIO.PCIE1.PERST_B, DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO5.IO00 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 204 /*!< */ +#define SC_P_USB_HSIC0_DATA 205 /*!< CONN.USB_HSIC0.DATA, DMA.I2C1.SDA, LSIO.GPIO5.IO01 */ +#define SC_P_USB_HSIC0_STROBE 206 /*!< CONN.USB_HSIC0.STROBE, DMA.I2C1.SCL, LSIO.GPIO5.IO02 */ +#define SC_P_CALIBRATION_0_HSIC 207 /*!< */ +#define SC_P_CALIBRATION_1_HSIC 208 /*!< */ +#define SC_P_EMMC0_CLK 209 /*!< CONN.EMMC0.CLK, CONN.NAND.READY_B */ +#define SC_P_EMMC0_CMD 210 /*!< CONN.EMMC0.CMD, CONN.NAND.DQS, AUD.MQS.R, LSIO.GPIO5.IO03 */ +#define SC_P_EMMC0_DATA0 211 /*!< CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO5.IO04 */ +#define SC_P_EMMC0_DATA1 212 /*!< CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO5.IO05 */ +#define SC_P_EMMC0_DATA2 213 /*!< CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO5.IO06 */ +#define SC_P_EMMC0_DATA3 214 /*!< CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO5.IO07 */ +#define SC_P_EMMC0_DATA4 215 /*!< CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO5.IO08 */ +#define SC_P_EMMC0_DATA5 216 /*!< CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO5.IO09 */ +#define SC_P_EMMC0_DATA6 217 /*!< CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO5.IO10 */ +#define SC_P_EMMC0_DATA7 218 /*!< CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO5.IO11 */ +#define SC_P_EMMC0_STROBE 219 /*!< CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO5.IO12 */ +#define SC_P_EMMC0_RESET_B 220 /*!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, CONN.USDHC1.VSELECT, LSIO.GPIO5.IO13 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 221 /*!< */ +#define SC_P_USDHC1_CLK 222 /*!< CONN.USDHC1.CLK, AUD.MQS.R */ +#define SC_P_USDHC1_CMD 223 /*!< CONN.USDHC1.CMD, AUD.MQS.L, LSIO.GPIO5.IO14 */ +#define SC_P_USDHC1_DATA0 224 /*!< CONN.USDHC1.DATA0, CONN.NAND.RE_N, LSIO.GPIO5.IO15 */ +#define SC_P_USDHC1_DATA1 225 /*!< CONN.USDHC1.DATA1, CONN.NAND.RE_P, LSIO.GPIO5.IO16 */ +#define SC_P_CTL_NAND_RE_P_N 226 /*!< */ +#define SC_P_USDHC1_DATA2 227 /*!< CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */ +#define SC_P_USDHC1_DATA3 228 /*!< CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */ +#define SC_P_CTL_NAND_DQS_P_N 229 /*!< */ +#define SC_P_USDHC1_DATA4 230 /*!< CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 */ +#define SC_P_USDHC1_DATA5 231 /*!< CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */ +#define SC_P_USDHC1_DATA6 232 /*!< CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 */ +#define SC_P_USDHC1_DATA7 233 /*!< CONN.USDHC1.DATA7, CONN.NAND.ALE, CONN.USDHC1.CD_B, LSIO.GPIO5.IO22 */ +#define SC_P_USDHC1_STROBE 234 /*!< CONN.USDHC1.STROBE, CONN.NAND.CE1_B, CONN.USDHC1.RESET_B, LSIO.GPIO5.IO23 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2 235 /*!< */ +#define SC_P_USDHC2_CLK 236 /*!< CONN.USDHC2.CLK, AUD.MQS.R, LSIO.GPIO5.IO24 */ +#define SC_P_USDHC2_CMD 237 /*!< CONN.USDHC2.CMD, AUD.MQS.L, LSIO.GPIO5.IO25 */ +#define SC_P_USDHC2_DATA0 238 /*!< CONN.USDHC2.DATA0, DMA.UART4.RX, LSIO.GPIO5.IO26 */ +#define SC_P_USDHC2_DATA1 239 /*!< CONN.USDHC2.DATA1, DMA.UART4.TX, LSIO.GPIO5.IO27 */ +#define SC_P_USDHC2_DATA2 240 /*!< CONN.USDHC2.DATA2, DMA.UART4.CTS_B, LSIO.GPIO5.IO28 */ +#define SC_P_USDHC2_DATA3 241 /*!< CONN.USDHC2.DATA3, DMA.UART4.RTS_B, LSIO.GPIO5.IO29 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 242 /*!< */ +#define SC_P_ENET0_RGMII_TXC 243 /*!< CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, LSIO.GPIO5.IO30 */ +#define SC_P_ENET0_RGMII_TX_CTL 244 /*!< CONN.ENET0.RGMII_TX_CTL, LSIO.GPIO5.IO31 */ +#define SC_P_ENET0_RGMII_TXD0 245 /*!< CONN.ENET0.RGMII_TXD0, LSIO.GPIO6.IO00 */ +#define SC_P_ENET0_RGMII_TXD1 246 /*!< CONN.ENET0.RGMII_TXD1, LSIO.GPIO6.IO01 */ +#define SC_P_ENET0_RGMII_TXD2 247 /*!< CONN.ENET0.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO02 */ +#define SC_P_ENET0_RGMII_TXD3 248 /*!< CONN.ENET0.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO03 */ +#define SC_P_ENET0_RGMII_RXC 249 /*!< CONN.ENET0.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO04 */ +#define SC_P_ENET0_RGMII_RX_CTL 250 /*!< CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 */ +#define SC_P_ENET0_RGMII_RXD0 251 /*!< CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */ +#define SC_P_ENET0_RGMII_RXD1 252 /*!< CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */ +#define SC_P_ENET0_RGMII_RXD2 253 /*!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO08 */ +#define SC_P_ENET0_RGMII_RXD3 254 /*!< CONN.ENET0.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO09 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 255 /*!< */ +#define SC_P_ENET1_RGMII_TXC 256 /*!< CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_OUT, CONN.ENET1.RCLK50M_IN, LSIO.GPIO6.IO10 */ +#define SC_P_ENET1_RGMII_TX_CTL 257 /*!< CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO6.IO11 */ +#define SC_P_ENET1_RGMII_TXD0 258 /*!< CONN.ENET1.RGMII_TXD0, LSIO.GPIO6.IO12 */ +#define SC_P_ENET1_RGMII_TXD1 259 /*!< CONN.ENET1.RGMII_TXD1, LSIO.GPIO6.IO13 */ +#define SC_P_ENET1_RGMII_TXD2 260 /*!< CONN.ENET1.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO14 */ +#define SC_P_ENET1_RGMII_TXD3 261 /*!< CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO15 */ +#define SC_P_ENET1_RGMII_RXC 262 /*!< CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO16 */ +#define SC_P_ENET1_RGMII_RX_CTL 263 /*!< CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 */ +#define SC_P_ENET1_RGMII_RXD0 264 /*!< CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */ +#define SC_P_ENET1_RGMII_RXD1 265 /*!< CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */ +#define SC_P_ENET1_RGMII_RXD2 266 /*!< CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */ +#define SC_P_ENET1_RGMII_RXD3 267 /*!< CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 268 /*!< */ +/*@}*/ + +/*! + * @name Pad Mux Definitions + * format: name padid padmux + */ +/*@{*/ +#define SC_P_SIM0_CLK_DMA_SIM0_CLK SC_P_SIM0_CLK 0 +#define SC_P_SIM0_CLK_LSIO_GPIO0_IO00 SC_P_SIM0_CLK 3 +#define SC_P_SIM0_RST_DMA_SIM0_RST SC_P_SIM0_RST 0 +#define SC_P_SIM0_RST_LSIO_GPIO0_IO01 SC_P_SIM0_RST 3 +#define SC_P_SIM0_IO_DMA_SIM0_IO SC_P_SIM0_IO 0 +#define SC_P_SIM0_IO_LSIO_GPIO0_IO02 SC_P_SIM0_IO 3 +#define SC_P_SIM0_PD_DMA_SIM0_PD SC_P_SIM0_PD 0 +#define SC_P_SIM0_PD_DMA_I2C3_SCL SC_P_SIM0_PD 1 +#define SC_P_SIM0_PD_LSIO_GPIO0_IO03 SC_P_SIM0_PD 3 +#define SC_P_SIM0_POWER_EN_DMA_SIM0_POWER_EN SC_P_SIM0_POWER_EN 0 +#define SC_P_SIM0_POWER_EN_DMA_I2C3_SDA SC_P_SIM0_POWER_EN 1 +#define SC_P_SIM0_POWER_EN_LSIO_GPIO0_IO04 SC_P_SIM0_POWER_EN 3 +#define SC_P_SIM0_GPIO0_00_DMA_SIM0_POWER_EN SC_P_SIM0_GPIO0_00 0 +#define SC_P_SIM0_GPIO0_00_LSIO_GPIO0_IO05 SC_P_SIM0_GPIO0_00 3 +#define SC_P_M40_I2C0_SCL_M40_I2C0_SCL SC_P_M40_I2C0_SCL 0 +#define SC_P_M40_I2C0_SCL_M40_UART0_RX SC_P_M40_I2C0_SCL 1 +#define SC_P_M40_I2C0_SCL_M40_GPIO0_IO02 SC_P_M40_I2C0_SCL 2 +#define SC_P_M40_I2C0_SCL_LSIO_GPIO0_IO06 SC_P_M40_I2C0_SCL 3 +#define SC_P_M40_I2C0_SDA_M40_I2C0_SDA SC_P_M40_I2C0_SDA 0 +#define SC_P_M40_I2C0_SDA_M40_UART0_TX SC_P_M40_I2C0_SDA 1 +#define SC_P_M40_I2C0_SDA_M40_GPIO0_IO03 SC_P_M40_I2C0_SDA 2 +#define SC_P_M40_I2C0_SDA_LSIO_GPIO0_IO07 SC_P_M40_I2C0_SDA 3 +#define SC_P_M40_GPIO0_00_M40_GPIO0_IO00 SC_P_M40_GPIO0_00 0 +#define SC_P_M40_GPIO0_00_M40_TPM0_CH0 SC_P_M40_GPIO0_00 1 +#define SC_P_M40_GPIO0_00_DMA_UART4_RX SC_P_M40_GPIO0_00 2 +#define SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08 SC_P_M40_GPIO0_00 3 +#define SC_P_M40_GPIO0_01_M40_GPIO0_IO01 SC_P_M40_GPIO0_01 0 +#define SC_P_M40_GPIO0_01_M40_TPM0_CH1 SC_P_M40_GPIO0_01 1 +#define SC_P_M40_GPIO0_01_DMA_UART4_TX SC_P_M40_GPIO0_01 2 +#define SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09 SC_P_M40_GPIO0_01 3 +#define SC_P_M41_I2C0_SCL_M41_I2C0_SCL SC_P_M41_I2C0_SCL 0 +#define SC_P_M41_I2C0_SCL_M41_UART0_RX SC_P_M41_I2C0_SCL 1 +#define SC_P_M41_I2C0_SCL_M41_GPIO0_IO02 SC_P_M41_I2C0_SCL 2 +#define SC_P_M41_I2C0_SCL_LSIO_GPIO0_IO10 SC_P_M41_I2C0_SCL 3 +#define SC_P_M41_I2C0_SDA_M41_I2C0_SDA SC_P_M41_I2C0_SDA 0 +#define SC_P_M41_I2C0_SDA_M41_UART0_TX SC_P_M41_I2C0_SDA 1 +#define SC_P_M41_I2C0_SDA_M41_GPIO0_IO03 SC_P_M41_I2C0_SDA 2 +#define SC_P_M41_I2C0_SDA_LSIO_GPIO0_IO11 SC_P_M41_I2C0_SDA 3 +#define SC_P_M41_GPIO0_00_M41_GPIO0_IO00 SC_P_M41_GPIO0_00 0 +#define SC_P_M41_GPIO0_00_M41_TPM0_CH0 SC_P_M41_GPIO0_00 1 +#define SC_P_M41_GPIO0_00_DMA_UART3_RX SC_P_M41_GPIO0_00 2 +#define SC_P_M41_GPIO0_00_LSIO_GPIO0_IO12 SC_P_M41_GPIO0_00 3 +#define SC_P_M41_GPIO0_01_M41_GPIO0_IO01 SC_P_M41_GPIO0_01 0 +#define SC_P_M41_GPIO0_01_M41_TPM0_CH1 SC_P_M41_GPIO0_01 1 +#define SC_P_M41_GPIO0_01_DMA_UART3_TX SC_P_M41_GPIO0_01 2 +#define SC_P_M41_GPIO0_01_LSIO_GPIO0_IO13 SC_P_M41_GPIO0_01 3 +#define SC_P_GPT0_CLK_LSIO_GPT0_CLK SC_P_GPT0_CLK 0 +#define SC_P_GPT0_CLK_DMA_I2C1_SCL SC_P_GPT0_CLK 1 +#define SC_P_GPT0_CLK_LSIO_KPP0_COL4 SC_P_GPT0_CLK 2 +#define SC_P_GPT0_CLK_LSIO_GPIO0_IO14 SC_P_GPT0_CLK 3 +#define SC_P_GPT0_CAPTURE_LSIO_GPT0_CAPTURE SC_P_GPT0_CAPTURE 0 +#define SC_P_GPT0_CAPTURE_DMA_I2C1_SDA SC_P_GPT0_CAPTURE 1 +#define SC_P_GPT0_CAPTURE_LSIO_KPP0_COL5 SC_P_GPT0_CAPTURE 2 +#define SC_P_GPT0_CAPTURE_LSIO_GPIO0_IO15 SC_P_GPT0_CAPTURE 3 +#define SC_P_GPT0_COMPARE_LSIO_GPT0_COMPARE SC_P_GPT0_COMPARE 0 +#define SC_P_GPT0_COMPARE_LSIO_PWM3_OUT SC_P_GPT0_COMPARE 1 +#define SC_P_GPT0_COMPARE_LSIO_KPP0_COL6 SC_P_GPT0_COMPARE 2 +#define SC_P_GPT0_COMPARE_LSIO_GPIO0_IO16 SC_P_GPT0_COMPARE 3 +#define SC_P_GPT1_CLK_LSIO_GPT1_CLK SC_P_GPT1_CLK 0 +#define SC_P_GPT1_CLK_DMA_I2C2_SCL SC_P_GPT1_CLK 1 +#define SC_P_GPT1_CLK_LSIO_KPP0_COL7 SC_P_GPT1_CLK 2 +#define SC_P_GPT1_CLK_LSIO_GPIO0_IO17 SC_P_GPT1_CLK 3 +#define SC_P_GPT1_CAPTURE_LSIO_GPT1_CAPTURE SC_P_GPT1_CAPTURE 0 +#define SC_P_GPT1_CAPTURE_DMA_I2C2_SDA SC_P_GPT1_CAPTURE 1 +#define SC_P_GPT1_CAPTURE_LSIO_KPP0_ROW4 SC_P_GPT1_CAPTURE 2 +#define SC_P_GPT1_CAPTURE_LSIO_GPIO0_IO18 SC_P_GPT1_CAPTURE 3 +#define SC_P_GPT1_COMPARE_LSIO_GPT1_COMPARE SC_P_GPT1_COMPARE 0 +#define SC_P_GPT1_COMPARE_LSIO_PWM2_OUT SC_P_GPT1_COMPARE 1 +#define SC_P_GPT1_COMPARE_LSIO_KPP0_ROW5 SC_P_GPT1_COMPARE 2 +#define SC_P_GPT1_COMPARE_LSIO_GPIO0_IO19 SC_P_GPT1_COMPARE 3 +#define SC_P_UART0_RX_DMA_UART0_RX SC_P_UART0_RX 0 +#define SC_P_UART0_RX_SCU_UART0_RX SC_P_UART0_RX 1 +#define SC_P_UART0_RX_LSIO_GPIO0_IO20 SC_P_UART0_RX 3 +#define SC_P_UART0_TX_DMA_UART0_TX SC_P_UART0_TX 0 +#define SC_P_UART0_TX_SCU_UART0_TX SC_P_UART0_TX 1 +#define SC_P_UART0_TX_LSIO_GPIO0_IO21 SC_P_UART0_TX 3 +#define SC_P_UART0_RTS_B_DMA_UART0_RTS_B SC_P_UART0_RTS_B 0 +#define SC_P_UART0_RTS_B_LSIO_PWM0_OUT SC_P_UART0_RTS_B 1 +#define SC_P_UART0_RTS_B_DMA_UART2_RX SC_P_UART0_RTS_B 2 +#define SC_P_UART0_RTS_B_LSIO_GPIO0_IO22 SC_P_UART0_RTS_B 3 +#define SC_P_UART0_CTS_B_DMA_UART0_CTS_B SC_P_UART0_CTS_B 0 +#define SC_P_UART0_CTS_B_LSIO_PWM1_OUT SC_P_UART0_CTS_B 1 +#define SC_P_UART0_CTS_B_DMA_UART2_TX SC_P_UART0_CTS_B 2 +#define SC_P_UART0_CTS_B_LSIO_GPIO0_IO23 SC_P_UART0_CTS_B 3 +#define SC_P_UART1_TX_DMA_UART1_TX SC_P_UART1_TX 0 +#define SC_P_UART1_TX_DMA_SPI3_SCK SC_P_UART1_TX 1 +#define SC_P_UART1_TX_LSIO_GPIO0_IO24 SC_P_UART1_TX 3 +#define SC_P_UART1_RX_DMA_UART1_RX SC_P_UART1_RX 0 +#define SC_P_UART1_RX_DMA_SPI3_SDO SC_P_UART1_RX 1 +#define SC_P_UART1_RX_LSIO_GPIO0_IO25 SC_P_UART1_RX 3 +#define SC_P_UART1_RTS_B_DMA_UART1_RTS_B SC_P_UART1_RTS_B 0 +#define SC_P_UART1_RTS_B_DMA_SPI3_SDI SC_P_UART1_RTS_B 1 +#define SC_P_UART1_RTS_B_DMA_UART1_CTS_B SC_P_UART1_RTS_B 2 +#define SC_P_UART1_RTS_B_LSIO_GPIO0_IO26 SC_P_UART1_RTS_B 3 +#define SC_P_UART1_CTS_B_DMA_UART1_CTS_B SC_P_UART1_CTS_B 0 +#define SC_P_UART1_CTS_B_DMA_SPI3_CS0 SC_P_UART1_CTS_B 1 +#define SC_P_UART1_CTS_B_DMA_UART1_RTS_B SC_P_UART1_CTS_B 2 +#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO27 SC_P_UART1_CTS_B 3 +#define SC_P_SCU_PMIC_MEMC_ON_SCU_GPIO0_IOXX_PMIC_MEMC_ON SC_P_SCU_PMIC_MEMC_ON 0 +#define SC_P_SCU_WDOG_OUT_SCU_WDOG0_WDOG_OUT SC_P_SCU_WDOG_OUT 0 +#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA SC_P_PMIC_I2C_SDA 0 +#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL SC_P_PMIC_I2C_SCL 0 +#define SC_P_PMIC_EARLY_WARNING_SCU_PMIC_EARLY_WARNING SC_P_PMIC_EARLY_WARNING 0 +#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B SC_P_PMIC_INT_B 0 +#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00 SC_P_SCU_GPIO0_00 0 +#define SC_P_SCU_GPIO0_00_SCU_UART0_RX SC_P_SCU_GPIO0_00 1 +#define SC_P_SCU_GPIO0_00_LSIO_GPIO0_IO28 SC_P_SCU_GPIO0_00 3 +#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01 SC_P_SCU_GPIO0_01 0 +#define SC_P_SCU_GPIO0_01_SCU_UART0_TX SC_P_SCU_GPIO0_01 1 +#define SC_P_SCU_GPIO0_01_LSIO_GPIO0_IO29 SC_P_SCU_GPIO0_01 3 +#define SC_P_SCU_GPIO0_02_SCU_GPIO0_IO02 SC_P_SCU_GPIO0_02 0 +#define SC_P_SCU_GPIO0_02_SCU_GPIO0_IOXX_PMIC_GPU0_ON SC_P_SCU_GPIO0_02 1 +#define SC_P_SCU_GPIO0_02_LSIO_GPIO0_IO30 SC_P_SCU_GPIO0_02 3 +#define SC_P_SCU_GPIO0_03_SCU_GPIO0_IO03 SC_P_SCU_GPIO0_03 0 +#define SC_P_SCU_GPIO0_03_SCU_GPIO0_IOXX_PMIC_GPU1_ON SC_P_SCU_GPIO0_03 1 +#define SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31 SC_P_SCU_GPIO0_03 3 +#define SC_P_SCU_GPIO0_04_SCU_GPIO0_IO04 SC_P_SCU_GPIO0_04 0 +#define SC_P_SCU_GPIO0_04_SCU_GPIO0_IOXX_PMIC_A72_ON SC_P_SCU_GPIO0_04 1 +#define SC_P_SCU_GPIO0_04_LSIO_GPIO1_IO00 SC_P_SCU_GPIO0_04 3 +#define SC_P_SCU_GPIO0_05_SCU_GPIO0_IO05 SC_P_SCU_GPIO0_05 0 +#define SC_P_SCU_GPIO0_05_SCU_GPIO0_IOXX_PMIC_A53_ON SC_P_SCU_GPIO0_05 1 +#define SC_P_SCU_GPIO0_05_LSIO_GPIO1_IO01 SC_P_SCU_GPIO0_05 3 +#define SC_P_SCU_GPIO0_06_SCU_GPIO0_IO06 SC_P_SCU_GPIO0_06 0 +#define SC_P_SCU_GPIO0_06_SCU_TPM0_CH0 SC_P_SCU_GPIO0_06 1 +#define SC_P_SCU_GPIO0_06_LSIO_GPIO1_IO02 SC_P_SCU_GPIO0_06 3 +#define SC_P_SCU_GPIO0_07_SCU_GPIO0_IO07 SC_P_SCU_GPIO0_07 0 +#define SC_P_SCU_GPIO0_07_SCU_TPM0_CH1 SC_P_SCU_GPIO0_07 1 +#define SC_P_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K SC_P_SCU_GPIO0_07 2 +#define SC_P_SCU_GPIO0_07_LSIO_GPIO1_IO03 SC_P_SCU_GPIO0_07 3 +#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 SC_P_SCU_BOOT_MODE0 0 +#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 SC_P_SCU_BOOT_MODE1 0 +#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 SC_P_SCU_BOOT_MODE2 0 +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 SC_P_SCU_BOOT_MODE3 0 +#define SC_P_SCU_BOOT_MODE4_SCU_DSC_BOOT_MODE4 SC_P_SCU_BOOT_MODE4 0 +#define SC_P_SCU_BOOT_MODE4_SCU_PMIC_I2C_SCL SC_P_SCU_BOOT_MODE4 1 +#define SC_P_SCU_BOOT_MODE5_SCU_DSC_BOOT_MODE5 SC_P_SCU_BOOT_MODE5 0 +#define SC_P_SCU_BOOT_MODE5_SCU_PMIC_I2C_SDA SC_P_SCU_BOOT_MODE5 1 +#define SC_P_LVDS0_GPIO00_LVDS0_GPIO0_IO00 SC_P_LVDS0_GPIO00 0 +#define SC_P_LVDS0_GPIO00_LVDS0_PWM0_OUT SC_P_LVDS0_GPIO00 1 +#define SC_P_LVDS0_GPIO00_LSIO_GPIO1_IO04 SC_P_LVDS0_GPIO00 3 +#define SC_P_LVDS0_GPIO01_LVDS0_GPIO0_IO01 SC_P_LVDS0_GPIO01 0 +#define SC_P_LVDS0_GPIO01_LSIO_GPIO1_IO05 SC_P_LVDS0_GPIO01 3 +#define SC_P_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL SC_P_LVDS0_I2C0_SCL 0 +#define SC_P_LVDS0_I2C0_SCL_LVDS0_GPIO0_IO02 SC_P_LVDS0_I2C0_SCL 1 +#define SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 SC_P_LVDS0_I2C0_SCL 3 +#define SC_P_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA SC_P_LVDS0_I2C0_SDA 0 +#define SC_P_LVDS0_I2C0_SDA_LVDS0_GPIO0_IO03 SC_P_LVDS0_I2C0_SDA 1 +#define SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 SC_P_LVDS0_I2C0_SDA 3 +#define SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL SC_P_LVDS0_I2C1_SCL 0 +#define SC_P_LVDS0_I2C1_SCL_DMA_UART2_TX SC_P_LVDS0_I2C1_SCL 1 +#define SC_P_LVDS0_I2C1_SCL_LSIO_GPIO1_IO08 SC_P_LVDS0_I2C1_SCL 3 +#define SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA SC_P_LVDS0_I2C1_SDA 0 +#define SC_P_LVDS0_I2C1_SDA_DMA_UART2_RX SC_P_LVDS0_I2C1_SDA 1 +#define SC_P_LVDS0_I2C1_SDA_LSIO_GPIO1_IO09 SC_P_LVDS0_I2C1_SDA 3 +#define SC_P_LVDS1_GPIO00_LVDS1_GPIO0_IO00 SC_P_LVDS1_GPIO00 0 +#define SC_P_LVDS1_GPIO00_LVDS1_PWM0_OUT SC_P_LVDS1_GPIO00 1 +#define SC_P_LVDS1_GPIO00_LSIO_GPIO1_IO10 SC_P_LVDS1_GPIO00 3 +#define SC_P_LVDS1_GPIO01_LVDS1_GPIO0_IO01 SC_P_LVDS1_GPIO01 0 +#define SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11 SC_P_LVDS1_GPIO01 3 +#define SC_P_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL SC_P_LVDS1_I2C0_SCL 0 +#define SC_P_LVDS1_I2C0_SCL_LVDS1_GPIO0_IO02 SC_P_LVDS1_I2C0_SCL 1 +#define SC_P_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 SC_P_LVDS1_I2C0_SCL 3 +#define SC_P_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA SC_P_LVDS1_I2C0_SDA 0 +#define SC_P_LVDS1_I2C0_SDA_LVDS1_GPIO0_IO03 SC_P_LVDS1_I2C0_SDA 1 +#define SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 SC_P_LVDS1_I2C0_SDA 3 +#define SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL SC_P_LVDS1_I2C1_SCL 0 +#define SC_P_LVDS1_I2C1_SCL_DMA_UART3_TX SC_P_LVDS1_I2C1_SCL 1 +#define SC_P_LVDS1_I2C1_SCL_LSIO_GPIO1_IO14 SC_P_LVDS1_I2C1_SCL 3 +#define SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA SC_P_LVDS1_I2C1_SDA 0 +#define SC_P_LVDS1_I2C1_SDA_DMA_UART3_RX SC_P_LVDS1_I2C1_SDA 1 +#define SC_P_LVDS1_I2C1_SDA_LSIO_GPIO1_IO15 SC_P_LVDS1_I2C1_SDA 3 +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL SC_P_MIPI_DSI0_I2C0_SCL 0 +#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO16 SC_P_MIPI_DSI0_I2C0_SCL 3 +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA SC_P_MIPI_DSI0_I2C0_SDA 0 +#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO17 SC_P_MIPI_DSI0_I2C0_SDA 3 +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 SC_P_MIPI_DSI0_GPIO0_00 0 +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT SC_P_MIPI_DSI0_GPIO0_00 1 +#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO18 SC_P_MIPI_DSI0_GPIO0_00 3 +#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 SC_P_MIPI_DSI0_GPIO0_01 0 +#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 SC_P_MIPI_DSI0_GPIO0_01 3 +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL SC_P_MIPI_DSI1_I2C0_SCL 0 +#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 SC_P_MIPI_DSI1_I2C0_SCL 3 +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA SC_P_MIPI_DSI1_I2C0_SDA 0 +#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 SC_P_MIPI_DSI1_I2C0_SDA 3 +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 SC_P_MIPI_DSI1_GPIO0_00 0 +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT SC_P_MIPI_DSI1_GPIO0_00 1 +#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 SC_P_MIPI_DSI1_GPIO0_00 3 +#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 SC_P_MIPI_DSI1_GPIO0_01 0 +#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 SC_P_MIPI_DSI1_GPIO0_01 3 +#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT SC_P_MIPI_CSI0_MCLK_OUT 0 +#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 SC_P_MIPI_CSI0_MCLK_OUT 3 +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL SC_P_MIPI_CSI0_I2C0_SCL 0 +#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO1_IO25 SC_P_MIPI_CSI0_I2C0_SCL 3 +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA SC_P_MIPI_CSI0_I2C0_SDA 0 +#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO1_IO26 SC_P_MIPI_CSI0_I2C0_SDA 3 +#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 SC_P_MIPI_CSI0_GPIO0_00 0 +#define SC_P_MIPI_CSI0_GPIO0_00_DMA_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 1 +#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI1_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 2 +#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 SC_P_MIPI_CSI0_GPIO0_00 3 +#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 SC_P_MIPI_CSI0_GPIO0_01 0 +#define SC_P_MIPI_CSI0_GPIO0_01_DMA_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 1 +#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI1_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 2 +#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 SC_P_MIPI_CSI0_GPIO0_01 3 +#define SC_P_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT SC_P_MIPI_CSI1_MCLK_OUT 0 +#define SC_P_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 SC_P_MIPI_CSI1_MCLK_OUT 3 +#define SC_P_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 SC_P_MIPI_CSI1_GPIO0_00 0 +#define SC_P_MIPI_CSI1_GPIO0_00_DMA_UART4_RX SC_P_MIPI_CSI1_GPIO0_00 1 +#define SC_P_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 SC_P_MIPI_CSI1_GPIO0_00 3 +#define SC_P_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 SC_P_MIPI_CSI1_GPIO0_01 0 +#define SC_P_MIPI_CSI1_GPIO0_01_DMA_UART4_TX SC_P_MIPI_CSI1_GPIO0_01 1 +#define SC_P_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 SC_P_MIPI_CSI1_GPIO0_01 3 +#define SC_P_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL SC_P_MIPI_CSI1_I2C0_SCL 0 +#define SC_P_MIPI_CSI1_I2C0_SCL_LSIO_GPIO2_IO00 SC_P_MIPI_CSI1_I2C0_SCL 3 +#define SC_P_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA SC_P_MIPI_CSI1_I2C0_SDA 0 +#define SC_P_MIPI_CSI1_I2C0_SDA_LSIO_GPIO2_IO01 SC_P_MIPI_CSI1_I2C0_SDA 3 +#define SC_P_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL SC_P_HDMI_TX0_TS_SCL 0 +#define SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL SC_P_HDMI_TX0_TS_SCL 1 +#define SC_P_HDMI_TX0_TS_SCL_LSIO_GPIO2_IO02 SC_P_HDMI_TX0_TS_SCL 3 +#define SC_P_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA SC_P_HDMI_TX0_TS_SDA 0 +#define SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA SC_P_HDMI_TX0_TS_SDA 1 +#define SC_P_HDMI_TX0_TS_SDA_LSIO_GPIO2_IO03 SC_P_HDMI_TX0_TS_SDA 3 +#define SC_P_ESAI1_FSR_AUD_ESAI1_FSR SC_P_ESAI1_FSR 0 +#define SC_P_ESAI1_FSR_LSIO_GPIO2_IO04 SC_P_ESAI1_FSR 3 +#define SC_P_ESAI1_FST_AUD_ESAI1_FST SC_P_ESAI1_FST 0 +#define SC_P_ESAI1_FST_AUD_SPDIF0_EXT_CLK SC_P_ESAI1_FST 1 +#define SC_P_ESAI1_FST_LSIO_GPIO2_IO05 SC_P_ESAI1_FST 3 +#define SC_P_ESAI1_SCKR_AUD_ESAI1_SCKR SC_P_ESAI1_SCKR 0 +#define SC_P_ESAI1_SCKR_LSIO_GPIO2_IO06 SC_P_ESAI1_SCKR 3 +#define SC_P_ESAI1_SCKT_AUD_ESAI1_SCKT SC_P_ESAI1_SCKT 0 +#define SC_P_ESAI1_SCKT_AUD_SAI2_RXC SC_P_ESAI1_SCKT 1 +#define SC_P_ESAI1_SCKT_AUD_SPDIF0_EXT_CLK SC_P_ESAI1_SCKT 2 +#define SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07 SC_P_ESAI1_SCKT 3 +#define SC_P_ESAI1_TX0_AUD_ESAI1_TX0 SC_P_ESAI1_TX0 0 +#define SC_P_ESAI1_TX0_AUD_SAI2_RXD SC_P_ESAI1_TX0 1 +#define SC_P_ESAI1_TX0_AUD_SPDIF0_RX SC_P_ESAI1_TX0 2 +#define SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 SC_P_ESAI1_TX0 3 +#define SC_P_ESAI1_TX1_AUD_ESAI1_TX1 SC_P_ESAI1_TX1 0 +#define SC_P_ESAI1_TX1_AUD_SAI2_RXFS SC_P_ESAI1_TX1 1 +#define SC_P_ESAI1_TX1_AUD_SPDIF0_TX SC_P_ESAI1_TX1 2 +#define SC_P_ESAI1_TX1_LSIO_GPIO2_IO09 SC_P_ESAI1_TX1 3 +#define SC_P_ESAI1_TX2_RX3_AUD_ESAI1_TX2_RX3 SC_P_ESAI1_TX2_RX3 0 +#define SC_P_ESAI1_TX2_RX3_AUD_SPDIF0_RX SC_P_ESAI1_TX2_RX3 1 +#define SC_P_ESAI1_TX2_RX3_LSIO_GPIO2_IO10 SC_P_ESAI1_TX2_RX3 3 +#define SC_P_ESAI1_TX3_RX2_AUD_ESAI1_TX3_RX2 SC_P_ESAI1_TX3_RX2 0 +#define SC_P_ESAI1_TX3_RX2_AUD_SPDIF0_TX SC_P_ESAI1_TX3_RX2 1 +#define SC_P_ESAI1_TX3_RX2_LSIO_GPIO2_IO11 SC_P_ESAI1_TX3_RX2 3 +#define SC_P_ESAI1_TX4_RX1_AUD_ESAI1_TX4_RX1 SC_P_ESAI1_TX4_RX1 0 +#define SC_P_ESAI1_TX4_RX1_LSIO_GPIO2_IO12 SC_P_ESAI1_TX4_RX1 3 +#define SC_P_ESAI1_TX5_RX0_AUD_ESAI1_TX5_RX0 SC_P_ESAI1_TX5_RX0 0 +#define SC_P_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 SC_P_ESAI1_TX5_RX0 3 +#define SC_P_SPDIF0_RX_AUD_SPDIF0_RX SC_P_SPDIF0_RX 0 +#define SC_P_SPDIF0_RX_AUD_MQS_R SC_P_SPDIF0_RX 1 +#define SC_P_SPDIF0_RX_AUD_ACM_MCLK_IN1 SC_P_SPDIF0_RX 2 +#define SC_P_SPDIF0_RX_LSIO_GPIO2_IO14 SC_P_SPDIF0_RX 3 +#define SC_P_SPDIF0_TX_AUD_SPDIF0_TX SC_P_SPDIF0_TX 0 +#define SC_P_SPDIF0_TX_AUD_MQS_L SC_P_SPDIF0_TX 1 +#define SC_P_SPDIF0_TX_AUD_ACM_MCLK_OUT1 SC_P_SPDIF0_TX 2 +#define SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 SC_P_SPDIF0_TX 3 +#define SC_P_SPDIF0_EXT_CLK_AUD_SPDIF0_EXT_CLK SC_P_SPDIF0_EXT_CLK 0 +#define SC_P_SPDIF0_EXT_CLK_DMA_DMA0_REQ_IN0 SC_P_SPDIF0_EXT_CLK 1 +#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16 SC_P_SPDIF0_EXT_CLK 3 +#define SC_P_SPI3_SCK_DMA_SPI3_SCK SC_P_SPI3_SCK 0 +#define SC_P_SPI3_SCK_LSIO_GPIO2_IO17 SC_P_SPI3_SCK 3 +#define SC_P_SPI3_SDO_DMA_SPI3_SDO SC_P_SPI3_SDO 0 +#define SC_P_SPI3_SDO_DMA_FTM_CH0 SC_P_SPI3_SDO 1 +#define SC_P_SPI3_SDO_LSIO_GPIO2_IO18 SC_P_SPI3_SDO 3 +#define SC_P_SPI3_SDI_DMA_SPI3_SDI SC_P_SPI3_SDI 0 +#define SC_P_SPI3_SDI_DMA_FTM_CH1 SC_P_SPI3_SDI 1 +#define SC_P_SPI3_SDI_LSIO_GPIO2_IO19 SC_P_SPI3_SDI 3 +#define SC_P_SPI3_CS0_DMA_SPI3_CS0 SC_P_SPI3_CS0 0 +#define SC_P_SPI3_CS0_DMA_FTM_CH2 SC_P_SPI3_CS0 1 +#define SC_P_SPI3_CS0_LSIO_GPIO2_IO20 SC_P_SPI3_CS0 3 +#define SC_P_SPI3_CS1_DMA_SPI3_CS1 SC_P_SPI3_CS1 0 +#define SC_P_SPI3_CS1_LSIO_GPIO2_IO21 SC_P_SPI3_CS1 3 +#define SC_P_ESAI0_FSR_AUD_ESAI0_FSR SC_P_ESAI0_FSR 0 +#define SC_P_ESAI0_FSR_LSIO_GPIO2_IO22 SC_P_ESAI0_FSR 3 +#define SC_P_ESAI0_FST_AUD_ESAI0_FST SC_P_ESAI0_FST 0 +#define SC_P_ESAI0_FST_LSIO_GPIO2_IO23 SC_P_ESAI0_FST 3 +#define SC_P_ESAI0_SCKR_AUD_ESAI0_SCKR SC_P_ESAI0_SCKR 0 +#define SC_P_ESAI0_SCKR_LSIO_GPIO2_IO24 SC_P_ESAI0_SCKR 3 +#define SC_P_ESAI0_SCKT_AUD_ESAI0_SCKT SC_P_ESAI0_SCKT 0 +#define SC_P_ESAI0_SCKT_LSIO_GPIO2_IO25 SC_P_ESAI0_SCKT 3 +#define SC_P_ESAI0_TX0_AUD_ESAI0_TX0 SC_P_ESAI0_TX0 0 +#define SC_P_ESAI0_TX0_LSIO_GPIO2_IO26 SC_P_ESAI0_TX0 3 +#define SC_P_ESAI0_TX1_AUD_ESAI0_TX1 SC_P_ESAI0_TX1 0 +#define SC_P_ESAI0_TX1_LSIO_GPIO2_IO27 SC_P_ESAI0_TX1 3 +#define SC_P_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 SC_P_ESAI0_TX2_RX3 0 +#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 SC_P_ESAI0_TX2_RX3 3 +#define SC_P_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 SC_P_ESAI0_TX3_RX2 0 +#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 SC_P_ESAI0_TX3_RX2 3 +#define SC_P_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 SC_P_ESAI0_TX4_RX1 0 +#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 SC_P_ESAI0_TX4_RX1 3 +#define SC_P_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 SC_P_ESAI0_TX5_RX0 0 +#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 SC_P_ESAI0_TX5_RX0 3 +#define SC_P_MCLK_IN0_AUD_ACM_MCLK_IN0 SC_P_MCLK_IN0 0 +#define SC_P_MCLK_IN0_AUD_ESAI0_RX_HF_CLK SC_P_MCLK_IN0 1 +#define SC_P_MCLK_IN0_AUD_ESAI1_RX_HF_CLK SC_P_MCLK_IN0 2 +#define SC_P_MCLK_IN0_LSIO_GPIO3_IO00 SC_P_MCLK_IN0 3 +#define SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 SC_P_MCLK_OUT0 0 +#define SC_P_MCLK_OUT0_AUD_ESAI0_TX_HF_CLK SC_P_MCLK_OUT0 1 +#define SC_P_MCLK_OUT0_AUD_ESAI1_TX_HF_CLK SC_P_MCLK_OUT0 2 +#define SC_P_MCLK_OUT0_LSIO_GPIO3_IO01 SC_P_MCLK_OUT0 3 +#define SC_P_SPI0_SCK_DMA_SPI0_SCK SC_P_SPI0_SCK 0 +#define SC_P_SPI0_SCK_AUD_SAI0_RXC SC_P_SPI0_SCK 1 +#define SC_P_SPI0_SCK_LSIO_GPIO3_IO02 SC_P_SPI0_SCK 3 +#define SC_P_SPI0_SDO_DMA_SPI0_SDO SC_P_SPI0_SDO 0 +#define SC_P_SPI0_SDO_AUD_SAI0_TXD SC_P_SPI0_SDO 1 +#define SC_P_SPI0_SDO_LSIO_GPIO3_IO03 SC_P_SPI0_SDO 3 +#define SC_P_SPI0_SDI_DMA_SPI0_SDI SC_P_SPI0_SDI 0 +#define SC_P_SPI0_SDI_AUD_SAI0_RXD SC_P_SPI0_SDI 1 +#define SC_P_SPI0_SDI_LSIO_GPIO3_IO04 SC_P_SPI0_SDI 3 +#define SC_P_SPI0_CS0_DMA_SPI0_CS0 SC_P_SPI0_CS0 0 +#define SC_P_SPI0_CS0_AUD_SAI0_RXFS SC_P_SPI0_CS0 1 +#define SC_P_SPI0_CS0_LSIO_GPIO3_IO05 SC_P_SPI0_CS0 3 +#define SC_P_SPI0_CS1_DMA_SPI0_CS1 SC_P_SPI0_CS1 0 +#define SC_P_SPI0_CS1_AUD_SAI0_TXC SC_P_SPI0_CS1 1 +#define SC_P_SPI0_CS1_LSIO_GPIO3_IO06 SC_P_SPI0_CS1 3 +#define SC_P_SPI2_SCK_DMA_SPI2_SCK SC_P_SPI2_SCK 0 +#define SC_P_SPI2_SCK_LSIO_GPIO3_IO07 SC_P_SPI2_SCK 3 +#define SC_P_SPI2_SDO_DMA_SPI2_SDO SC_P_SPI2_SDO 0 +#define SC_P_SPI2_SDO_LSIO_GPIO3_IO08 SC_P_SPI2_SDO 3 +#define SC_P_SPI2_SDI_DMA_SPI2_SDI SC_P_SPI2_SDI 0 +#define SC_P_SPI2_SDI_LSIO_GPIO3_IO09 SC_P_SPI2_SDI 3 +#define SC_P_SPI2_CS0_DMA_SPI2_CS0 SC_P_SPI2_CS0 0 +#define SC_P_SPI2_CS0_LSIO_GPIO3_IO10 SC_P_SPI2_CS0 3 +#define SC_P_SPI2_CS1_DMA_SPI2_CS1 SC_P_SPI2_CS1 0 +#define SC_P_SPI2_CS1_AUD_SAI0_TXFS SC_P_SPI2_CS1 1 +#define SC_P_SPI2_CS1_LSIO_GPIO3_IO11 SC_P_SPI2_CS1 3 +#define SC_P_SAI1_RXC_AUD_SAI1_RXC SC_P_SAI1_RXC 0 +#define SC_P_SAI1_RXC_AUD_SAI0_TXD SC_P_SAI1_RXC 1 +#define SC_P_SAI1_RXC_LSIO_GPIO3_IO12 SC_P_SAI1_RXC 3 +#define SC_P_SAI1_RXD_AUD_SAI1_RXD SC_P_SAI1_RXD 0 +#define SC_P_SAI1_RXD_AUD_SAI0_TXFS SC_P_SAI1_RXD 1 +#define SC_P_SAI1_RXD_LSIO_GPIO3_IO13 SC_P_SAI1_RXD 3 +#define SC_P_SAI1_RXFS_AUD_SAI1_RXFS SC_P_SAI1_RXFS 0 +#define SC_P_SAI1_RXFS_AUD_SAI0_RXD SC_P_SAI1_RXFS 1 +#define SC_P_SAI1_RXFS_LSIO_GPIO3_IO14 SC_P_SAI1_RXFS 3 +#define SC_P_SAI1_TXC_AUD_SAI1_TXC SC_P_SAI1_TXC 0 +#define SC_P_SAI1_TXC_AUD_SAI0_TXC SC_P_SAI1_TXC 1 +#define SC_P_SAI1_TXC_LSIO_GPIO3_IO15 SC_P_SAI1_TXC 3 +#define SC_P_SAI1_TXD_AUD_SAI1_TXD SC_P_SAI1_TXD 0 +#define SC_P_SAI1_TXD_AUD_SAI1_RXC SC_P_SAI1_TXD 1 +#define SC_P_SAI1_TXD_LSIO_GPIO3_IO16 SC_P_SAI1_TXD 3 +#define SC_P_SAI1_TXFS_AUD_SAI1_TXFS SC_P_SAI1_TXFS 0 +#define SC_P_SAI1_TXFS_AUD_SAI1_RXFS SC_P_SAI1_TXFS 1 +#define SC_P_SAI1_TXFS_LSIO_GPIO3_IO17 SC_P_SAI1_TXFS 3 +#define SC_P_ADC_IN7_DMA_ADC1_IN3 SC_P_ADC_IN7 0 +#define SC_P_ADC_IN7_DMA_SPI1_CS1 SC_P_ADC_IN7 1 +#define SC_P_ADC_IN7_LSIO_KPP0_ROW3 SC_P_ADC_IN7 2 +#define SC_P_ADC_IN7_LSIO_GPIO3_IO25 SC_P_ADC_IN7 3 +#define SC_P_ADC_IN6_DMA_ADC1_IN2 SC_P_ADC_IN6 0 +#define SC_P_ADC_IN6_DMA_SPI1_CS0 SC_P_ADC_IN6 1 +#define SC_P_ADC_IN6_LSIO_KPP0_ROW2 SC_P_ADC_IN6 2 +#define SC_P_ADC_IN6_LSIO_GPIO3_IO24 SC_P_ADC_IN6 3 +#define SC_P_ADC_IN5_DMA_ADC1_IN1 SC_P_ADC_IN5 0 +#define SC_P_ADC_IN5_DMA_SPI1_SDI SC_P_ADC_IN5 1 +#define SC_P_ADC_IN5_LSIO_KPP0_ROW1 SC_P_ADC_IN5 2 +#define SC_P_ADC_IN5_LSIO_GPIO3_IO23 SC_P_ADC_IN5 3 +#define SC_P_ADC_IN4_DMA_ADC1_IN0 SC_P_ADC_IN4 0 +#define SC_P_ADC_IN4_DMA_SPI1_SDO SC_P_ADC_IN4 1 +#define SC_P_ADC_IN4_LSIO_KPP0_ROW0 SC_P_ADC_IN4 2 +#define SC_P_ADC_IN4_LSIO_GPIO3_IO22 SC_P_ADC_IN4 3 +#define SC_P_ADC_IN3_DMA_ADC0_IN3 SC_P_ADC_IN3 0 +#define SC_P_ADC_IN3_DMA_SPI1_SCK SC_P_ADC_IN3 1 +#define SC_P_ADC_IN3_LSIO_KPP0_COL3 SC_P_ADC_IN3 2 +#define SC_P_ADC_IN3_LSIO_GPIO3_IO21 SC_P_ADC_IN3 3 +#define SC_P_ADC_IN2_DMA_ADC0_IN2 SC_P_ADC_IN2 0 +#define SC_P_ADC_IN2_LSIO_KPP0_COL2 SC_P_ADC_IN2 2 +#define SC_P_ADC_IN2_LSIO_GPIO3_IO20 SC_P_ADC_IN2 3 +#define SC_P_ADC_IN1_DMA_ADC0_IN1 SC_P_ADC_IN1 0 +#define SC_P_ADC_IN1_LSIO_KPP0_COL1 SC_P_ADC_IN1 2 +#define SC_P_ADC_IN1_LSIO_GPIO3_IO19 SC_P_ADC_IN1 3 +#define SC_P_ADC_IN0_DMA_ADC0_IN0 SC_P_ADC_IN0 0 +#define SC_P_ADC_IN0_LSIO_KPP0_COL0 SC_P_ADC_IN0 2 +#define SC_P_ADC_IN0_LSIO_GPIO3_IO18 SC_P_ADC_IN0 3 +#define SC_P_MLB_SIG_CONN_MLB_SIG SC_P_MLB_SIG 0 +#define SC_P_MLB_SIG_AUD_SAI3_RXC SC_P_MLB_SIG 1 +#define SC_P_MLB_SIG_LSIO_GPIO3_IO26 SC_P_MLB_SIG 3 +#define SC_P_MLB_CLK_CONN_MLB_CLK SC_P_MLB_CLK 0 +#define SC_P_MLB_CLK_AUD_SAI3_RXFS SC_P_MLB_CLK 1 +#define SC_P_MLB_CLK_LSIO_GPIO3_IO27 SC_P_MLB_CLK 3 +#define SC_P_MLB_DATA_CONN_MLB_DATA SC_P_MLB_DATA 0 +#define SC_P_MLB_DATA_AUD_SAI3_RXD SC_P_MLB_DATA 1 +#define SC_P_MLB_DATA_LSIO_GPIO3_IO28 SC_P_MLB_DATA 3 +#define SC_P_FLEXCAN0_RX_DMA_FLEXCAN0_RX SC_P_FLEXCAN0_RX 0 +#define SC_P_FLEXCAN0_RX_LSIO_GPIO3_IO29 SC_P_FLEXCAN0_RX 3 +#define SC_P_FLEXCAN0_TX_DMA_FLEXCAN0_TX SC_P_FLEXCAN0_TX 0 +#define SC_P_FLEXCAN0_TX_LSIO_GPIO3_IO30 SC_P_FLEXCAN0_TX 3 +#define SC_P_FLEXCAN1_RX_DMA_FLEXCAN1_RX SC_P_FLEXCAN1_RX 0 +#define SC_P_FLEXCAN1_RX_LSIO_GPIO3_IO31 SC_P_FLEXCAN1_RX 3 +#define SC_P_FLEXCAN1_TX_DMA_FLEXCAN1_TX SC_P_FLEXCAN1_TX 0 +#define SC_P_FLEXCAN1_TX_LSIO_GPIO4_IO00 SC_P_FLEXCAN1_TX 3 +#define SC_P_FLEXCAN2_RX_DMA_FLEXCAN2_RX SC_P_FLEXCAN2_RX 0 +#define SC_P_FLEXCAN2_RX_LSIO_GPIO4_IO01 SC_P_FLEXCAN2_RX 3 +#define SC_P_FLEXCAN2_TX_DMA_FLEXCAN2_TX SC_P_FLEXCAN2_TX 0 +#define SC_P_FLEXCAN2_TX_LSIO_GPIO4_IO02 SC_P_FLEXCAN2_TX 3 +#define SC_P_USB_SS3_TC0_DMA_I2C1_SCL SC_P_USB_SS3_TC0 0 +#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR SC_P_USB_SS3_TC0 1 +#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 SC_P_USB_SS3_TC0 3 +#define SC_P_USB_SS3_TC1_DMA_I2C1_SCL SC_P_USB_SS3_TC1 0 +#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC1 1 +#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 SC_P_USB_SS3_TC1 3 +#define SC_P_USB_SS3_TC2_DMA_I2C1_SDA SC_P_USB_SS3_TC2 0 +#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC SC_P_USB_SS3_TC2 1 +#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 SC_P_USB_SS3_TC2 3 +#define SC_P_USB_SS3_TC3_DMA_I2C1_SDA SC_P_USB_SS3_TC3 0 +#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC SC_P_USB_SS3_TC3 1 +#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 SC_P_USB_SS3_TC3 3 +#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B SC_P_USDHC1_RESET_B 0 +#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 SC_P_USDHC1_RESET_B 3 +#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT SC_P_USDHC1_VSELECT 0 +#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO08 SC_P_USDHC1_VSELECT 3 +#define SC_P_USDHC2_RESET_B_CONN_USDHC2_RESET_B SC_P_USDHC2_RESET_B 0 +#define SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 SC_P_USDHC2_RESET_B 3 +#define SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT SC_P_USDHC2_VSELECT 0 +#define SC_P_USDHC2_VSELECT_LSIO_GPIO4_IO10 SC_P_USDHC2_VSELECT 3 +#define SC_P_USDHC2_WP_CONN_USDHC2_WP SC_P_USDHC2_WP 0 +#define SC_P_USDHC2_WP_LSIO_GPIO4_IO11 SC_P_USDHC2_WP 3 +#define SC_P_USDHC2_CD_B_CONN_USDHC2_CD_B SC_P_USDHC2_CD_B 0 +#define SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 SC_P_USDHC2_CD_B 3 +#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO SC_P_ENET0_MDIO 0 +#define SC_P_ENET0_MDIO_DMA_I2C4_SDA SC_P_ENET0_MDIO 1 +#define SC_P_ENET0_MDIO_LSIO_GPIO4_IO13 SC_P_ENET0_MDIO 3 +#define SC_P_ENET0_MDC_CONN_ENET0_MDC SC_P_ENET0_MDC 0 +#define SC_P_ENET0_MDC_DMA_I2C4_SCL SC_P_ENET0_MDC 1 +#define SC_P_ENET0_MDC_LSIO_GPIO4_IO14 SC_P_ENET0_MDC 3 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M SC_P_ENET0_REFCLK_125M_25M 0 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS SC_P_ENET0_REFCLK_125M_25M 1 +#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 SC_P_ENET0_REFCLK_125M_25M 3 +#define SC_P_ENET1_REFCLK_125M_25M_CONN_ENET1_REFCLK_125M_25M SC_P_ENET1_REFCLK_125M_25M 0 +#define SC_P_ENET1_REFCLK_125M_25M_CONN_ENET1_PPS SC_P_ENET1_REFCLK_125M_25M 1 +#define SC_P_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 SC_P_ENET1_REFCLK_125M_25M 3 +#define SC_P_ENET1_MDIO_CONN_ENET1_MDIO SC_P_ENET1_MDIO 0 +#define SC_P_ENET1_MDIO_DMA_I2C4_SDA SC_P_ENET1_MDIO 1 +#define SC_P_ENET1_MDIO_LSIO_GPIO4_IO17 SC_P_ENET1_MDIO 3 +#define SC_P_ENET1_MDC_CONN_ENET1_MDC SC_P_ENET1_MDC 0 +#define SC_P_ENET1_MDC_DMA_I2C4_SCL SC_P_ENET1_MDC 1 +#define SC_P_ENET1_MDC_LSIO_GPIO4_IO18 SC_P_ENET1_MDC 3 +#define SC_P_QSPI1A_SS0_B_LSIO_QSPI1A_SS0_B SC_P_QSPI1A_SS0_B 0 +#define SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 SC_P_QSPI1A_SS0_B 3 +#define SC_P_QSPI1A_SS1_B_LSIO_QSPI1A_SS1_B SC_P_QSPI1A_SS1_B 0 +#define SC_P_QSPI1A_SS1_B_LSIO_QSPI1A_SCLK2 SC_P_QSPI1A_SS1_B 1 +#define SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20 SC_P_QSPI1A_SS1_B 3 +#define SC_P_QSPI1A_SCLK_LSIO_QSPI1A_SCLK SC_P_QSPI1A_SCLK 0 +#define SC_P_QSPI1A_SCLK_LSIO_GPIO4_IO21 SC_P_QSPI1A_SCLK 3 +#define SC_P_QSPI1A_DQS_LSIO_QSPI1A_DQS SC_P_QSPI1A_DQS 0 +#define SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22 SC_P_QSPI1A_DQS 3 +#define SC_P_QSPI1A_DATA3_LSIO_QSPI1A_DATA3 SC_P_QSPI1A_DATA3 0 +#define SC_P_QSPI1A_DATA3_DMA_I2C1_SDA SC_P_QSPI1A_DATA3 1 +#define SC_P_QSPI1A_DATA3_CONN_USB_OTG1_OC SC_P_QSPI1A_DATA3 2 +#define SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23 SC_P_QSPI1A_DATA3 3 +#define SC_P_QSPI1A_DATA2_LSIO_QSPI1A_DATA2 SC_P_QSPI1A_DATA2 0 +#define SC_P_QSPI1A_DATA2_DMA_I2C1_SCL SC_P_QSPI1A_DATA2 1 +#define SC_P_QSPI1A_DATA2_CONN_USB_OTG2_PWR SC_P_QSPI1A_DATA2 2 +#define SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24 SC_P_QSPI1A_DATA2 3 +#define SC_P_QSPI1A_DATA1_LSIO_QSPI1A_DATA1 SC_P_QSPI1A_DATA1 0 +#define SC_P_QSPI1A_DATA1_DMA_I2C1_SDA SC_P_QSPI1A_DATA1 1 +#define SC_P_QSPI1A_DATA1_CONN_USB_OTG2_OC SC_P_QSPI1A_DATA1 2 +#define SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 SC_P_QSPI1A_DATA1 3 +#define SC_P_QSPI1A_DATA0_LSIO_QSPI1A_DATA0 SC_P_QSPI1A_DATA0 0 +#define SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 SC_P_QSPI1A_DATA0 3 +#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 SC_P_QSPI0A_DATA0 0 +#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 SC_P_QSPI0A_DATA1 0 +#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 SC_P_QSPI0A_DATA2 0 +#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 SC_P_QSPI0A_DATA3 0 +#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS SC_P_QSPI0A_DQS 0 +#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B SC_P_QSPI0A_SS0_B 0 +#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B SC_P_QSPI0A_SS1_B 0 +#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SCLK2 SC_P_QSPI0A_SS1_B 1 +#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK SC_P_QSPI0A_SCLK 0 +#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK SC_P_QSPI0B_SCLK 0 +#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 SC_P_QSPI0B_DATA0 0 +#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 SC_P_QSPI0B_DATA1 0 +#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 SC_P_QSPI0B_DATA2 0 +#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 SC_P_QSPI0B_DATA3 0 +#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS SC_P_QSPI0B_DQS 0 +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B SC_P_QSPI0B_SS0_B 0 +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B SC_P_QSPI0B_SS1_B 0 +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SCLK2 SC_P_QSPI0B_SS1_B 1 +#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B SC_P_PCIE_CTRL0_CLKREQ_B 0 +#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 SC_P_PCIE_CTRL0_CLKREQ_B 3 +#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B SC_P_PCIE_CTRL0_WAKE_B 0 +#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 SC_P_PCIE_CTRL0_WAKE_B 3 +#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B SC_P_PCIE_CTRL0_PERST_B 0 +#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 SC_P_PCIE_CTRL0_PERST_B 3 +#define SC_P_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B SC_P_PCIE_CTRL1_CLKREQ_B 0 +#define SC_P_PCIE_CTRL1_CLKREQ_B_DMA_I2C1_SDA SC_P_PCIE_CTRL1_CLKREQ_B 1 +#define SC_P_PCIE_CTRL1_CLKREQ_B_CONN_USB_OTG2_OC SC_P_PCIE_CTRL1_CLKREQ_B 2 +#define SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 SC_P_PCIE_CTRL1_CLKREQ_B 3 +#define SC_P_PCIE_CTRL1_WAKE_B_HSIO_PCIE1_WAKE_B SC_P_PCIE_CTRL1_WAKE_B 0 +#define SC_P_PCIE_CTRL1_WAKE_B_DMA_I2C1_SCL SC_P_PCIE_CTRL1_WAKE_B 1 +#define SC_P_PCIE_CTRL1_WAKE_B_CONN_USB_OTG2_PWR SC_P_PCIE_CTRL1_WAKE_B 2 +#define SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 SC_P_PCIE_CTRL1_WAKE_B 3 +#define SC_P_PCIE_CTRL1_PERST_B_HSIO_PCIE1_PERST_B SC_P_PCIE_CTRL1_PERST_B 0 +#define SC_P_PCIE_CTRL1_PERST_B_DMA_I2C1_SCL SC_P_PCIE_CTRL1_PERST_B 1 +#define SC_P_PCIE_CTRL1_PERST_B_CONN_USB_OTG1_PWR SC_P_PCIE_CTRL1_PERST_B 2 +#define SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 SC_P_PCIE_CTRL1_PERST_B 3 +#define SC_P_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA SC_P_USB_HSIC0_DATA 0 +#define SC_P_USB_HSIC0_DATA_DMA_I2C1_SDA SC_P_USB_HSIC0_DATA 1 +#define SC_P_USB_HSIC0_DATA_LSIO_GPIO5_IO01 SC_P_USB_HSIC0_DATA 3 +#define SC_P_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE SC_P_USB_HSIC0_STROBE 0 +#define SC_P_USB_HSIC0_STROBE_DMA_I2C1_SCL SC_P_USB_HSIC0_STROBE 1 +#define SC_P_USB_HSIC0_STROBE_LSIO_GPIO5_IO02 SC_P_USB_HSIC0_STROBE 3 +#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK SC_P_EMMC0_CLK 0 +#define SC_P_EMMC0_CLK_CONN_NAND_READY_B SC_P_EMMC0_CLK 1 +#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD SC_P_EMMC0_CMD 0 +#define SC_P_EMMC0_CMD_CONN_NAND_DQS SC_P_EMMC0_CMD 1 +#define SC_P_EMMC0_CMD_AUD_MQS_R SC_P_EMMC0_CMD 2 +#define SC_P_EMMC0_CMD_LSIO_GPIO5_IO03 SC_P_EMMC0_CMD 3 +#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 SC_P_EMMC0_DATA0 0 +#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00 SC_P_EMMC0_DATA0 1 +#define SC_P_EMMC0_DATA0_LSIO_GPIO5_IO04 SC_P_EMMC0_DATA0 3 +#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 SC_P_EMMC0_DATA1 0 +#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01 SC_P_EMMC0_DATA1 1 +#define SC_P_EMMC0_DATA1_LSIO_GPIO5_IO05 SC_P_EMMC0_DATA1 3 +#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 SC_P_EMMC0_DATA2 0 +#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02 SC_P_EMMC0_DATA2 1 +#define SC_P_EMMC0_DATA2_LSIO_GPIO5_IO06 SC_P_EMMC0_DATA2 3 +#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 SC_P_EMMC0_DATA3 0 +#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03 SC_P_EMMC0_DATA3 1 +#define SC_P_EMMC0_DATA3_LSIO_GPIO5_IO07 SC_P_EMMC0_DATA3 3 +#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 SC_P_EMMC0_DATA4 0 +#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04 SC_P_EMMC0_DATA4 1 +#define SC_P_EMMC0_DATA4_LSIO_GPIO5_IO08 SC_P_EMMC0_DATA4 3 +#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 SC_P_EMMC0_DATA5 0 +#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05 SC_P_EMMC0_DATA5 1 +#define SC_P_EMMC0_DATA5_LSIO_GPIO5_IO09 SC_P_EMMC0_DATA5 3 +#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 SC_P_EMMC0_DATA6 0 +#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06 SC_P_EMMC0_DATA6 1 +#define SC_P_EMMC0_DATA6_LSIO_GPIO5_IO10 SC_P_EMMC0_DATA6 3 +#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 SC_P_EMMC0_DATA7 0 +#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07 SC_P_EMMC0_DATA7 1 +#define SC_P_EMMC0_DATA7_LSIO_GPIO5_IO11 SC_P_EMMC0_DATA7 3 +#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE SC_P_EMMC0_STROBE 0 +#define SC_P_EMMC0_STROBE_CONN_NAND_CLE SC_P_EMMC0_STROBE 1 +#define SC_P_EMMC0_STROBE_LSIO_GPIO5_IO12 SC_P_EMMC0_STROBE 3 +#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B SC_P_EMMC0_RESET_B 0 +#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B SC_P_EMMC0_RESET_B 1 +#define SC_P_EMMC0_RESET_B_CONN_USDHC1_VSELECT SC_P_EMMC0_RESET_B 2 +#define SC_P_EMMC0_RESET_B_LSIO_GPIO5_IO13 SC_P_EMMC0_RESET_B 3 +#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK SC_P_USDHC1_CLK 0 +#define SC_P_USDHC1_CLK_AUD_MQS_R SC_P_USDHC1_CLK 1 +#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD SC_P_USDHC1_CMD 0 +#define SC_P_USDHC1_CMD_AUD_MQS_L SC_P_USDHC1_CMD 1 +#define SC_P_USDHC1_CMD_LSIO_GPIO5_IO14 SC_P_USDHC1_CMD 3 +#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 SC_P_USDHC1_DATA0 0 +#define SC_P_USDHC1_DATA0_CONN_NAND_RE_N SC_P_USDHC1_DATA0 1 +#define SC_P_USDHC1_DATA0_LSIO_GPIO5_IO15 SC_P_USDHC1_DATA0 3 +#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 SC_P_USDHC1_DATA1 0 +#define SC_P_USDHC1_DATA1_CONN_NAND_RE_P SC_P_USDHC1_DATA1 1 +#define SC_P_USDHC1_DATA1_LSIO_GPIO5_IO16 SC_P_USDHC1_DATA1 3 +#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 SC_P_USDHC1_DATA2 0 +#define SC_P_USDHC1_DATA2_CONN_NAND_DQS_N SC_P_USDHC1_DATA2 1 +#define SC_P_USDHC1_DATA2_LSIO_GPIO5_IO17 SC_P_USDHC1_DATA2 3 +#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 SC_P_USDHC1_DATA3 0 +#define SC_P_USDHC1_DATA3_CONN_NAND_DQS_P SC_P_USDHC1_DATA3 1 +#define SC_P_USDHC1_DATA3_LSIO_GPIO5_IO18 SC_P_USDHC1_DATA3 3 +#define SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4 SC_P_USDHC1_DATA4 0 +#define SC_P_USDHC1_DATA4_CONN_NAND_CE0_B SC_P_USDHC1_DATA4 1 +#define SC_P_USDHC1_DATA4_AUD_MQS_R SC_P_USDHC1_DATA4 2 +#define SC_P_USDHC1_DATA4_LSIO_GPIO5_IO19 SC_P_USDHC1_DATA4 3 +#define SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5 SC_P_USDHC1_DATA5 0 +#define SC_P_USDHC1_DATA5_CONN_NAND_RE_B SC_P_USDHC1_DATA5 1 +#define SC_P_USDHC1_DATA5_AUD_MQS_L SC_P_USDHC1_DATA5 2 +#define SC_P_USDHC1_DATA5_LSIO_GPIO5_IO20 SC_P_USDHC1_DATA5 3 +#define SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6 SC_P_USDHC1_DATA6 0 +#define SC_P_USDHC1_DATA6_CONN_NAND_WE_B SC_P_USDHC1_DATA6 1 +#define SC_P_USDHC1_DATA6_CONN_USDHC1_WP SC_P_USDHC1_DATA6 2 +#define SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 SC_P_USDHC1_DATA6 3 +#define SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7 SC_P_USDHC1_DATA7 0 +#define SC_P_USDHC1_DATA7_CONN_NAND_ALE SC_P_USDHC1_DATA7 1 +#define SC_P_USDHC1_DATA7_CONN_USDHC1_CD_B SC_P_USDHC1_DATA7 2 +#define SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 SC_P_USDHC1_DATA7 3 +#define SC_P_USDHC1_STROBE_CONN_USDHC1_STROBE SC_P_USDHC1_STROBE 0 +#define SC_P_USDHC1_STROBE_CONN_NAND_CE1_B SC_P_USDHC1_STROBE 1 +#define SC_P_USDHC1_STROBE_CONN_USDHC1_RESET_B SC_P_USDHC1_STROBE 2 +#define SC_P_USDHC1_STROBE_LSIO_GPIO5_IO23 SC_P_USDHC1_STROBE 3 +#define SC_P_USDHC2_CLK_CONN_USDHC2_CLK SC_P_USDHC2_CLK 0 +#define SC_P_USDHC2_CLK_AUD_MQS_R SC_P_USDHC2_CLK 1 +#define SC_P_USDHC2_CLK_LSIO_GPIO5_IO24 SC_P_USDHC2_CLK 3 +#define SC_P_USDHC2_CMD_CONN_USDHC2_CMD SC_P_USDHC2_CMD 0 +#define SC_P_USDHC2_CMD_AUD_MQS_L SC_P_USDHC2_CMD 1 +#define SC_P_USDHC2_CMD_LSIO_GPIO5_IO25 SC_P_USDHC2_CMD 3 +#define SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 SC_P_USDHC2_DATA0 0 +#define SC_P_USDHC2_DATA0_DMA_UART4_RX SC_P_USDHC2_DATA0 1 +#define SC_P_USDHC2_DATA0_LSIO_GPIO5_IO26 SC_P_USDHC2_DATA0 3 +#define SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 SC_P_USDHC2_DATA1 0 +#define SC_P_USDHC2_DATA1_DMA_UART4_TX SC_P_USDHC2_DATA1 1 +#define SC_P_USDHC2_DATA1_LSIO_GPIO5_IO27 SC_P_USDHC2_DATA1 3 +#define SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 SC_P_USDHC2_DATA2 0 +#define SC_P_USDHC2_DATA2_DMA_UART4_CTS_B SC_P_USDHC2_DATA2 1 +#define SC_P_USDHC2_DATA2_LSIO_GPIO5_IO28 SC_P_USDHC2_DATA2 3 +#define SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 SC_P_USDHC2_DATA3 0 +#define SC_P_USDHC2_DATA3_DMA_UART4_RTS_B SC_P_USDHC2_DATA3 1 +#define SC_P_USDHC2_DATA3_LSIO_GPIO5_IO29 SC_P_USDHC2_DATA3 3 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC SC_P_ENET0_RGMII_TXC 0 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT SC_P_ENET0_RGMII_TXC 1 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN SC_P_ENET0_RGMII_TXC 2 +#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 SC_P_ENET0_RGMII_TXC 3 +#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL SC_P_ENET0_RGMII_TX_CTL 0 +#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 SC_P_ENET0_RGMII_TX_CTL 3 +#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 SC_P_ENET0_RGMII_TXD0 0 +#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 SC_P_ENET0_RGMII_TXD0 3 +#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 SC_P_ENET0_RGMII_TXD1 0 +#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 SC_P_ENET0_RGMII_TXD1 3 +#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 SC_P_ENET0_RGMII_TXD2 0 +#define SC_P_ENET0_RGMII_TXD2_DMA_UART3_TX SC_P_ENET0_RGMII_TXD2 1 +#define SC_P_ENET0_RGMII_TXD2_VPU_TSI_S1_VID SC_P_ENET0_RGMII_TXD2 2 +#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 SC_P_ENET0_RGMII_TXD2 3 +#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 SC_P_ENET0_RGMII_TXD3 0 +#define SC_P_ENET0_RGMII_TXD3_DMA_UART3_RTS_B SC_P_ENET0_RGMII_TXD3 1 +#define SC_P_ENET0_RGMII_TXD3_VPU_TSI_S1_SYNC SC_P_ENET0_RGMII_TXD3 2 +#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 SC_P_ENET0_RGMII_TXD3 3 +#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC SC_P_ENET0_RGMII_RXC 0 +#define SC_P_ENET0_RGMII_RXC_DMA_UART3_CTS_B SC_P_ENET0_RGMII_RXC 1 +#define SC_P_ENET0_RGMII_RXC_VPU_TSI_S1_DATA SC_P_ENET0_RGMII_RXC 2 +#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 SC_P_ENET0_RGMII_RXC 3 +#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL SC_P_ENET0_RGMII_RX_CTL 0 +#define SC_P_ENET0_RGMII_RX_CTL_VPU_TSI_S0_VID SC_P_ENET0_RGMII_RX_CTL 2 +#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 SC_P_ENET0_RGMII_RX_CTL 3 +#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 SC_P_ENET0_RGMII_RXD0 0 +#define SC_P_ENET0_RGMII_RXD0_VPU_TSI_S0_SYNC SC_P_ENET0_RGMII_RXD0 2 +#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 SC_P_ENET0_RGMII_RXD0 3 +#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 SC_P_ENET0_RGMII_RXD1 0 +#define SC_P_ENET0_RGMII_RXD1_VPU_TSI_S0_DATA SC_P_ENET0_RGMII_RXD1 2 +#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 SC_P_ENET0_RGMII_RXD1 3 +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 SC_P_ENET0_RGMII_RXD2 0 +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER SC_P_ENET0_RGMII_RXD2 1 +#define SC_P_ENET0_RGMII_RXD2_VPU_TSI_S0_CLK SC_P_ENET0_RGMII_RXD2 2 +#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 SC_P_ENET0_RGMII_RXD2 3 +#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 SC_P_ENET0_RGMII_RXD3 0 +#define SC_P_ENET0_RGMII_RXD3_DMA_UART3_RX SC_P_ENET0_RGMII_RXD3 1 +#define SC_P_ENET0_RGMII_RXD3_VPU_TSI_S1_CLK SC_P_ENET0_RGMII_RXD3 2 +#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 SC_P_ENET0_RGMII_RXD3 3 +#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC SC_P_ENET1_RGMII_TXC 0 +#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT SC_P_ENET1_RGMII_TXC 1 +#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_IN SC_P_ENET1_RGMII_TXC 2 +#define SC_P_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 SC_P_ENET1_RGMII_TXC 3 +#define SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL SC_P_ENET1_RGMII_TX_CTL 0 +#define SC_P_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 SC_P_ENET1_RGMII_TX_CTL 3 +#define SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 SC_P_ENET1_RGMII_TXD0 0 +#define SC_P_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 SC_P_ENET1_RGMII_TXD0 3 +#define SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 SC_P_ENET1_RGMII_TXD1 0 +#define SC_P_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 SC_P_ENET1_RGMII_TXD1 3 +#define SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 SC_P_ENET1_RGMII_TXD2 0 +#define SC_P_ENET1_RGMII_TXD2_DMA_UART3_TX SC_P_ENET1_RGMII_TXD2 1 +#define SC_P_ENET1_RGMII_TXD2_VPU_TSI_S1_VID SC_P_ENET1_RGMII_TXD2 2 +#define SC_P_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 SC_P_ENET1_RGMII_TXD2 3 +#define SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 SC_P_ENET1_RGMII_TXD3 0 +#define SC_P_ENET1_RGMII_TXD3_DMA_UART3_RTS_B SC_P_ENET1_RGMII_TXD3 1 +#define SC_P_ENET1_RGMII_TXD3_VPU_TSI_S1_SYNC SC_P_ENET1_RGMII_TXD3 2 +#define SC_P_ENET1_RGMII_TXD3_LSIO_GPIO6_IO15 SC_P_ENET1_RGMII_TXD3 3 +#define SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC SC_P_ENET1_RGMII_RXC 0 +#define SC_P_ENET1_RGMII_RXC_DMA_UART3_CTS_B SC_P_ENET1_RGMII_RXC 1 +#define SC_P_ENET1_RGMII_RXC_VPU_TSI_S1_DATA SC_P_ENET1_RGMII_RXC 2 +#define SC_P_ENET1_RGMII_RXC_LSIO_GPIO6_IO16 SC_P_ENET1_RGMII_RXC 3 +#define SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL SC_P_ENET1_RGMII_RX_CTL 0 +#define SC_P_ENET1_RGMII_RX_CTL_VPU_TSI_S0_VID SC_P_ENET1_RGMII_RX_CTL 2 +#define SC_P_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 SC_P_ENET1_RGMII_RX_CTL 3 +#define SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 SC_P_ENET1_RGMII_RXD0 0 +#define SC_P_ENET1_RGMII_RXD0_VPU_TSI_S0_SYNC SC_P_ENET1_RGMII_RXD0 2 +#define SC_P_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 SC_P_ENET1_RGMII_RXD0 3 +#define SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 SC_P_ENET1_RGMII_RXD1 0 +#define SC_P_ENET1_RGMII_RXD1_VPU_TSI_S0_DATA SC_P_ENET1_RGMII_RXD1 2 +#define SC_P_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 SC_P_ENET1_RGMII_RXD1 3 +#define SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 SC_P_ENET1_RGMII_RXD2 0 +#define SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER SC_P_ENET1_RGMII_RXD2 1 +#define SC_P_ENET1_RGMII_RXD2_VPU_TSI_S0_CLK SC_P_ENET1_RGMII_RXD2 2 +#define SC_P_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 SC_P_ENET1_RGMII_RXD2 3 +#define SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 SC_P_ENET1_RGMII_RXD3 0 +#define SC_P_ENET1_RGMII_RXD3_DMA_UART3_RX SC_P_ENET1_RGMII_RXD3 1 +#define SC_P_ENET1_RGMII_RXD3_VPU_TSI_S1_CLK SC_P_ENET1_RGMII_RXD3 2 +#define SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 SC_P_ENET1_RGMII_RXD3 3 +/*@}*/ + +#endif /* SC_PADS_H */ + diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h b/include/dt-bindings/pinctrl/pads-imx8qxp.h new file mode 100644 index 0000000000..8049735841 --- /dev/null +++ b/include/dt-bindings/pinctrl/pads-imx8qxp.h @@ -0,0 +1,770 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file used to configure SoC pad list. + */ + +#ifndef SC_PADS_H +#define SC_PADS_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Pad Definitions + */ +/*@{*/ +#define SC_P_PCIE_CTRL0_PERST_B 0 /*!< HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */ +#define SC_P_PCIE_CTRL0_CLKREQ_B 1 /*!< HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */ +#define SC_P_PCIE_CTRL0_WAKE_B 2 /*!< HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 /*!< */ +#define SC_P_USB_SS3_TC0 4 /*!< ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */ +#define SC_P_USB_SS3_TC1 5 /*!< ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */ +#define SC_P_USB_SS3_TC2 6 /*!< ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 */ +#define SC_P_USB_SS3_TC3 7 /*!< ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */ +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8 /*!< */ +#define SC_P_EMMC0_CLK 9 /*!< CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */ +#define SC_P_EMMC0_CMD 10 /*!< CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */ +#define SC_P_EMMC0_DATA0 11 /*!< CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */ +#define SC_P_EMMC0_DATA1 12 /*!< CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */ +#define SC_P_EMMC0_DATA2 13 /*!< CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */ +#define SC_P_EMMC0_DATA3 14 /*!< CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15 /*!< */ +#define SC_P_EMMC0_DATA4 16 /*!< CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */ +#define SC_P_EMMC0_DATA5 17 /*!< CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */ +#define SC_P_EMMC0_DATA6 18 /*!< CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */ +#define SC_P_EMMC0_DATA7 19 /*!< CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 */ +#define SC_P_EMMC0_STROBE 20 /*!< CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 */ +#define SC_P_EMMC0_RESET_B 21 /*!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22 /*!< */ +#define SC_P_USDHC1_RESET_B 23 /*!< CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 */ +#define SC_P_USDHC1_VSELECT 24 /*!< CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20 */ +#define SC_P_CTL_NAND_RE_P_N 25 /*!< */ +#define SC_P_USDHC1_WP 26 /*!< CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */ +#define SC_P_USDHC1_CD_B 27 /*!< CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22 */ +#define SC_P_CTL_NAND_DQS_P_N 28 /*!< */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29 /*!< */ +#define SC_P_USDHC1_CLK 30 /*!< CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */ +#define SC_P_USDHC1_CMD 31 /*!< CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */ +#define SC_P_USDHC1_DATA0 32 /*!< CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */ +#define SC_P_USDHC1_DATA1 33 /*!< CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */ +#define SC_P_USDHC1_DATA2 34 /*!< CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, LSIO.GPIO4.IO27 */ +#define SC_P_USDHC1_DATA3 35 /*!< CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, LSIO.GPIO4.IO28 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36 /*!< */ +#define SC_P_ENET0_RGMII_TXC 37 /*!< CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */ +#define SC_P_ENET0_RGMII_TX_CTL 38 /*!< CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */ +#define SC_P_ENET0_RGMII_TXD0 39 /*!< CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 */ +#define SC_P_ENET0_RGMII_TXD1 40 /*!< CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */ +#define SC_P_ENET0_RGMII_TXD2 41 /*!< CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 */ +#define SC_P_ENET0_RGMII_TXD3 42 /*!< CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, LSIO.GPIO5.IO02 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43 /*!< */ +#define SC_P_ENET0_RGMII_RXC 44 /*!< CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */ +#define SC_P_ENET0_RGMII_RX_CTL 45 /*!< CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */ +#define SC_P_ENET0_RGMII_RXD0 46 /*!< CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */ +#define SC_P_ENET0_RGMII_RXD1 47 /*!< CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */ +#define SC_P_ENET0_RGMII_RXD2 48 /*!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */ +#define SC_P_ENET0_RGMII_RXD3 49 /*!< CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO5.IO08 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50 /*!< */ +#define SC_P_ENET0_REFCLK_125M_25M 51 /*!< CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO5.IO09 */ +#define SC_P_ENET0_MDIO 52 /*!< CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO5.IO10 */ +#define SC_P_ENET0_MDC 53 /*!< CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO5.IO11 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54 /*!< */ +#define SC_P_ESAI0_FSR 55 /*!< ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN */ +#define SC_P_ESAI0_FST 56 /*!< ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01, CONN.ENET1.RGMII_TXD2, LSIO.GPIO0.IO01 */ +#define SC_P_ESAI0_SCKR 57 /*!< ADMA.ESAI0.SCKR, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO0.IO02 */ +#define SC_P_ESAI0_SCKT 58 /*!< ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D03, CONN.ENET1.RGMII_TXD3, LSIO.GPIO0.IO03 */ +#define SC_P_ESAI0_TX0 59 /*!< ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D04, CONN.ENET1.RGMII_RXC, LSIO.GPIO0.IO04 */ +#define SC_P_ESAI0_TX1 60 /*!< ADMA.ESAI0.TX1, ADMA.LCDIF.D05, CONN.ENET1.RGMII_RXD3, LSIO.GPIO0.IO05 */ +#define SC_P_ESAI0_TX2_RX3 61 /*!< ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D06, CONN.ENET1.RGMII_RXD2, LSIO.GPIO0.IO06 */ +#define SC_P_ESAI0_TX3_RX2 62 /*!< ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD1, LSIO.GPIO0.IO07 */ +#define SC_P_ESAI0_TX4_RX1 63 /*!< ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D08, CONN.ENET1.RGMII_TXD0, LSIO.GPIO0.IO08 */ +#define SC_P_ESAI0_TX5_RX0 64 /*!< ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D09, CONN.ENET1.RGMII_TXD1, LSIO.GPIO0.IO09 */ +#define SC_P_SPDIF0_RX 65 /*!< ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, LSIO.GPIO0.IO10 */ +#define SC_P_SPDIF0_TX 66 /*!< ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO0.IO11 */ +#define SC_P_SPDIF0_EXT_CLK 67 /*!< ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, LSIO.GPIO0.IO12 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68 /*!< */ +#define SC_P_SPI3_SCK 69 /*!< ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */ +#define SC_P_SPI3_SDO 70 /*!< ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */ +#define SC_P_SPI3_SDI 71 /*!< ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */ +#define SC_P_SPI3_CS0 72 /*!< ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16 */ +#define SC_P_SPI3_CS1 73 /*!< ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16 */ +#define SC_P_MCLK_IN1 74 /*!< ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17 */ +#define SC_P_MCLK_IN0 75 /*!< ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO0.IO19 */ +#define SC_P_MCLK_OUT0 76 /*!< ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO0.IO20 */ +#define SC_P_UART1_TX 77 /*!< ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21 */ +#define SC_P_UART1_RX 78 /*!< ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22 */ +#define SC_P_UART1_RTS_B 79 /*!< ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK */ +#define SC_P_UART1_CTS_B 80 /*!< ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO24 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81 /*!< */ +#define SC_P_SAI0_TXD 82 /*!< ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, LSIO.GPIO0.IO25 */ +#define SC_P_SAI0_TXC 83 /*!< ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, LSIO.GPIO0.IO26 */ +#define SC_P_SAI0_RXD 84 /*!< ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, LSIO.GPIO0.IO27 */ +#define SC_P_SAI0_TXFS 85 /*!< ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO0.IO28 */ +#define SC_P_SAI1_RXD 86 /*!< ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D21, LSIO.GPIO0.IO29 */ +#define SC_P_SAI1_RXC 87 /*!< ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22, LSIO.GPIO0.IO30 */ +#define SC_P_SAI1_RXFS 88 /*!< ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO0.IO31 */ +#define SC_P_SPI2_CS0 89 /*!< ADMA.SPI2.CS0, LSIO.GPIO1.IO00 */ +#define SC_P_SPI2_SDO 90 /*!< ADMA.SPI2.SDO, LSIO.GPIO1.IO01 */ +#define SC_P_SPI2_SDI 91 /*!< ADMA.SPI2.SDI, LSIO.GPIO1.IO02 */ +#define SC_P_SPI2_SCK 92 /*!< ADMA.SPI2.SCK, LSIO.GPIO1.IO03 */ +#define SC_P_SPI0_SCK 93 /*!< ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO04 */ +#define SC_P_SPI0_SDI 94 /*!< ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO1.IO05 */ +#define SC_P_SPI0_SDO 95 /*!< ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO06 */ +#define SC_P_SPI0_CS1 96 /*!< ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO1.IO07 */ +#define SC_P_SPI0_CS0 97 /*!< ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO1.IO08 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98 /*!< */ +#define SC_P_ADC_IN1 99 /*!< ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO09 */ +#define SC_P_ADC_IN0 100 /*!< ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO10 */ +#define SC_P_ADC_IN3 101 /*!< ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO1.IO11 */ +#define SC_P_ADC_IN2 102 /*!< ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO1.IO12 */ +#define SC_P_ADC_IN5 103 /*!< ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO1.IO13 */ +#define SC_P_ADC_IN4 104 /*!< ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO1.IO14 */ +#define SC_P_FLEXCAN0_RX 105 /*!< ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO1.IO15 */ +#define SC_P_FLEXCAN0_TX 106 /*!< ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO1.IO16 */ +#define SC_P_FLEXCAN1_RX 107 /*!< ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, LSIO.GPIO1.IO17 */ +#define SC_P_FLEXCAN1_TX 108 /*!< ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18 */ +#define SC_P_FLEXCAN2_RX 109 /*!< ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19 */ +#define SC_P_FLEXCAN2_TX 110 /*!< ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20 */ +#define SC_P_UART0_RX 111 /*!< ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, SCU.UART0.RX, LSIO.GPIO1.IO21 */ +#define SC_P_UART0_TX 112 /*!< ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, SCU.UART0.TX, LSIO.GPIO1.IO22 */ +#define SC_P_UART2_TX 113 /*!< ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */ +#define SC_P_UART2_RX 114 /*!< ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115 /*!< */ +#define SC_P_MIPI_DSI0_I2C0_SCL 116 /*!< MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 */ +#define SC_P_MIPI_DSI0_I2C0_SDA 117 /*!< MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 */ +#define SC_P_MIPI_DSI0_GPIO0_00 118 /*!< MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO27 */ +#define SC_P_MIPI_DSI0_GPIO0_01 119 /*!< MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */ +#define SC_P_MIPI_DSI1_I2C0_SCL 120 /*!< MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 */ +#define SC_P_MIPI_DSI1_I2C0_SDA 121 /*!< MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 */ +#define SC_P_MIPI_DSI1_GPIO0_00 122 /*!< MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO31 */ +#define SC_P_MIPI_DSI1_GPIO0_01 123 /*!< MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124 /*!< */ +#define SC_P_JTAG_TRST_B 125 /*!< SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */ +#define SC_P_PMIC_I2C_SCL 126 /*!< SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */ +#define SC_P_PMIC_I2C_SDA 127 /*!< SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */ +#define SC_P_PMIC_INT_B 128 /*!< SCU.DSC.PMIC_INT_B */ +#define SC_P_SCU_GPIO0_00 129 /*!< SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, LSIO.GPIO2.IO03 */ +#define SC_P_SCU_GPIO0_01 130 /*!< SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, SCU.WDOG0.WDOG_OUT */ +#define SC_P_SCU_PMIC_STANDBY 131 /*!< SCU.DSC.PMIC_STANDBY */ +#define SC_P_SCU_BOOT_MODE0 132 /*!< SCU.DSC.BOOT_MODE0 */ +#define SC_P_SCU_BOOT_MODE1 133 /*!< SCU.DSC.BOOT_MODE1 */ +#define SC_P_SCU_BOOT_MODE2 134 /*!< SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA */ +#define SC_P_SCU_BOOT_MODE3 135 /*!< SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, SCU.DSC.RTC_CLOCK_OUTPUT_32K */ +#define SC_P_CSI_D00 136 /*!< CI_PI.D02, ADMA.SAI0.RXC */ +#define SC_P_CSI_D01 137 /*!< CI_PI.D03, ADMA.SAI0.RXD */ +#define SC_P_CSI_D02 138 /*!< CI_PI.D04, ADMA.SAI0.RXFS */ +#define SC_P_CSI_D03 139 /*!< CI_PI.D05, ADMA.SAI2.RXC */ +#define SC_P_CSI_D04 140 /*!< CI_PI.D06, ADMA.SAI2.RXD */ +#define SC_P_CSI_D05 141 /*!< CI_PI.D07, ADMA.SAI2.RXFS */ +#define SC_P_CSI_D06 142 /*!< CI_PI.D08, ADMA.SAI3.RXC */ +#define SC_P_CSI_D07 143 /*!< CI_PI.D09, ADMA.SAI3.RXD */ +#define SC_P_CSI_HSYNC 144 /*!< CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS */ +#define SC_P_CSI_VSYNC 145 /*!< CI_PI.VSYNC, CI_PI.D01 */ +#define SC_P_CSI_PCLK 146 /*!< CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */ +#define SC_P_CSI_MCLK 147 /*!< CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */ +#define SC_P_CSI_EN 148 /*!< CI_PI.EN, CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */ +#define SC_P_CSI_RESET 149 /*!< CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150 /*!< */ +#define SC_P_MIPI_CSI0_MCLK_OUT 151 /*!< MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */ +#define SC_P_MIPI_CSI0_I2C0_SCL 152 /*!< MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 */ +#define SC_P_MIPI_CSI0_I2C0_SDA 153 /*!< MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 */ +#define SC_P_MIPI_CSI0_GPIO0_01 154 /*!< MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */ +#define SC_P_MIPI_CSI0_GPIO0_00 155 /*!< MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */ +#define SC_P_QSPI0A_DATA0 156 /*!< LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */ +#define SC_P_QSPI0A_DATA1 157 /*!< LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */ +#define SC_P_QSPI0A_DATA2 158 /*!< LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */ +#define SC_P_QSPI0A_DATA3 159 /*!< LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */ +#define SC_P_QSPI0A_DQS 160 /*!< LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */ +#define SC_P_QSPI0A_SS0_B 161 /*!< LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */ +#define SC_P_QSPI0A_SS1_B 162 /*!< LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */ +#define SC_P_QSPI0A_SCLK 163 /*!< LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164 /*!< */ +#define SC_P_QSPI0B_SCLK 165 /*!< LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */ +#define SC_P_QSPI0B_DATA0 166 /*!< LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO3.IO18 */ +#define SC_P_QSPI0B_DATA1 167 /*!< LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO3.IO19 */ +#define SC_P_QSPI0B_DATA2 168 /*!< LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */ +#define SC_P_QSPI0B_DATA3 169 /*!< LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */ +#define SC_P_QSPI0B_DQS 170 /*!< LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 */ +#define SC_P_QSPI0B_SS0_B 171 /*!< LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */ +#define SC_P_QSPI0B_SS1_B 172 /*!< LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO3.IO24 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173 /*!< */ +/*@}*/ + +/*! + * @name Pad Mux Definitions + * format: name padid padmux + */ +/*@{*/ +#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B SC_P_PCIE_CTRL0_PERST_B 0 +#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 SC_P_PCIE_CTRL0_PERST_B 4 +#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B SC_P_PCIE_CTRL0_CLKREQ_B 0 +#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 SC_P_PCIE_CTRL0_CLKREQ_B 4 +#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B SC_P_PCIE_CTRL0_WAKE_B 0 +#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 SC_P_PCIE_CTRL0_WAKE_B 4 +#define SC_P_USB_SS3_TC0_ADMA_I2C1_SCL SC_P_USB_SS3_TC0 0 +#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR SC_P_USB_SS3_TC0 1 +#define SC_P_USB_SS3_TC0_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC0 2 +#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 SC_P_USB_SS3_TC0 4 +#define SC_P_USB_SS3_TC1_ADMA_I2C1_SCL SC_P_USB_SS3_TC1 0 +#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC1 1 +#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 SC_P_USB_SS3_TC1 4 +#define SC_P_USB_SS3_TC2_ADMA_I2C1_SDA SC_P_USB_SS3_TC2 0 +#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC SC_P_USB_SS3_TC2 1 +#define SC_P_USB_SS3_TC2_CONN_USB_OTG2_OC SC_P_USB_SS3_TC2 2 +#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 SC_P_USB_SS3_TC2 4 +#define SC_P_USB_SS3_TC3_ADMA_I2C1_SDA SC_P_USB_SS3_TC3 0 +#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC SC_P_USB_SS3_TC3 1 +#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 SC_P_USB_SS3_TC3 4 +#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK SC_P_EMMC0_CLK 0 +#define SC_P_EMMC0_CLK_CONN_NAND_READY_B SC_P_EMMC0_CLK 1 +#define SC_P_EMMC0_CLK_LSIO_GPIO4_IO07 SC_P_EMMC0_CLK 4 +#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD SC_P_EMMC0_CMD 0 +#define SC_P_EMMC0_CMD_CONN_NAND_DQS SC_P_EMMC0_CMD 1 +#define SC_P_EMMC0_CMD_LSIO_GPIO4_IO08 SC_P_EMMC0_CMD 4 +#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 SC_P_EMMC0_DATA0 0 +#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00 SC_P_EMMC0_DATA0 1 +#define SC_P_EMMC0_DATA0_LSIO_GPIO4_IO09 SC_P_EMMC0_DATA0 4 +#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 SC_P_EMMC0_DATA1 0 +#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01 SC_P_EMMC0_DATA1 1 +#define SC_P_EMMC0_DATA1_LSIO_GPIO4_IO10 SC_P_EMMC0_DATA1 4 +#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 SC_P_EMMC0_DATA2 0 +#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02 SC_P_EMMC0_DATA2 1 +#define SC_P_EMMC0_DATA2_LSIO_GPIO4_IO11 SC_P_EMMC0_DATA2 4 +#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 SC_P_EMMC0_DATA3 0 +#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03 SC_P_EMMC0_DATA3 1 +#define SC_P_EMMC0_DATA3_LSIO_GPIO4_IO12 SC_P_EMMC0_DATA3 4 +#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 SC_P_EMMC0_DATA4 0 +#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04 SC_P_EMMC0_DATA4 1 +#define SC_P_EMMC0_DATA4_CONN_EMMC0_WP SC_P_EMMC0_DATA4 3 +#define SC_P_EMMC0_DATA4_LSIO_GPIO4_IO13 SC_P_EMMC0_DATA4 4 +#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 SC_P_EMMC0_DATA5 0 +#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05 SC_P_EMMC0_DATA5 1 +#define SC_P_EMMC0_DATA5_CONN_EMMC0_VSELECT SC_P_EMMC0_DATA5 3 +#define SC_P_EMMC0_DATA5_LSIO_GPIO4_IO14 SC_P_EMMC0_DATA5 4 +#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 SC_P_EMMC0_DATA6 0 +#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06 SC_P_EMMC0_DATA6 1 +#define SC_P_EMMC0_DATA6_CONN_MLB_CLK SC_P_EMMC0_DATA6 3 +#define SC_P_EMMC0_DATA6_LSIO_GPIO4_IO15 SC_P_EMMC0_DATA6 4 +#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 SC_P_EMMC0_DATA7 0 +#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07 SC_P_EMMC0_DATA7 1 +#define SC_P_EMMC0_DATA7_CONN_MLB_SIG SC_P_EMMC0_DATA7 3 +#define SC_P_EMMC0_DATA7_LSIO_GPIO4_IO16 SC_P_EMMC0_DATA7 4 +#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE SC_P_EMMC0_STROBE 0 +#define SC_P_EMMC0_STROBE_CONN_NAND_CLE SC_P_EMMC0_STROBE 1 +#define SC_P_EMMC0_STROBE_CONN_MLB_DATA SC_P_EMMC0_STROBE 3 +#define SC_P_EMMC0_STROBE_LSIO_GPIO4_IO17 SC_P_EMMC0_STROBE 4 +#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B SC_P_EMMC0_RESET_B 0 +#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B SC_P_EMMC0_RESET_B 1 +#define SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18 SC_P_EMMC0_RESET_B 4 +#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B SC_P_USDHC1_RESET_B 0 +#define SC_P_USDHC1_RESET_B_CONN_NAND_RE_N SC_P_USDHC1_RESET_B 1 +#define SC_P_USDHC1_RESET_B_ADMA_SPI2_SCK SC_P_USDHC1_RESET_B 2 +#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 SC_P_USDHC1_RESET_B 4 +#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT SC_P_USDHC1_VSELECT 0 +#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_P SC_P_USDHC1_VSELECT 1 +#define SC_P_USDHC1_VSELECT_ADMA_SPI2_SDO SC_P_USDHC1_VSELECT 2 +#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_B SC_P_USDHC1_VSELECT 3 +#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO20 SC_P_USDHC1_VSELECT 4 +#define SC_P_USDHC1_WP_CONN_USDHC1_WP SC_P_USDHC1_WP 0 +#define SC_P_USDHC1_WP_CONN_NAND_DQS_N SC_P_USDHC1_WP 1 +#define SC_P_USDHC1_WP_ADMA_SPI2_SDI SC_P_USDHC1_WP 2 +#define SC_P_USDHC1_WP_LSIO_GPIO4_IO21 SC_P_USDHC1_WP 4 +#define SC_P_USDHC1_CD_B_CONN_USDHC1_CD_B SC_P_USDHC1_CD_B 0 +#define SC_P_USDHC1_CD_B_CONN_NAND_DQS_P SC_P_USDHC1_CD_B 1 +#define SC_P_USDHC1_CD_B_ADMA_SPI2_CS0 SC_P_USDHC1_CD_B 2 +#define SC_P_USDHC1_CD_B_CONN_NAND_DQS SC_P_USDHC1_CD_B 3 +#define SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 SC_P_USDHC1_CD_B 4 +#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK SC_P_USDHC1_CLK 0 +#define SC_P_USDHC1_CLK_ADMA_UART3_RX SC_P_USDHC1_CLK 2 +#define SC_P_USDHC1_CLK_LSIO_GPIO4_IO23 SC_P_USDHC1_CLK 4 +#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD SC_P_USDHC1_CMD 0 +#define SC_P_USDHC1_CMD_CONN_NAND_CE0_B SC_P_USDHC1_CMD 1 +#define SC_P_USDHC1_CMD_ADMA_MQS_R SC_P_USDHC1_CMD 2 +#define SC_P_USDHC1_CMD_LSIO_GPIO4_IO24 SC_P_USDHC1_CMD 4 +#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 SC_P_USDHC1_DATA0 0 +#define SC_P_USDHC1_DATA0_CONN_NAND_CE1_B SC_P_USDHC1_DATA0 1 +#define SC_P_USDHC1_DATA0_ADMA_MQS_L SC_P_USDHC1_DATA0 2 +#define SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25 SC_P_USDHC1_DATA0 4 +#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 SC_P_USDHC1_DATA1 0 +#define SC_P_USDHC1_DATA1_CONN_NAND_RE_B SC_P_USDHC1_DATA1 1 +#define SC_P_USDHC1_DATA1_ADMA_UART3_TX SC_P_USDHC1_DATA1 2 +#define SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26 SC_P_USDHC1_DATA1 4 +#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 SC_P_USDHC1_DATA2 0 +#define SC_P_USDHC1_DATA2_CONN_NAND_WE_B SC_P_USDHC1_DATA2 1 +#define SC_P_USDHC1_DATA2_ADMA_UART3_CTS_B SC_P_USDHC1_DATA2 2 +#define SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27 SC_P_USDHC1_DATA2 4 +#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 SC_P_USDHC1_DATA3 0 +#define SC_P_USDHC1_DATA3_CONN_NAND_ALE SC_P_USDHC1_DATA3 1 +#define SC_P_USDHC1_DATA3_ADMA_UART3_RTS_B SC_P_USDHC1_DATA3 2 +#define SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28 SC_P_USDHC1_DATA3 4 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC SC_P_ENET0_RGMII_TXC 0 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT SC_P_ENET0_RGMII_TXC 1 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN SC_P_ENET0_RGMII_TXC 2 +#define SC_P_ENET0_RGMII_TXC_CONN_NAND_CE1_B SC_P_ENET0_RGMII_TXC 3 +#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 SC_P_ENET0_RGMII_TXC 4 +#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL SC_P_ENET0_RGMII_TX_CTL 0 +#define SC_P_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B SC_P_ENET0_RGMII_TX_CTL 3 +#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 SC_P_ENET0_RGMII_TX_CTL 4 +#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 SC_P_ENET0_RGMII_TXD0 0 +#define SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT SC_P_ENET0_RGMII_TXD0 3 +#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 SC_P_ENET0_RGMII_TXD0 4 +#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 SC_P_ENET0_RGMII_TXD1 0 +#define SC_P_ENET0_RGMII_TXD1_CONN_USDHC1_WP SC_P_ENET0_RGMII_TXD1 3 +#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 SC_P_ENET0_RGMII_TXD1 4 +#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 SC_P_ENET0_RGMII_TXD2 0 +#define SC_P_ENET0_RGMII_TXD2_CONN_MLB_CLK SC_P_ENET0_RGMII_TXD2 1 +#define SC_P_ENET0_RGMII_TXD2_CONN_NAND_CE0_B SC_P_ENET0_RGMII_TXD2 2 +#define SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B SC_P_ENET0_RGMII_TXD2 3 +#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 SC_P_ENET0_RGMII_TXD2 4 +#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 SC_P_ENET0_RGMII_TXD3 0 +#define SC_P_ENET0_RGMII_TXD3_CONN_MLB_SIG SC_P_ENET0_RGMII_TXD3 1 +#define SC_P_ENET0_RGMII_TXD3_CONN_NAND_RE_B SC_P_ENET0_RGMII_TXD3 2 +#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 SC_P_ENET0_RGMII_TXD3 4 +#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC SC_P_ENET0_RGMII_RXC 0 +#define SC_P_ENET0_RGMII_RXC_CONN_MLB_DATA SC_P_ENET0_RGMII_RXC 1 +#define SC_P_ENET0_RGMII_RXC_CONN_NAND_WE_B SC_P_ENET0_RGMII_RXC 2 +#define SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK SC_P_ENET0_RGMII_RXC 3 +#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 SC_P_ENET0_RGMII_RXC 4 +#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL SC_P_ENET0_RGMII_RX_CTL 0 +#define SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD SC_P_ENET0_RGMII_RX_CTL 3 +#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 SC_P_ENET0_RGMII_RX_CTL 4 +#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 SC_P_ENET0_RGMII_RXD0 0 +#define SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 SC_P_ENET0_RGMII_RXD0 3 +#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 SC_P_ENET0_RGMII_RXD0 4 +#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 SC_P_ENET0_RGMII_RXD1 0 +#define SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 SC_P_ENET0_RGMII_RXD1 3 +#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 SC_P_ENET0_RGMII_RXD1 4 +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 SC_P_ENET0_RGMII_RXD2 0 +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER SC_P_ENET0_RGMII_RXD2 1 +#define SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 SC_P_ENET0_RGMII_RXD2 3 +#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 SC_P_ENET0_RGMII_RXD2 4 +#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 SC_P_ENET0_RGMII_RXD3 0 +#define SC_P_ENET0_RGMII_RXD3_CONN_NAND_ALE SC_P_ENET0_RGMII_RXD3 2 +#define SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 SC_P_ENET0_RGMII_RXD3 3 +#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 SC_P_ENET0_RGMII_RXD3 4 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M SC_P_ENET0_REFCLK_125M_25M 0 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS SC_P_ENET0_REFCLK_125M_25M 1 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS SC_P_ENET0_REFCLK_125M_25M 2 +#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 SC_P_ENET0_REFCLK_125M_25M 4 +#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO SC_P_ENET0_MDIO 0 +#define SC_P_ENET0_MDIO_ADMA_I2C3_SDA SC_P_ENET0_MDIO 1 +#define SC_P_ENET0_MDIO_CONN_ENET1_MDIO SC_P_ENET0_MDIO 2 +#define SC_P_ENET0_MDIO_LSIO_GPIO5_IO10 SC_P_ENET0_MDIO 4 +#define SC_P_ENET0_MDC_CONN_ENET0_MDC SC_P_ENET0_MDC 0 +#define SC_P_ENET0_MDC_ADMA_I2C3_SCL SC_P_ENET0_MDC 1 +#define SC_P_ENET0_MDC_CONN_ENET1_MDC SC_P_ENET0_MDC 2 +#define SC_P_ENET0_MDC_LSIO_GPIO5_IO11 SC_P_ENET0_MDC 4 +#define SC_P_ESAI0_FSR_ADMA_ESAI0_FSR SC_P_ESAI0_FSR 0 +#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT SC_P_ESAI0_FSR 1 +#define SC_P_ESAI0_FSR_ADMA_LCDIF_D00 SC_P_ESAI0_FSR 2 +#define SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC SC_P_ESAI0_FSR 3 +#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN SC_P_ESAI0_FSR 4 +#define SC_P_ESAI0_FST_ADMA_ESAI0_FST SC_P_ESAI0_FST 0 +#define SC_P_ESAI0_FST_CONN_MLB_CLK SC_P_ESAI0_FST 1 +#define SC_P_ESAI0_FST_ADMA_LCDIF_D01 SC_P_ESAI0_FST 2 +#define SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 SC_P_ESAI0_FST 3 +#define SC_P_ESAI0_FST_LSIO_GPIO0_IO01 SC_P_ESAI0_FST 4 +#define SC_P_ESAI0_SCKR_ADMA_ESAI0_SCKR SC_P_ESAI0_SCKR 0 +#define SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 SC_P_ESAI0_SCKR 2 +#define SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL SC_P_ESAI0_SCKR 3 +#define SC_P_ESAI0_SCKR_LSIO_GPIO0_IO02 SC_P_ESAI0_SCKR 4 +#define SC_P_ESAI0_SCKT_ADMA_ESAI0_SCKT SC_P_ESAI0_SCKT 0 +#define SC_P_ESAI0_SCKT_CONN_MLB_SIG SC_P_ESAI0_SCKT 1 +#define SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 SC_P_ESAI0_SCKT 2 +#define SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 SC_P_ESAI0_SCKT 3 +#define SC_P_ESAI0_SCKT_LSIO_GPIO0_IO03 SC_P_ESAI0_SCKT 4 +#define SC_P_ESAI0_TX0_ADMA_ESAI0_TX0 SC_P_ESAI0_TX0 0 +#define SC_P_ESAI0_TX0_CONN_MLB_DATA SC_P_ESAI0_TX0 1 +#define SC_P_ESAI0_TX0_ADMA_LCDIF_D04 SC_P_ESAI0_TX0 2 +#define SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC SC_P_ESAI0_TX0 3 +#define SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 SC_P_ESAI0_TX0 4 +#define SC_P_ESAI0_TX1_ADMA_ESAI0_TX1 SC_P_ESAI0_TX1 0 +#define SC_P_ESAI0_TX1_ADMA_LCDIF_D05 SC_P_ESAI0_TX1 2 +#define SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 SC_P_ESAI0_TX1 3 +#define SC_P_ESAI0_TX1_LSIO_GPIO0_IO05 SC_P_ESAI0_TX1 4 +#define SC_P_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 SC_P_ESAI0_TX2_RX3 0 +#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER SC_P_ESAI0_TX2_RX3 1 +#define SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 SC_P_ESAI0_TX2_RX3 2 +#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 SC_P_ESAI0_TX2_RX3 3 +#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 SC_P_ESAI0_TX2_RX3 4 +#define SC_P_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 SC_P_ESAI0_TX3_RX2 0 +#define SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 SC_P_ESAI0_TX3_RX2 2 +#define SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 SC_P_ESAI0_TX3_RX2 3 +#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 SC_P_ESAI0_TX3_RX2 4 +#define SC_P_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 SC_P_ESAI0_TX4_RX1 0 +#define SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 SC_P_ESAI0_TX4_RX1 2 +#define SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 SC_P_ESAI0_TX4_RX1 3 +#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO0_IO08 SC_P_ESAI0_TX4_RX1 4 +#define SC_P_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 SC_P_ESAI0_TX5_RX0 0 +#define SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 SC_P_ESAI0_TX5_RX0 2 +#define SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 SC_P_ESAI0_TX5_RX0 3 +#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO0_IO09 SC_P_ESAI0_TX5_RX0 4 +#define SC_P_SPDIF0_RX_ADMA_SPDIF0_RX SC_P_SPDIF0_RX 0 +#define SC_P_SPDIF0_RX_ADMA_MQS_R SC_P_SPDIF0_RX 1 +#define SC_P_SPDIF0_RX_ADMA_LCDIF_D10 SC_P_SPDIF0_RX 2 +#define SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 SC_P_SPDIF0_RX 3 +#define SC_P_SPDIF0_RX_LSIO_GPIO0_IO10 SC_P_SPDIF0_RX 4 +#define SC_P_SPDIF0_TX_ADMA_SPDIF0_TX SC_P_SPDIF0_TX 0 +#define SC_P_SPDIF0_TX_ADMA_MQS_L SC_P_SPDIF0_TX 1 +#define SC_P_SPDIF0_TX_ADMA_LCDIF_D11 SC_P_SPDIF0_TX 2 +#define SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL SC_P_SPDIF0_TX 3 +#define SC_P_SPDIF0_TX_LSIO_GPIO0_IO11 SC_P_SPDIF0_TX 4 +#define SC_P_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK SC_P_SPDIF0_EXT_CLK 0 +#define SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 SC_P_SPDIF0_EXT_CLK 2 +#define SC_P_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M SC_P_SPDIF0_EXT_CLK 3 +#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 SC_P_SPDIF0_EXT_CLK 4 +#define SC_P_SPI3_SCK_ADMA_SPI3_SCK SC_P_SPI3_SCK 0 +#define SC_P_SPI3_SCK_ADMA_LCDIF_D13 SC_P_SPI3_SCK 2 +#define SC_P_SPI3_SCK_LSIO_GPIO0_IO13 SC_P_SPI3_SCK 4 +#define SC_P_SPI3_SDO_ADMA_SPI3_SDO SC_P_SPI3_SDO 0 +#define SC_P_SPI3_SDO_ADMA_LCDIF_D14 SC_P_SPI3_SDO 2 +#define SC_P_SPI3_SDO_LSIO_GPIO0_IO14 SC_P_SPI3_SDO 4 +#define SC_P_SPI3_SDI_ADMA_SPI3_SDI SC_P_SPI3_SDI 0 +#define SC_P_SPI3_SDI_ADMA_LCDIF_D15 SC_P_SPI3_SDI 2 +#define SC_P_SPI3_SDI_LSIO_GPIO0_IO15 SC_P_SPI3_SDI 4 +#define SC_P_SPI3_CS0_ADMA_SPI3_CS0 SC_P_SPI3_CS0 0 +#define SC_P_SPI3_CS0_ADMA_ACM_MCLK_OUT1 SC_P_SPI3_CS0 1 +#define SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC SC_P_SPI3_CS0 2 +#define SC_P_SPI3_CS0_LSIO_GPIO0_IO16 SC_P_SPI3_CS0 4 +#define SC_P_SPI3_CS1_ADMA_SPI3_CS1 SC_P_SPI3_CS1 0 +#define SC_P_SPI3_CS1_ADMA_I2C3_SCL SC_P_SPI3_CS1 1 +#define SC_P_SPI3_CS1_ADMA_LCDIF_RESET SC_P_SPI3_CS1 2 +#define SC_P_SPI3_CS1_ADMA_SPI2_CS0 SC_P_SPI3_CS1 3 +#define SC_P_SPI3_CS1_ADMA_LCDIF_D16 SC_P_SPI3_CS1 4 +#define SC_P_MCLK_IN1_ADMA_ACM_MCLK_IN1 SC_P_MCLK_IN1 0 +#define SC_P_MCLK_IN1_ADMA_I2C3_SDA SC_P_MCLK_IN1 1 +#define SC_P_MCLK_IN1_ADMA_LCDIF_EN SC_P_MCLK_IN1 2 +#define SC_P_MCLK_IN1_ADMA_SPI2_SCK SC_P_MCLK_IN1 3 +#define SC_P_MCLK_IN1_ADMA_LCDIF_D17 SC_P_MCLK_IN1 4 +#define SC_P_MCLK_IN0_ADMA_ACM_MCLK_IN0 SC_P_MCLK_IN0 0 +#define SC_P_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK SC_P_MCLK_IN0 1 +#define SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC SC_P_MCLK_IN0 2 +#define SC_P_MCLK_IN0_ADMA_SPI2_SDI SC_P_MCLK_IN0 3 +#define SC_P_MCLK_IN0_LSIO_GPIO0_IO19 SC_P_MCLK_IN0 4 +#define SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 SC_P_MCLK_OUT0 0 +#define SC_P_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK SC_P_MCLK_OUT0 1 +#define SC_P_MCLK_OUT0_ADMA_LCDIF_CLK SC_P_MCLK_OUT0 2 +#define SC_P_MCLK_OUT0_ADMA_SPI2_SDO SC_P_MCLK_OUT0 3 +#define SC_P_MCLK_OUT0_LSIO_GPIO0_IO20 SC_P_MCLK_OUT0 4 +#define SC_P_UART1_TX_ADMA_UART1_TX SC_P_UART1_TX 0 +#define SC_P_UART1_TX_LSIO_PWM0_OUT SC_P_UART1_TX 1 +#define SC_P_UART1_TX_LSIO_GPT0_CAPTURE SC_P_UART1_TX 2 +#define SC_P_UART1_TX_LSIO_GPIO0_IO21 SC_P_UART1_TX 4 +#define SC_P_UART1_RX_ADMA_UART1_RX SC_P_UART1_RX 0 +#define SC_P_UART1_RX_LSIO_PWM1_OUT SC_P_UART1_RX 1 +#define SC_P_UART1_RX_LSIO_GPT0_COMPARE SC_P_UART1_RX 2 +#define SC_P_UART1_RX_LSIO_GPT1_CLK SC_P_UART1_RX 3 +#define SC_P_UART1_RX_LSIO_GPIO0_IO22 SC_P_UART1_RX 4 +#define SC_P_UART1_RTS_B_ADMA_UART1_RTS_B SC_P_UART1_RTS_B 0 +#define SC_P_UART1_RTS_B_LSIO_PWM2_OUT SC_P_UART1_RTS_B 1 +#define SC_P_UART1_RTS_B_ADMA_LCDIF_D16 SC_P_UART1_RTS_B 2 +#define SC_P_UART1_RTS_B_LSIO_GPT1_CAPTURE SC_P_UART1_RTS_B 3 +#define SC_P_UART1_RTS_B_LSIO_GPT0_CLK SC_P_UART1_RTS_B 4 +#define SC_P_UART1_CTS_B_ADMA_UART1_CTS_B SC_P_UART1_CTS_B 0 +#define SC_P_UART1_CTS_B_LSIO_PWM3_OUT SC_P_UART1_CTS_B 1 +#define SC_P_UART1_CTS_B_ADMA_LCDIF_D17 SC_P_UART1_CTS_B 2 +#define SC_P_UART1_CTS_B_LSIO_GPT1_COMPARE SC_P_UART1_CTS_B 3 +#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO24 SC_P_UART1_CTS_B 4 +#define SC_P_SAI0_TXD_ADMA_SAI0_TXD SC_P_SAI0_TXD 0 +#define SC_P_SAI0_TXD_ADMA_SAI1_RXC SC_P_SAI0_TXD 1 +#define SC_P_SAI0_TXD_ADMA_SPI1_SDO SC_P_SAI0_TXD 2 +#define SC_P_SAI0_TXD_ADMA_LCDIF_D18 SC_P_SAI0_TXD 3 +#define SC_P_SAI0_TXD_LSIO_GPIO0_IO25 SC_P_SAI0_TXD 4 +#define SC_P_SAI0_TXC_ADMA_SAI0_TXC SC_P_SAI0_TXC 0 +#define SC_P_SAI0_TXC_ADMA_SAI1_TXD SC_P_SAI0_TXC 1 +#define SC_P_SAI0_TXC_ADMA_SPI1_SDI SC_P_SAI0_TXC 2 +#define SC_P_SAI0_TXC_ADMA_LCDIF_D19 SC_P_SAI0_TXC 3 +#define SC_P_SAI0_TXC_LSIO_GPIO0_IO26 SC_P_SAI0_TXC 4 +#define SC_P_SAI0_RXD_ADMA_SAI0_RXD SC_P_SAI0_RXD 0 +#define SC_P_SAI0_RXD_ADMA_SAI1_RXFS SC_P_SAI0_RXD 1 +#define SC_P_SAI0_RXD_ADMA_SPI1_CS0 SC_P_SAI0_RXD 2 +#define SC_P_SAI0_RXD_ADMA_LCDIF_D20 SC_P_SAI0_RXD 3 +#define SC_P_SAI0_RXD_LSIO_GPIO0_IO27 SC_P_SAI0_RXD 4 +#define SC_P_SAI0_TXFS_ADMA_SAI0_TXFS SC_P_SAI0_TXFS 0 +#define SC_P_SAI0_TXFS_ADMA_SPI2_CS1 SC_P_SAI0_TXFS 1 +#define SC_P_SAI0_TXFS_ADMA_SPI1_SCK SC_P_SAI0_TXFS 2 +#define SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 SC_P_SAI0_TXFS 4 +#define SC_P_SAI1_RXD_ADMA_SAI1_RXD SC_P_SAI1_RXD 0 +#define SC_P_SAI1_RXD_ADMA_SAI0_RXFS SC_P_SAI1_RXD 1 +#define SC_P_SAI1_RXD_ADMA_SPI1_CS1 SC_P_SAI1_RXD 2 +#define SC_P_SAI1_RXD_ADMA_LCDIF_D21 SC_P_SAI1_RXD 3 +#define SC_P_SAI1_RXD_LSIO_GPIO0_IO29 SC_P_SAI1_RXD 4 +#define SC_P_SAI1_RXC_ADMA_SAI1_RXC SC_P_SAI1_RXC 0 +#define SC_P_SAI1_RXC_ADMA_SAI1_TXC SC_P_SAI1_RXC 1 +#define SC_P_SAI1_RXC_ADMA_LCDIF_D22 SC_P_SAI1_RXC 3 +#define SC_P_SAI1_RXC_LSIO_GPIO0_IO30 SC_P_SAI1_RXC 4 +#define SC_P_SAI1_RXFS_ADMA_SAI1_RXFS SC_P_SAI1_RXFS 0 +#define SC_P_SAI1_RXFS_ADMA_SAI1_TXFS SC_P_SAI1_RXFS 1 +#define SC_P_SAI1_RXFS_ADMA_LCDIF_D23 SC_P_SAI1_RXFS 3 +#define SC_P_SAI1_RXFS_LSIO_GPIO0_IO31 SC_P_SAI1_RXFS 4 +#define SC_P_SPI2_CS0_ADMA_SPI2_CS0 SC_P_SPI2_CS0 0 +#define SC_P_SPI2_CS0_LSIO_GPIO1_IO00 SC_P_SPI2_CS0 4 +#define SC_P_SPI2_SDO_ADMA_SPI2_SDO SC_P_SPI2_SDO 0 +#define SC_P_SPI2_SDO_LSIO_GPIO1_IO01 SC_P_SPI2_SDO 4 +#define SC_P_SPI2_SDI_ADMA_SPI2_SDI SC_P_SPI2_SDI 0 +#define SC_P_SPI2_SDI_LSIO_GPIO1_IO02 SC_P_SPI2_SDI 4 +#define SC_P_SPI2_SCK_ADMA_SPI2_SCK SC_P_SPI2_SCK 0 +#define SC_P_SPI2_SCK_LSIO_GPIO1_IO03 SC_P_SPI2_SCK 4 +#define SC_P_SPI0_SCK_ADMA_SPI0_SCK SC_P_SPI0_SCK 0 +#define SC_P_SPI0_SCK_ADMA_SAI0_TXC SC_P_SPI0_SCK 1 +#define SC_P_SPI0_SCK_M40_I2C0_SCL SC_P_SPI0_SCK 2 +#define SC_P_SPI0_SCK_M40_GPIO0_IO00 SC_P_SPI0_SCK 3 +#define SC_P_SPI0_SCK_LSIO_GPIO1_IO04 SC_P_SPI0_SCK 4 +#define SC_P_SPI0_SDI_ADMA_SPI0_SDI SC_P_SPI0_SDI 0 +#define SC_P_SPI0_SDI_ADMA_SAI0_TXD SC_P_SPI0_SDI 1 +#define SC_P_SPI0_SDI_M40_TPM0_CH0 SC_P_SPI0_SDI 2 +#define SC_P_SPI0_SDI_M40_GPIO0_IO02 SC_P_SPI0_SDI 3 +#define SC_P_SPI0_SDI_LSIO_GPIO1_IO05 SC_P_SPI0_SDI 4 +#define SC_P_SPI0_SDO_ADMA_SPI0_SDO SC_P_SPI0_SDO 0 +#define SC_P_SPI0_SDO_ADMA_SAI0_TXFS SC_P_SPI0_SDO 1 +#define SC_P_SPI0_SDO_M40_I2C0_SDA SC_P_SPI0_SDO 2 +#define SC_P_SPI0_SDO_M40_GPIO0_IO01 SC_P_SPI0_SDO 3 +#define SC_P_SPI0_SDO_LSIO_GPIO1_IO06 SC_P_SPI0_SDO 4 +#define SC_P_SPI0_CS1_ADMA_SPI0_CS1 SC_P_SPI0_CS1 0 +#define SC_P_SPI0_CS1_ADMA_SAI0_RXC SC_P_SPI0_CS1 1 +#define SC_P_SPI0_CS1_ADMA_SAI1_TXD SC_P_SPI0_CS1 2 +#define SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT SC_P_SPI0_CS1 3 +#define SC_P_SPI0_CS1_LSIO_GPIO1_IO07 SC_P_SPI0_CS1 4 +#define SC_P_SPI0_CS0_ADMA_SPI0_CS0 SC_P_SPI0_CS0 0 +#define SC_P_SPI0_CS0_ADMA_SAI0_RXD SC_P_SPI0_CS0 1 +#define SC_P_SPI0_CS0_M40_TPM0_CH1 SC_P_SPI0_CS0 2 +#define SC_P_SPI0_CS0_M40_GPIO0_IO03 SC_P_SPI0_CS0 3 +#define SC_P_SPI0_CS0_LSIO_GPIO1_IO08 SC_P_SPI0_CS0 4 +#define SC_P_ADC_IN1_ADMA_ADC_IN1 SC_P_ADC_IN1 0 +#define SC_P_ADC_IN1_M40_I2C0_SDA SC_P_ADC_IN1 1 +#define SC_P_ADC_IN1_M40_GPIO0_IO01 SC_P_ADC_IN1 2 +#define SC_P_ADC_IN1_LSIO_GPIO1_IO09 SC_P_ADC_IN1 4 +#define SC_P_ADC_IN0_ADMA_ADC_IN0 SC_P_ADC_IN0 0 +#define SC_P_ADC_IN0_M40_I2C0_SCL SC_P_ADC_IN0 1 +#define SC_P_ADC_IN0_M40_GPIO0_IO00 SC_P_ADC_IN0 2 +#define SC_P_ADC_IN0_LSIO_GPIO1_IO10 SC_P_ADC_IN0 4 +#define SC_P_ADC_IN3_ADMA_ADC_IN3 SC_P_ADC_IN3 0 +#define SC_P_ADC_IN3_M40_UART0_TX SC_P_ADC_IN3 1 +#define SC_P_ADC_IN3_M40_GPIO0_IO03 SC_P_ADC_IN3 2 +#define SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0 SC_P_ADC_IN3 3 +#define SC_P_ADC_IN3_LSIO_GPIO1_IO11 SC_P_ADC_IN3 4 +#define SC_P_ADC_IN2_ADMA_ADC_IN2 SC_P_ADC_IN2 0 +#define SC_P_ADC_IN2_M40_UART0_RX SC_P_ADC_IN2 1 +#define SC_P_ADC_IN2_M40_GPIO0_IO02 SC_P_ADC_IN2 2 +#define SC_P_ADC_IN2_ADMA_ACM_MCLK_IN0 SC_P_ADC_IN2 3 +#define SC_P_ADC_IN2_LSIO_GPIO1_IO12 SC_P_ADC_IN2 4 +#define SC_P_ADC_IN5_ADMA_ADC_IN5 SC_P_ADC_IN5 0 +#define SC_P_ADC_IN5_M40_TPM0_CH1 SC_P_ADC_IN5 1 +#define SC_P_ADC_IN5_M40_GPIO0_IO05 SC_P_ADC_IN5 2 +#define SC_P_ADC_IN5_LSIO_GPIO1_IO13 SC_P_ADC_IN5 4 +#define SC_P_ADC_IN4_ADMA_ADC_IN4 SC_P_ADC_IN4 0 +#define SC_P_ADC_IN4_M40_TPM0_CH0 SC_P_ADC_IN4 1 +#define SC_P_ADC_IN4_M40_GPIO0_IO04 SC_P_ADC_IN4 2 +#define SC_P_ADC_IN4_LSIO_GPIO1_IO14 SC_P_ADC_IN4 4 +#define SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX SC_P_FLEXCAN0_RX 0 +#define SC_P_FLEXCAN0_RX_ADMA_SAI2_RXC SC_P_FLEXCAN0_RX 1 +#define SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B SC_P_FLEXCAN0_RX 2 +#define SC_P_FLEXCAN0_RX_ADMA_SAI1_TXC SC_P_FLEXCAN0_RX 3 +#define SC_P_FLEXCAN0_RX_LSIO_GPIO1_IO15 SC_P_FLEXCAN0_RX 4 +#define SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX SC_P_FLEXCAN0_TX 0 +#define SC_P_FLEXCAN0_TX_ADMA_SAI2_RXD SC_P_FLEXCAN0_TX 1 +#define SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B SC_P_FLEXCAN0_TX 2 +#define SC_P_FLEXCAN0_TX_ADMA_SAI1_TXFS SC_P_FLEXCAN0_TX 3 +#define SC_P_FLEXCAN0_TX_LSIO_GPIO1_IO16 SC_P_FLEXCAN0_TX 4 +#define SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX SC_P_FLEXCAN1_RX 0 +#define SC_P_FLEXCAN1_RX_ADMA_SAI2_RXFS SC_P_FLEXCAN1_RX 1 +#define SC_P_FLEXCAN1_RX_ADMA_FTM_CH2 SC_P_FLEXCAN1_RX 2 +#define SC_P_FLEXCAN1_RX_ADMA_SAI1_TXD SC_P_FLEXCAN1_RX 3 +#define SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 SC_P_FLEXCAN1_RX 4 +#define SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX SC_P_FLEXCAN1_TX 0 +#define SC_P_FLEXCAN1_TX_ADMA_SAI3_RXC SC_P_FLEXCAN1_TX 1 +#define SC_P_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 SC_P_FLEXCAN1_TX 2 +#define SC_P_FLEXCAN1_TX_ADMA_SAI1_RXD SC_P_FLEXCAN1_TX 3 +#define SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 SC_P_FLEXCAN1_TX 4 +#define SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX SC_P_FLEXCAN2_RX 0 +#define SC_P_FLEXCAN2_RX_ADMA_SAI3_RXD SC_P_FLEXCAN2_RX 1 +#define SC_P_FLEXCAN2_RX_ADMA_UART3_RX SC_P_FLEXCAN2_RX 2 +#define SC_P_FLEXCAN2_RX_ADMA_SAI1_RXFS SC_P_FLEXCAN2_RX 3 +#define SC_P_FLEXCAN2_RX_LSIO_GPIO1_IO19 SC_P_FLEXCAN2_RX 4 +#define SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX SC_P_FLEXCAN2_TX 0 +#define SC_P_FLEXCAN2_TX_ADMA_SAI3_RXFS SC_P_FLEXCAN2_TX 1 +#define SC_P_FLEXCAN2_TX_ADMA_UART3_TX SC_P_FLEXCAN2_TX 2 +#define SC_P_FLEXCAN2_TX_ADMA_SAI1_RXC SC_P_FLEXCAN2_TX 3 +#define SC_P_FLEXCAN2_TX_LSIO_GPIO1_IO20 SC_P_FLEXCAN2_TX 4 +#define SC_P_UART0_RX_ADMA_UART0_RX SC_P_UART0_RX 0 +#define SC_P_UART0_RX_ADMA_MQS_R SC_P_UART0_RX 1 +#define SC_P_UART0_RX_ADMA_FLEXCAN0_RX SC_P_UART0_RX 2 +#define SC_P_UART0_RX_SCU_UART0_RX SC_P_UART0_RX 3 +#define SC_P_UART0_RX_LSIO_GPIO1_IO21 SC_P_UART0_RX 4 +#define SC_P_UART0_TX_ADMA_UART0_TX SC_P_UART0_TX 0 +#define SC_P_UART0_TX_ADMA_MQS_L SC_P_UART0_TX 1 +#define SC_P_UART0_TX_ADMA_FLEXCAN0_TX SC_P_UART0_TX 2 +#define SC_P_UART0_TX_SCU_UART0_TX SC_P_UART0_TX 3 +#define SC_P_UART0_TX_LSIO_GPIO1_IO22 SC_P_UART0_TX 4 +#define SC_P_UART2_TX_ADMA_UART2_TX SC_P_UART2_TX 0 +#define SC_P_UART2_TX_ADMA_FTM_CH1 SC_P_UART2_TX 1 +#define SC_P_UART2_TX_ADMA_FLEXCAN1_TX SC_P_UART2_TX 2 +#define SC_P_UART2_TX_LSIO_GPIO1_IO23 SC_P_UART2_TX 4 +#define SC_P_UART2_RX_ADMA_UART2_RX SC_P_UART2_RX 0 +#define SC_P_UART2_RX_ADMA_FTM_CH0 SC_P_UART2_RX 1 +#define SC_P_UART2_RX_ADMA_FLEXCAN1_RX SC_P_UART2_RX 2 +#define SC_P_UART2_RX_LSIO_GPIO1_IO24 SC_P_UART2_RX 4 +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL SC_P_MIPI_DSI0_I2C0_SCL 0 +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02 SC_P_MIPI_DSI0_I2C0_SCL 1 +#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 SC_P_MIPI_DSI0_I2C0_SCL 4 +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA SC_P_MIPI_DSI0_I2C0_SDA 0 +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03 SC_P_MIPI_DSI0_I2C0_SDA 1 +#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 SC_P_MIPI_DSI0_I2C0_SDA 4 +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 SC_P_MIPI_DSI0_GPIO0_00 0 +#define SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL SC_P_MIPI_DSI0_GPIO0_00 1 +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT SC_P_MIPI_DSI0_GPIO0_00 2 +#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 SC_P_MIPI_DSI0_GPIO0_00 4 +#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 SC_P_MIPI_DSI0_GPIO0_01 0 +#define SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA SC_P_MIPI_DSI0_GPIO0_01 1 +#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 SC_P_MIPI_DSI0_GPIO0_01 4 +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL SC_P_MIPI_DSI1_I2C0_SCL 0 +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02 SC_P_MIPI_DSI1_I2C0_SCL 1 +#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29 SC_P_MIPI_DSI1_I2C0_SCL 4 +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA SC_P_MIPI_DSI1_I2C0_SDA 0 +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03 SC_P_MIPI_DSI1_I2C0_SDA 1 +#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 SC_P_MIPI_DSI1_I2C0_SDA 4 +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 SC_P_MIPI_DSI1_GPIO0_00 0 +#define SC_P_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL SC_P_MIPI_DSI1_GPIO0_00 1 +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT SC_P_MIPI_DSI1_GPIO0_00 2 +#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 SC_P_MIPI_DSI1_GPIO0_00 4 +#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 SC_P_MIPI_DSI1_GPIO0_01 0 +#define SC_P_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA SC_P_MIPI_DSI1_GPIO0_01 1 +#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 SC_P_MIPI_DSI1_GPIO0_01 4 +#define SC_P_JTAG_TRST_B_SCU_JTAG_TRST_B SC_P_JTAG_TRST_B 0 +#define SC_P_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT SC_P_JTAG_TRST_B 1 +#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL SC_P_PMIC_I2C_SCL 0 +#define SC_P_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON SC_P_PMIC_I2C_SCL 1 +#define SC_P_PMIC_I2C_SCL_LSIO_GPIO2_IO01 SC_P_PMIC_I2C_SCL 4 +#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA SC_P_PMIC_I2C_SDA 0 +#define SC_P_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON SC_P_PMIC_I2C_SDA 1 +#define SC_P_PMIC_I2C_SDA_LSIO_GPIO2_IO02 SC_P_PMIC_I2C_SDA 4 +#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B SC_P_PMIC_INT_B 0 +#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00 SC_P_SCU_GPIO0_00 0 +#define SC_P_SCU_GPIO0_00_SCU_UART0_RX SC_P_SCU_GPIO0_00 1 +#define SC_P_SCU_GPIO0_00_M40_UART0_RX SC_P_SCU_GPIO0_00 2 +#define SC_P_SCU_GPIO0_00_ADMA_UART3_RX SC_P_SCU_GPIO0_00 3 +#define SC_P_SCU_GPIO0_00_LSIO_GPIO2_IO03 SC_P_SCU_GPIO0_00 4 +#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01 SC_P_SCU_GPIO0_01 0 +#define SC_P_SCU_GPIO0_01_SCU_UART0_TX SC_P_SCU_GPIO0_01 1 +#define SC_P_SCU_GPIO0_01_M40_UART0_TX SC_P_SCU_GPIO0_01 2 +#define SC_P_SCU_GPIO0_01_ADMA_UART3_TX SC_P_SCU_GPIO0_01 3 +#define SC_P_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT SC_P_SCU_GPIO0_01 4 +#define SC_P_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY SC_P_SCU_PMIC_STANDBY 0 +#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 SC_P_SCU_BOOT_MODE0 0 +#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 SC_P_SCU_BOOT_MODE1 0 +#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 SC_P_SCU_BOOT_MODE2 0 +#define SC_P_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA SC_P_SCU_BOOT_MODE2 1 +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 SC_P_SCU_BOOT_MODE3 0 +#define SC_P_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL SC_P_SCU_BOOT_MODE3 1 +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K SC_P_SCU_BOOT_MODE3 3 +#define SC_P_CSI_D00_CI_PI_D02 SC_P_CSI_D00 0 +#define SC_P_CSI_D00_ADMA_SAI0_RXC SC_P_CSI_D00 2 +#define SC_P_CSI_D01_CI_PI_D03 SC_P_CSI_D01 0 +#define SC_P_CSI_D01_ADMA_SAI0_RXD SC_P_CSI_D01 2 +#define SC_P_CSI_D02_CI_PI_D04 SC_P_CSI_D02 0 +#define SC_P_CSI_D02_ADMA_SAI0_RXFS SC_P_CSI_D02 2 +#define SC_P_CSI_D03_CI_PI_D05 SC_P_CSI_D03 0 +#define SC_P_CSI_D03_ADMA_SAI2_RXC SC_P_CSI_D03 2 +#define SC_P_CSI_D04_CI_PI_D06 SC_P_CSI_D04 0 +#define SC_P_CSI_D04_ADMA_SAI2_RXD SC_P_CSI_D04 2 +#define SC_P_CSI_D05_CI_PI_D07 SC_P_CSI_D05 0 +#define SC_P_CSI_D05_ADMA_SAI2_RXFS SC_P_CSI_D05 2 +#define SC_P_CSI_D06_CI_PI_D08 SC_P_CSI_D06 0 +#define SC_P_CSI_D06_ADMA_SAI3_RXC SC_P_CSI_D06 2 +#define SC_P_CSI_D07_CI_PI_D09 SC_P_CSI_D07 0 +#define SC_P_CSI_D07_ADMA_SAI3_RXD SC_P_CSI_D07 2 +#define SC_P_CSI_HSYNC_CI_PI_HSYNC SC_P_CSI_HSYNC 0 +#define SC_P_CSI_HSYNC_CI_PI_D00 SC_P_CSI_HSYNC 1 +#define SC_P_CSI_HSYNC_ADMA_SAI3_RXFS SC_P_CSI_HSYNC 2 +#define SC_P_CSI_VSYNC_CI_PI_VSYNC SC_P_CSI_VSYNC 0 +#define SC_P_CSI_VSYNC_CI_PI_D01 SC_P_CSI_VSYNC 1 +#define SC_P_CSI_PCLK_CI_PI_PCLK SC_P_CSI_PCLK 0 +#define SC_P_CSI_PCLK_MIPI_CSI0_I2C0_SCL SC_P_CSI_PCLK 1 +#define SC_P_CSI_PCLK_ADMA_SPI1_SCK SC_P_CSI_PCLK 3 +#define SC_P_CSI_PCLK_LSIO_GPIO3_IO00 SC_P_CSI_PCLK 4 +#define SC_P_CSI_MCLK_CI_PI_MCLK SC_P_CSI_MCLK 0 +#define SC_P_CSI_MCLK_MIPI_CSI0_I2C0_SDA SC_P_CSI_MCLK 1 +#define SC_P_CSI_MCLK_ADMA_SPI1_SDO SC_P_CSI_MCLK 3 +#define SC_P_CSI_MCLK_LSIO_GPIO3_IO01 SC_P_CSI_MCLK 4 +#define SC_P_CSI_EN_CI_PI_EN SC_P_CSI_EN 0 +#define SC_P_CSI_EN_CI_PI_I2C_SCL SC_P_CSI_EN 1 +#define SC_P_CSI_EN_ADMA_I2C3_SCL SC_P_CSI_EN 2 +#define SC_P_CSI_EN_ADMA_SPI1_SDI SC_P_CSI_EN 3 +#define SC_P_CSI_EN_LSIO_GPIO3_IO02 SC_P_CSI_EN 4 +#define SC_P_CSI_RESET_CI_PI_RESET SC_P_CSI_RESET 0 +#define SC_P_CSI_RESET_CI_PI_I2C_SDA SC_P_CSI_RESET 1 +#define SC_P_CSI_RESET_ADMA_I2C3_SDA SC_P_CSI_RESET 2 +#define SC_P_CSI_RESET_ADMA_SPI1_CS0 SC_P_CSI_RESET 3 +#define SC_P_CSI_RESET_LSIO_GPIO3_IO03 SC_P_CSI_RESET 4 +#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT SC_P_MIPI_CSI0_MCLK_OUT 0 +#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 SC_P_MIPI_CSI0_MCLK_OUT 4 +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL SC_P_MIPI_CSI0_I2C0_SCL 0 +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02 SC_P_MIPI_CSI0_I2C0_SCL 1 +#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 SC_P_MIPI_CSI0_I2C0_SCL 4 +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA SC_P_MIPI_CSI0_I2C0_SDA 0 +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03 SC_P_MIPI_CSI0_I2C0_SDA 1 +#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 SC_P_MIPI_CSI0_I2C0_SDA 4 +#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 SC_P_MIPI_CSI0_GPIO0_01 0 +#define SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 1 +#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 SC_P_MIPI_CSI0_GPIO0_01 4 +#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 SC_P_MIPI_CSI0_GPIO0_00 0 +#define SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 1 +#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 SC_P_MIPI_CSI0_GPIO0_00 4 +#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 SC_P_QSPI0A_DATA0 0 +#define SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 SC_P_QSPI0A_DATA0 4 +#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 SC_P_QSPI0A_DATA1 0 +#define SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 SC_P_QSPI0A_DATA1 4 +#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 SC_P_QSPI0A_DATA2 0 +#define SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 SC_P_QSPI0A_DATA2 4 +#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 SC_P_QSPI0A_DATA3 0 +#define SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 SC_P_QSPI0A_DATA3 4 +#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS SC_P_QSPI0A_DQS 0 +#define SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 SC_P_QSPI0A_DQS 4 +#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B SC_P_QSPI0A_SS0_B 0 +#define SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 SC_P_QSPI0A_SS0_B 4 +#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B SC_P_QSPI0A_SS1_B 0 +#define SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 SC_P_QSPI0A_SS1_B 4 +#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK SC_P_QSPI0A_SCLK 0 +#define SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 SC_P_QSPI0A_SCLK 4 +#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK SC_P_QSPI0B_SCLK 0 +#define SC_P_QSPI0B_SCLK_LSIO_QSPI1A_SCLK SC_P_QSPI0B_SCLK 1 +#define SC_P_QSPI0B_SCLK_LSIO_KPP0_COL0 SC_P_QSPI0B_SCLK 2 +#define SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 SC_P_QSPI0B_SCLK 4 +#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 SC_P_QSPI0B_DATA0 0 +#define SC_P_QSPI0B_DATA0_LSIO_QSPI1A_DATA0 SC_P_QSPI0B_DATA0 1 +#define SC_P_QSPI0B_DATA0_LSIO_KPP0_COL1 SC_P_QSPI0B_DATA0 2 +#define SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 SC_P_QSPI0B_DATA0 4 +#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 SC_P_QSPI0B_DATA1 0 +#define SC_P_QSPI0B_DATA1_LSIO_QSPI1A_DATA1 SC_P_QSPI0B_DATA1 1 +#define SC_P_QSPI0B_DATA1_LSIO_KPP0_COL2 SC_P_QSPI0B_DATA1 2 +#define SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 SC_P_QSPI0B_DATA1 4 +#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 SC_P_QSPI0B_DATA2 0 +#define SC_P_QSPI0B_DATA2_LSIO_QSPI1A_DATA2 SC_P_QSPI0B_DATA2 1 +#define SC_P_QSPI0B_DATA2_LSIO_KPP0_COL3 SC_P_QSPI0B_DATA2 2 +#define SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 SC_P_QSPI0B_DATA2 4 +#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 SC_P_QSPI0B_DATA3 0 +#define SC_P_QSPI0B_DATA3_LSIO_QSPI1A_DATA3 SC_P_QSPI0B_DATA3 1 +#define SC_P_QSPI0B_DATA3_LSIO_KPP0_ROW0 SC_P_QSPI0B_DATA3 2 +#define SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 SC_P_QSPI0B_DATA3 4 +#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS SC_P_QSPI0B_DQS 0 +#define SC_P_QSPI0B_DQS_LSIO_QSPI1A_DQS SC_P_QSPI0B_DQS 1 +#define SC_P_QSPI0B_DQS_LSIO_KPP0_ROW1 SC_P_QSPI0B_DQS 2 +#define SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 SC_P_QSPI0B_DQS 4 +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B SC_P_QSPI0B_SS0_B 0 +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B SC_P_QSPI0B_SS0_B 1 +#define SC_P_QSPI0B_SS0_B_LSIO_KPP0_ROW2 SC_P_QSPI0B_SS0_B 2 +#define SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 SC_P_QSPI0B_SS0_B 4 +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B SC_P_QSPI0B_SS1_B 0 +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B SC_P_QSPI0B_SS1_B 1 +#define SC_P_QSPI0B_SS1_B_LSIO_KPP0_ROW3 SC_P_QSPI0B_SS1_B 2 +#define SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 SC_P_QSPI0B_SS1_B 4 +/*@}*/ + +#endif /* SC_PADS_H */ + diff --git a/include/dt-bindings/soc/imx_rsrc.h b/include/dt-bindings/soc/imx_rsrc.h new file mode 100644 index 0000000000..b2154e9a94 --- /dev/null +++ b/include/dt-bindings/soc/imx_rsrc.h @@ -0,0 +1,560 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef DT_BINDINGS_RSCRC_IMX_H +#define DT_BINDINGS_RSCRC_IMX_H + +/*! + * These defines are used to indicate a resource. Resources include peripherals + * and bus masters (but not memory regions). Note items from list should + * never be changed or removed (only added to@the end of the list). + */ +#define SC_R_A53 0 +#define SC_R_A53_0 1 +#define SC_R_A53_1 2 +#define SC_R_A53_2 3 +#define SC_R_A53_3 4 +#define SC_R_A72 5 +#define SC_R_A72_0 6 +#define SC_R_A72_1 7 +#define SC_R_A72_2 8 +#define SC_R_A72_3 9 +#define SC_R_CCI 10 +#define SC_R_DB 11 +#define SC_R_DRC_0 12 +#define SC_R_DRC_1 13 +#define SC_R_GIC_SMMU 14 +#define SC_R_IRQSTR_M4_0 15 +#define SC_R_IRQSTR_M4_1 16 +#define SC_R_SMMU 17 +#define SC_R_GIC 18 +#define SC_R_DC_0_BLIT0 19 +#define SC_R_DC_0_BLIT1 20 +#define SC_R_DC_0_BLIT2 21 +#define SC_R_DC_0_BLIT_OUT 22 +#define SC_R_DC_0_CAPTURE0 23 +#define SC_R_DC_0_CAPTURE1 24 +#define SC_R_DC_0_WARP 25 +#define SC_R_DC_0_INTEGRAL0 26 +#define SC_R_DC_0_INTEGRAL1 27 +#define SC_R_DC_0_VIDEO0 28 +#define SC_R_DC_0_VIDEO1 29 +#define SC_R_DC_0_FRAC0 30 +#define SC_R_DC_0_FRAC1 31 +#define SC_R_DC_0 32 +#define SC_R_GPU_2_PID0 33 +#define SC_R_DC_0_PLL_0 34 +#define SC_R_DC_0_PLL_1 35 +#define SC_R_DC_1_BLIT0 36 +#define SC_R_DC_1_BLIT1 37 +#define SC_R_DC_1_BLIT2 38 +#define SC_R_DC_1_BLIT_OUT 39 +#define SC_R_DC_1_CAPTURE0 40 +#define SC_R_DC_1_CAPTURE1 41 +#define SC_R_DC_1_WARP 42 +#define SC_R_DC_1_INTEGRAL0 43 +#define SC_R_DC_1_INTEGRAL1 44 +#define SC_R_DC_1_VIDEO0 45 +#define SC_R_DC_1_VIDEO1 46 +#define SC_R_DC_1_FRAC0 47 +#define SC_R_DC_1_FRAC1 48 +#define SC_R_DC_1 49 +#define SC_R_GPU_3_PID0 50 +#define SC_R_DC_1_PLL_0 51 +#define SC_R_DC_1_PLL_1 52 +#define SC_R_SPI_0 53 +#define SC_R_SPI_1 54 +#define SC_R_SPI_2 55 +#define SC_R_SPI_3 56 +#define SC_R_UART_0 57 +#define SC_R_UART_1 58 +#define SC_R_UART_2 59 +#define SC_R_UART_3 60 +#define SC_R_UART_4 61 +#define SC_R_EMVSIM_0 62 +#define SC_R_EMVSIM_1 63 +#define SC_R_DMA_0_CH0 64 +#define SC_R_DMA_0_CH1 65 +#define SC_R_DMA_0_CH2 66 +#define SC_R_DMA_0_CH3 67 +#define SC_R_DMA_0_CH4 68 +#define SC_R_DMA_0_CH5 69 +#define SC_R_DMA_0_CH6 70 +#define SC_R_DMA_0_CH7 71 +#define SC_R_DMA_0_CH8 72 +#define SC_R_DMA_0_CH9 73 +#define SC_R_DMA_0_CH10 74 +#define SC_R_DMA_0_CH11 75 +#define SC_R_DMA_0_CH12 76 +#define SC_R_DMA_0_CH13 77 +#define SC_R_DMA_0_CH14 78 +#define SC_R_DMA_0_CH15 79 +#define SC_R_DMA_0_CH16 80 +#define SC_R_DMA_0_CH17 81 +#define SC_R_DMA_0_CH18 82 +#define SC_R_DMA_0_CH19 83 +#define SC_R_DMA_0_CH20 84 +#define SC_R_DMA_0_CH21 85 +#define SC_R_DMA_0_CH22 86 +#define SC_R_DMA_0_CH23 87 +#define SC_R_DMA_0_CH24 88 +#define SC_R_DMA_0_CH25 89 +#define SC_R_DMA_0_CH26 90 +#define SC_R_DMA_0_CH27 91 +#define SC_R_DMA_0_CH28 92 +#define SC_R_DMA_0_CH29 93 +#define SC_R_DMA_0_CH30 94 +#define SC_R_DMA_0_CH31 95 +#define SC_R_I2C_0 96 +#define SC_R_I2C_1 97 +#define SC_R_I2C_2 98 +#define SC_R_I2C_3 99 +#define SC_R_I2C_4 100 +#define SC_R_ADC_0 101 +#define SC_R_ADC_1 102 +#define SC_R_FTM_0 103 +#define SC_R_FTM_1 104 +#define SC_R_CAN_0 105 +#define SC_R_CAN_1 106 +#define SC_R_CAN_2 107 +#define SC_R_DMA_1_CH0 108 +#define SC_R_DMA_1_CH1 109 +#define SC_R_DMA_1_CH2 110 +#define SC_R_DMA_1_CH3 111 +#define SC_R_DMA_1_CH4 112 +#define SC_R_DMA_1_CH5 113 +#define SC_R_DMA_1_CH6 114 +#define SC_R_DMA_1_CH7 115 +#define SC_R_DMA_1_CH8 116 +#define SC_R_DMA_1_CH9 117 +#define SC_R_DMA_1_CH10 118 +#define SC_R_DMA_1_CH11 119 +#define SC_R_DMA_1_CH12 120 +#define SC_R_DMA_1_CH13 121 +#define SC_R_DMA_1_CH14 122 +#define SC_R_DMA_1_CH15 123 +#define SC_R_DMA_1_CH16 124 +#define SC_R_DMA_1_CH17 125 +#define SC_R_DMA_1_CH18 126 +#define SC_R_DMA_1_CH19 127 +#define SC_R_DMA_1_CH20 128 +#define SC_R_DMA_1_CH21 129 +#define SC_R_DMA_1_CH22 130 +#define SC_R_DMA_1_CH23 131 +#define SC_R_DMA_1_CH24 132 +#define SC_R_DMA_1_CH25 133 +#define SC_R_DMA_1_CH26 134 +#define SC_R_DMA_1_CH27 135 +#define SC_R_DMA_1_CH28 136 +#define SC_R_DMA_1_CH29 137 +#define SC_R_DMA_1_CH30 138 +#define SC_R_DMA_1_CH31 139 +#define SC_R_UNUSED1 140 +#define SC_R_UNUSED2 141 +#define SC_R_UNUSED3 142 +#define SC_R_UNUSED4 143 +#define SC_R_GPU_0_PID0 144 +#define SC_R_GPU_0_PID1 145 +#define SC_R_GPU_0_PID2 146 +#define SC_R_GPU_0_PID3 147 +#define SC_R_GPU_1_PID0 148 +#define SC_R_GPU_1_PID1 149 +#define SC_R_GPU_1_PID2 150 +#define SC_R_GPU_1_PID3 151 +#define SC_R_PCIE_A 152 +#define SC_R_SERDES_0 153 +#define SC_R_MATCH_0 154 +#define SC_R_MATCH_1 155 +#define SC_R_MATCH_2 156 +#define SC_R_MATCH_3 157 +#define SC_R_MATCH_4 158 +#define SC_R_MATCH_5 159 +#define SC_R_MATCH_6 160 +#define SC_R_MATCH_7 161 +#define SC_R_MATCH_8 162 +#define SC_R_MATCH_9 163 +#define SC_R_MATCH_10 164 +#define SC_R_MATCH_11 165 +#define SC_R_MATCH_12 166 +#define SC_R_MATCH_13 167 +#define SC_R_MATCH_14 168 +#define SC_R_PCIE_B 169 +#define SC_R_SATA_0 170 +#define SC_R_SERDES_1 171 +#define SC_R_HSIO_GPIO 172 +#define SC_R_MATCH_15 173 +#define SC_R_MATCH_16 174 +#define SC_R_MATCH_17 175 +#define SC_R_MATCH_18 176 +#define SC_R_MATCH_19 177 +#define SC_R_MATCH_20 178 +#define SC_R_MATCH_21 179 +#define SC_R_MATCH_22 180 +#define SC_R_MATCH_23 181 +#define SC_R_MATCH_24 182 +#define SC_R_MATCH_25 183 +#define SC_R_MATCH_26 184 +#define SC_R_MATCH_27 185 +#define SC_R_MATCH_28 186 +#define SC_R_LCD_0 187 +#define SC_R_LCD_0_PWM_0 188 +#define SC_R_LCD_0_I2C_0 189 +#define SC_R_LCD_0_I2C_1 190 +#define SC_R_PWM_0 191 +#define SC_R_PWM_1 192 +#define SC_R_PWM_2 193 +#define SC_R_PWM_3 194 +#define SC_R_PWM_4 195 +#define SC_R_PWM_5 196 +#define SC_R_PWM_6 197 +#define SC_R_PWM_7 198 +#define SC_R_GPIO_0 199 +#define SC_R_GPIO_1 200 +#define SC_R_GPIO_2 201 +#define SC_R_GPIO_3 202 +#define SC_R_GPIO_4 203 +#define SC_R_GPIO_5 204 +#define SC_R_GPIO_6 205 +#define SC_R_GPIO_7 206 +#define SC_R_GPT_0 207 +#define SC_R_GPT_1 208 +#define SC_R_GPT_2 209 +#define SC_R_GPT_3 210 +#define SC_R_GPT_4 211 +#define SC_R_KPP 212 +#define SC_R_MU_0A 213 +#define SC_R_MU_1A 214 +#define SC_R_MU_2A 215 +#define SC_R_MU_3A 216 +#define SC_R_MU_4A 217 +#define SC_R_MU_5A 218 +#define SC_R_MU_6A 219 +#define SC_R_MU_7A 220 +#define SC_R_MU_8A 221 +#define SC_R_MU_9A 222 +#define SC_R_MU_10A 223 +#define SC_R_MU_11A 224 +#define SC_R_MU_12A 225 +#define SC_R_MU_13A 226 +#define SC_R_MU_5B 227 +#define SC_R_MU_6B 228 +#define SC_R_MU_7B 229 +#define SC_R_MU_8B 230 +#define SC_R_MU_9B 231 +#define SC_R_MU_10B 232 +#define SC_R_MU_11B 233 +#define SC_R_MU_12B 234 +#define SC_R_MU_13B 235 +#define SC_R_ROM_0 236 +#define SC_R_FSPI_0 237 +#define SC_R_FSPI_1 238 +#define SC_R_IEE 239 +#define SC_R_IEE_R0 240 +#define SC_R_IEE_R1 241 +#define SC_R_IEE_R2 242 +#define SC_R_IEE_R3 243 +#define SC_R_IEE_R4 244 +#define SC_R_IEE_R5 245 +#define SC_R_IEE_R6 246 +#define SC_R_IEE_R7 247 +#define SC_R_SDHC_0 248 +#define SC_R_SDHC_1 249 +#define SC_R_SDHC_2 250 +#define SC_R_ENET_0 251 +#define SC_R_ENET_1 252 +#define SC_R_MLB_0 253 +#define SC_R_DMA_2_CH0 254 +#define SC_R_DMA_2_CH1 255 +#define SC_R_DMA_2_CH2 256 +#define SC_R_DMA_2_CH3 257 +#define SC_R_DMA_2_CH4 258 +#define SC_R_USB_0 259 +#define SC_R_USB_1 260 +#define SC_R_USB_0_PHY 261 +#define SC_R_USB_2 262 +#define SC_R_USB_2_PHY 263 +#define SC_R_DTCP 264 +#define SC_R_NAND 265 +#define SC_R_LVDS_0 266 +#define SC_R_LVDS_0_PWM_0 267 +#define SC_R_LVDS_0_I2C_0 268 +#define SC_R_LVDS_0_I2C_1 269 +#define SC_R_LVDS_1 270 +#define SC_R_LVDS_1_PWM_0 271 +#define SC_R_LVDS_1_I2C_0 272 +#define SC_R_LVDS_1_I2C_1 273 +#define SC_R_LVDS_2 274 +#define SC_R_LVDS_2_PWM_0 275 +#define SC_R_LVDS_2_I2C_0 276 +#define SC_R_LVDS_2_I2C_1 277 +#define SC_R_M4_0_PID0 278 +#define SC_R_M4_0_PID1 279 +#define SC_R_M4_0_PID2 280 +#define SC_R_M4_0_PID3 281 +#define SC_R_M4_0_PID4 282 +#define SC_R_M4_0_RGPIO 283 +#define SC_R_M4_0_SEMA42 284 +#define SC_R_M4_0_TPM 285 +#define SC_R_M4_0_PIT 286 +#define SC_R_M4_0_UART 287 +#define SC_R_M4_0_I2C 288 +#define SC_R_M4_0_INTMUX 289 +#define SC_R_M4_0_SIM 290 +#define SC_R_M4_0_WDOG 291 +#define SC_R_M4_0_MU_0B 292 +#define SC_R_M4_0_MU_0A0 293 +#define SC_R_M4_0_MU_0A1 294 +#define SC_R_M4_0_MU_0A2 295 +#define SC_R_M4_0_MU_0A3 296 +#define SC_R_M4_0_MU_1A 297 +#define SC_R_M4_1_PID0 298 +#define SC_R_M4_1_PID1 299 +#define SC_R_M4_1_PID2 300 +#define SC_R_M4_1_PID3 301 +#define SC_R_M4_1_PID4 302 +#define SC_R_M4_1_RGPIO 303 +#define SC_R_M4_1_SEMA42 304 +#define SC_R_M4_1_TPM 305 +#define SC_R_M4_1_PIT 306 +#define SC_R_M4_1_UART 307 +#define SC_R_M4_1_I2C 308 +#define SC_R_M4_1_INTMUX 309 +#define SC_R_M4_1_SIM 310 +#define SC_R_M4_1_WDOG 311 +#define SC_R_M4_1_MU_0B 312 +#define SC_R_M4_1_MU_0A0 313 +#define SC_R_M4_1_MU_0A1 314 +#define SC_R_M4_1_MU_0A2 315 +#define SC_R_M4_1_MU_0A3 316 +#define SC_R_M4_1_MU_1A 317 +#define SC_R_SAI_0 318 +#define SC_R_SAI_1 319 +#define SC_R_SAI_2 320 +#define SC_R_IRQSTR_SCU2 321 +#define SC_R_IRQSTR_DSP 322 +#define SC_R_UNUSED5 323 +#define SC_R_OCRAM 324 +#define SC_R_AUDIO_PLL_0 325 +#define SC_R_PI_0 326 +#define SC_R_PI_0_PWM_0 327 +#define SC_R_PI_0_PWM_1 328 +#define SC_R_PI_0_I2C_0 329 +#define SC_R_PI_0_PLL 330 +#define SC_R_PI_1 331 +#define SC_R_PI_1_PWM_0 332 +#define SC_R_PI_1_PWM_1 333 +#define SC_R_PI_1_I2C_0 334 +#define SC_R_PI_1_PLL 335 +#define SC_R_SC_PID0 336 +#define SC_R_SC_PID1 337 +#define SC_R_SC_PID2 338 +#define SC_R_SC_PID3 339 +#define SC_R_SC_PID4 340 +#define SC_R_SC_SEMA42 341 +#define SC_R_SC_TPM 342 +#define SC_R_SC_PIT 343 +#define SC_R_SC_UART 344 +#define SC_R_SC_I2C 345 +#define SC_R_SC_MU_0B 346 +#define SC_R_SC_MU_0A0 347 +#define SC_R_SC_MU_0A1 348 +#define SC_R_SC_MU_0A2 349 +#define SC_R_SC_MU_0A3 350 +#define SC_R_SC_MU_1A 351 +#define SC_R_SYSCNT_RD 352 +#define SC_R_SYSCNT_CMP 353 +#define SC_R_DEBUG 354 +#define SC_R_SYSTEM 355 +#define SC_R_SNVS 356 +#define SC_R_OTP 357 +#define SC_R_VPU_PID0 358 +#define SC_R_VPU_PID1 359 +#define SC_R_VPU_PID2 360 +#define SC_R_VPU_PID3 361 +#define SC_R_VPU_PID4 362 +#define SC_R_VPU_PID5 363 +#define SC_R_VPU_PID6 364 +#define SC_R_VPU_PID7 365 +#define SC_R_VPU_UART 366 +#define SC_R_VPUCORE 367 +#define SC_R_VPUCORE_0 368 +#define SC_R_VPUCORE_1 369 +#define SC_R_VPUCORE_2 370 +#define SC_R_VPUCORE_3 371 +#define SC_R_DMA_4_CH0 372 +#define SC_R_DMA_4_CH1 373 +#define SC_R_DMA_4_CH2 374 +#define SC_R_DMA_4_CH3 375 +#define SC_R_DMA_4_CH4 376 +#define SC_R_ISI_CH0 377 +#define SC_R_ISI_CH1 378 +#define SC_R_ISI_CH2 379 +#define SC_R_ISI_CH3 380 +#define SC_R_ISI_CH4 381 +#define SC_R_ISI_CH5 382 +#define SC_R_ISI_CH6 383 +#define SC_R_ISI_CH7 384 +#define SC_R_MJPEG_DEC_S0 385 +#define SC_R_MJPEG_DEC_S1 386 +#define SC_R_MJPEG_DEC_S2 387 +#define SC_R_MJPEG_DEC_S3 388 +#define SC_R_MJPEG_ENC_S0 389 +#define SC_R_MJPEG_ENC_S1 390 +#define SC_R_MJPEG_ENC_S2 391 +#define SC_R_MJPEG_ENC_S3 392 +#define SC_R_MIPI_0 393 +#define SC_R_MIPI_0_PWM_0 394 +#define SC_R_MIPI_0_I2C_0 395 +#define SC_R_MIPI_0_I2C_1 396 +#define SC_R_MIPI_1 397 +#define SC_R_MIPI_1_PWM_0 398 +#define SC_R_MIPI_1_I2C_0 399 +#define SC_R_MIPI_1_I2C_1 400 +#define SC_R_CSI_0 401 +#define SC_R_CSI_0_PWM_0 402 +#define SC_R_CSI_0_I2C_0 403 +#define SC_R_CSI_1 404 +#define SC_R_CSI_1_PWM_0 405 +#define SC_R_CSI_1_I2C_0 406 +#define SC_R_HDMI 407 +#define SC_R_HDMI_I2S 408 +#define SC_R_HDMI_I2C_0 409 +#define SC_R_HDMI_PLL_0 410 +#define SC_R_HDMI_RX 411 +#define SC_R_HDMI_RX_BYPASS 412 +#define SC_R_HDMI_RX_I2C_0 413 +#define SC_R_ASRC_0 414 +#define SC_R_ESAI_0 415 +#define SC_R_SPDIF_0 416 +#define SC_R_SPDIF_1 417 +#define SC_R_SAI_3 418 +#define SC_R_SAI_4 419 +#define SC_R_SAI_5 420 +#define SC_R_GPT_5 421 +#define SC_R_GPT_6 422 +#define SC_R_GPT_7 423 +#define SC_R_GPT_8 424 +#define SC_R_GPT_9 425 +#define SC_R_GPT_10 426 +#define SC_R_DMA_2_CH5 427 +#define SC_R_DMA_2_CH6 428 +#define SC_R_DMA_2_CH7 429 +#define SC_R_DMA_2_CH8 430 +#define SC_R_DMA_2_CH9 431 +#define SC_R_DMA_2_CH10 432 +#define SC_R_DMA_2_CH11 433 +#define SC_R_DMA_2_CH12 434 +#define SC_R_DMA_2_CH13 435 +#define SC_R_DMA_2_CH14 436 +#define SC_R_DMA_2_CH15 437 +#define SC_R_DMA_2_CH16 438 +#define SC_R_DMA_2_CH17 439 +#define SC_R_DMA_2_CH18 440 +#define SC_R_DMA_2_CH19 441 +#define SC_R_DMA_2_CH20 442 +#define SC_R_DMA_2_CH21 443 +#define SC_R_DMA_2_CH22 444 +#define SC_R_DMA_2_CH23 445 +#define SC_R_DMA_2_CH24 446 +#define SC_R_DMA_2_CH25 447 +#define SC_R_DMA_2_CH26 448 +#define SC_R_DMA_2_CH27 449 +#define SC_R_DMA_2_CH28 450 +#define SC_R_DMA_2_CH29 451 +#define SC_R_DMA_2_CH30 452 +#define SC_R_DMA_2_CH31 453 +#define SC_R_ASRC_1 454 +#define SC_R_ESAI_1 455 +#define SC_R_SAI_6 456 +#define SC_R_SAI_7 457 +#define SC_R_AMIX 458 +#define SC_R_MQS_0 459 +#define SC_R_DMA_3_CH0 460 +#define SC_R_DMA_3_CH1 461 +#define SC_R_DMA_3_CH2 462 +#define SC_R_DMA_3_CH3 463 +#define SC_R_DMA_3_CH4 464 +#define SC_R_DMA_3_CH5 465 +#define SC_R_DMA_3_CH6 466 +#define SC_R_DMA_3_CH7 467 +#define SC_R_DMA_3_CH8 468 +#define SC_R_DMA_3_CH9 469 +#define SC_R_DMA_3_CH10 470 +#define SC_R_DMA_3_CH11 471 +#define SC_R_DMA_3_CH12 472 +#define SC_R_DMA_3_CH13 473 +#define SC_R_DMA_3_CH14 474 +#define SC_R_DMA_3_CH15 475 +#define SC_R_DMA_3_CH16 476 +#define SC_R_DMA_3_CH17 477 +#define SC_R_DMA_3_CH18 478 +#define SC_R_DMA_3_CH19 479 +#define SC_R_DMA_3_CH20 480 +#define SC_R_DMA_3_CH21 481 +#define SC_R_DMA_3_CH22 482 +#define SC_R_DMA_3_CH23 483 +#define SC_R_DMA_3_CH24 484 +#define SC_R_DMA_3_CH25 485 +#define SC_R_DMA_3_CH26 486 +#define SC_R_DMA_3_CH27 487 +#define SC_R_DMA_3_CH28 488 +#define SC_R_DMA_3_CH29 489 +#define SC_R_DMA_3_CH30 490 +#define SC_R_DMA_3_CH31 491 +#define SC_R_AUDIO_PLL_1 492 +#define SC_R_AUDIO_CLK_0 493 +#define SC_R_AUDIO_CLK_1 494 +#define SC_R_MCLK_OUT_0 495 +#define SC_R_MCLK_OUT_1 496 +#define SC_R_PMIC_0 497 +#define SC_R_PMIC_1 498 +#define SC_R_SECO 499 +#define SC_R_CAAM_JR1 500 +#define SC_R_CAAM_JR2 501 +#define SC_R_CAAM_JR3 502 +#define SC_R_SECO_MU_2 503 +#define SC_R_SECO_MU_3 504 +#define SC_R_SECO_MU_4 505 +#define SC_R_HDMI_RX_PWM_0 506 +#define SC_R_A35 507 +#define SC_R_A35_0 508 +#define SC_R_A35_1 509 +#define SC_R_A35_2 510 +#define SC_R_A35_3 511 +#define SC_R_DSP 512 +#define SC_R_DSP_RAM 513 +#define SC_R_CAAM_JR1_OUT 514 +#define SC_R_CAAM_JR2_OUT 515 +#define SC_R_CAAM_JR3_OUT 516 +#define SC_R_VPU_DEC_0 517 +#define SC_R_VPU_ENC_0 518 +#define SC_R_CAAM_JR0 519 +#define SC_R_CAAM_JR0_OUT 520 +#define SC_R_PMIC_2 521 +#define SC_R_DBLOGIC 522 +#define SC_R_HDMI_PLL_1 523 +#define SC_R_BOARD_R0 524 +#define SC_R_BOARD_R1 525 +#define SC_R_BOARD_R2 526 +#define SC_R_BOARD_R3 527 +#define SC_R_BOARD_R4 528 +#define SC_R_BOARD_R5 529 +#define SC_R_BOARD_R6 530 +#define SC_R_BOARD_R7 531 +#define SC_R_MJPEG_DEC_MP 532 +#define SC_R_MJPEG_ENC_MP 533 +#define SC_R_VPU_TS_0 534 +#define SC_R_VPU_MU_0 535 +#define SC_R_VPU_MU_1 536 +#define SC_R_VPU_MU_2 537 +#define SC_R_VPU_MU_3 538 +#define SC_R_VPU_ENC_1 539 +#define SC_R_VPU 540 +#define SC_R_LAST 541 + +#endif /* DT_BINDINGS_RSCRC_IMX_H */ + -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 01/41] imx: import SCFW API 2018-05-28 12:24 ` [U-Boot] [PATCH 01/41] imx: import SCFW API Peng Fan @ 2018-06-12 9:41 ` Peng Fan 0 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-06-12 9:41 UTC (permalink / raw) To: u-boot Hi Stefano, Fabio, Do you have any comments on the patchset? Thanks, Peng. > -----Original Message----- > From: Peng Fan > Sent: 2018年5月28日 20:25 > To: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com> > Cc: u-boot at lists.denx.de; Peng Fan <peng.fan@nxp.com> > Subject: [PATCH 01/41] imx: import SCFW API > > The SCFW API files are generated from scfw source code and imported > to U-Boot source code withou code changes. > > The commit in SCFW is > commit a5759de95691("SCF-69 Fix the voltage for 1.06GHz setpoint on A72.") > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > arch/arm/include/asm/arch-imx8/imx8qm_pads.h | 295 +++++++ > arch/arm/include/asm/arch-imx8/imx8qxp_pads.h | 200 +++++ > arch/arm/include/asm/arch-imx8/sci/ipc.h | 67 ++ > arch/arm/include/asm/arch-imx8/sci/rpc.h | 131 +++ > arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h | 160 ++++ > arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h | 523 +++++++++++ > arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h | 568 ++++++++++++ > arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h | 686 > +++++++++++++++ > arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h | 759 > ++++++++++++++++ > arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h | 306 +++++++ > arch/arm/include/asm/arch-imx8/sci/types.h | 862 > ++++++++++++++++++ > arch/arm/mach-imx/imx8/Makefile | 11 + > arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h | 54 ++ > arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c | 76 ++ > arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h | 76 ++ > arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c | 515 +++++++++++ > arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h | 68 ++ > arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c | 475 ++++++++++ > arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h | 73 ++ > arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c | 460 ++++++++++ > arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h | 83 ++ > arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c | 645 > ++++++++++++++ > arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h | 67 ++ > arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c | 365 ++++++++ > include/dt-bindings/pinctrl/pads-imx8qm.h | 975 > +++++++++++++++++++++ > include/dt-bindings/pinctrl/pads-imx8qxp.h | 770 > ++++++++++++++++ > include/dt-bindings/soc/imx_rsrc.h | 560 ++++++++++++ > 27 files changed, 9830 insertions(+) > create mode 100644 arch/arm/include/asm/arch-imx8/imx8qm_pads.h > create mode 100644 arch/arm/include/asm/arch-imx8/imx8qxp_pads.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/ipc.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/rpc.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/types.h > create mode 100644 arch/arm/mach-imx/imx8/Makefile > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c > create mode 100644 include/dt-bindings/pinctrl/pads-imx8qm.h > create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h > create mode 100644 include/dt-bindings/soc/imx_rsrc.h > > diff --git a/arch/arm/include/asm/arch-imx8/imx8qm_pads.h > b/arch/arm/include/asm/arch-imx8/imx8qm_pads.h > new file mode 100644 > index 0000000000..5cd2b76759 > --- /dev/null > +++ b/arch/arm/include/asm/arch-imx8/imx8qm_pads.h > @@ -0,0 +1,295 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * Header file used to configure SoC pad list. > + */ > + > +#ifndef SC_PADS_H > +#define SC_PADS_H > + > +/* Includes */ > + > +/* Defines */ > + > +/*! > + * @name Pad Definitions > + */ > +/*@{*/ > +#define SC_P_SIM0_CLK 0 /*!< > DMA.SIM0.CLK, LSIO.GPIO0.IO00 */ > +#define SC_P_SIM0_RST 1 /*!< > DMA.SIM0.RST, LSIO.GPIO0.IO01 */ > +#define SC_P_SIM0_IO 2 /*!< > DMA.SIM0.IO, LSIO.GPIO0.IO02 */ > +#define SC_P_SIM0_PD 3 /*!< > DMA.SIM0.PD, DMA.I2C3.SCL, LSIO.GPIO0.IO03 */ > +#define SC_P_SIM0_POWER_EN 4 /*!< > DMA.SIM0.POWER_EN, DMA.I2C3.SDA, LSIO.GPIO0.IO04 */ > +#define SC_P_SIM0_GPIO0_00 5 /*!< > DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM 6 /*!< */ > +#define SC_P_M40_I2C0_SCL 7 /*!< > M40.I2C0.SCL, M40.UART0.RX, M40.GPIO0.IO02, LSIO.GPIO0.IO06 */ > +#define SC_P_M40_I2C0_SDA 8 /*!< > M40.I2C0.SDA, M40.UART0.TX, M40.GPIO0.IO03, LSIO.GPIO0.IO07 */ > +#define SC_P_M40_GPIO0_00 9 /*!< > M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */ > +#define SC_P_M40_GPIO0_01 10 /*!< > M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */ > +#define SC_P_M41_I2C0_SCL 11 /*!< > M41.I2C0.SCL, M41.UART0.RX, M41.GPIO0.IO02, LSIO.GPIO0.IO10 */ > +#define SC_P_M41_I2C0_SDA 12 /*!< > M41.I2C0.SDA, M41.UART0.TX, M41.GPIO0.IO03, LSIO.GPIO0.IO11 */ > +#define SC_P_M41_GPIO0_00 13 /*!< > M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */ > +#define SC_P_M41_GPIO0_01 14 /*!< > M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */ > +#define SC_P_GPT0_CLK 15 /*!< > LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */ > +#define SC_P_GPT0_CAPTURE 16 /*!< > LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */ > +#define SC_P_GPT0_COMPARE 17 /*!< > LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */ > +#define SC_P_GPT1_CLK 18 /*!< > LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */ > +#define SC_P_GPT1_CAPTURE 19 /*!< > LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */ > +#define SC_P_GPT1_COMPARE 20 /*!< > LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */ > +#define SC_P_UART0_RX 21 /*!< > DMA.UART0.RX, SCU.UART0.RX, LSIO.GPIO0.IO20 */ > +#define SC_P_UART0_TX 22 /*!< > DMA.UART0.TX, SCU.UART0.TX, LSIO.GPIO0.IO21 */ > +#define SC_P_UART0_RTS_B 23 /*!< > DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */ > +#define SC_P_UART0_CTS_B 24 /*!< > DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */ > +#define SC_P_UART1_TX 25 /*!< > DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */ > +#define SC_P_UART1_RX 26 /*!< > DMA.UART1.RX, DMA.SPI3.SDO, LSIO.GPIO0.IO25 */ > +#define SC_P_UART1_RTS_B 27 /*!< > DMA.UART1.RTS_B, DMA.SPI3.SDI, DMA.UART1.CTS_B, LSIO.GPIO0.IO26 */ > +#define SC_P_UART1_CTS_B 28 /*!< > DMA.UART1.CTS_B, DMA.SPI3.CS0, DMA.UART1.RTS_B, LSIO.GPIO0.IO27 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 29 /*!< */ > +#define SC_P_SCU_PMIC_MEMC_ON 30 /*!< > SCU.GPIO0.IOXX_PMIC_MEMC_ON */ > +#define SC_P_SCU_WDOG_OUT 31 /*!< > SCU.WDOG0.WDOG_OUT */ > +#define SC_P_PMIC_I2C_SDA 32 /*!< > SCU.PMIC_I2C.SDA */ > +#define SC_P_PMIC_I2C_SCL 33 /*!< > SCU.PMIC_I2C.SCL */ > +#define SC_P_PMIC_EARLY_WARNING 34 /*!< > SCU.PMIC_EARLY_WARNING */ > +#define SC_P_PMIC_INT_B 35 /*!< > SCU.DSC.PMIC_INT_B */ > +#define SC_P_SCU_GPIO0_00 36 /*!< > SCU.GPIO0.IO00, SCU.UART0.RX, LSIO.GPIO0.IO28 */ > +#define SC_P_SCU_GPIO0_01 37 /*!< > SCU.GPIO0.IO01, SCU.UART0.TX, LSIO.GPIO0.IO29 */ > +#define SC_P_SCU_GPIO0_02 38 /*!< > SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */ > +#define SC_P_SCU_GPIO0_03 39 /*!< > SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */ > +#define SC_P_SCU_GPIO0_04 40 /*!< > SCU.GPIO0.IO04, SCU.GPIO0.IOXX_PMIC_A72_ON, LSIO.GPIO1.IO00 */ > +#define SC_P_SCU_GPIO0_05 41 /*!< > SCU.GPIO0.IO05, SCU.GPIO0.IOXX_PMIC_A53_ON, LSIO.GPIO1.IO01 */ > +#define SC_P_SCU_GPIO0_06 42 /*!< > SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */ > +#define SC_P_SCU_GPIO0_07 43 /*!< > SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, > LSIO.GPIO1.IO03 */ > +#define SC_P_SCU_BOOT_MODE0 44 /*!< > SCU.DSC.BOOT_MODE0 */ > +#define SC_P_SCU_BOOT_MODE1 45 /*!< > SCU.DSC.BOOT_MODE1 */ > +#define SC_P_SCU_BOOT_MODE2 46 /*!< > SCU.DSC.BOOT_MODE2 */ > +#define SC_P_SCU_BOOT_MODE3 47 /*!< > SCU.DSC.BOOT_MODE3 */ > +#define SC_P_SCU_BOOT_MODE4 48 /*!< > SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */ > +#define SC_P_SCU_BOOT_MODE5 49 /*!< > SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */ > +#define SC_P_LVDS0_GPIO00 50 /*!< > LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */ > +#define SC_P_LVDS0_GPIO01 51 /*!< > LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */ > +#define SC_P_LVDS0_I2C0_SCL 52 /*!< > LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */ > +#define SC_P_LVDS0_I2C0_SDA 53 /*!< > LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */ > +#define SC_P_LVDS0_I2C1_SCL 54 /*!< > LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */ > +#define SC_P_LVDS0_I2C1_SDA 55 /*!< > LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */ > +#define SC_P_LVDS1_GPIO00 56 /*!< > LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */ > +#define SC_P_LVDS1_GPIO01 57 /*!< > LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */ > +#define SC_P_LVDS1_I2C0_SCL 58 /*!< > LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */ > +#define SC_P_LVDS1_I2C0_SDA 59 /*!< > LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */ > +#define SC_P_LVDS1_I2C1_SCL 60 /*!< > LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */ > +#define SC_P_LVDS1_I2C1_SDA 61 /*!< > LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62 /*!< */ > +#define SC_P_MIPI_DSI0_I2C0_SCL 63 /*!< > MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */ > +#define SC_P_MIPI_DSI0_I2C0_SDA 64 /*!< > MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */ > +#define SC_P_MIPI_DSI0_GPIO0_00 65 /*!< > MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 */ > +#define SC_P_MIPI_DSI0_GPIO0_01 66 /*!< > MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */ > +#define SC_P_MIPI_DSI1_I2C0_SCL 67 /*!< > MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */ > +#define SC_P_MIPI_DSI1_I2C0_SDA 68 /*!< > MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */ > +#define SC_P_MIPI_DSI1_GPIO0_00 69 /*!< > MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 */ > +#define SC_P_MIPI_DSI1_GPIO0_01 70 /*!< > MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 71 /*!< */ > +#define SC_P_MIPI_CSI0_MCLK_OUT 72 /*!< > MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */ > +#define SC_P_MIPI_CSI0_I2C0_SCL 73 /*!< > MIPI_CSI0.I2C0.SCL, LSIO.GPIO1.IO25 */ > +#define SC_P_MIPI_CSI0_I2C0_SDA 74 /*!< > MIPI_CSI0.I2C0.SDA, LSIO.GPIO1.IO26 */ > +#define SC_P_MIPI_CSI0_GPIO0_00 75 /*!< > MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, MIPI_CSI1.I2C0.SCL, LSIO.GPIO1.IO27 */ > +#define SC_P_MIPI_CSI0_GPIO0_01 76 /*!< > MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, MIPI_CSI1.I2C0.SDA, LSIO.GPIO1.IO28 > */ > +#define SC_P_MIPI_CSI1_MCLK_OUT 77 /*!< > MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */ > +#define SC_P_MIPI_CSI1_GPIO0_00 78 /*!< > MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */ > +#define SC_P_MIPI_CSI1_GPIO0_01 79 /*!< > MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */ > +#define SC_P_MIPI_CSI1_I2C0_SCL 80 /*!< > MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */ > +#define SC_P_MIPI_CSI1_I2C0_SDA 81 /*!< > MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */ > +#define SC_P_HDMI_TX0_TS_SCL 82 /*!< > HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */ > +#define SC_P_HDMI_TX0_TS_SDA 83 /*!< > HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */ > +#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 84 /*!< */ > +#define SC_P_ESAI1_FSR 85 /*!< > AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */ > +#define SC_P_ESAI1_FST 86 /*!< > AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */ > +#define SC_P_ESAI1_SCKR 87 /*!< > AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */ > +#define SC_P_ESAI1_SCKT 88 /*!< > AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 */ > +#define SC_P_ESAI1_TX0 89 /*!< > AUD.ESAI1.TX0, AUD.SAI2.RXD, AUD.SPDIF0.RX, LSIO.GPIO2.IO08 */ > +#define SC_P_ESAI1_TX1 90 /*!< > AUD.ESAI1.TX1, AUD.SAI2.RXFS, AUD.SPDIF0.TX, LSIO.GPIO2.IO09 */ > +#define SC_P_ESAI1_TX2_RX3 91 /*!< > AUD.ESAI1.TX2_RX3, AUD.SPDIF0.RX, LSIO.GPIO2.IO10 */ > +#define SC_P_ESAI1_TX3_RX2 92 /*!< > AUD.ESAI1.TX3_RX2, AUD.SPDIF0.TX, LSIO.GPIO2.IO11 */ > +#define SC_P_ESAI1_TX4_RX1 93 /*!< > AUD.ESAI1.TX4_RX1, LSIO.GPIO2.IO12 */ > +#define SC_P_ESAI1_TX5_RX0 94 /*!< > AUD.ESAI1.TX5_RX0, LSIO.GPIO2.IO13 */ > +#define SC_P_SPDIF0_RX 95 /*!< > AUD.SPDIF0.RX, AUD.MQS.R, AUD.ACM.MCLK_IN1, LSIO.GPIO2.IO14 */ > +#define SC_P_SPDIF0_TX 96 /*!< > AUD.SPDIF0.TX, AUD.MQS.L, AUD.ACM.MCLK_OUT1, LSIO.GPIO2.IO15 */ > +#define SC_P_SPDIF0_EXT_CLK 97 /*!< > AUD.SPDIF0.EXT_CLK, DMA.DMA0.REQ_IN0, LSIO.GPIO2.IO16 */ > +#define SC_P_SPI3_SCK 98 /*!< > DMA.SPI3.SCK, LSIO.GPIO2.IO17 */ > +#define SC_P_SPI3_SDO 99 /*!< > DMA.SPI3.SDO, DMA.FTM.CH0, LSIO.GPIO2.IO18 */ > +#define SC_P_SPI3_SDI 100 /*!< > DMA.SPI3.SDI, DMA.FTM.CH1, LSIO.GPIO2.IO19 */ > +#define SC_P_SPI3_CS0 101 /*!< > DMA.SPI3.CS0, DMA.FTM.CH2, LSIO.GPIO2.IO20 */ > +#define SC_P_SPI3_CS1 102 /*!< > DMA.SPI3.CS1, LSIO.GPIO2.IO21 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 103 /*!< */ > +#define SC_P_ESAI0_FSR 104 /*!< > AUD.ESAI0.FSR, LSIO.GPIO2.IO22 */ > +#define SC_P_ESAI0_FST 105 /*!< > AUD.ESAI0.FST, LSIO.GPIO2.IO23 */ > +#define SC_P_ESAI0_SCKR 106 /*!< > AUD.ESAI0.SCKR, LSIO.GPIO2.IO24 */ > +#define SC_P_ESAI0_SCKT 107 /*!< > AUD.ESAI0.SCKT, LSIO.GPIO2.IO25 */ > +#define SC_P_ESAI0_TX0 108 /*!< > AUD.ESAI0.TX0, LSIO.GPIO2.IO26 */ > +#define SC_P_ESAI0_TX1 109 /*!< > AUD.ESAI0.TX1, LSIO.GPIO2.IO27 */ > +#define SC_P_ESAI0_TX2_RX3 110 /*!< > AUD.ESAI0.TX2_RX3, LSIO.GPIO2.IO28 */ > +#define SC_P_ESAI0_TX3_RX2 111 /*!< > AUD.ESAI0.TX3_RX2, LSIO.GPIO2.IO29 */ > +#define SC_P_ESAI0_TX4_RX1 112 /*!< > AUD.ESAI0.TX4_RX1, LSIO.GPIO2.IO30 */ > +#define SC_P_ESAI0_TX5_RX0 113 /*!< > AUD.ESAI0.TX5_RX0, LSIO.GPIO2.IO31 */ > +#define SC_P_MCLK_IN0 114 /*!< > AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, AUD.ESAI1.RX_HF_CLK, > LSIO.GPIO3.IO00 */ > +#define SC_P_MCLK_OUT0 115 /*!< > AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, AUD.ESAI1.TX_HF_CLK, > LSIO.GPIO3.IO01 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC 116 /*!< */ > +#define SC_P_SPI0_SCK 117 /*!< > DMA.SPI0.SCK, AUD.SAI0.RXC, LSIO.GPIO3.IO02 */ > +#define SC_P_SPI0_SDO 118 /*!< > DMA.SPI0.SDO, AUD.SAI0.TXD, LSIO.GPIO3.IO03 */ > +#define SC_P_SPI0_SDI 119 /*!< > DMA.SPI0.SDI, AUD.SAI0.RXD, LSIO.GPIO3.IO04 */ > +#define SC_P_SPI0_CS0 120 /*!< > DMA.SPI0.CS0, AUD.SAI0.RXFS, LSIO.GPIO3.IO05 */ > +#define SC_P_SPI0_CS1 121 /*!< > DMA.SPI0.CS1, AUD.SAI0.TXC, LSIO.GPIO3.IO06 */ > +#define SC_P_SPI2_SCK 122 /*!< > DMA.SPI2.SCK, LSIO.GPIO3.IO07 */ > +#define SC_P_SPI2_SDO 123 /*!< > DMA.SPI2.SDO, LSIO.GPIO3.IO08 */ > +#define SC_P_SPI2_SDI 124 /*!< > DMA.SPI2.SDI, LSIO.GPIO3.IO09 */ > +#define SC_P_SPI2_CS0 125 /*!< > DMA.SPI2.CS0, LSIO.GPIO3.IO10 */ > +#define SC_P_SPI2_CS1 126 /*!< > DMA.SPI2.CS1, AUD.SAI0.TXFS, LSIO.GPIO3.IO11 */ > +#define SC_P_SAI1_RXC 127 /*!< > AUD.SAI1.RXC, AUD.SAI0.TXD, LSIO.GPIO3.IO12 */ > +#define SC_P_SAI1_RXD 128 /*!< > AUD.SAI1.RXD, AUD.SAI0.TXFS, LSIO.GPIO3.IO13 */ > +#define SC_P_SAI1_RXFS 129 /*!< > AUD.SAI1.RXFS, AUD.SAI0.RXD, LSIO.GPIO3.IO14 */ > +#define SC_P_SAI1_TXC 130 /*!< > AUD.SAI1.TXC, AUD.SAI0.TXC, LSIO.GPIO3.IO15 */ > +#define SC_P_SAI1_TXD 131 /*!< > AUD.SAI1.TXD, AUD.SAI1.RXC, LSIO.GPIO3.IO16 */ > +#define SC_P_SAI1_TXFS 132 /*!< > AUD.SAI1.TXFS, AUD.SAI1.RXFS, LSIO.GPIO3.IO17 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 133 /*!< */ > +#define SC_P_ADC_IN7 134 /*!< > DMA.ADC1.IN3, DMA.SPI1.CS1, LSIO.KPP0.ROW3, LSIO.GPIO3.IO25 */ > +#define SC_P_ADC_IN6 135 /*!< > DMA.ADC1.IN2, DMA.SPI1.CS0, LSIO.KPP0.ROW2, LSIO.GPIO3.IO24 */ > +#define SC_P_ADC_IN5 136 /*!< > DMA.ADC1.IN1, DMA.SPI1.SDI, LSIO.KPP0.ROW1, LSIO.GPIO3.IO23 */ > +#define SC_P_ADC_IN4 137 /*!< > DMA.ADC1.IN0, DMA.SPI1.SDO, LSIO.KPP0.ROW0, LSIO.GPIO3.IO22 */ > +#define SC_P_ADC_IN3 138 /*!< > DMA.ADC0.IN3, DMA.SPI1.SCK, LSIO.KPP0.COL3, LSIO.GPIO3.IO21 */ > +#define SC_P_ADC_IN2 139 /*!< > DMA.ADC0.IN2, LSIO.KPP0.COL2, LSIO.GPIO3.IO20 */ > +#define SC_P_ADC_IN1 140 /*!< > DMA.ADC0.IN1, LSIO.KPP0.COL1, LSIO.GPIO3.IO19 */ > +#define SC_P_ADC_IN0 141 /*!< > DMA.ADC0.IN0, LSIO.KPP0.COL0, LSIO.GPIO3.IO18 */ > +#define SC_P_MLB_SIG 142 /*!< > CONN.MLB.SIG, AUD.SAI3.RXC, LSIO.GPIO3.IO26 */ > +#define SC_P_MLB_CLK 143 /*!< > CONN.MLB.CLK, AUD.SAI3.RXFS, LSIO.GPIO3.IO27 */ > +#define SC_P_MLB_DATA 144 /*!< > CONN.MLB.DATA, AUD.SAI3.RXD, LSIO.GPIO3.IO28 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 145 /*!< */ > +#define SC_P_FLEXCAN0_RX 146 /*!< > DMA.FLEXCAN0.RX, LSIO.GPIO3.IO29 */ > +#define SC_P_FLEXCAN0_TX 147 /*!< > DMA.FLEXCAN0.TX, LSIO.GPIO3.IO30 */ > +#define SC_P_FLEXCAN1_RX 148 /*!< > DMA.FLEXCAN1.RX, LSIO.GPIO3.IO31 */ > +#define SC_P_FLEXCAN1_TX 149 /*!< > DMA.FLEXCAN1.TX, LSIO.GPIO4.IO00 */ > +#define SC_P_FLEXCAN2_RX 150 /*!< > DMA.FLEXCAN2.RX, LSIO.GPIO4.IO01 */ > +#define SC_P_FLEXCAN2_TX 151 /*!< > DMA.FLEXCAN2.TX, LSIO.GPIO4.IO02 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 152 /*!< */ > +#define SC_P_USB_SS3_TC0 153 /*!< > DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO4.IO03 */ > +#define SC_P_USB_SS3_TC1 154 /*!< > DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */ > +#define SC_P_USB_SS3_TC2 155 /*!< > DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO05 */ > +#define SC_P_USB_SS3_TC3 156 /*!< > DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */ > +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 157 /*!< */ > +#define SC_P_USDHC1_RESET_B 158 /*!< > CONN.USDHC1.RESET_B, LSIO.GPIO4.IO07 */ > +#define SC_P_USDHC1_VSELECT 159 /*!< > CONN.USDHC1.VSELECT, LSIO.GPIO4.IO08 */ > +#define SC_P_USDHC2_RESET_B 160 /*!< > CONN.USDHC2.RESET_B, LSIO.GPIO4.IO09 */ > +#define SC_P_USDHC2_VSELECT 161 /*!< > CONN.USDHC2.VSELECT, LSIO.GPIO4.IO10 */ > +#define SC_P_USDHC2_WP 162 /*!< > CONN.USDHC2.WP, LSIO.GPIO4.IO11 */ > +#define SC_P_USDHC2_CD_B 163 /*!< > CONN.USDHC2.CD_B, LSIO.GPIO4.IO12 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 164 /*!< */ > +#define SC_P_ENET0_MDIO 165 /*!< > CONN.ENET0.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO13 */ > +#define SC_P_ENET0_MDC 166 /*!< > CONN.ENET0.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO14 */ > +#define SC_P_ENET0_REFCLK_125M_25M 167 /*!< > CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, LSIO.GPIO4.IO15 */ > +#define SC_P_ENET1_REFCLK_125M_25M 168 /*!< > CONN.ENET1.REFCLK_125M_25M, CONN.ENET1.PPS, LSIO.GPIO4.IO16 */ > +#define SC_P_ENET1_MDIO 169 /*!< > CONN.ENET1.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO17 */ > +#define SC_P_ENET1_MDC 170 /*!< > CONN.ENET1.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO18 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 171 /*!< */ > +#define SC_P_QSPI1A_SS0_B 172 /*!< > LSIO.QSPI1A.SS0_B, LSIO.GPIO4.IO19 */ > +#define SC_P_QSPI1A_SS1_B 173 /*!< > LSIO.QSPI1A.SS1_B, LSIO.QSPI1A.SCLK2, LSIO.GPIO4.IO20 */ > +#define SC_P_QSPI1A_SCLK 174 /*!< > LSIO.QSPI1A.SCLK, LSIO.GPIO4.IO21 */ > +#define SC_P_QSPI1A_DQS 175 /*!< > LSIO.QSPI1A.DQS, LSIO.GPIO4.IO22 */ > +#define SC_P_QSPI1A_DATA3 176 /*!< > LSIO.QSPI1A.DATA3, DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO23 */ > +#define SC_P_QSPI1A_DATA2 177 /*!< > LSIO.QSPI1A.DATA2, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO24 */ > +#define SC_P_QSPI1A_DATA1 178 /*!< > LSIO.QSPI1A.DATA1, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO25 */ > +#define SC_P_QSPI1A_DATA0 179 /*!< > LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1 180 /*!< */ > +#define SC_P_QSPI0A_DATA0 181 /*!< > LSIO.QSPI0A.DATA0 */ > +#define SC_P_QSPI0A_DATA1 182 /*!< > LSIO.QSPI0A.DATA1 */ > +#define SC_P_QSPI0A_DATA2 183 /*!< > LSIO.QSPI0A.DATA2 */ > +#define SC_P_QSPI0A_DATA3 184 /*!< > LSIO.QSPI0A.DATA3 */ > +#define SC_P_QSPI0A_DQS 185 /*!< > LSIO.QSPI0A.DQS */ > +#define SC_P_QSPI0A_SS0_B 186 /*!< > LSIO.QSPI0A.SS0_B */ > +#define SC_P_QSPI0A_SS1_B 187 /*!< > LSIO.QSPI0A.SS1_B, LSIO.QSPI0A.SCLK2 */ > +#define SC_P_QSPI0A_SCLK 188 /*!< > LSIO.QSPI0A.SCLK */ > +#define SC_P_QSPI0B_SCLK 189 /*!< > LSIO.QSPI0B.SCLK */ > +#define SC_P_QSPI0B_DATA0 190 /*!< > LSIO.QSPI0B.DATA0 */ > +#define SC_P_QSPI0B_DATA1 191 /*!< > LSIO.QSPI0B.DATA1 */ > +#define SC_P_QSPI0B_DATA2 192 /*!< > LSIO.QSPI0B.DATA2 */ > +#define SC_P_QSPI0B_DATA3 193 /*!< > LSIO.QSPI0B.DATA3 */ > +#define SC_P_QSPI0B_DQS 194 /*!< > LSIO.QSPI0B.DQS */ > +#define SC_P_QSPI0B_SS0_B 195 /*!< > LSIO.QSPI0B.SS0_B */ > +#define SC_P_QSPI0B_SS1_B 196 /*!< > LSIO.QSPI0B.SS1_B, LSIO.QSPI0B.SCLK2 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 197 /*!< */ > +#define SC_P_PCIE_CTRL0_CLKREQ_B 198 /*!< > HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO27 */ > +#define SC_P_PCIE_CTRL0_WAKE_B 199 /*!< > HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO28 */ > +#define SC_P_PCIE_CTRL0_PERST_B 200 /*!< > HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO29 */ > +#define SC_P_PCIE_CTRL1_CLKREQ_B 201 /*!< > HSIO.PCIE1.CLKREQ_B, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO30 > */ > +#define SC_P_PCIE_CTRL1_WAKE_B 202 /*!< > HSIO.PCIE1.WAKE_B, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO31 > */ > +#define SC_P_PCIE_CTRL1_PERST_B 203 /*!< > HSIO.PCIE1.PERST_B, DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO5.IO00 > */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 204 /*!< */ > +#define SC_P_USB_HSIC0_DATA 205 /*!< > CONN.USB_HSIC0.DATA, DMA.I2C1.SDA, LSIO.GPIO5.IO01 */ > +#define SC_P_USB_HSIC0_STROBE 206 /*!< > CONN.USB_HSIC0.STROBE, DMA.I2C1.SCL, LSIO.GPIO5.IO02 */ > +#define SC_P_CALIBRATION_0_HSIC 207 /*!< */ > +#define SC_P_CALIBRATION_1_HSIC 208 /*!< */ > +#define SC_P_EMMC0_CLK 209 /*!< > CONN.EMMC0.CLK, CONN.NAND.READY_B */ > +#define SC_P_EMMC0_CMD 210 /*!< > CONN.EMMC0.CMD, CONN.NAND.DQS, AUD.MQS.R, LSIO.GPIO5.IO03 */ > +#define SC_P_EMMC0_DATA0 211 /*!< > CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO5.IO04 */ > +#define SC_P_EMMC0_DATA1 212 /*!< > CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO5.IO05 */ > +#define SC_P_EMMC0_DATA2 213 /*!< > CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO5.IO06 */ > +#define SC_P_EMMC0_DATA3 214 /*!< > CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO5.IO07 */ > +#define SC_P_EMMC0_DATA4 215 /*!< > CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO5.IO08 */ > +#define SC_P_EMMC0_DATA5 216 /*!< > CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO5.IO09 */ > +#define SC_P_EMMC0_DATA6 217 /*!< > CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO5.IO10 */ > +#define SC_P_EMMC0_DATA7 218 /*!< > CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO5.IO11 */ > +#define SC_P_EMMC0_STROBE 219 /*!< > CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO5.IO12 */ > +#define SC_P_EMMC0_RESET_B 220 /*!< > CONN.EMMC0.RESET_B, CONN.NAND.WP_B, CONN.USDHC1.VSELECT, > LSIO.GPIO5.IO13 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 221 /*!< */ > +#define SC_P_USDHC1_CLK 222 /*!< > CONN.USDHC1.CLK, AUD.MQS.R */ > +#define SC_P_USDHC1_CMD 223 /*!< > CONN.USDHC1.CMD, AUD.MQS.L, LSIO.GPIO5.IO14 */ > +#define SC_P_USDHC1_DATA0 224 /*!< > CONN.USDHC1.DATA0, CONN.NAND.RE_N, LSIO.GPIO5.IO15 */ > +#define SC_P_USDHC1_DATA1 225 /*!< > CONN.USDHC1.DATA1, CONN.NAND.RE_P, LSIO.GPIO5.IO16 */ > +#define SC_P_CTL_NAND_RE_P_N 226 /*!< */ > +#define SC_P_USDHC1_DATA2 227 /*!< > CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */ > +#define SC_P_USDHC1_DATA3 228 /*!< > CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */ > +#define SC_P_CTL_NAND_DQS_P_N 229 /*!< */ > +#define SC_P_USDHC1_DATA4 230 /*!< > CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 */ > +#define SC_P_USDHC1_DATA5 231 /*!< > CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */ > +#define SC_P_USDHC1_DATA6 232 /*!< > CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 > */ > +#define SC_P_USDHC1_DATA7 233 /*!< > CONN.USDHC1.DATA7, CONN.NAND.ALE, CONN.USDHC1.CD_B, > LSIO.GPIO5.IO22 */ > +#define SC_P_USDHC1_STROBE 234 /*!< > CONN.USDHC1.STROBE, CONN.NAND.CE1_B, CONN.USDHC1.RESET_B, > LSIO.GPIO5.IO23 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2 235 /*!< */ > +#define SC_P_USDHC2_CLK 236 /*!< > CONN.USDHC2.CLK, AUD.MQS.R, LSIO.GPIO5.IO24 */ > +#define SC_P_USDHC2_CMD 237 /*!< > CONN.USDHC2.CMD, AUD.MQS.L, LSIO.GPIO5.IO25 */ > +#define SC_P_USDHC2_DATA0 238 /*!< > CONN.USDHC2.DATA0, DMA.UART4.RX, LSIO.GPIO5.IO26 */ > +#define SC_P_USDHC2_DATA1 239 /*!< > CONN.USDHC2.DATA1, DMA.UART4.TX, LSIO.GPIO5.IO27 */ > +#define SC_P_USDHC2_DATA2 240 /*!< > CONN.USDHC2.DATA2, DMA.UART4.CTS_B, LSIO.GPIO5.IO28 */ > +#define SC_P_USDHC2_DATA3 241 /*!< > CONN.USDHC2.DATA3, DMA.UART4.RTS_B, LSIO.GPIO5.IO29 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 242 /*!< */ > +#define SC_P_ENET0_RGMII_TXC 243 /*!< > CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, > CONN.ENET0.RCLK50M_IN, LSIO.GPIO5.IO30 */ > +#define SC_P_ENET0_RGMII_TX_CTL 244 /*!< > CONN.ENET0.RGMII_TX_CTL, LSIO.GPIO5.IO31 */ > +#define SC_P_ENET0_RGMII_TXD0 245 /*!< > CONN.ENET0.RGMII_TXD0, LSIO.GPIO6.IO00 */ > +#define SC_P_ENET0_RGMII_TXD1 246 /*!< > CONN.ENET0.RGMII_TXD1, LSIO.GPIO6.IO01 */ > +#define SC_P_ENET0_RGMII_TXD2 247 /*!< > CONN.ENET0.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO02 > */ > +#define SC_P_ENET0_RGMII_TXD3 248 /*!< > CONN.ENET0.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, > LSIO.GPIO6.IO03 */ > +#define SC_P_ENET0_RGMII_RXC 249 /*!< > CONN.ENET0.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, > LSIO.GPIO6.IO04 */ > +#define SC_P_ENET0_RGMII_RX_CTL 250 /*!< > CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 */ > +#define SC_P_ENET0_RGMII_RXD0 251 /*!< > CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */ > +#define SC_P_ENET0_RGMII_RXD1 252 /*!< > CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */ > +#define SC_P_ENET0_RGMII_RXD2 253 /*!< > CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, VPU.TSI_S0.CLK, > LSIO.GPIO6.IO08 */ > +#define SC_P_ENET0_RGMII_RXD3 254 /*!< > CONN.ENET0.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO09 > */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 255 /*!< */ > +#define SC_P_ENET1_RGMII_TXC 256 /*!< > CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_OUT, > CONN.ENET1.RCLK50M_IN, LSIO.GPIO6.IO10 */ > +#define SC_P_ENET1_RGMII_TX_CTL 257 /*!< > CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO6.IO11 */ > +#define SC_P_ENET1_RGMII_TXD0 258 /*!< > CONN.ENET1.RGMII_TXD0, LSIO.GPIO6.IO12 */ > +#define SC_P_ENET1_RGMII_TXD1 259 /*!< > CONN.ENET1.RGMII_TXD1, LSIO.GPIO6.IO13 */ > +#define SC_P_ENET1_RGMII_TXD2 260 /*!< > CONN.ENET1.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO14 > */ > +#define SC_P_ENET1_RGMII_TXD3 261 /*!< > CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, > LSIO.GPIO6.IO15 */ > +#define SC_P_ENET1_RGMII_RXC 262 /*!< > CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, > LSIO.GPIO6.IO16 */ > +#define SC_P_ENET1_RGMII_RX_CTL 263 /*!< > CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 */ > +#define SC_P_ENET1_RGMII_RXD0 264 /*!< > CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */ > +#define SC_P_ENET1_RGMII_RXD1 265 /*!< > CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */ > +#define SC_P_ENET1_RGMII_RXD2 266 /*!< > CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, > LSIO.GPIO6.IO20 */ > +#define SC_P_ENET1_RGMII_RXD3 267 /*!< > CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 > */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 268 /*!< */ > +/*@}*/ > + > +#endif /* SC_PADS_H */ > + > diff --git a/arch/arm/include/asm/arch-imx8/imx8qxp_pads.h > b/arch/arm/include/asm/arch-imx8/imx8qxp_pads.h > new file mode 100644 > index 0000000000..8db40c549a > --- /dev/null > +++ b/arch/arm/include/asm/arch-imx8/imx8qxp_pads.h > @@ -0,0 +1,200 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * Header file used to configure SoC pad list. > + */ > + > +#ifndef SC_PADS_H > +#define SC_PADS_H > + > +/* Includes */ > + > +/* Defines */ > + > +/*! > + * @name Pad Definitions > + */ > +/*@{*/ > +#define SC_P_PCIE_CTRL0_PERST_B 0 /*!< > HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */ > +#define SC_P_PCIE_CTRL0_CLKREQ_B 1 /*!< > HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */ > +#define SC_P_PCIE_CTRL0_WAKE_B 2 /*!< > HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 /*!< */ > +#define SC_P_USB_SS3_TC0 4 /*!< > ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, > LSIO.GPIO4.IO03 */ > +#define SC_P_USB_SS3_TC1 5 /*!< > ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */ > +#define SC_P_USB_SS3_TC2 6 /*!< > ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 > */ > +#define SC_P_USB_SS3_TC3 7 /*!< > ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */ > +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8 /*!< */ > +#define SC_P_EMMC0_CLK 9 /*!< > CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */ > +#define SC_P_EMMC0_CMD 10 /*!< > CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */ > +#define SC_P_EMMC0_DATA0 11 /*!< > CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */ > +#define SC_P_EMMC0_DATA1 12 /*!< > CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */ > +#define SC_P_EMMC0_DATA2 13 /*!< > CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */ > +#define SC_P_EMMC0_DATA3 14 /*!< > CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15 /*!< */ > +#define SC_P_EMMC0_DATA4 16 /*!< > CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, > LSIO.GPIO4.IO13 */ > +#define SC_P_EMMC0_DATA5 17 /*!< > CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, > LSIO.GPIO4.IO14 */ > +#define SC_P_EMMC0_DATA6 18 /*!< > CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 > */ > +#define SC_P_EMMC0_DATA7 19 /*!< > CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 > */ > +#define SC_P_EMMC0_STROBE 20 /*!< > CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 > */ > +#define SC_P_EMMC0_RESET_B 21 /*!< > CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22 /*!< */ > +#define SC_P_USDHC1_RESET_B 23 /*!< > CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 > */ > +#define SC_P_USDHC1_VSELECT 24 /*!< > CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, > CONN.NAND.RE_B, LSIO.GPIO4.IO20 */ > +#define SC_P_CTL_NAND_RE_P_N 25 /*!< */ > +#define SC_P_USDHC1_WP 26 /*!< > CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */ > +#define SC_P_USDHC1_CD_B 27 /*!< > CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, > LSIO.GPIO4.IO22 */ > +#define SC_P_CTL_NAND_DQS_P_N 28 /*!< */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29 /*!< */ > +#define SC_P_USDHC1_CLK 30 /*!< > CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */ > +#define SC_P_USDHC1_CMD 31 /*!< > CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */ > +#define SC_P_USDHC1_DATA0 32 /*!< > CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */ > +#define SC_P_USDHC1_DATA1 33 /*!< > CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 > */ > +#define SC_P_USDHC1_DATA2 34 /*!< > CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, > LSIO.GPIO4.IO27 */ > +#define SC_P_USDHC1_DATA3 35 /*!< > CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, > LSIO.GPIO4.IO28 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36 /*!< */ > +#define SC_P_ENET0_RGMII_TXC 37 /*!< > CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, > CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */ > +#define SC_P_ENET0_RGMII_TX_CTL 38 /*!< > CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */ > +#define SC_P_ENET0_RGMII_TXD0 39 /*!< > CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 */ > +#define SC_P_ENET0_RGMII_TXD1 40 /*!< > CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */ > +#define SC_P_ENET0_RGMII_TXD2 41 /*!< > CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, > CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 */ > +#define SC_P_ENET0_RGMII_TXD3 42 /*!< > CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, > LSIO.GPIO5.IO02 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43 /*!< */ > +#define SC_P_ENET0_RGMII_RXC 44 /*!< > CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, > CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */ > +#define SC_P_ENET0_RGMII_RX_CTL 45 /*!< > CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */ > +#define SC_P_ENET0_RGMII_RXD0 46 /*!< > CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */ > +#define SC_P_ENET0_RGMII_RXD1 47 /*!< > CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */ > +#define SC_P_ENET0_RGMII_RXD2 48 /*!< > CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, > LSIO.GPIO5.IO07 */ > +#define SC_P_ENET0_RGMII_RXD3 49 /*!< > CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, > LSIO.GPIO5.IO08 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50 /*!< */ > +#define SC_P_ENET0_REFCLK_125M_25M 51 /*!< > CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, > LSIO.GPIO5.IO09 */ > +#define SC_P_ENET0_MDIO 52 /*!< > CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO5.IO10 */ > +#define SC_P_ENET0_MDC 53 /*!< > CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO5.IO11 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54 /*!< */ > +#define SC_P_ESAI0_FSR 55 /*!< > ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, > CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN */ > +#define SC_P_ESAI0_FST 56 /*!< > ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01, > CONN.ENET1.RGMII_TXD2, LSIO.GPIO0.IO01 */ > +#define SC_P_ESAI0_SCKR 57 /*!< > ADMA.ESAI0.SCKR, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TX_CTL, > LSIO.GPIO0.IO02 */ > +#define SC_P_ESAI0_SCKT 58 /*!< > ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D03, > CONN.ENET1.RGMII_TXD3, LSIO.GPIO0.IO03 */ > +#define SC_P_ESAI0_TX0 59 /*!< > ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D04, > CONN.ENET1.RGMII_RXC, LSIO.GPIO0.IO04 */ > +#define SC_P_ESAI0_TX1 60 /*!< > ADMA.ESAI0.TX1, ADMA.LCDIF.D05, CONN.ENET1.RGMII_RXD3, > LSIO.GPIO0.IO05 */ > +#define SC_P_ESAI0_TX2_RX3 61 /*!< > ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D06, > CONN.ENET1.RGMII_RXD2, LSIO.GPIO0.IO06 */ > +#define SC_P_ESAI0_TX3_RX2 62 /*!< > ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD1, > LSIO.GPIO0.IO07 */ > +#define SC_P_ESAI0_TX4_RX1 63 /*!< > ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D08, CONN.ENET1.RGMII_TXD0, > LSIO.GPIO0.IO08 */ > +#define SC_P_ESAI0_TX5_RX0 64 /*!< > ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D09, CONN.ENET1.RGMII_TXD1, > LSIO.GPIO0.IO09 */ > +#define SC_P_SPDIF0_RX 65 /*!< > ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, > LSIO.GPIO0.IO10 */ > +#define SC_P_SPDIF0_TX 66 /*!< > ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, > CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO0.IO11 */ > +#define SC_P_SPDIF0_EXT_CLK 67 /*!< > ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, > LSIO.GPIO0.IO12 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68 /*!< */ > +#define SC_P_SPI3_SCK 69 /*!< > ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */ > +#define SC_P_SPI3_SDO 70 /*!< > ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */ > +#define SC_P_SPI3_SDI 71 /*!< > ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */ > +#define SC_P_SPI3_CS0 72 /*!< > ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, > LSIO.GPIO0.IO16 */ > +#define SC_P_SPI3_CS1 73 /*!< > ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, > ADMA.LCDIF.D16 */ > +#define SC_P_MCLK_IN1 74 /*!< > ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, > ADMA.LCDIF.D17 */ > +#define SC_P_MCLK_IN0 75 /*!< > ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, > ADMA.SPI2.SDI, LSIO.GPIO0.IO19 */ > +#define SC_P_MCLK_OUT0 76 /*!< > ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, > ADMA.SPI2.SDO, LSIO.GPIO0.IO20 */ > +#define SC_P_UART1_TX 77 /*!< > ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21 */ > +#define SC_P_UART1_RX 78 /*!< > ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, > LSIO.GPIO0.IO22 */ > +#define SC_P_UART1_RTS_B 79 /*!< > ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, > LSIO.GPT0.CLK */ > +#define SC_P_UART1_CTS_B 80 /*!< > ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, > LSIO.GPIO0.IO24 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81 /*!< */ > +#define SC_P_SAI0_TXD 82 /*!< > ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, > LSIO.GPIO0.IO25 */ > +#define SC_P_SAI0_TXC 83 /*!< > ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, > LSIO.GPIO0.IO26 */ > +#define SC_P_SAI0_RXD 84 /*!< > ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, > LSIO.GPIO0.IO27 */ > +#define SC_P_SAI0_TXFS 85 /*!< > ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO0.IO28 */ > +#define SC_P_SAI1_RXD 86 /*!< > ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D21, > LSIO.GPIO0.IO29 */ > +#define SC_P_SAI1_RXC 87 /*!< > ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22, LSIO.GPIO0.IO30 */ > +#define SC_P_SAI1_RXFS 88 /*!< > ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO0.IO31 */ > +#define SC_P_SPI2_CS0 89 /*!< > ADMA.SPI2.CS0, LSIO.GPIO1.IO00 */ > +#define SC_P_SPI2_SDO 90 /*!< > ADMA.SPI2.SDO, LSIO.GPIO1.IO01 */ > +#define SC_P_SPI2_SDI 91 /*!< > ADMA.SPI2.SDI, LSIO.GPIO1.IO02 */ > +#define SC_P_SPI2_SCK 92 /*!< > ADMA.SPI2.SCK, LSIO.GPIO1.IO03 */ > +#define SC_P_SPI0_SCK 93 /*!< > ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, > LSIO.GPIO1.IO04 */ > +#define SC_P_SPI0_SDI 94 /*!< > ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, > LSIO.GPIO1.IO05 */ > +#define SC_P_SPI0_SDO 95 /*!< > ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, > LSIO.GPIO1.IO06 */ > +#define SC_P_SPI0_CS1 96 /*!< > ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, > LSIO.GPIO1.IO07 */ > +#define SC_P_SPI0_CS0 97 /*!< > ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, > LSIO.GPIO1.IO08 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98 /*!< */ > +#define SC_P_ADC_IN1 99 /*!< > ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO09 */ > +#define SC_P_ADC_IN0 100 /*!< > ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO10 */ > +#define SC_P_ADC_IN3 101 /*!< > ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, > LSIO.GPIO1.IO11 */ > +#define SC_P_ADC_IN2 102 /*!< > ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, > LSIO.GPIO1.IO12 */ > +#define SC_P_ADC_IN5 103 /*!< > ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO1.IO13 */ > +#define SC_P_ADC_IN4 104 /*!< > ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO1.IO14 */ > +#define SC_P_FLEXCAN0_RX 105 /*!< > ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, > LSIO.GPIO1.IO15 */ > +#define SC_P_FLEXCAN0_TX 106 /*!< > ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, > LSIO.GPIO1.IO16 */ > +#define SC_P_FLEXCAN1_RX 107 /*!< > ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, > LSIO.GPIO1.IO17 */ > +#define SC_P_FLEXCAN1_TX 108 /*!< > ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, > LSIO.GPIO1.IO18 */ > +#define SC_P_FLEXCAN2_RX 109 /*!< > ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, > LSIO.GPIO1.IO19 */ > +#define SC_P_FLEXCAN2_TX 110 /*!< > ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, > LSIO.GPIO1.IO20 */ > +#define SC_P_UART0_RX 111 /*!< > ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, SCU.UART0.RX, > LSIO.GPIO1.IO21 */ > +#define SC_P_UART0_TX 112 /*!< > ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, SCU.UART0.TX, > LSIO.GPIO1.IO22 */ > +#define SC_P_UART2_TX 113 /*!< > ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */ > +#define SC_P_UART2_RX 114 /*!< > ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115 /*!< */ > +#define SC_P_MIPI_DSI0_I2C0_SCL 116 /*!< > MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 */ > +#define SC_P_MIPI_DSI0_I2C0_SDA 117 /*!< > MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 */ > +#define SC_P_MIPI_DSI0_GPIO0_00 118 /*!< > MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, > LSIO.GPIO1.IO27 */ > +#define SC_P_MIPI_DSI0_GPIO0_01 119 /*!< > MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */ > +#define SC_P_MIPI_DSI1_I2C0_SCL 120 /*!< > MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 */ > +#define SC_P_MIPI_DSI1_I2C0_SDA 121 /*!< > MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 */ > +#define SC_P_MIPI_DSI1_GPIO0_00 122 /*!< > MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, > LSIO.GPIO1.IO31 */ > +#define SC_P_MIPI_DSI1_GPIO0_01 123 /*!< > MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124 /*!< */ > +#define SC_P_JTAG_TRST_B 125 /*!< > SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */ > +#define SC_P_PMIC_I2C_SCL 126 /*!< > SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */ > +#define SC_P_PMIC_I2C_SDA 127 /*!< > SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */ > +#define SC_P_PMIC_INT_B 128 /*!< > SCU.DSC.PMIC_INT_B */ > +#define SC_P_SCU_GPIO0_00 129 /*!< > SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, > LSIO.GPIO2.IO03 */ > +#define SC_P_SCU_GPIO0_01 130 /*!< > SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, > SCU.WDOG0.WDOG_OUT */ > +#define SC_P_SCU_PMIC_STANDBY 131 /*!< > SCU.DSC.PMIC_STANDBY */ > +#define SC_P_SCU_BOOT_MODE0 132 /*!< > SCU.DSC.BOOT_MODE0 */ > +#define SC_P_SCU_BOOT_MODE1 133 /*!< > SCU.DSC.BOOT_MODE1 */ > +#define SC_P_SCU_BOOT_MODE2 134 /*!< > SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA */ > +#define SC_P_SCU_BOOT_MODE3 135 /*!< > SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, > SCU.DSC.RTC_CLOCK_OUTPUT_32K */ > +#define SC_P_CSI_D00 136 /*!< > CI_PI.D02, ADMA.SAI0.RXC */ > +#define SC_P_CSI_D01 137 /*!< > CI_PI.D03, ADMA.SAI0.RXD */ > +#define SC_P_CSI_D02 138 /*!< > CI_PI.D04, ADMA.SAI0.RXFS */ > +#define SC_P_CSI_D03 139 /*!< > CI_PI.D05, ADMA.SAI2.RXC */ > +#define SC_P_CSI_D04 140 /*!< > CI_PI.D06, ADMA.SAI2.RXD */ > +#define SC_P_CSI_D05 141 /*!< > CI_PI.D07, ADMA.SAI2.RXFS */ > +#define SC_P_CSI_D06 142 /*!< > CI_PI.D08, ADMA.SAI3.RXC */ > +#define SC_P_CSI_D07 143 /*!< > CI_PI.D09, ADMA.SAI3.RXD */ > +#define SC_P_CSI_HSYNC 144 /*!< > CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS */ > +#define SC_P_CSI_VSYNC 145 /*!< > CI_PI.VSYNC, CI_PI.D01 */ > +#define SC_P_CSI_PCLK 146 /*!< > CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */ > +#define SC_P_CSI_MCLK 147 /*!< > CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */ > +#define SC_P_CSI_EN 148 /*!< CI_PI.EN, > CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */ > +#define SC_P_CSI_RESET 149 /*!< > CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 > */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150 /*!< */ > +#define SC_P_MIPI_CSI0_MCLK_OUT 151 /*!< > MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */ > +#define SC_P_MIPI_CSI0_I2C0_SCL 152 /*!< > MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 */ > +#define SC_P_MIPI_CSI0_I2C0_SDA 153 /*!< > MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 */ > +#define SC_P_MIPI_CSI0_GPIO0_01 154 /*!< > MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */ > +#define SC_P_MIPI_CSI0_GPIO0_00 155 /*!< > MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */ > +#define SC_P_QSPI0A_DATA0 156 /*!< > LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */ > +#define SC_P_QSPI0A_DATA1 157 /*!< > LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */ > +#define SC_P_QSPI0A_DATA2 158 /*!< > LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */ > +#define SC_P_QSPI0A_DATA3 159 /*!< > LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */ > +#define SC_P_QSPI0A_DQS 160 /*!< > LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */ > +#define SC_P_QSPI0A_SS0_B 161 /*!< > LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */ > +#define SC_P_QSPI0A_SS1_B 162 /*!< > LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */ > +#define SC_P_QSPI0A_SCLK 163 /*!< > LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164 /*!< */ > +#define SC_P_QSPI0B_SCLK 165 /*!< > LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */ > +#define SC_P_QSPI0B_DATA0 166 /*!< > LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO3.IO18 */ > +#define SC_P_QSPI0B_DATA1 167 /*!< > LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO3.IO19 */ > +#define SC_P_QSPI0B_DATA2 168 /*!< > LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */ > +#define SC_P_QSPI0B_DATA3 169 /*!< > LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */ > +#define SC_P_QSPI0B_DQS 170 /*!< > LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 */ > +#define SC_P_QSPI0B_SS0_B 171 /*!< > LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */ > +#define SC_P_QSPI0B_SS1_B 172 /*!< > LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO3.IO24 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173 /*!< */ > +/*@}*/ > + > +#endif /* SC_PADS_H */ > + > diff --git a/arch/arm/include/asm/arch-imx8/sci/ipc.h > b/arch/arm/include/asm/arch-imx8/sci/ipc.h > new file mode 100755 > index 0000000000..3759ac4c45 > --- /dev/null > +++ b/arch/arm/include/asm/arch-imx8/sci/ipc.h > @@ -0,0 +1,67 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * Header file for the IPC implementation. > + */ > + > +#ifndef SC_IPC_H > +#define SC_IPC_H > + > +/* Includes */ > + > +#include <asm/arch/sci/types.h> > + > +/* Defines */ > + > +/* Types */ > + > +/* Functions */ > + > +/*! > + * This function opens an IPC channel. > + * > + * @param[out] ipc return pointer for ipc handle > + * @param[in] id id of channel to open > + * > + * @return Returns an error code (SC_ERR_NONE = success, SC_ERR_IPC > + * otherwise). > + * > + * The \a id parameter is implementation specific. Could be an MU > + * address, pointer to a driver path, channel index, etc. > + */ > +sc_err_t sc_ipc_open(sc_ipc_t *ipc, sc_ipc_id_t id); > + > +/*! > + * This function closes an IPC channel. > + * > + * @param[in] ipc id of channel to close > + */ > +void sc_ipc_close(sc_ipc_t ipc); > + > +/*! > + * This function reads a message from an IPC channel. > + * > + * @param[in] ipc id of channel read from > + * @param[out] data pointer to message buffer to read > + * > + * This function will block if no message is available to be read. > + */ > +void sc_ipc_read(sc_ipc_t ipc, void *data); > + > +/*! > + * This function writes a message to an IPC channel. > + * > + * @param[in] ipc id of channel to write to > + * @param[in] data pointer to message buffer to write > + * > + * This function will block if the outgoing buffer is full. > + */ > +void sc_ipc_write(sc_ipc_t ipc, void *data); > + > +#endif /* SC_IPC_H */ > + > diff --git a/arch/arm/include/asm/arch-imx8/sci/rpc.h > b/arch/arm/include/asm/arch-imx8/sci/rpc.h > new file mode 100755 > index 0000000000..afb891e2c5 > --- /dev/null > +++ b/arch/arm/include/asm/arch-imx8/sci/rpc.h > @@ -0,0 +1,131 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * Header file for the RPC implementation. > + */ > + > +#ifndef SC_RPC_H > +#define SC_RPC_H > + > +/* Includes */ > + > +#include <asm/arch/sci/types.h> > +#include <asm/arch/sci/ipc.h> > + > +/* Defines */ > + > +#define SC_RPC_VERSION 1U > + > +#define SC_RPC_MAX_MSG 8U > + > +#define RPC_VER(MSG) ((MSG)->version) > +#define RPC_SIZE(MSG) ((MSG)->size) > +#define RPC_SVC(MSG) ((MSG)->svc) > +#define RPC_FUNC(MSG) ((MSG)->func) > +#define RPC_R8(MSG) ((MSG)->func) > +#define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4U]) > +#define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2U]) > +#define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[(IDX)]) > +#define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U]) > +#define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2U]) > +#define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[(IDX)]) > + > +#define SC_RPC_SVC_UNKNOWN 0U > +#define SC_RPC_SVC_RETURN 1U > +#define SC_RPC_SVC_PM 2U > +#define SC_RPC_SVC_RM 3U > +#define SC_RPC_SVC_TIMER 5U > +#define SC_RPC_SVC_PAD 6U > +#define SC_RPC_SVC_MISC 7U > +#define SC_RPC_SVC_IRQ 8U > +#define SC_RPC_SVC_ABORT 9U > + > +#define SC_RPC_ASYNC_STATE_RD_START 0U > +#define SC_RPC_ASYNC_STATE_RD_ACTIVE 1U > +#define SC_RPC_ASYNC_STATE_RD_DONE 2U > +#define SC_RPC_ASYNC_STATE_WR_START 3U > +#define SC_RPC_ASYNC_STATE_WR_ACTIVE 4U > +#define SC_RPC_ASYNC_STATE_WR_DONE 5U > + > +#define SC_RPC_MU_GIR_SVC 0x1U > +#define SC_RPC_MU_GIR_DBG 0x8U > + > +/* Types */ > + > +typedef uint8_t sc_rpc_svc_t; > + > +typedef struct sc_rpc_msg_s > +{ > + uint8_t version; > + uint8_t size; > + uint8_t svc; > + uint8_t func; > + union > + { > + int32_t i32[(SC_RPC_MAX_MSG - 1U)]; > + int16_t i16[(SC_RPC_MAX_MSG - 1U) * 2U]; > + int8_t i8[(SC_RPC_MAX_MSG - 1U) * 4U]; > + uint32_t u32[(SC_RPC_MAX_MSG - 1U)]; > + uint16_t u16[(SC_RPC_MAX_MSG - 1U) * 2U]; > + uint8_t u8[(SC_RPC_MAX_MSG - 1U) * 4U]; > + } DATA; > +} sc_rpc_msg_t; > + > +typedef uint8_t sc_rpc_async_state_t; > + > +typedef struct sc_rpc_async_msg_s > +{ > + sc_rpc_async_state_t state; > + uint8_t wordIdx; > + sc_rpc_msg_t msg; > + uint32_t timeStamp; > +} sc_rpc_async_msg_t; > + > +/* Functions */ > + > +/*! > + * This is an internal function to send an RPC message over an IPC > + * channel. It is called by client-side SCFW API function shims. > + * > + * @param[in] ipc IPC handle > + * @param[in,out] msg handle to a message > + * @param[in] no_resp response flag > + * > + * If \a no_resp is SC_FALSE then this function waits for a response > + * and returns the result in \a msg. > + */ > +void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, sc_bool_t no_resp); > + > +/*! > + * This is an internal function to dispath an RPC call that has > + * arrived via IPC over an MU. It is called by server-side SCFW. > + * > + * @param[in] mu MU message arrived on > + * @param[in,out] msg handle to a message > + * > + * The function result is returned in \a msg. > + */ > +void sc_rpc_dispatch(sc_rsrc_t mu, sc_rpc_msg_t *msg); > + > +/*! > + * This function translates an RPC message and forwards on to the > + * normal RPC API. It is used only by hypervisors. > + * > + * @param[in] ipc IPC handle > + * @param[in,out] msg handle to a message > + * > + * This function decodes a message, calls macros to translate the > + * resources, pads, addresses, partitions, memory regions, etc. and > + * then forwards on to the hypervisors SCFW API.Return results are > + * translated back abd placed back into the message to be returned > + * to the original API. > + */ > +void sc_rpc_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg); > + > +#endif /* SC_RPC_H */ > + > diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h > b/arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h > new file mode 100755 > index 0000000000..1e266c39b4 > --- /dev/null > +++ b/arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h > @@ -0,0 +1,160 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * Header file containing the public API for the System Controller (SC) > + * Interrupt (IRQ) function. > + * > + * @addtogroup IRQ_SVC (SVC) Interrupt Service > + * > + * Module for the Interrupt (IRQ) service. > + * > + * @{ > + */ > + > +#ifndef SC_IRQ_API_H > +#define SC_IRQ_API_H > + > +/* Includes */ > + > +#include <asm/arch/sci/types.h> > + > +/* Defines */ > + > +#define SC_IRQ_NUM_GROUP 4U /*!< Number of groups */ > + > +/*! > + * @name Defines for sc_irq_group_t > + */ > +/*@{*/ > +#define SC_IRQ_GROUP_TEMP 0U /*!< Temp interrupts */ > +#define SC_IRQ_GROUP_WDOG 1U /*!< Watchdog interrupts */ > +#define SC_IRQ_GROUP_RTC 2U /*!< RTC interrupts */ > +#define SC_IRQ_GROUP_WAKE 3U /*!< Wakeup interrupts */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_irq_temp_t > + */ > +/*@{*/ > +#define SC_IRQ_TEMP_HIGH (1U << 0U) /*!< Temp alarm > interrupt */ > +#define SC_IRQ_TEMP_CPU0_HIGH (1U << 1U) /*!< CPU0 temp alarm > interrupt */ > +#define SC_IRQ_TEMP_CPU1_HIGH (1U << 2U) /*!< CPU1 temp alarm > interrupt */ > +#define SC_IRQ_TEMP_GPU0_HIGH (1U << 3U) /*!< GPU0 temp > alarm interrupt */ > +#define SC_IRQ_TEMP_GPU1_HIGH (1U << 4U) /*!< GPU1 temp > alarm interrupt */ > +#define SC_IRQ_TEMP_DRC0_HIGH (1U << 5U) /*!< DRC0 temp alarm > interrupt */ > +#define SC_IRQ_TEMP_DRC1_HIGH (1U << 6U) /*!< DRC1 temp alarm > interrupt */ > +#define SC_IRQ_TEMP_VPU_HIGH (1U << 7U) /*!< DRC1 temp > alarm interrupt */ > +#define SC_IRQ_TEMP_PMIC0_HIGH (1U << 8U) /*!< PMIC0 temp > alarm interrupt */ > +#define SC_IRQ_TEMP_PMIC1_HIGH (1U << 9U) /*!< PMIC1 temp > alarm interrupt */ > +#define SC_IRQ_TEMP_LOW (1U << 10U) /*!< Temp alarm > interrupt */ > +#define SC_IRQ_TEMP_CPU0_LOW (1U << 11U) /*!< CPU0 temp > alarm interrupt */ > +#define SC_IRQ_TEMP_CPU1_LOW (1U << 12U) /*!< CPU1 temp > alarm interrupt */ > +#define SC_IRQ_TEMP_GPU0_LOW (1U << 13U) /*!< GPU0 temp > alarm interrupt */ > +#define SC_IRQ_TEMP_GPU1_LOW (1U << 14U) /*!< GPU1 temp > alarm interrupt */ > +#define SC_IRQ_TEMP_DRC0_LOW (1U << 15U) /*!< DRC0 temp > alarm interrupt */ > +#define SC_IRQ_TEMP_DRC1_LOW (1U << 16U) /*!< DRC1 temp > alarm interrupt */ > +#define SC_IRQ_TEMP_VPU_LOW (1U << 17U) /*!< DRC1 temp > alarm interrupt */ > +#define SC_IRQ_TEMP_PMIC0_LOW (1U << 18U) /*!< PMIC0 temp > alarm interrupt */ > +#define SC_IRQ_TEMP_PMIC1_LOW (1U << 19U) /*!< PMIC1 temp > alarm interrupt */ > +#define SC_IRQ_TEMP_PMIC2_HIGH (1U << 20U) /*!< PMIC2 temp > alarm interrupt */ > +#define SC_IRQ_TEMP_PMIC2_LOW (1U << 21U) /*!< PMIC2 temp > alarm interrupt */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_irq_wdog_t > + */ > +/*@{*/ > +#define SC_IRQ_WDOG (1U << 0U /*!< Watchdog > interrupt */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_irq_rtc_t > + */ > +/*@{*/ > +#define SC_IRQ_RTC (1U << 0U) /*!< RTC interrupt */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_irq_wake_t > + */ > +/*@{*/ > +#define SC_IRQ_BUTTON (1U << 0U) /*!< Button interrupt > */ > +#define SC_IRQ_PAD (1U << 1U) /*!< Pad wakeup */ > +/*@}*/ > + > +/* Types */ > + > +/*! > + * This type is used to declare an interrupt group. > + */ > +typedef uint8_t sc_irq_group_t; > + > +/*! > + * This type is used to declare a bit mask of temp interrupts. > + */ > +typedef uint8_t sc_irq_temp_t; > + > +/*! > + * This type is used to declare a bit mask of watchdog interrupts. > + */ > +typedef uint8_t sc_irq_wdog_t; > + > +/*! > + * This type is used to declare a bit mask of RTC interrupts. > + */ > +typedef uint8_t sc_irq_rtc_t; > + > +/*! > + * This type is used to declare a bit mask of wakeup interrupts. > + */ > +typedef uint8_t sc_irq_wake_t; > + > +/* Functions */ > + > +/*! > + * This function enables/disables interrupts. If pending interrupts > + * are unmasked, an interrupt will be triggered. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource MU channel > + * @param[in] group group the interrupts are in > + * @param[in] mask mask of interrupts to affect > + * @param[in] enable state to change interrupts to > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if group invalid > + */ > +sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_irq_group_t group, uint32_t mask, sc_bool_t enable); > + > +/*! > + * This function returns the current interrupt status (regardless if > + * masked). Automatically clears pending interrupts. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource MU channel > + * @param[in] group groups the interrupts are in > + * @param[in] status status of interrupts > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if group invalid > + * > + * The returned \a status may show interrupts pending that are > + * currently masked. > + */ > +sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_irq_group_t group, uint32_t *status); > + > +#endif /* SC_IRQ_API_H */ > + > +/**@}*/ > + > diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h > b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h > new file mode 100755 > index 0000000000..210dd04c7c > --- /dev/null > +++ b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h > @@ -0,0 +1,523 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * Header file containing the public API for the System Controller (SC) > + * Miscellaneous (MISC) function. > + * > + * @addtogroup MISC_SVC (SVC) Miscellaneous Service > + * > + * Module for the Miscellaneous (MISC) service. > + * > + * @{ > + */ > + > +#ifndef SC_MISC_API_H > +#define SC_MISC_API_H > + > +/* Includes */ > + > +#include <asm/arch/sci/types.h> > +#include <asm/arch/sci/svc/rm/api.h> > + > +/* Defines */ > + > +/*! > + * @name Defines for type widths > + */ > +/*@{*/ > +#define SC_MISC_DMA_GRP_W 5U /*!< Width of > sc_misc_dma_group_t */ > +/*@}*/ > + > +/*! Max DMA channel priority group */ > +#define SC_MISC_DMA_GRP_MAX 31U > + > +/*! > + * @name Defines for sc_misc_boot_status_t > + */ > +/*@{*/ > +#define SC_MISC_BOOT_STATUS_SUCCESS 0U /*!< Success */ > +#define SC_MISC_BOOT_STATUS_SECURITY 1U /*!< Security violation > */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_misc_seco_auth_cmd_t > + */ > +/*@{*/ > +#define SC_MISC_SECO_AUTH_SECO_FW 0U /*!< SECO Firmware > */ > +#define SC_MISC_SECO_AUTH_HDMI_TX_FW 1U /*!< HDMI TX > Firmware */ > +#define SC_MISC_SECO_AUTH_HDMI_RX_FW 2U /*!< HDMI RX > Firmware */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_misc_temp_t > + */ > +/*@{*/ > +#define SC_MISC_TEMP 0U /*!< Temp sensor */ > +#define SC_MISC_TEMP_HIGH 1U /*!< Temp high alarm > */ > +#define SC_MISC_TEMP_LOW 2U /*!< Temp low alarm > */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_misc_seco_auth_cmd_t > + */ > +/*@{*/ > +#define SC_MISC_AUTH_CONTAINER 0U /*!< Authenticate > container */ > +#define SC_MISC_VERIFY_IMAGE 1U /*!< Verify image */ > +#define SC_MISC_REL_CONTAINER 2U /*!< Release container > */ > +/*@}*/ > + > +/* Types */ > + > +/*! > + * This type is used to store a DMA channel priority group. > + */ > +typedef uint8_t sc_misc_dma_group_t; > + > +/*! > + * This type is used report boot status. > + */ > +typedef uint8_t sc_misc_boot_status_t; > + > +/*! > + * This type is used to issue SECO authenticate commands. > + */ > +typedef uint8_t sc_misc_seco_auth_cmd_t; > + > +/*! > + * This type is used report boot status. > + */ > +typedef uint8_t sc_misc_temp_t; > + > +/* Functions */ > + > +/*! > + * @name Control Functions > + * @{ > + */ > + > +/*! > + * This function sets a miscellaneous control value. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource resource the control is associated with > + * @param[in] ctrl control to change > + * @param[in] val value to apply to the control > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent > + * of the owner > + * > + * Refer to the [Control List](@ref CONTROLS) for valid control values. > + */ > +sc_err_t sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_ctrl_t ctrl, uint32_t val); > + > +/*! > + * This function gets a miscellaneous control value. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource resource the control is associated with > + * @param[in] ctrl control to get > + * @param[out] val pointer to return the control value > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent > + * of the owner > + * > + * Refer to the [Control List](@ref CONTROLS) for valid control values. > + */ > +sc_err_t sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_ctrl_t ctrl, uint32_t *val); > + > +/* @} */ > + > +/*! > + * @name DMA Functions > + * @{ > + */ > + > +/*! > + * This function configures the max DMA channel priority group for a > + * partition. > + * > + * @param[in] ipc IPC handle > + * @param[in] pt handle of partition to assign \a max > + * @param[in] max max priority group (0-31) > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the parent > + * of the affected partition > + * > + * Valid \a max range is 0-31 with 0 being the lowest and 31 the highest. > + * Default is the max priority group for the parent partition of \a pt. > + */ > +sc_err_t sc_misc_set_max_dma_group(sc_ipc_t ipc, sc_rm_pt_t pt, > + sc_misc_dma_group_t max); > + > +/*! > + * This function configures the priority group for a DMA channel. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource DMA channel resource > + * @param[in] group priority group (0-31) > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the owner or parent > + * of the owner of the DMA channel > + * > + * Valid \a group range is 0-31 with 0 being the lowest and 31 the highest. > + * The max value of \a group is limited by the partition max set using > + * sc_misc_set_max_dma_group(). > + */ > +sc_err_t sc_misc_set_dma_group(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_misc_dma_group_t group); > + > +/* @} */ > + > +/*! > + * @name Security Functions > + * @{ > + */ > + > +/*! > + * This function loads a SECO image. > + * > + * @param[in] ipc IPC handle > + * @param[in] addr_src address of image source > + * @param[in] addr_dst address of image destination > + * @param[in] len lenth of image to load > + * @param[in] fw SC_TRUE = firmware load > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors codes: > + * - SC_ERR_PARM if word fuse index param out of range or invalid > + * - SC_ERR_UNAVAILABLE if SECO not available > + * > + * This is used to load images via the SECO. Examples include SECO > + * Firmware and IVT/CSF data used for authentication. These are usually > + * loaded into SECO TCM. \a addr_src is in secure memory. > + * > + * See the Security Reference Manual (SRM) for more info. > + */ > +sc_err_t sc_misc_seco_image_load(sc_ipc_t ipc, sc_faddr_t addr_src, > + sc_faddr_t addr_dst, uint32_t len, sc_bool_t fw); > + > +/*! > + * This function is used to authenticate a SECO image or command. > + * > + * @param[in] ipc IPC handle > + * @param[in] cmd authenticate command > + * @param[in] addr address of/or metadata > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors codes: > + * - SC_ERR_PARM if word fuse index param out of range or invalid > + * - SC_ERR_UNAVAILABLE if SECO not available > + * > + * This is used to authenticate a SECO image or issue a security > + * command. \a addr often points to an container. It is also > + * just data (or even unused) for some commands. > + * > + * See the Security Reference Manual (SRM) for more info. > + */ > +sc_err_t sc_misc_seco_authenticate(sc_ipc_t ipc, > + sc_misc_seco_auth_cmd_t cmd, sc_faddr_t addr); > + > +/*! > + * This function securely writes a group of fuse words. > + * > + * @param[in] ipc IPC handle > + * @param[in] addr address of message block > + * > + * @return Returns and error code (SC_ERR_NONE = success). > + * > + * Return errors codes: > + * - SC_ERR_UNAVAILABLE if SECO not available > + * > + * Note \a addr must be a pointer into secure RAM. The contents at > + * this location are a signed fuse command message block. > + * > + * See the Security Reference Manual (SRM) for more info. > + */ > +sc_err_t sc_misc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr); > + > +/*! > + * This function securely enables debug. > + * > + * @param[in] ipc IPC handle > + * @param[in] addr address of message block > + * > + * @return Returns and error code (SC_ERR_NONE = success). > + * > + * Return errors codes: > + * - SC_ERR_UNAVAILABLE if SECO not available > + * > + * Note \a addr must be a pointer into secure RAM. The contents at > + * this location are a signed fuse command message block. > + * > + * See the Security Reference Manual (SRM) for more info. > + */ > +sc_err_t sc_misc_seco_enable_debug(sc_ipc_t ipc, sc_faddr_t addr); > + > +/*! > + * This function updates the lifecycle of the device. > + * > + * @param[in] ipc IPC handle > + * @param[in] lifecycle new lifecycle > + * > + * @return Returns and error code (SC_ERR_NONE = success). > + * > + * Return errors codes: > + * - SC_ERR_UNAVAILABLE if SECO not available > + * > + * See the Security Reference Manual (SRM) for more info. > + */ > +sc_err_t sc_misc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t lifecycle); > + > +/*! > + * This function securely reverses the lifecycle. > + * > + * @param[in] ipc IPC handle > + * @param[in] addr address of message block > + * > + * @return Returns and error code (SC_ERR_NONE = success). > + * > + * Return errors codes: > + * - SC_ERR_UNAVAILABLE if SECO not available > + * > + * Note \a addr must be a pointer into secure RAM. The contents at > + * this location are a signed fuse command message block. > + * > + * See the Security Reference Manual (SRM) for more info. > + */ > +sc_err_t sc_misc_seco_return_lifecycle(sc_ipc_t ipc, sc_faddr_t addr); > + > +/*! > + * This function is used to return the SECO FW build info. > + * > + * @param[in] ipc IPC handle > + * @param[out] version pointer to return build number > + * @param[out] commit pointer to return commit ID (git SHA-1) > + */ > +void sc_misc_seco_build_info(sc_ipc_t ipc, uint32_t *version, > + uint32_t *commit); > + > +/* @} */ > + > +/*! > + * @name Debug Functions > + * @{ > + */ > + > +/*! > + * This function is used output a debug character from the SCU UART. > + * > + * @param[in] ipc IPC handle > + * @param[in] ch character to output > + */ > +void sc_misc_debug_out(sc_ipc_t ipc, uint8_t ch); > + > +/*! > + * This function starts/stops emulation waveform capture. > + * > + * @param[in] ipc IPC handle > + * @param[in] enable flag to enable/disable capture > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_UNAVAILABLE if not running on emulation > + */ > +sc_err_t sc_misc_waveform_capture(sc_ipc_t ipc, sc_bool_t enable); > + > +/*! > + * This function is used to return the SCFW build info. > + * > + * @param[in] ipc IPC handle > + * @param[out] build pointer to return build number > + * @param[out] commit pointer to return commit ID (git SHA-1) > + */ > +void sc_misc_build_info(sc_ipc_t ipc, uint32_t *build, > + uint32_t *commit); > + > +/*! > + * This function is used to return the device's unique ID. > + * > + * @param[in] ipc IPC handle > + * @param[out] id_l pointer to return lower 32-bit of ID [31:0] > + * @param[out] id_h pointer to return upper 32-bits of ID > [63:32] > + */ > +void sc_misc_unique_id(sc_ipc_t ipc, uint32_t *id_l, > + uint32_t *id_h); > + > +/* @} */ > + > +/*! > + * @name Other Functions > + * @{ > + */ > + > +/*! > + * This function configures the ARI match value for PCIe/SATA resources. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource match resource > + * @param[in] resource_mst PCIe/SATA master to match > + * @param[in] ari ARI to match > + * @param[in] enable enable match or not > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the owner or parent > + * of the owner of the resource and translation > + * > + * For PCIe, the ARI is the 16-bit value that includes the bus number, > + * device number, and function number. For SATA, this value includes the > + * FISType and PM_Port. > + */ > +sc_err_t sc_misc_set_ari(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_rsrc_t resource_mst, uint16_t ari, sc_bool_t enable); > + > +/*! > + * This function reports boot status. > + * > + * @param[in] ipc IPC handle > + * @param[in] status boot status > + * > + * This is used by SW partitions to report status of boot. This is > + * normally used to report a boot failure. > + */ > +void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status); > + > +/*! > + * This function tells the SCFW that a CPU is done booting. > + * > + * @param[in] ipc IPC handle > + * @param[in] cpu CPU that is done booting > + * > + * This is called by early booting CPUs to report they are done with > + * initialization. After starting early CPUs, the SCFW halts the > + * booting process until they are done. During this time, early > + * CPUs can call the SCFW with lower latency as the SCFW is idle. > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the CPU owner > + */ > +sc_err_t sc_misc_boot_done(sc_ipc_t ipc, sc_rsrc_t cpu); > + > +/*! > + * This function reads a given fuse word index. > + * > + * @param[in] ipc IPC handle > + * @param[in] word fuse word index > + * @param[out] val fuse read value > + * > + * @return Returns and error code (SC_ERR_NONE = success). > + * > + * Return errors codes: > + * - SC_ERR_PARM if word fuse index param out of range or invalid > + * - SC_ERR_NOACCESS if read operation failed > + * - SC_ERR_LOCKED if read operation is locked > + */ > +sc_err_t sc_misc_otp_fuse_read(sc_ipc_t ipc, uint32_t word, uint32_t *val); > + > +/*! > + * This function writes a given fuse word index. > + * > + * @param[in] ipc IPC handle > + * @param[in] word fuse word index > + * @param[in] val fuse write value > + * > + * @return Returns and error code (SC_ERR_NONE = success). > + * > + * Return errors codes: > + * - SC_ERR_PARM if word fuse index param out of range or invalid > + * - SC_ERR_NOACCESS if write operation failed > + * - SC_ERR_LOCKED if write operation is locked > + */ > +sc_err_t sc_misc_otp_fuse_write(sc_ipc_t ipc, uint32_t word, uint32_t val); > + > +/*! > + * This function sets a temp sensor alarm. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource resource with sensor > + * @param[in] temp alarm to set > + * @param[in] celsius whole part of temp to set > + * @param[in] tenths fractional part of temp to set > + * > + * @return Returns and error code (SC_ERR_NONE = success). > + * > + * This function will enable the alarm interrupt if the temp requested is > + * not the min/max temp. This enable automatically clears when the alarm > + * occurs and this function has to be called again to re-enable. > + * > + * Return errors codes: > + * - SC_ERR_PARM if parameters invalid > + */ > +sc_err_t sc_misc_set_temp(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_misc_temp_t temp, int16_t celsius, int8_t tenths); > + > +/*! > + * This function gets a temp sensor value. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource resource with sensor > + * @param[in] temp value to get (sensor or alarm) > + * @param[out] celsius whole part of temp to get > + * @param[out] tenths fractional part of temp to get > + * > + * @return Returns and error code (SC_ERR_NONE = success). > + * > + * Return errors codes: > + * - SC_ERR_PARM if parameters invalid > + */ > +sc_err_t sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_misc_temp_t temp, int16_t *celsius, int8_t *tenths); > + > +/*! > + * This function returns the boot device. > + * > + * @param[in] ipc IPC handle > + * @param[out] dev pointer to return boot device > + */ > +void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *dev); > + > +/*! > + * This function returns the current status of the ON/OFF button. > + * > + * @param[in] ipc IPC handle > + * @param[out] status pointer to return button status > + */ > +void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status); > + > +/* @} */ > + > +#endif /* SC_MISC_API_H */ > + > +/**@}*/ > + > diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h > b/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h > new file mode 100755 > index 0000000000..76cb0dab9a > --- /dev/null > +++ b/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h > @@ -0,0 +1,568 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * Header file containing the public API for the System Controller (SC) > + * Pad Control (PAD) function. > + * > + * @addtogroup PAD_SVC (SVC) Pad Service > + * > + * Module for the Pad Control (PAD) service. > + * > + * @details > + * > + * Pad configuration is managed by SC firmware. The pad configuration > + * features supported by the SC firmware include: > + * > + * - Configuring the mux, input/output connection, and low-power isolation > + mode. > + * - Configuring the technology-specific pad setting such as drive strength, > + * pullup/pulldown, etc. > + * - Configuring compensation for pad groups with dual voltage capability. > + * > + * Pad functions fall into one of three categories. Generic functions are > + * common to all SoCs and all process technologies. SoC functions are raw > + * low-level functions. Technology-specific functions are specific to the > + * process technology. > + * > + * The list of pads is SoC specific. Refer to the SoC [Pad List](@ref PADS) > + * for valid pad values. Note that all pads exist on a die but may or > + * may not be brought out by the specific package. Mapping of pads to > + * package pins/balls is documented in the associated Data Sheet. Some pads > + * may not be brought out because the part (die+package) is defeatured and > + * some pads may connect to the substrate in the package. > + * > + * Some pads (SC_P_COMP_*) that can be specified are not individual pads > + * but are in fact pad groups. These groups have additional configuration > + * that can be done using the sc_pad_set_gp_28fdsoi_comp() function. More > + * info on these can be found in the associated Reference Manual. > + * > + * Pads are managed as a resource by the Resource Manager (RM). They > have > + * assigned owners and only the owners can configure the pads. Some of the > + * pads are reserved for use by the SCFW itself and this can be overriden > + * with the implementation of board_config_sc(). Additionally, pads may > + * be assigned to various other partitions via the implementation of > + * board_system_config(). > + * > + * Note muxing two input pads to the same IP functional signal will > + * result in undefined behavior. > + * @{ > + */ > + > +#ifndef SC_PAD_API_H > +#define SC_PAD_API_H > + > +/* Includes */ > + > +#include <asm/arch/sci/types.h> > +#include <asm/arch/sci/svc/rm/api.h> > + > +/* Defines */ > + > +/*! > + * @name Defines for type widths > + */ > +/*@{*/ > +#define SC_PAD_MUX_W 3U /*!< Width of mux parameter > */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_pad_config_t > + */ > +/*@{*/ > +#define SC_PAD_CONFIG_NORMAL 0U /*!< Normal */ > +#define SC_PAD_CONFIG_OD 1U /*!< Open Drain */ > +#define SC_PAD_CONFIG_OD_IN 2U /*!< Open Drain and input */ > +#define SC_PAD_CONFIG_OUT_IN 3U /*!< Output and input */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_pad_iso_t > + */ > +/*@{*/ > +#define SC_PAD_ISO_OFF 0U /*!< ISO latch is transparent */ > +#define SC_PAD_ISO_EARLY 1U /*!< Follow EARLY_ISO */ > +#define SC_PAD_ISO_LATE 2U /*!< Follow LATE_ISO */ > +#define SC_PAD_ISO_ON 3U /*!< ISO latched data is held */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_pad_28fdsoi_dse_t > + */ > +/*@{*/ > +#define SC_PAD_28FDSOI_DSE_18V_1MA 0U /*!< Drive strength of > 1mA for 1.8v */ > +#define SC_PAD_28FDSOI_DSE_18V_2MA 1U /*!< Drive strength of > 2mA for 1.8v */ > +#define SC_PAD_28FDSOI_DSE_18V_4MA 2U /*!< Drive strength of > 4mA for 1.8v */ > +#define SC_PAD_28FDSOI_DSE_18V_6MA 3U /*!< Drive strength of > 6mA for 1.8v */ > +#define SC_PAD_28FDSOI_DSE_18V_8MA 4U /*!< Drive strength of > 8mA for 1.8v */ > +#define SC_PAD_28FDSOI_DSE_18V_10MA 5U /*!< Drive strength of > 10mA for 1.8v */ > +#define SC_PAD_28FDSOI_DSE_18V_12MA 6U /*!< Drive strength of > 12mA for 1.8v */ > +#define SC_PAD_28FDSOI_DSE_18V_HS 7U /*!< High-speed drive > strength for 1.8v */ > +#define SC_PAD_28FDSOI_DSE_33V_2MA 0U /*!< Drive strength of > 2mA for 3.3v */ > +#define SC_PAD_28FDSOI_DSE_33V_4MA 1U /*!< Drive strength of > 4mA for 3.3v */ > +#define SC_PAD_28FDSOI_DSE_33V_8MA 2U /*!< Drive strength of > 8mA for 3.3v */ > +#define SC_PAD_28FDSOI_DSE_33V_12MA 3U /*!< Drive strength of > 12mA for 3.3v */ > +#define SC_PAD_28FDSOI_DSE_DV_HIGH 0U /*!< High drive strength > for dual volt */ > +#define SC_PAD_28FDSOI_DSE_DV_LOW 1U /*!< Low drive strength > for dual volt */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_pad_28fdsoi_ps_t > + */ > +/*@{*/ > +#define SC_PAD_28FDSOI_PS_KEEPER 0U /*!< Bus-keeper (only valid for > 1.8v) */ > +#define SC_PAD_28FDSOI_PS_PU 1U /*!< Pull-up */ > +#define SC_PAD_28FDSOI_PS_PD 2U /*!< Pull-down */ > +#define SC_PAD_28FDSOI_PS_NONE 3U /*!< No pull (disabled) */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_pad_28fdsoi_pus_t > + */ > +/*@{*/ > +#define SC_PAD_28FDSOI_PUS_30K_PD 0U /*!< 30K pull-down */ > +#define SC_PAD_28FDSOI_PUS_100K_PU 1U /*!< 100K pull-up */ > +#define SC_PAD_28FDSOI_PUS_3K_PU 2U /*!< 3K pull-up */ > +#define SC_PAD_28FDSOI_PUS_30K_PU 3U /*!< 30K pull-up */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_pad_wakeup_t > + */ > +/*@{*/ > +#define SC_PAD_WAKEUP_OFF 0U /*!< Off */ > +#define SC_PAD_WAKEUP_CLEAR 1U /*!< Clears pending flag */ > +#define SC_PAD_WAKEUP_LOW_LVL 4U /*!< Low level */ > +#define SC_PAD_WAKEUP_FALL_EDGE 5U /*!< Falling edge */ > +#define SC_PAD_WAKEUP_RISE_EDGE 6U /*!< Rising edge */ > +#define SC_PAD_WAKEUP_HIGH_LVL 7U /*!< High-level */ > +/*@}*/ > + > +/* Types */ > + > +/*! > + * This type is used to declare a pad config. It determines how the > + * output data is driven, pull-up is controlled, and input signal is > + * connected. Normal and OD are typical and only connect the input > + * when the output is not driven. The IN options are less common and > + * force an input connection even when driving the output. > + */ > +typedef uint8_t sc_pad_config_t; > + > +/*! > + * This type is used to declare a pad low-power isolation config. > + * ISO_LATE is the most common setting. ISO_EARLY is only used when > + * an output pad is directly determined by another input pad. The > + * other two are only used when SW wants to directly contol isolation. > + */ > +typedef uint8_t sc_pad_iso_t; > + > +/*! > + * This type is used to declare a drive strength. Note it is specific > + * to 28FDSOI. Also note that valid values depend on the pad type. > + */ > +typedef uint8_t sc_pad_28fdsoi_dse_t; > + > +/*! > + * This type is used to declare a pull select. Note it is specific > + * to 28FDSOI. > + */ > +typedef uint8_t sc_pad_28fdsoi_ps_t; > + > +/*! > + * This type is used to declare a pull-up select. Note it is specific > + * to 28FDSOI HSIC pads. > + */ > +typedef uint8_t sc_pad_28fdsoi_pus_t; > + > +/*! > + * This type is used to declare a wakeup mode of a pad. > + */ > +typedef uint8_t sc_pad_wakeup_t; > + > +/* Functions */ > + > +/*! > + * @name Generic Functions > + * @{ > + */ > + > +/*! > + * This function configures the mux settings for a pad. This includes > + * the signal mux, pad config, and low-power isolation mode. > + * > + * @param[in] ipc IPC handle > + * @param[in] pad pad to configure > + * @param[in] mux mux setting > + * @param[in] config pad config > + * @param[in] iso low-power isolation mode > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the pad owner > + * > + * Note muxing two input pads to the same IP functional signal will > + * result in undefined behavior. > + * > + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. > + */ > +sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad, > + uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso); > + > +/*! > + * This function gets the mux settings for a pad. This includes > + * the signal mux, pad config, and low-power isolation mode. > + * > + * @param[in] ipc IPC handle > + * @param[in] pad pad to query > + * @param[out] mux pointer to return mux setting > + * @param[out] config pointer to return pad config > + * @param[out] iso pointer to return low-power isolation mode > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the pad owner > + * > + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. > + */ > +sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pad_t pad, > + uint8_t *mux, sc_pad_config_t *config, sc_pad_iso_t *iso); > + > +/*! > + * This function configures the general purpose pad control. This > + * is technology dependent and includes things like drive strength, > + * slew rate, pull up/down, etc. Refer to the SoC Reference Manual > + * for bit field details. > + * > + * @param[in] ipc IPC handle > + * @param[in] pad pad to configure > + * @param[in] ctrl control value to set > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the pad owner > + * > + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. > + */ > +sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t ctrl); > + > +/*! > + * This function gets the general purpose pad control. This > + * is technology dependent and includes things like drive strength, > + * slew rate, pull up/down, etc. Refer to the SoC Reference Manual > + * for bit field details. > + * > + * @param[in] ipc IPC handle > + * @param[in] pad pad to query > + * @param[out] ctrl pointer to return control value > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the pad owner > + * > + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. > + */ > +sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl); > + > +/*! > + * This function configures the wakeup mode of the pad. > + * > + * @param[in] ipc IPC handle > + * @param[in] pad pad to configure > + * @param[in] wakeup wakeup to set > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the pad owner > + * > + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. > + */ > +sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad, > + sc_pad_wakeup_t wakeup); > + > +/*! > + * This function gets the wakeup mode of a pad. > + * > + * @param[in] ipc IPC handle > + * @param[in] pad pad to query > + * @param[out] wakeup pointer to return wakeup > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the pad owner > + * > + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. > + */ > +sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad, > + sc_pad_wakeup_t *wakeup); > + > +/*! > + * This function configures a pad. > + * > + * @param[in] ipc IPC handle > + * @param[in] pad pad to configure > + * @param[in] mux mux setting > + * @param[in] config pad config > + * @param[in] iso low-power isolation mode > + * @param[in] ctrl control value > + * @param[in] wakeup wakeup to set > + * > + * @see sc_pad_set_mux(). > + * @see sc_pad_set_gp(). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the pad owner > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Note muxing two input pads to the same IP functional signal will > + * result in undefined behavior. > + * > + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. > + */ > +sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux, > + sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl, > + sc_pad_wakeup_t wakeup); > + > +/*! > + * This function gets a pad's config. > + * > + * @param[in] ipc IPC handle > + * @param[in] pad pad to query > + * @param[out] mux pointer to return mux setting > + * @param[out] config pointer to return pad config > + * @param[out] iso pointer to return low-power isolation mode > + * @param[out] ctrl pointer to return control value > + * @param[out] wakeup pointer to return wakeup to set > + * > + * @see sc_pad_set_mux(). > + * @see sc_pad_set_gp(). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the pad owner > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. > + */ > +sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t *mux, > + sc_pad_config_t *config, sc_pad_iso_t *iso, uint32_t *ctrl, > + sc_pad_wakeup_t *wakeup); > + > +/* @} */ > + > +/*! > + * @name SoC Specific Functions > + * @{ > + */ > + > +/*! > + * This function configures the settings for a pad. This setting is SoC > + * specific. > + * > + * @param[in] ipc IPC handle > + * @param[in] pad pad to configure > + * @param[in] val value to set > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the pad owner > + * > + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. > + */ > +sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, uint32_t val); > + > +/*! > + * This function gets the settings for a pad. This setting is SoC > + * specific. > + * > + * @param[in] ipc IPC handle > + * @param[in] pad pad to query > + * @param[out] val pointer to return setting > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the pad owner > + * > + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. > + */ > +sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val); > + > +/* @} */ > + > +/*! > + * @name Technology Specific Functions > + * @{ > + */ > + > +/*! > + * This function configures the pad control specific to 28FDSOI. > + * > + * @param[in] ipc IPC handle > + * @param[in] pad pad to configure > + * @param[in] dse drive strength > + * @param[in] ps pull select > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, > + * - SC_ERR_UNAVAILABLE if process not applicable > + * > + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. > + */ > +sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad, > + sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps); > + > +/*! > + * This function gets the pad control specific to 28FDSOI. > + * > + * @param[in] ipc IPC handle > + * @param[in] pad pad to query > + * @param[out] dse pointer to return drive strength > + * @param[out] ps pointer to return pull select > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, > + * - SC_ERR_UNAVAILABLE if process not applicable > + * > + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. > + */ > +sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad, > + sc_pad_28fdsoi_dse_t *dse, sc_pad_28fdsoi_ps_t *ps); > + > +/*! > + * This function configures the pad control specific to 28FDSOI. > + * > + * @param[in] ipc IPC handle > + * @param[in] pad pad to configure > + * @param[in] dse drive strength > + * @param[in] hys hysteresis > + * @param[in] pus pull-up select > + * @param[in] pke pull keeper enable > + * @param[in] pue pull-up enable > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, > + * - SC_ERR_UNAVAILABLE if process not applicable > + * > + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. > + */ > +sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad, > + sc_pad_28fdsoi_dse_t dse, sc_bool_t hys, sc_pad_28fdsoi_pus_t pus, > + sc_bool_t pke, sc_bool_t pue); > + > +/*! > + * This function gets the pad control specific to 28FDSOI. > + * > + * @param[in] ipc IPC handle > + * @param[in] pad pad to query > + * @param[out] dse pointer to return drive strength > + * @param[out] hys pointer to return hysteresis > + * @param[out] pus pointer to return pull-up select > + * @param[out] pke pointer to return pull keeper enable > + * @param[out] pue pointer to return pull-up enable > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, > + * - SC_ERR_UNAVAILABLE if process not applicable > + * > + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. > + */ > +sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad, > + sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys, sc_pad_28fdsoi_pus_t *pus, > + sc_bool_t *pke, sc_bool_t *pue); > + > +/*! > + * This function configures the compensation control specific to 28FDSOI. > + * > + * @param[in] ipc IPC handle > + * @param[in] pad pad to configure > + * @param[in] compen compensation/freeze mode > + * @param[in] fastfrz fast freeze > + * @param[in] rasrcp compensation code for PMOS > + * @param[in] rasrcn compensation code for NMOS > + * @param[in] nasrc_sel NASRC read select > + * @param[in] psw_ovr 2.5v override > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, > + * - SC_ERR_UNAVAILABLE if process not applicable > + * > + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. > + * > + * Note \a psw_ovr is only applicable to pads supporting 2.5 volt > + * operation (e.g. some Ethernet pads). > + */ > +sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad, > + uint8_t compen, sc_bool_t fastfrz, uint8_t rasrcp, uint8_t rasrcn, > + sc_bool_t nasrc_sel, sc_bool_t psw_ovr); > + > +/*! > + * This function gets the compensation control specific to 28FDSOI. > + * > + * @param[in] ipc IPC handle > + * @param[in] pad pad to query > + * @param[out] compen pointer to return compensation/freeze > mode > + * @param[out] fastfrz pointer to return fast freeze > + * @param[out] rasrcp pointer to return compensation code for > PMOS > + * @param[out] rasrcn pointer to return compensation code for > NMOS > + * @param[out] nasrc_sel pointer to return NASRC read select > + * @param[out] compok pointer to return compensation status > + * @param[out] nasrc pointer to return NASRCP/NASRCN > + * @param[out] psw_ovr pointer to return the 2.5v override > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, > + * - SC_ERR_UNAVAILABLE if process not applicable > + * > + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. > + */ > +sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad, > + uint8_t *compen, sc_bool_t *fastfrz, uint8_t *rasrcp, uint8_t *rasrcn, > + sc_bool_t *nasrc_sel, sc_bool_t *compok, uint8_t *nasrc, sc_bool_t > *psw_ovr); > + > +/* @} */ > + > +#endif /* SC_PAD_API_H */ > + > +/**@}*/ > + > diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h > b/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h > new file mode 100755 > index 0000000000..25d8f063e6 > --- /dev/null > +++ b/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h > @@ -0,0 +1,686 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * Header file containing the public API for the System Controller (SC) > + * Power Management (PM) function. This includes functions for power state > + * control, clock control, reset control, and wake-up event control. > + * > + * @addtogroup PM_SVC (SVC) Power Management Service > + * > + * Module for the Power Management (PM) service. > + * > + * @{ > + */ > + > +#ifndef SC_PM_API_H > +#define SC_PM_API_H > + > +/* Includes */ > + > +#include <asm/arch/sci/types.h> > +#include <asm/arch/sci/svc/rm/api.h> > + > +/* Defines */ > + > +/*! > + * @name Defines for type widths > + */ > +/*@{*/ > +#define SC_PM_POWER_MODE_W 2U /*!< Width of > sc_pm_power_mode_t */ > +#define SC_PM_CLOCK_MODE_W 3U /*!< Width of > sc_pm_clock_mode_t */ > +#define SC_PM_RESET_TYPE_W 2U /*!< Width of > sc_pm_reset_type_t */ > +#define SC_PM_RESET_REASON_W 3U /*!< Width of > sc_pm_reset_reason_t */ > +/*@}*/ > + > +/*! > + * @name Defines for clock indexes (sc_pm_clk_t) > + */ > +/*@{*/ > +/*@}*/ > + > +/*! > + * @name Defines for ALL parameters > + */ > +/*@{*/ > +#define SC_PM_CLK_ALL UINT8_MAX /*!< All clocks */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_pm_power_mode_t > + */ > +/*@{*/ > +#define SC_PM_PW_MODE_OFF 0U /*!< Power off */ > +#define SC_PM_PW_MODE_STBY 1U /*!< Power in standby */ > +#define SC_PM_PW_MODE_LP 2U /*!< Power in low-power */ > +#define SC_PM_PW_MODE_ON 3U /*!< Power on */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_pm_clk_t > + */ > +/*@{*/ > +#define SC_PM_CLK_SLV_BUS 0U /*!< Slave bus clock */ > +#define SC_PM_CLK_MST_BUS 1U /*!< Master bus clock */ > +#define SC_PM_CLK_PER 2U /*!< Peripheral clock */ > +#define SC_PM_CLK_PHY 3U /*!< Phy clock */ > +#define SC_PM_CLK_MISC 4U /*!< Misc clock */ > +#define SC_PM_CLK_MISC0 0U /*!< Misc 0 clock */ > +#define SC_PM_CLK_MISC1 1U /*!< Misc 1 clock */ > +#define SC_PM_CLK_MISC2 2U /*!< Misc 2 clock */ > +#define SC_PM_CLK_MISC3 3U /*!< Misc 3 clock */ > +#define SC_PM_CLK_MISC4 4U /*!< Misc 4 clock */ > +#define SC_PM_CLK_CPU 2U /*!< CPU clock */ > +#define SC_PM_CLK_PLL 4U /*!< PLL */ > +#define SC_PM_CLK_BYPASS 4U /*!< Bypass clock */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_pm_clk_mode_t > + */ > +/*@{*/ > +#define SC_PM_CLK_MODE_ROM_INIT 0U /*!< Clock is > initialized by ROM. */ > +#define SC_PM_CLK_MODE_OFF 1U /*!< Clock is disabled > */ > +#define SC_PM_CLK_MODE_ON 2U /*!< Clock is enabled. > */ > +#define SC_PM_CLK_MODE_AUTOGATE_SW 3U /*!< Clock is in SW > autogate mode */ > +#define SC_PM_CLK_MODE_AUTOGATE_HW 4U /*!< Clock is in HW > autogate mode */ > +#define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /*!< Clock is in > SW-HW autogate mode */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_pm_clk_parent_t > + */ > +/*@{*/ > +#define SC_PM_PARENT_XTAL 0U /*!< Parent is XTAL. */ > +#define SC_PM_PARENT_PLL0 1U /*!< Parent is PLL0 */ > +#define SC_PM_PARENT_PLL1 2U /*!< Parent is PLL1 or > PLL0/2 */ > +#define SC_PM_PARENT_PLL2 3U /*!< Parent in PLL2 or > PLL0/4 */ > +#define SC_PM_PARENT_BYPS 4U /*!< Parent is a bypass > clock. */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_pm_reset_type_t > + */ > +/*@{*/ > +#define SC_PM_RESET_TYPE_COLD 0U /*!< Cold reset */ > +#define SC_PM_RESET_TYPE_WARM 1U /*!< Warm reset */ > +#define SC_PM_RESET_TYPE_BOARD 2U /*!< Board reset */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_pm_reset_cause_t > + */ > +/*@{*/ > +#define SC_PM_RESET_CAUSE_TEMP 0U /*!< Reset due to > temp panic alarm */ > +#define SC_PM_RESET_CAUSE_FAULT 1U /*!< Reset due to fault > exception */ > +#define SC_PM_RESET_CAUSE_IRQ 2U /*!< Reset due to SCU > reset IRQ */ > +#define SC_PM_RESET_CAUSE_WDOG 3U /*!< Reset due to SW > WDOG */ > +#define SC_PM_RESET_CAUSE_API 4U /*!< Reset due to > pm_reset() or monitor */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_pm_reset_reason_t > + */ > +/*@{*/ > +#define SC_PM_RESET_REASON_POR 0U /*!< Power on reset > */ > +#define SC_PM_RESET_REASON_WARM 1U /*!< Warm reset */ > +#define SC_PM_RESET_REASON_SW 2U /*!< Software reset > */ > +#define SC_PM_RESET_REASON_WDOG 3U /*!< Watchdog > reset */ > +#define SC_PM_RESET_REASON_LOCKUP 4U /*!< Lockup reset */ > +#define SC_PM_RESET_REASON_TAMPER 5U /*!< Tamper reset */ > +#define SC_PM_RESET_REASON_TEMP 6U /*!< Temp reset */ > +#define SC_PM_RESET_REASON_LOW_VOLT 7U /*!< Low voltage > reset */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_pm_sys_if_t > + */ > +/*@{*/ > +#define SC_PM_SYS_IF_INTERCONNECT 0U /*!< System > interconnect */ > +#define SC_PM_SYS_IF_MU 1U /*!< AP -> SCU > message units */ > +#define SC_PM_SYS_IF_OCMEM 2U /*!< On-chip memory > (ROM/OCRAM) */ > +#define SC_PM_SYS_IF_DDR 3U /*!< DDR memory */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_pm_wake_src_t > + */ > +/*@{*/ > +#define SC_PM_WAKE_SRC_NONE 0U /*!< No wake source, > used for self-kill */ > +#define SC_PM_WAKE_SRC_SCU 1U /*!< Wakeup from > SCU to resume CPU (IRQSTEER & GIC powered down) */ > +#define SC_PM_WAKE_SRC_IRQSTEER 2U /*!< Wakeup from > IRQSTEER to resume CPU (GIC powered down) */ > +#define SC_PM_WAKE_SRC_IRQSTEER_GIC 3U /*!< Wakeup from > IRQSTEER+GIC to wake CPU (GIC clock gated) */ > +#define SC_PM_WAKE_SRC_GIC 4U /*!< Wakeup from GIC > to wake CPU */ > +/*@}*/ > + > +/* Types */ > + > +/*! > + * This type is used to declare a power mode. Note resources only use > + * SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON. The other modes are > used only > + * as system power modes. > + */ > +typedef uint8_t sc_pm_power_mode_t; > + > +/*! > + * This type is used to declare a clock. > + */ > +typedef uint8_t sc_pm_clk_t; > + > +/*! > + * This type is used to declare a clock mode. > + */ > +typedef uint8_t sc_pm_clk_mode_t; > + > +/*! > + * This type is used to declare the clock parent. > + */ > +typedef uint8_t sc_pm_clk_parent_t; > + > +/*! > + * This type is used to declare clock rates. > + */ > +typedef uint32_t sc_pm_clock_rate_t; > + > +/*! > + * This type is used to declare a desired reset type. > + */ > +typedef uint8_t sc_pm_reset_type_t; > + > +/*! > + * This type is used to declare a desired reset type. > + */ > +typedef uint8_t sc_pm_reset_cause; > + > +/*! > + * This type is used to declare a reason for a reset. > + */ > +typedef uint8_t sc_pm_reset_reason_t; > + > +/*! > + * This type is used to specify a system-level interface to be power managed. > + */ > +typedef uint8_t sc_pm_sys_if_t; > + > +/*! > + * This type is used to specify a wake source for CPU resources. > + */ > +typedef uint8_t sc_pm_wake_src_t; > + > +/* Functions */ > + > +/*! > + * @name Power Functions > + * @{ > + */ > + > +/*! > + * This function sets the system power mode. Only the owner of the > + * SC_R_SYSTEM resource can do this. > + * > + * @param[in] ipc IPC handle > + * @param[in] mode power mode to apply > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_PARM if invalid mode, > + * - SC_ERR_NOACCESS if caller not the owner of SC_R_SYSTEM > + * > + * @see sc_pm_set_sys_power_mode(). > + */ > +sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_pm_power_mode_t > mode); > + > +/*! > + * This function sets the power mode of a partition. > + * > + * @param[in] ipc IPC handle > + * @param[in] pt handle of partition > + * @param[in] mode power mode to apply > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_PARM if invalid partition or mode, > + * - SC_ERR_NOACCESS if caller's partition is not the owner or > + * parent of \a pt > + * > + * The power mode of the partitions is a max power any resource will > + * be set to. Calling this will result in all resources owned > + * by \a pt to have their power changed to the lower of \a mode or the > + * individual resource mode set using sc_pm_set_resource_power_mode(). > + */ > +sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, > + sc_pm_power_mode_t mode); > + > +/*! > + * This function gets the power mode of a partition. > + * > + * @param[in] ipc IPC handle > + * @param[in] pt handle of partition > + * @param[out] mode pointer to return power mode > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_PARM if invalid partition > + */ > +sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, > + sc_pm_power_mode_t *mode); > + > +/*! > + * This function sets the power mode of a resource. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource ID of the resource > + * @param[in] mode power mode to apply > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_PARM if invalid resource or mode, > + * - SC_ERR_NOACCESS if caller's partition is not the resource owner > + * or parent of the owner > + * > + * Resources must be at SC_PM_PW_MODE_LP mode or higher to access > them, > + * otherwise the master will get a bus error or hang. > + * > + * This function will record the individual resource power mode > + * and change it if the requested mode is lower than or equal to the > + * partition power mode set with sc_pm_set_partition_power_mode(). > + * In other words, the power mode of the resource will be the minimum > + * of the resource power mode and the partition power mode. > + * > + * Note some resources are still not accessible even when powered up if bus > + * transactions go through a fabric not powered up. Examples of this are > + * resources in display and capture subsystems which require the display > + * controller or the imaging subsytem to be powered up first. > + * > + * Not that resources are grouped into power domains by the underlying > + * hardware. If any resource in the domain is on, the entire power domain > + * will be on. Other power domains required to access the resource will > + * also be turned on. Clocks required to access the peripheral will be > + * turned on. Refer to the SoC RM for more info on power domains and access > + * infrastructure (bus fabrics, clock domains, etc.). > + */ > +sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_pm_power_mode_t mode); > + > +/*! > + * This function gets the power mode of a resource. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource ID of the resource > + * @param[out] mode pointer to return power mode > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Note only SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON are valid. > The value > + * returned does not reflect the power mode of the partition.. > + */ > +sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_pm_power_mode_t *mode); > + > +/*! > + * This function requests the low power mode some of the resources > + * can enter based on their state. This API is only valid for the > + * following resources : SC_R_A53, SC_R_A53_0, SC_R_A53_1, SC_A53_2, > + * SC_A53_3, SC_R_A72, SC_R_A72_0, SC_R_A72_1, SC_R_CC1, SC_R_A35, > + * SC_R_A35_0, SC_R_A35_1, SC_R_A35_2, SC_R_A35_3. > + * For all other resources it will return SC_ERR_PARAM. > + * This function will set the low power mode the cores, cluster > + * and cluster associated resources will enter when all the cores > + * in a given cluster execute WFI > + * > + * @param[in] ipc IPC handle > + * @param[in] resource ID of the resource > + * @param[in] mode power mode to apply > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + */ > +sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_pm_power_mode_t mode); > + > +/*! > + * This function requests low-power mode entry for CPU/cluster > + * resources. This API is only valid for the following resources: > + * SC_R_A53, SC_R_A53_x, SC_R_A72, SC_R_A72_x, SC_R_A35, SC_R_A35_x, > + * SC_R_CCI. For all other resources it will return SC_ERR_PARAM. > + * For individual core resources, the specified power mode > + * and wake source will be applied after the core has entered > + * WFI. For cluster resources, the specified power mode is > + * applied after all cores in the cluster have entered low-power mode. > + * For multicluster resources, the specified power mode is applied > + * after all clusters have reached low-power mode. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource ID of the resource > + * @param[in] mode power mode to apply > + * @param[in] wake_src wake source for low-power exit > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + */ > +sc_err_t sc_pm_req_cpu_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_pm_power_mode_t mode, sc_pm_wake_src_t wake_src); > + > +/*! > + * This function is used to set the resume address of a CPU. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource ID of the CPU resource > + * @param[in] address 64-bit resume address > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_PARM if invalid resource or address, > + * - SC_ERR_NOACCESS if caller's partition is not the parent of the > + * resource (CPU) owner > + */ > +sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_faddr_t address); > + > +/*! > + * This function is used to set parameters for CPU resume from > + * low-power mode. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource ID of the CPU resource > + * @param[in] isPrimary set SC_TRUE if primary wake CPU > + * @param[in] address 64-bit resume address > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_PARM if invalid resource or address, > + * - SC_ERR_NOACCESS if caller's partition is not the parent of the > + * resource (CPU) owner > + */ > +sc_err_t sc_pm_set_cpu_resume(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_bool_t isPrimary, sc_faddr_t address); > + > +/*! > + * This function requests the power mode configuration for system-level > + * interfaces including messaging units, interconnect, and memories. This API > + * is only valid for the following resources : SC_R_A53, SC_R_A72, and > + * SC_R_M4_x_PID_y. For all other resources, it will return SC_ERR_PARAM. > + * The requested power mode will be captured and applied to system-level > + * resources as system conditions allow. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource ID of the resource > + * @param[in] sys_if system-level interface to be configured > + * @param[in] hpm high-power mode for the system interface > + * @param[in] lpm low-power mode for the system interface > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + */ > +sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, > sc_pm_power_mode_t lpm); > + > +/* @} */ > + > +/*! > + * @name Clock/PLL Functions > + * @{ > + */ > + > +/*! > + * This function sets the rate of a resource's clock/PLL. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource ID of the resource > + * @param[in] clk clock/PLL to affect > + * @param[in,out] rate pointer to rate to set, > + * return actual rate > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_PARM if invalid resource or clock/PLL, > + * - SC_ERR_NOACCESS if caller's partition is not the resource owner > + * or parent of the owner, > + * - SC_ERR_UNAVAILABLE if clock/PLL not applicable to this resource, > + * - SC_ERR_LOCKED if rate locked (usually because shared clock/PLL) > + * > + * Refer to the [Clock List](@ref CLOCKS) for valid clock/PLL values. > + */ > +sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); > + > +/*! > + * This function gets the rate of a resource's clock/PLL. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource ID of the resource > + * @param[in] clk clock/PLL to affect > + * @param[out] rate pointer to return rate > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_PARM if invalid resource or clock/PLL, > + * - SC_ERR_NOACCESS if caller's partition is not the resource owner > + * or parent of the owner, > + * - SC_ERR_UNAVAILABLE if clock/PLL not applicable to this resource > + * > + * Refer to the [Clock List](@ref CLOCKS) for valid clock/PLL values. > + */ > +sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); > + > +/*! > + * This function enables/disables a resource's clock. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource ID of the resource > + * @param[in] clk clock to affect > + * @param[in] enable enable if SC_TRUE; otherwise disabled > + * @param[in] autog HW auto clock gating > + * > + * If \a resource is SC_R_ALL then all resources owned will be affected. > + * No error will be returned. > + * > + * If \a clk is SC_PM_CLK_ALL, then an error will be returned if any > + * of the available clocks returns an error. > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_PARM if invalid resource or clock, > + * - SC_ERR_NOACCESS if caller's partition is not the resource owner > + * or parent of the owner, > + * - SC_ERR_UNAVAILABLE if clock not applicable to this resource > + * > + * Refer to the [Clock List](@ref CLOCKS) for valid clock values. > + */ > +sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog); > + > +/*! > + * This function sets the parent of a resource's clock. > + * This function should only be called when the clock is disabled. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource ID of the resource > + * @param[in] clk clock to affect > + * @param[in] parent New parent of the clock. > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_PARM if invalid resource or clock, > + * - SC_ERR_NOACCESS if caller's partition is not the resource owner > + * or parent of the owner, > + * - SC_ERR_UNAVAILABLE if clock not applicable to this resource > + * - SC_ERR_BUSY if clock is currently enabled. > + * - SC_ERR_NOPOWER if resource not powered > + * > + * Refer to the [Clock List](@ref CLOCKS) for valid clock values. > + */ > +sc_err_t sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_pm_clk_t clk, sc_pm_clk_parent_t parent); > + > +/*! > + * This function gets the parent of a resource's clock. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource ID of the resource > + * @param[in] clk clock to affect > + * @param[out] parent pointer to return parent of clock. > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_PARM if invalid resource or clock, > + * - SC_ERR_NOACCESS if caller's partition is not the resource owner > + * or parent of the owner, > + * - SC_ERR_UNAVAILABLE if clock not applicable to this resource > + * > + * Refer to the [Clock List](@ref CLOCKS) for valid clock values. > + */ > +sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_pm_clk_t clk, sc_pm_clk_parent_t *parent); > + > +/* @} */ > + > +/*! > + * @name Reset Functions > + * @{ > + */ > + > +/*! > + * This function is used to reset the system. Only the owner of the > + * SC_R_SYSTEM resource can do this. > + * > + * @param[in] ipc IPC handle > + * @param[in] type reset type > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_PARM if invalid type, > + * - SC_ERR_NOACCESS if caller not the owner of SC_R_SYSTEM > + * > + * If this function returns, then the reset did not occur due to an > + * invalid parameter. > + */ > +sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type); > + > +/*! > + * This function gets a caller's reset reason. > + * > + * @param[in] ipc IPC handle > + * @param[out] reason pointer to return reset reason > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + */ > +sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason); > + > +/*! > + * This function is used to boot a partition. > + * > + * @param[in] ipc IPC handle > + * @param[in] pt handle of partition to boot > + * @param[in] resource_cpu ID of the CPU resource to start > + * @param[in] boot_addr 64-bit boot address > + * @param[in] resource_mu ID of the MU that must be powered > + * @param[in] resource_dev ID of the boot device that must be powered > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_PARM if invalid partition, resource, or addr, > + * - SC_ERR_NOACCESS if caller's partition is not the parent of the > + * partition to boot > + */ > +sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt, > + sc_rsrc_t resource_cpu, sc_faddr_t boot_addr, > + sc_rsrc_t resource_mu, sc_rsrc_t resource_dev); > + > +/*! > + * This function is used to reboot the caller's partition. > + * > + * @param[in] ipc IPC handle > + * @param[in] type reset type > + * > + * If \a type is SC_PM_RESET_TYPE_COLD, then most peripherals owned by > + * the calling partition will be reset if possible. SC state (partitions, > + * power, clocks, etc.) is reset. The boot SW of the booting CPU must be > + * able to handle peripherals that that are not reset. > + * > + * If \a type is SC_PM_RESET_TYPE_WARM, then only the boot CPU is reset. > + * SC state (partitions, power, clocks, etc.) are NOT reset. The boot SW > + * of the booting CPU must be able to handle peripherals and SC state that > + * that are not reset. > + * > + * If \a type is SC_PM_RESET_TYPE_BOARD, then return with no action. > + * > + * If this function returns, then the reset did not occur due to an > + * invalid parameter. > + */ > +void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type); > + > +/*! > + * This function is used to reboot a partition. > + * > + * @param[in] ipc IPC handle > + * @param[in] pt handle of partition to reboot > + * @param[in] type reset type > + * > + * If \a type is SC_PM_RESET_TYPE_COLD, then most peripherals owned by > + * the calling partition will be reset if possible. SC state (partitions, > + * power, clocks, etc.) is reset. The boot SW of the booting CPU must be > + * able to handle peripherals that that are not reset. > + * > + * If \a type is SC_PM_RESET_TYPE_WARM, then only the boot CPU is reset. > + * SC state (partitions, power, clocks, etc.) are NOT reset. The boot SW > + * of the booting CPU must be able to handle peripherals and SC state that > + * that are not reset. > + * > + * If \a type is SC_PM_RESET_TYPE_BOARD, then return with no action. > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_PARM if invalid partition or type > + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt, > + * > + * Most peripherals owned by the partition will be reset if > + * possible. SC state (partitions, power, clocks, etc.) is reset. The > + * boot SW of the booting CPU must be able to handle peripherals that > + * that are not reset. > + */ > +sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt, > + sc_pm_reset_type_t type); > + > +/*! > + * This function is used to start/stop a CPU. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource ID of the CPU resource > + * @param[in] enable start if SC_TRUE; otherwise stop > + * @param[in] address 64-bit boot address > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_PARM if invalid resource or address, > + * - SC_ERR_NOACCESS if caller's partition is not the parent of the > + * resource (CPU) owner > + */ > +sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, > + sc_faddr_t address); > + > +/* @} */ > + > +#endif /* SC_PM_API_H */ > + > +/**@}*/ > + > diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h > b/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h > new file mode 100755 > index 0000000000..0de009a00e > --- /dev/null > +++ b/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h > @@ -0,0 +1,759 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * Header file containing the public API for the System Controller (SC) > + * Resource Management (RM) function. This includes functions for > + * partitioning resources, pads, and memory regions. > + * > + * @addtogroup RM_SVC (SVC) Resource Management Service > + * > + * Module for the Resource Management (RM) service. > + * > + * @includedoc rm/details.dox > + * > + * @{ > + */ > + > +#ifndef SC_RM_API_H > +#define SC_RM_API_H > + > +/* Includes */ > + > +#include <asm/arch/sci/types.h> > + > +/* Defines */ > + > +/*! > + * @name Defines for type widths > + */ > +/*@{*/ > +#define SC_RM_PARTITION_W 5U /*!< Width of sc_rm_pt_t */ > +#define SC_RM_MEMREG_W 6U /*!< Width of sc_rm_mr_t */ > +#define SC_RM_DID_W 4U /*!< Width of sc_rm_did_t */ > +#define SC_RM_SID_W 6U /*!< Width of sc_rm_sid_t */ > +#define SC_RM_SPA_W 2U /*!< Width of sc_rm_spa_t */ > +#define SC_RM_PERM_W 3U /*!< Width of sc_rm_perm_t */ > +/*@}*/ > + > +/*! > + * @name Defines for ALL parameters > + */ > +/*@{*/ > +#define SC_RM_PT_ALL ((sc_rm_pt_t) UINT8_MAX) /*!< All > partitions */ > +#define SC_RM_MR_ALL ((sc_rm_mr_t) UINT8_MAX) /*!< All > memory regions */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_rm_spa_t > + */ > +/*@{*/ > +#define SC_RM_SPA_PASSTHRU 0U /*!< Pass through (attribute driven by > master) */ > +#define SC_RM_SPA_PASSSID 1U /*!< Pass through and output on SID */ > +#define SC_RM_SPA_ASSERT 2U /*!< Assert (force to be > secure/privileged) */ > +#define SC_RM_SPA_NEGATE 3U /*!< Negate (force to be > non-secure/user) */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_rm_perm_t > + */ > +/*@{*/ > +#define SC_RM_PERM_NONE 0U /*!< No access */ > +#define SC_RM_PERM_SEC_R 1U /*!< Secure RO */ > +#define SC_RM_PERM_SECPRIV_RW 2U /*!< Secure privilege R/W */ > +#define SC_RM_PERM_SEC_RW 3U /*!< Secure R/W */ > +#define SC_RM_PERM_NSPRIV_R 4U /*!< Secure R/W, non-secure > privilege RO */ > +#define SC_RM_PERM_NS_R 5U /*!< Secure R/W, non-secure RO > */ > +#define SC_RM_PERM_NSPRIV_RW 6U /*!< Secure R/W, non-secure > privilege R/W */ > +#define SC_RM_PERM_FULL 7U /*!< Full access */ > +/*@}*/ > + > +/* Types */ > + > +/*! > + * This type is used to declare a resource partition. > + */ > +typedef uint8_t sc_rm_pt_t; > + > +/*! > + * This type is used to declare a memory region. > + */ > +typedef uint8_t sc_rm_mr_t; > + > +/*! > + * This type is used to declare a resource domain ID used by the > + * isolation HW. > + */ > +typedef uint8_t sc_rm_did_t; > + > +/*! > + * This type is used to declare an SMMU StreamID. > + */ > +typedef uint16_t sc_rm_sid_t; > + > +/*! > + * This type is a used to declare master transaction attributes. > + */ > +typedef uint8_t sc_rm_spa_t; > + > +/*! > + * This type is used to declare a resource/memory region access permission. > + * Refer to the XRDC2 Block Guide for more information. > + */ > +typedef uint8_t sc_rm_perm_t; > + > +/* Functions */ > + > +/*! > + * @name Partition Functions > + * @{ > + */ > + > +/*! > + * This function requests that the SC create a new resource partition. > + * > + * @param[in] ipc IPC handle > + * @param[out] pt return handle for partition; used for > subsequent function > + * calls associated with this partition > + * @param[in] secure boolean indicating if this partition should > be secure; only > + * valid if caller is secure > + * @param[in] isolated boolean indicating if this partition should be > HW isolated > + * via XRDC; set SC_TRUE if new DID is > desired > + * @param[in] restricted boolean indicating if this partition should be > restricted; set > + * SC_TRUE if masters in this partition > cannot create new partitions > + * @param[in] grant boolean indicating if this partition should > always grant > + * access and control to the parent > + * @param[in] coherent boolean indicating if this partition is > coherent; > + * set SC_TRUE if only this partition will > contain both AP clusters > + * and they will be coherent via the CCI > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_NOACCESS if caller's partition is restricted, > + * - SC_ERR_PARM if caller's partition is not secure but a new secure partition > is requested, > + * - SC_ERR_LOCKED if caller's partition is locked, > + * - SC_ERR_UNAVAILABLE if partition table is full (no more allocation space) > + * > + * Marking as non-secure prevents subsequent functions from configuring > masters in this > + * partition to assert the secure signal. If restricted then the new partition is > limited > + * in what functions it can call, especially those associated with managing > partitions. > + * > + * The grant option is usually used to isolate a bus master's traffic to specific > + * memory without isolating the peripheral interface of the master or the API > + * controls of that master. > + */ > +sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure, > + sc_bool_t isolated, sc_bool_t restricted, sc_bool_t grant, sc_bool_t > coherent); > + > +/*! > + * This function makes a partition confidential. > + * > + * @param[in] ipc IPC handle > + * @param[in] pt handle of partition that is granting > + * @param[in] retro retroactive > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if \a pt out of range, > + * - SC_ERR_NOACCESS if caller's not allowed to change \a pt > + * - SC_ERR_LOCKED if partition \a pt is locked > + * > + * Call to make a partition confidential. Confidential means only this > + * partition should be able to grant access permissions to this partition. > + * > + * If retroactive, then all resources owned by other partitions will have > + * access rights for this partition removed, even if locked. > + */ > +sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t retro); > + > +/*! > + * This function frees a partition and assigns all resources to the caller. > + * > + * @param[in] ipc IPC handle > + * @param[in] pt handle of partition to free > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_NOACCESS if caller's partition is restricted, > + * - SC_PARM if \a pt out of range or invalid, > + * - SC_ERR_NOACCESS if \a pt is the SC partition, > + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt, > + * - SC_ERR_LOCKED if \a pt or caller's partition is locked > + * > + * All resources, memory regions, and pads are assigned to the caller/parent. > + * The partition watchdog is disabled (even if locked). DID is freed. > + */ > +sc_err_t sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt); > + > +/*! > + * This function returns the DID of a partition. > + * > + * @param[in] ipc IPC handle > + * > + * @return Returns the domain ID (DID) of the caller's partition. > + * > + * The DID is a SoC-specific internal ID used by the HW resource > + * protection mechanism. It is only required by clients when using the > + * SEMA42 module as the DID is sometimes connected to the master ID. > + */ > +sc_rm_did_t sc_rm_get_did(sc_ipc_t ipc); > + > +/*! > + * This function forces a partition to use a specific static DID. > + * > + * @param[in] ipc IPC handle > + * @param[in] pt handle of partition to assign \a did > + * @param[in] did static DID to assign > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_NOACCESS if caller's partition is restricted, > + * - SC_PARM if \a pt or \a did out of range, > + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt, > + * - SC_ERR_LOCKED if \a pt is locked > + * > + * Assumes no assigned resources or memory regions yet! The number of static > + * DID is fixed by the SC at boot. > + */ > +sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt, > + sc_rm_did_t did); > + > +/*! > + * This function locks a partition. > + * > + * @param[in] ipc IPC handle > + * @param[in] pt handle of partition to lock > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if \a pt out of range, > + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt > + * > + * If a partition is locked it cannot be freed, have resources/pads assigned > + * to/from it, memory regions created/assigned, DID changed, or parent > changed. > + */ > +sc_err_t sc_rm_partition_lock(sc_ipc_t ipc, sc_rm_pt_t pt); > + > +/*! > + * This function gets the partition handle of the caller. > + * > + * @param[in] ipc IPC handle > + * @param[out] pt return handle for caller's partition > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + */ > +sc_err_t sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt); > + > +/*! > + * This function sets a new parent for a partition. > + * > + * @param[in] ipc IPC handle > + * @param[in] pt handle of partition for which parent is to be > + * changed > + * @param[in] pt_parent handle of partition to set as parent > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_NOACCESS if caller's partition is restricted, > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt, > + * - SC_ERR_LOCKED if either partition is locked > + */ > +sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, > + sc_rm_pt_t pt_parent); > + > +/*! > + * This function moves all movable resources/pads owned by a source partition > + * to a destination partition. It can be used to more quickly set up a new > + * partition if a majority of the caller's resources are to be moved to a > + * new partition. > + * > + * @param[in] ipc IPC handle > + * @param[in] pt_src handle of partition from which resources > should > + * be moved from > + * @param[in] pt_dst handle of partition to which resources > should be > + * moved to > + * @param[in] move_rsrc boolean to indicate if resources should be > moved > + * @param[in] move_pads boolean to indicate if pads should be > moved > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * By default, all resources are movable. This can be changed using the > + * sc_rm_set_resource_movable() function. Note all masters defaulted to > SMMU > + * bypass. > + * > + * Return errors: > + * - SC_ERR_NOACCESS if caller's partition is restricted, > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not \a pt_src or the > + * parent of \a pt_src, > + * - SC_ERR_LOCKED if either partition is locked > + */ > +sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst, > + sc_bool_t move_rsrc, sc_bool_t move_pads); > + > +/* @} */ > + > +/*! > + * @name Resource Functions > + * @{ > + */ > + > +/*! > + * This function assigns ownership of a resource to a partition. > + * > + * @param[in] ipc IPC handle > + * @param[in] pt handle of partition to which resource > should be > + * assigned > + * @param[in] resource resource to assign > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * This action resets the resource's master and peripheral attributes. > + * Privilege attribute will be PASSTHRU, security attribute will be > + * ASSERT if the partition si secure and NEGATE if it is not, and > + * masters will defaulted to SMMU bypass. Access permissions will reset > + * to SEC_RW for the owning partition only for secure partitions, FULL for > + * non-secure. DEfault is no access by other partitions. > + * > + * Return errors: > + * - SC_ERR_NOACCESS if caller's partition is restricted, > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent > + * of the owner, > + * - SC_ERR_LOCKED if the owning partition or \a pt is locked > + */ > +sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, > + sc_rsrc_t resource); > + > +/*! > + * This function flags resources as movable or not. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource_fst first resource for which flag should be set > + * @param[in] resource_lst last resource for which flag should be set > + * @param[in] movable movable flag (SC_TRUE is movable) > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if resources are out of range, > + * - SC_ERR_NOACCESS if caller's partition is not a parent of a resource owner, > + * - SC_ERR_LOCKED if the owning partition is locked > + * > + * This function is used to determine the set of resources that will be > + * moved using the sc_rm_move_all() function. All resources are movable > + * by default so this function is normally used to prevent a set of > + * resources from moving. > + */ > +sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst, > + sc_rsrc_t resource_lst, sc_bool_t movable); > + > +/*! > + * This function flags all of a subsystem's resources as movable > + * or not. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource resource to use to identify subsystem > + * @param[in] movable movable flag (SC_TRUE is movable) > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_PARM if a function argument is out of range > + * > + * Note \a resource is used to find the associated subsystem. Only > + * resources owned by the caller are set. > + */ > +sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_bool_t movable); > + > +/*! > + * This function sets attributes for a resource which is a bus master (i.e. > + * capable of DMA). > + * > + * @param[in] ipc IPC handle > + * @param[in] resource master resource for which attributes should > apply > + * @param[in] sa security attribute > + * @param[in] pa privilege attribute > + * @param[in] smmu_bypass SMMU bypass mode > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_NOACCESS if caller's partition is restricted, > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not a parent of the resource > owner, > + * - SC_ERR_LOCKED if the owning partition is locked > + * > + * This function configures how the HW isolation will see bus transactions > + * from the specified master. Note the security attribute will only be > + * changed if the caller's partition is secure. > + */ > +sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_rm_spa_t sa, sc_rm_spa_t pa, sc_bool_t smmu_bypass); > + > +/*! > + * This function sets the StreamID for a resource which is a bus master (i.e. > + * capable of DMA). > + * > + * @param[in] ipc IPC handle > + * @param[in] resource master resource for which attributes should > apply > + * @param[in] sid StreamID > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_NOACCESS if caller's partition is restricted, > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent > + * of the owner, > + * - SC_ERR_LOCKED if the owning partition is locked > + * > + * This function configures the SID attribute associated with all bus transactions > + * from this master. Note 0 is not a valid SID as it is reserved to indicate > + * bypass. > + */ > +sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_rm_sid_t sid); > + > +/*! > + * This function sets access permissions for a peripheral resource. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource peripheral resource for which permissions > should apply > + * @param[in] pt handle of partition \a perm should by > applied for > + * @param[in] perm permissions to apply to \a resource for \a > pt > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent > + * of the owner, > + * - SC_ERR_LOCKED if the owning partition is locked > + * - SC_ERR_LOCKED if the \a pt is confidential and the caller isn't \a pt > + * > + * This function configures how the HW isolation will restrict access to a > + * peripheral based on the attributes of a transaction from bus master. > + */ > +sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_rm_pt_t pt, sc_rm_perm_t perm); > + > +/*! > + * This function gets ownership status of a resource. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource resource to check > + * > + * @return Returns a boolean (SC_TRUE if caller's partition owns the resource). > + * > + * If \a resource is out of range then SC_FALSE is returned. > + */ > +sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource); > + > +/*! > + * This function is used to test if a resource is a bus master. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource resource to check > + * > + * @return Returns a boolean (SC_TRUE if the resource is a bus master). > + * > + * If \a resource is out of range then SC_FALSE is returned. > + */ > +sc_bool_t sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource); > + > +/*! > + * This function is used to test if a resource is a peripheral. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource resource to check > + * > + * @return Returns a boolean (SC_TRUE if the resource is a peripheral). > + * > + * If \a resource is out of range then SC_FALSE is returned. > + */ > +sc_bool_t sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource); > + > +/*! > + * This function is used to obtain info about a resource. > + * > + * @param[in] ipc IPC handle > + * @param[in] resource resource to inquire about > + * @param[out] sid pointer to return StreamID > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if \a resource is out of range > + */ > +sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_rm_sid_t *sid); > + > +/* @} */ > + > +/*! > + * @name Memory Region Functions > + * @{ > + */ > + > +/*! > + * This function requests that the SC create a new memory region. > + * > + * @param[in] ipc IPC handle > + * @param[out] mr return handle for region; used for > + * subsequent function calls > + * associated with this region > + * @param[in] addr_start start address of region (physical) > + * @param[in] addr_end end address of region (physical) > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_PARM if the new memory region is misaligned, > + * - SC_ERR_LOCKED if caller's partition is locked, > + * - SC_ERR_PARM if the new memory region spans multiple existing regions, > + * - SC_ERR_NOACCESS if caller's partition does not own the memory > containing > + * the new region, > + * - SC_ERR_UNAVAILABLE if memory region table is full (no more allocation > + * space) > + * > + * The area covered by the memory region must currently be owned by the > caller. > + * By default, the new region will have access permission set to allow the > + * caller to access. > + */ > +sc_err_t sc_rm_memreg_alloc(sc_ipc_t ipc, sc_rm_mr_t *mr, > + sc_faddr_t addr_start, sc_faddr_t addr_end); > + > +/*! > + * This function requests that the SC split a memory region. > + * > + * @param[in] ipc IPC handle > + * @param[in] mr handle of memory region to split > + * @param[out] mr_ret return handle for new region; used for > + * subsequent function calls > + * associated with this region > + * @param[in] addr_start start address of region (physical) > + * @param[in] addr_end end address of region (physical) > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_PARM if the new memory region is not start/end part of mr, > + * - SC_ERR_LOCKED if caller's partition is locked, > + * - SC_ERR_PARM if the new memory region spans multiple existing regions, > + * - SC_ERR_NOACCESS if caller's partition does not own the memory > containing > + * the new region, > + * - SC_ERR_UNAVAILABLE if memory region table is full (no more allocation > + * space) > + * > + * Note the new region must start or end on the split region. > + */ > +sc_err_t sc_rm_memreg_split(sc_ipc_t ipc, sc_rm_mr_t mr, > + sc_rm_mr_t *mr_ret, sc_faddr_t addr_start, sc_faddr_t addr_end); > + > +/*! > + * This function frees a memory region. > + * > + * @param[in] ipc IPC handle > + * @param[in] mr handle of memory region to free > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if \a mr out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not a parent of \a mr, > + * - SC_ERR_LOCKED if the owning partition of \a mr is locked > + */ > +sc_err_t sc_rm_memreg_free(sc_ipc_t ipc, sc_rm_mr_t mr); > + > +/*! > + * Internal SC function to find a memory region. > + * > + * @see sc_rm_find_memreg(). > + */ > +/*! > + * This function finds a memory region. > + * > + * @param[in] ipc IPC handle > + * @param[out] mr return handle for region; used for > + * subsequent function calls > + * associated with this region > + * @param[in] addr_start start address of region to search for > + * @param[in] addr_end end address of region to search for > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_NOTFOUND if region not found, > + * > + * Searches only for regions owned by the caller. Finds first > + * region containing the range specified. > + */ > +sc_err_t sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, > + sc_faddr_t addr_start, sc_faddr_t addr_end); > + > +/*! > + * This function assigns ownership of a memory region. > + * > + * @param[in] ipc IPC handle > + * @param[in] pt handle of partition to which memory region > + * should be assigned > + * @param[in] mr handle of memory region to assign > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the \a mr owner or parent > + * of the owner, > + * - SC_ERR_LOCKED if the owning partition or \a pt is locked > + */ > +sc_err_t sc_rm_assign_memreg(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_mr_t mr); > + > +/*! > + * This function sets access permissions for a memory region. > + * > + * @param[in] ipc IPC handle > + * @param[in] mr handle of memory region for which > permissions > + * should apply > + * @param[in] pt handle of partition \a perm should by > + * applied for > + * @param[in] perm permissions to apply to \a mr for \a pt > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the region owner or parent > + * of the owner, > + * - SC_ERR_LOCKED if the owning partition is locked > + * - SC_ERR_LOCKED if the \a pt is confidential and the caller isn't \a pt > + * > + * This function configures how the HW isolation will restrict access to a > + * memory region based on the attributes of a transaction from bus master. > + */ > +sc_err_t sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr, > + sc_rm_pt_t pt, sc_rm_perm_t perm); > + > +/*! > + * This function gets ownership status of a memory region. > + * > + * @param[in] ipc IPC handle > + * @param[in] mr handle of memory region to check > + * > + * @return Returns a boolean (SC_TRUE if caller's partition owns the > + * memory region). > + * > + * If \a mr is out of range then SC_FALSE is returned. > + */ > +sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr); > + > +/*! > + * This function is used to obtain info about a memory region. > + * > + * @param[in] ipc IPC handle > + * @param[in] mr handle of memory region to inquire about > + * @param[out] addr_start pointer to return start address > + * @param[out] addr_end pointer to return end address > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if \a mr is out of range > + */ > +sc_err_t sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, > + sc_faddr_t *addr_start, sc_faddr_t *addr_end); > + > +/* @} */ > + > +/*! > + * @name Pad Functions > + * @{ > + */ > + > +/*! > + * This function assigns ownership of a pad to a partition. > + * > + * @param[in] ipc IPC handle > + * @param[in] pt handle of partition to which pad should > + * be assigned > + * @param[in] pad pad to assign > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_NOACCESS if caller's partition is restricted, > + * - SC_PARM if arguments out of range or invalid, > + * - SC_ERR_NOACCESS if caller's partition is not the pad owner or parent > + * of the owner, > + * - SC_ERR_LOCKED if the owning partition or \a pt is locked > + */ > +sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad); > + > +/*! > + * This function flags pads as movable or not. > + * > + * @param[in] ipc IPC handle > + * @param[in] pad_fst first pad for which flag should be set > + * @param[in] pad_lst last pad for which flag should be set > + * @param[in] movable movable flag (SC_TRUE is movable) > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_PARM if pads are out of range, > + * - SC_ERR_NOACCESS if caller's partition is not a parent of a pad owner, > + * - SC_ERR_LOCKED if the owning partition is locked > + * > + * This function is used to determine the set of pads that will be > + * moved using the sc_rm_move_all() function. All pads are movable > + * by default so this function is normally used to prevent a set of > + * pads from moving. > + */ > +sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst, > + sc_pad_t pad_lst, sc_bool_t movable); > + > +/*! > + * This function gets ownership status of a pad. > + * > + * @param[in] ipc IPC handle > + * @param[in] pad pad to check > + * > + * @return Returns a boolean (SC_TRUE if caller's partition owns the pad). > + * > + * If \a pad is out of range then SC_FALSE is returned. > + */ > +sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad); > + > +/* @} */ > + > +/*! > + * @name Debug Functions > + * @{ > + */ > + > +/*! > + * This function dumps the RM state for debug. > + * > + * @param[in] ipc IPC handle > + */ > +void sc_rm_dump(sc_ipc_t ipc); > + > +/* @} */ > + > +#endif /* SC_RM_API_H */ > + > +/**@}*/ > + > diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h > b/arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h > new file mode 100755 > index 0000000000..631dab1531 > --- /dev/null > +++ b/arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h > @@ -0,0 +1,306 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * Header file containing the public API for the System Controller (SC) > + * Timer function. > + * > + * @addtogroup TIMER_SVC (SVC) Timer Service > + * > + * Module for the Timer service. This includes support for the watchdog, RTC, > + * and system counter. Note every resource partition has a watchdog it can > + * use. > + * > + * @{ > + */ > + > +#ifndef SC_TIMER_API_H > +#define SC_TIMER_API_H > + > +/* Includes */ > + > +#include <asm/arch/sci/types.h> > +#include <asm/arch/sci/svc/rm/api.h> > + > +/* Defines */ > + > +/*! > + * @name Defines for type widths > + */ > +/*@{*/ > +#define SC_TIMER_ACTION_W 3U /*!< Width of > sc_timer_wdog_action_t */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_timer_wdog_action_t > + */ > +/*@{*/ > +#define SC_TIMER_WDOG_ACTION_PARTITION 0U /*!< Reset > partition */ > +#define SC_TIMER_WDOG_ACTION_WARM 1U /*!< Warm > reset system */ > +#define SC_TIMER_WDOG_ACTION_COLD 2U /*!< Cold reset > system */ > +#define SC_TIMER_WDOG_ACTION_BOARD 3U /*!< Reset > board */ > +#define SC_TIMER_WDOG_ACTION_IRQ 4U /*!< Only > generate IRQs */ > +/*@}*/ > + > +/* Types */ > + > +/*! > + * This type is used to configure the watchdog action. > + */ > +typedef uint8_t sc_timer_wdog_action_t; > + > +/*! > + * This type is used to declare a watchdog time value in milliseconds. > + */ > +typedef uint32_t sc_timer_wdog_time_t; > + > +/* Functions */ > + > +/*! > + * @name Wathdog Functions > + * @{ > + */ > + > +/*! > + * This function sets the watchdog timeout in milliseconds. If not > + * set then the timeout defaults to the max. Once locked this value > + * cannot be changed. > + * > + * @param[in] ipc IPC handle > + * @param[in] timeout timeout period for the watchdog > + * > + * @return Returns an error code (SC_ERR_NONE = success, SC_ERR_LOCKED > + * = locked). > + */ > +sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc, > + sc_timer_wdog_time_t timeout); > + > +/*! > + * This function sets the watchdog pre-timeout in milliseconds. If not > + * set then the pre-timeout defaults to the max. Once locked this value > + * cannot be changed. > + * > + * @param[in] ipc IPC handle > + * @param[in] pre_timeout pre-timeout period for the watchdog > + * > + * When the pre-timout expires an IRQ will be generated. Note this timeout > + * clears when the IRQ is triggered. An IRQ is generated for the failing > + * partition and all of its child partitions. > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + */ > +sc_err_t sc_timer_set_wdog_pre_timeout(sc_ipc_t ipc, > + sc_timer_wdog_time_t pre_timeout); > + > +/*! > + * This function starts the watchdog. > + * > + * @param[in] ipc IPC handle > + * @param[in] lock boolean indicating the lock status > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * If \a lock is set then the watchdog cannot be stopped or the timeout > + * period changed. > + */ > +sc_err_t sc_timer_start_wdog(sc_ipc_t ipc, sc_bool_t lock); > + > +/*! > + * This function stops the watchdog if it is not locked. > + * > + * @param[in] ipc IPC handle > + * > + * @return Returns an error code (SC_ERR_NONE = success, SC_ERR_LOCKED > + * = locked). > + */ > +sc_err_t sc_timer_stop_wdog(sc_ipc_t ipc); > + > +/*! > + * This function pings (services, kicks) the watchdog resetting the time > + * before expiration back to the timeout. > + * > + * @param[in] ipc IPC handle > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + */ > +sc_err_t sc_timer_ping_wdog(sc_ipc_t ipc); > + > +/*! > + * This function gets the status of the watchdog. All arguments are > + * in milliseconds. > + * > + * @param[in] ipc IPC handle > + * @param[out] timeout pointer to return the timeout > + * @param[out] max_timeout pointer to return the max timeout > + * @param[out] remaining_time pointer to return the time remaining > + * until trigger > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + */ > +sc_err_t sc_timer_get_wdog_status(sc_ipc_t ipc, > + sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *max_timeout, > + sc_timer_wdog_time_t *remaining_time); > + > +/*! > + * This function gets the status of the watchdog of a partition. All > + * arguments are in milliseconds. > + * > + * @param[in] ipc IPC handle > + * @param[in] pt partition to query > + * @param[out] enb pointer to return enable status > + * @param[out] timeout pointer to return the timeout > + * @param[out] remaining_time pointer to return the time remaining > + * until trigger > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + */ > +sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t > *enb, > + sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t > *remaining_time); > + > +/*! > + * This function configures the action to be taken when a watchdog > + * expires. > + * > + * @param[in] ipc IPC handle > + * @param[in] pt partition to affect > + * @param[in] action action to take > + * > + * Default action is inherited from the parent. > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_PARM if invalid parameters, > + * - SC_ERR_NOACCESS if caller's partition is not the SYSTEM owner, > + * - SC_ERR_LOCKED if the watchdog is locked > + */ > +sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc, > + sc_rm_pt_t pt, sc_timer_wdog_action_t action); > + > +/* @} */ > + > +/*! > + * @name Real-Time Clock (RTC) Functions > + * @{ > + */ > + > +/*! > + * This function sets the RTC time. Only the owner of the SC_R_SYSTEM > + * resource can set the time. > + * > + * @param[in] ipc IPC handle > + * @param[in] year year (min 1970) > + * @param[in] mon month (1-12) > + * @param[in] day day of the month (1-31) > + * @param[in] hour hour (0-23) > + * @param[in] min minute (0-59) > + * @param[in] sec second (0-59) > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_PARM if invalid time/date parameters, > + * - SC_ERR_NOACCESS if caller's partition is not the SYSTEM owner > + */ > +sc_err_t sc_timer_set_rtc_time(sc_ipc_t ipc, uint16_t year, uint8_t mon, > + uint8_t day, uint8_t hour, uint8_t min, uint8_t sec); > + > +/*! > + * This function gets the RTC time. > + * > + * @param[in] ipc IPC handle > + * @param[out] year pointer to return year (min 1970) > + * @param[out] mon pointer to return month (1-12) > + * @param[out] day pointer to return day of the month (1-31) > + * @param[out] hour pointer to return hour (0-23) > + * @param[out] min pointer to return minute (0-59) > + * @param[out] sec pointer to return second (0-59) > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + */ > +sc_err_t sc_timer_get_rtc_time(sc_ipc_t ipc, uint16_t *year, uint8_t *mon, > + uint8_t *day, uint8_t *hour, uint8_t *min, uint8_t *sec); > + > +/*! > + * This function gets the RTC time in seconds since 1/1/1970. > + * > + * @param[in] ipc IPC handle > + * @param[out] sec pointer to return second > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + */ > +sc_err_t sc_timer_get_rtc_sec1970(sc_ipc_t ipc, uint32_t *sec); > + > +/*! > + * This function sets the RTC alarm. > + * > + * @param[in] ipc IPC handle > + * @param[in] year year (min 1970) > + * @param[in] mon month (1-12) > + * @param[in] day day of the month (1-31) > + * @param[in] hour hour (0-23) > + * @param[in] min minute (0-59) > + * @param[in] sec second (0-59) > + * > + * Note this alarm setting clears when the alarm is triggered. > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_PARM if invalid time/date parameters > + */ > +sc_err_t sc_timer_set_rtc_alarm(sc_ipc_t ipc, uint16_t year, uint8_t mon, > + uint8_t day, uint8_t hour, uint8_t min, uint8_t sec); > + > +/*! > + * This function sets the RTC alarm. > + * > + * @param[in] ipc IPC handle > + * @param[in] sec period in seconds > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_PARM if invalid time/date parameters > + */ > +sc_err_t sc_timer_set_rtc_periodic_alarm(sc_ipc_t ipc, uint32_t sec); > + > +/*! > + * This function sets the RTC alarm. > + * > + * @param[in] ipc IPC handle > + * > + * Note this alarm setting clears when the alarm is triggered. > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + * > + * Return errors: > + * - SC_ERR_PARM if invalid time/date parameters > + */ > +sc_err_t sc_timer_cancel_rtc_alarm(sc_ipc_t ipc); > + > +/*! > + * This function sets the RTC calibration value. Only the owner of the > SC_R_SYSTEM > + * resource can set the calibration. > + * > + * @param[in] ipc IPC handle > + * @param[in] count calbration count (-16 to 15) > + * > + * The calibration value is a 5-bit value including the sign bit, which is > + * implemented in 2's complement. It is added or subtracted from the RTC on > + * a perdiodic basis, once per 32768 cycles of the RTC clock. > + * > + * @return Returns an error code (SC_ERR_NONE = success). > + */ > +sc_err_t sc_timer_set_rtc_calb(sc_ipc_t ipc, int8_t count); > + > +/* @} */ > + > +#endif /* SC_TIMER_API_H */ > + > +/**@}*/ > + > diff --git a/arch/arm/include/asm/arch-imx8/sci/types.h > b/arch/arm/include/asm/arch-imx8/sci/types.h > new file mode 100755 > index 0000000000..e4c37a0480 > --- /dev/null > +++ b/arch/arm/include/asm/arch-imx8/sci/types.h > @@ -0,0 +1,862 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * Header file containing types used across multiple service APIs. > + */ > + > +#ifndef SC_TYPES_H > +#define SC_TYPES_H > + > +/* Includes */ > +#include <linux/types.h> > + > +/* Defines */ > +/*! > + * This type is used to declare a handle for an IPC communication > + * channel. Its meaning is specific to the IPC implementation. > + */ > +typedef uint64_t sc_ipc_t; > + > +/*! > + * This type is used to declare an ID for an IPC communication > + * channel. Its meaning is specific to the IPC implementation. > + */ > +typedef uint64_t sc_ipc_id_t; > + > +/*! > + * @name Defines for common frequencies > + */ > +/*@{*/ > +#define SC_32KHZ 32768U /*!< 32KHz */ > +#define SC_10MHZ 10000000U /*!< 10MHz */ > +#define SC_20MHZ 20000000U /*!< 20MHz */ > +#define SC_25MHZ 25000000U /*!< 25MHz */ > +#define SC_27MHZ 27000000U /*!< 27MHz */ > +#define SC_40MHZ 40000000U /*!< 40MHz */ > +#define SC_45MHZ 45000000U /*!< 45MHz */ > +#define SC_50MHZ 50000000U /*!< 50MHz */ > +#define SC_60MHZ 60000000U /*!< 60MHz */ > +#define SC_66MHZ 66666666U /*!< 66MHz */ > +#define SC_74MHZ 74250000U /*!< 74.25MHz */ > +#define SC_80MHZ 80000000U /*!< 80MHz */ > +#define SC_83MHZ 83333333U /*!< 83MHz */ > +#define SC_84MHZ 84375000U /*!< 84.37MHz */ > +#define SC_100MHZ 100000000U /*!< 100MHz */ > +#define SC_125MHZ 125000000U /*!< 125MHz */ > +#define SC_133MHZ 133333333U /*!< 133MHz */ > +#define SC_135MHZ 135000000U /*!< 135MHz */ > +#define SC_150MHZ 150000000U /*!< 150MHz */ > +#define SC_160MHZ 160000000U /*!< 160MHz */ > +#define SC_166MHZ 166666666U /*!< 166MHz */ > +#define SC_175MHZ 175000000U /*!< 175MHz */ > +#define SC_180MHZ 180000000U /*!< 180MHz */ > +#define SC_200MHZ 200000000U /*!< 200MHz */ > +#define SC_250MHZ 250000000U /*!< 250MHz */ > +#define SC_266MHZ 266666666U /*!< 266MHz */ > +#define SC_300MHZ 300000000U /*!< 300MHz */ > +#define SC_312MHZ 312500000U /*!< 312.5MHZ */ > +#define SC_320MHZ 320000000U /*!< 320MHz */ > +#define SC_325MHZ 325000000U /*!< 325MHz */ > +#define SC_333MHZ 333333333U /*!< 333MHz */ > +#define SC_350MHZ 350000000U /*!< 350MHz */ > +#define SC_372MHZ 372000000U /*!< 372MHz */ > +#define SC_375MHZ 375000000U /*!< 375MHz */ > +#define SC_400MHZ 400000000U /*!< 400MHz */ > +#define SC_500MHZ 500000000U /*!< 500MHz */ > +#define SC_594MHZ 594000000U /*!< 594MHz */ > +#define SC_625MHZ 625000000U /*!< 625MHz */ > +#define SC_640MHZ 640000000U /*!< 640MHz */ > +#define SC_650MHZ 650000000U /*!< 650MHz */ > +#define SC_667MHZ 666666667U /*!< 667MHz */ > +#define SC_675MHZ 675000000U /*!< 675MHz */ > +#define SC_700MHZ 700000000U /*!< 700MHz */ > +#define SC_720MHZ 720000000U /*!< 720MHz */ > +#define SC_750MHZ 750000000U /*!< 750MHz */ > +#define SC_800MHZ 800000000U /*!< 800MHz */ > +#define SC_850MHZ 850000000U /*!< 850MHz */ > +#define SC_900MHZ 900000000U /*!< 900MHz */ > +#define SC_1000MHZ 1000000000U /*!< 1GHz */ > +#define SC_1060MHZ 1060000000U /*!< 1.06GHz */ > +#define SC_1188MHZ 1188000000U /*!< 1.188GHz */ > +#define SC_1260MHZ 1260000000U /*!< 1.26GHz */ > +#define SC_1280MHZ 1280000000U /*!< 1.28GHz */ > +#define SC_1300MHZ 1300000000U /*!< 1.3GHz */ > +#define SC_1400MHZ 1400000000U /*!< 1.4GHz */ > +#define SC_1500MHZ 1500000000U /*!< 1.5GHz */ > +#define SC_1600MHZ 1600000000U /*!< 1.6GHz */ > +#define SC_1800MHZ 1800000000U /*!< 1.8GHz */ > +#define SC_2000MHZ 2000000000U /*!< 2.0GHz */ > +#define SC_2112MHZ 2112000000U /*!< 2.12GHz */ > +/*@}*/ > + > +/*! > + * @name Defines for 24M related frequencies > + */ > +/*@{*/ > +#define SC_8MHZ 8000000U /*!< 8MHz */ > +#define SC_12MHZ 12000000U /*!< 12MHz */ > +#define SC_19MHZ 19800000U /*!< 19.8MHz */ > +#define SC_24MHZ 24000000U /*!< 24MHz */ > +#define SC_48MHZ 48000000U /*!< 48MHz */ > +#define SC_120MHZ 120000000U /*!< 120MHz */ > +#define SC_132MHZ 132000000U /*!< 132MHz */ > +#define SC_144MHZ 144000000U /*!< 144MHz */ > +#define SC_192MHZ 192000000U /*!< 192MHz */ > +#define SC_211MHZ 211200000U /*!< 211.2MHz */ > +#define SC_240MHZ 240000000U /*!< 240MHz */ > +#define SC_264MHZ 264000000U /*!< 264MHz */ > +#define SC_352MHZ 352000000U /*!< 352MHz */ > +#define SC_360MHZ 360000000U /*!< 360MHz */ > +#define SC_384MHZ 384000000U /*!< 384MHz */ > +#define SC_396MHZ 396000000U /*!< 396MHz */ > +#define SC_432MHZ 432000000U /*!< 432MHz */ > +#define SC_480MHZ 480000000U /*!< 480MHz */ > +#define SC_600MHZ 600000000U /*!< 600MHz */ > +#define SC_744MHZ 744000000U /*!< 744MHz */ > +#define SC_792MHZ 792000000U /*!< 792MHz */ > +#define SC_864MHZ 864000000U /*!< 864MHz */ > +#define SC_960MHZ 960000000U /*!< 960MHz */ > +#define SC_1056MHZ 1056000000U /*!< 1056MHz */ > +#define SC_1104MHZ 1104000000U /*!< 1104MHz */ > +#define SC_1200MHZ 1200000000U /*!< 1.2GHz */ > +#define SC_1464MHZ 1464000000U /*!< 1.464GHz */ > +#define SC_2400MHZ 2400000000U /*!< 2.4GHz */ > +/*@}*/ > + > +/*! > + * @name Defines for A/V related frequencies > + */ > +/*@{*/ > +#define SC_62MHZ 62937500U /*!< 62.9375MHz */ > +#define SC_755MHZ 755250000U /*!< 755.25MHz */ > +/*@}*/ > + > +/*! > + * @name Defines for type widths > + */ > +/*@{*/ > +#define SC_FADDR_W 36U /*!< Width of sc_faddr_t */ > +#define SC_BOOL_W 1U /*!< Width of sc_bool_t */ > +#define SC_ERR_W 4U /*!< Width of sc_err_t */ > +#define SC_RSRC_W 10U /*!< Width of sc_rsrc_t */ > +#define SC_CTRL_W 6U /*!< Width of sc_ctrl_t */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_bool_t > + */ > +/*@{*/ > +#define SC_FALSE ((sc_bool_t) 0U) /*!< True */ > +#define SC_TRUE ((sc_bool_t) 1U) /*!< False */ > +/*@}*/ > + > +/*! > + * @name Defines for sc_err_t. > + */ > +/*@{*/ > +#define SC_ERR_NONE 0U /*!< Success */ > +#define SC_ERR_VERSION 1U /*!< Incompatible API version */ > +#define SC_ERR_CONFIG 2U /*!< Configuration error */ > +#define SC_ERR_PARM 3U /*!< Bad parameter */ > +#define SC_ERR_NOACCESS 4U /*!< Permission error (no access) > */ > +#define SC_ERR_LOCKED 5U /*!< Permission error (locked) */ > +#define SC_ERR_UNAVAILABLE 6U /*!< Unavailable (out of resources) > */ > +#define SC_ERR_NOTFOUND 7U /*!< Not found */ > +#define SC_ERR_NOPOWER 8U /*!< No power */ > +#define SC_ERR_IPC 9U /*!< Generic IPC error */ > +#define SC_ERR_BUSY 10U /*!< Resource is currently > busy/active */ > +#define SC_ERR_FAIL 11U /*!< General I/O failure */ > +#define SC_ERR_LAST 12U > +/*@}*/ > + > +/*! > + * @name Defines for sc_rsrc_t. > + */ > +/*@{*/ > +#define SC_R_A53 0U > +#define SC_R_A53_0 1U > +#define SC_R_A53_1 2U > +#define SC_R_A53_2 3U > +#define SC_R_A53_3 4U > +#define SC_R_A72 5U > +#define SC_R_A72_0 6U > +#define SC_R_A72_1 7U > +#define SC_R_A72_2 8U > +#define SC_R_A72_3 9U > +#define SC_R_CCI 10U > +#define SC_R_DB 11U > +#define SC_R_DRC_0 12U > +#define SC_R_DRC_1 13U > +#define SC_R_GIC_SMMU 14U > +#define SC_R_IRQSTR_M4_0 15U > +#define SC_R_IRQSTR_M4_1 16U > +#define SC_R_SMMU 17U > +#define SC_R_GIC 18U > +#define SC_R_DC_0_BLIT0 19U > +#define SC_R_DC_0_BLIT1 20U > +#define SC_R_DC_0_BLIT2 21U > +#define SC_R_DC_0_BLIT_OUT 22U > +#define SC_R_DC_0_CAPTURE0 23U > +#define SC_R_DC_0_CAPTURE1 24U > +#define SC_R_DC_0_WARP 25U > +#define SC_R_DC_0_INTEGRAL0 26U > +#define SC_R_DC_0_INTEGRAL1 27U > +#define SC_R_DC_0_VIDEO0 28U > +#define SC_R_DC_0_VIDEO1 29U > +#define SC_R_DC_0_FRAC0 30U > +#define SC_R_DC_0_FRAC1 31U > +#define SC_R_DC_0 32U > +#define SC_R_GPU_2_PID0 33U > +#define SC_R_DC_0_PLL_0 34U > +#define SC_R_DC_0_PLL_1 35U > +#define SC_R_DC_1_BLIT0 36U > +#define SC_R_DC_1_BLIT1 37U > +#define SC_R_DC_1_BLIT2 38U > +#define SC_R_DC_1_BLIT_OUT 39U > +#define SC_R_DC_1_CAPTURE0 40U > +#define SC_R_DC_1_CAPTURE1 41U > +#define SC_R_DC_1_WARP 42U > +#define SC_R_DC_1_INTEGRAL0 43U > +#define SC_R_DC_1_INTEGRAL1 44U > +#define SC_R_DC_1_VIDEO0 45U > +#define SC_R_DC_1_VIDEO1 46U > +#define SC_R_DC_1_FRAC0 47U > +#define SC_R_DC_1_FRAC1 48U > +#define SC_R_DC_1 49U > +#define SC_R_GPU_3_PID0 50U > +#define SC_R_DC_1_PLL_0 51U > +#define SC_R_DC_1_PLL_1 52U > +#define SC_R_SPI_0 53U > +#define SC_R_SPI_1 54U > +#define SC_R_SPI_2 55U > +#define SC_R_SPI_3 56U > +#define SC_R_UART_0 57U > +#define SC_R_UART_1 58U > +#define SC_R_UART_2 59U > +#define SC_R_UART_3 60U > +#define SC_R_UART_4 61U > +#define SC_R_EMVSIM_0 62U > +#define SC_R_EMVSIM_1 63U > +#define SC_R_DMA_0_CH0 64U > +#define SC_R_DMA_0_CH1 65U > +#define SC_R_DMA_0_CH2 66U > +#define SC_R_DMA_0_CH3 67U > +#define SC_R_DMA_0_CH4 68U > +#define SC_R_DMA_0_CH5 69U > +#define SC_R_DMA_0_CH6 70U > +#define SC_R_DMA_0_CH7 71U > +#define SC_R_DMA_0_CH8 72U > +#define SC_R_DMA_0_CH9 73U > +#define SC_R_DMA_0_CH10 74U > +#define SC_R_DMA_0_CH11 75U > +#define SC_R_DMA_0_CH12 76U > +#define SC_R_DMA_0_CH13 77U > +#define SC_R_DMA_0_CH14 78U > +#define SC_R_DMA_0_CH15 79U > +#define SC_R_DMA_0_CH16 80U > +#define SC_R_DMA_0_CH17 81U > +#define SC_R_DMA_0_CH18 82U > +#define SC_R_DMA_0_CH19 83U > +#define SC_R_DMA_0_CH20 84U > +#define SC_R_DMA_0_CH21 85U > +#define SC_R_DMA_0_CH22 86U > +#define SC_R_DMA_0_CH23 87U > +#define SC_R_DMA_0_CH24 88U > +#define SC_R_DMA_0_CH25 89U > +#define SC_R_DMA_0_CH26 90U > +#define SC_R_DMA_0_CH27 91U > +#define SC_R_DMA_0_CH28 92U > +#define SC_R_DMA_0_CH29 93U > +#define SC_R_DMA_0_CH30 94U > +#define SC_R_DMA_0_CH31 95U > +#define SC_R_I2C_0 96U > +#define SC_R_I2C_1 97U > +#define SC_R_I2C_2 98U > +#define SC_R_I2C_3 99U > +#define SC_R_I2C_4 100U > +#define SC_R_ADC_0 101U > +#define SC_R_ADC_1 102U > +#define SC_R_FTM_0 103U > +#define SC_R_FTM_1 104U > +#define SC_R_CAN_0 105U > +#define SC_R_CAN_1 106U > +#define SC_R_CAN_2 107U > +#define SC_R_DMA_1_CH0 108U > +#define SC_R_DMA_1_CH1 109U > +#define SC_R_DMA_1_CH2 110U > +#define SC_R_DMA_1_CH3 111U > +#define SC_R_DMA_1_CH4 112U > +#define SC_R_DMA_1_CH5 113U > +#define SC_R_DMA_1_CH6 114U > +#define SC_R_DMA_1_CH7 115U > +#define SC_R_DMA_1_CH8 116U > +#define SC_R_DMA_1_CH9 117U > +#define SC_R_DMA_1_CH10 118U > +#define SC_R_DMA_1_CH11 119U > +#define SC_R_DMA_1_CH12 120U > +#define SC_R_DMA_1_CH13 121U > +#define SC_R_DMA_1_CH14 122U > +#define SC_R_DMA_1_CH15 123U > +#define SC_R_DMA_1_CH16 124U > +#define SC_R_DMA_1_CH17 125U > +#define SC_R_DMA_1_CH18 126U > +#define SC_R_DMA_1_CH19 127U > +#define SC_R_DMA_1_CH20 128U > +#define SC_R_DMA_1_CH21 129U > +#define SC_R_DMA_1_CH22 130U > +#define SC_R_DMA_1_CH23 131U > +#define SC_R_DMA_1_CH24 132U > +#define SC_R_DMA_1_CH25 133U > +#define SC_R_DMA_1_CH26 134U > +#define SC_R_DMA_1_CH27 135U > +#define SC_R_DMA_1_CH28 136U > +#define SC_R_DMA_1_CH29 137U > +#define SC_R_DMA_1_CH30 138U > +#define SC_R_DMA_1_CH31 139U > +#define SC_R_UNUSED1 140U > +#define SC_R_UNUSED2 141U > +#define SC_R_UNUSED3 142U > +#define SC_R_UNUSED4 143U > +#define SC_R_GPU_0_PID0 144U > +#define SC_R_GPU_0_PID1 145U > +#define SC_R_GPU_0_PID2 146U > +#define SC_R_GPU_0_PID3 147U > +#define SC_R_GPU_1_PID0 148U > +#define SC_R_GPU_1_PID1 149U > +#define SC_R_GPU_1_PID2 150U > +#define SC_R_GPU_1_PID3 151U > +#define SC_R_PCIE_A 152U > +#define SC_R_SERDES_0 153U > +#define SC_R_MATCH_0 154U > +#define SC_R_MATCH_1 155U > +#define SC_R_MATCH_2 156U > +#define SC_R_MATCH_3 157U > +#define SC_R_MATCH_4 158U > +#define SC_R_MATCH_5 159U > +#define SC_R_MATCH_6 160U > +#define SC_R_MATCH_7 161U > +#define SC_R_MATCH_8 162U > +#define SC_R_MATCH_9 163U > +#define SC_R_MATCH_10 164U > +#define SC_R_MATCH_11 165U > +#define SC_R_MATCH_12 166U > +#define SC_R_MATCH_13 167U > +#define SC_R_MATCH_14 168U > +#define SC_R_PCIE_B 169U > +#define SC_R_SATA_0 170U > +#define SC_R_SERDES_1 171U > +#define SC_R_HSIO_GPIO 172U > +#define SC_R_MATCH_15 173U > +#define SC_R_MATCH_16 174U > +#define SC_R_MATCH_17 175U > +#define SC_R_MATCH_18 176U > +#define SC_R_MATCH_19 177U > +#define SC_R_MATCH_20 178U > +#define SC_R_MATCH_21 179U > +#define SC_R_MATCH_22 180U > +#define SC_R_MATCH_23 181U > +#define SC_R_MATCH_24 182U > +#define SC_R_MATCH_25 183U > +#define SC_R_MATCH_26 184U > +#define SC_R_MATCH_27 185U > +#define SC_R_MATCH_28 186U > +#define SC_R_LCD_0 187U > +#define SC_R_LCD_0_PWM_0 188U > +#define SC_R_LCD_0_I2C_0 189U > +#define SC_R_LCD_0_I2C_1 190U > +#define SC_R_PWM_0 191U > +#define SC_R_PWM_1 192U > +#define SC_R_PWM_2 193U > +#define SC_R_PWM_3 194U > +#define SC_R_PWM_4 195U > +#define SC_R_PWM_5 196U > +#define SC_R_PWM_6 197U > +#define SC_R_PWM_7 198U > +#define SC_R_GPIO_0 199U > +#define SC_R_GPIO_1 200U > +#define SC_R_GPIO_2 201U > +#define SC_R_GPIO_3 202U > +#define SC_R_GPIO_4 203U > +#define SC_R_GPIO_5 204U > +#define SC_R_GPIO_6 205U > +#define SC_R_GPIO_7 206U > +#define SC_R_GPT_0 207U > +#define SC_R_GPT_1 208U > +#define SC_R_GPT_2 209U > +#define SC_R_GPT_3 210U > +#define SC_R_GPT_4 211U > +#define SC_R_KPP 212U > +#define SC_R_MU_0A 213U > +#define SC_R_MU_1A 214U > +#define SC_R_MU_2A 215U > +#define SC_R_MU_3A 216U > +#define SC_R_MU_4A 217U > +#define SC_R_MU_5A 218U > +#define SC_R_MU_6A 219U > +#define SC_R_MU_7A 220U > +#define SC_R_MU_8A 221U > +#define SC_R_MU_9A 222U > +#define SC_R_MU_10A 223U > +#define SC_R_MU_11A 224U > +#define SC_R_MU_12A 225U > +#define SC_R_MU_13A 226U > +#define SC_R_MU_5B 227U > +#define SC_R_MU_6B 228U > +#define SC_R_MU_7B 229U > +#define SC_R_MU_8B 230U > +#define SC_R_MU_9B 231U > +#define SC_R_MU_10B 232U > +#define SC_R_MU_11B 233U > +#define SC_R_MU_12B 234U > +#define SC_R_MU_13B 235U > +#define SC_R_ROM_0 236U > +#define SC_R_FSPI_0 237U > +#define SC_R_FSPI_1 238U > +#define SC_R_IEE 239U > +#define SC_R_IEE_R0 240U > +#define SC_R_IEE_R1 241U > +#define SC_R_IEE_R2 242U > +#define SC_R_IEE_R3 243U > +#define SC_R_IEE_R4 244U > +#define SC_R_IEE_R5 245U > +#define SC_R_IEE_R6 246U > +#define SC_R_IEE_R7 247U > +#define SC_R_SDHC_0 248U > +#define SC_R_SDHC_1 249U > +#define SC_R_SDHC_2 250U > +#define SC_R_ENET_0 251U > +#define SC_R_ENET_1 252U > +#define SC_R_MLB_0 253U > +#define SC_R_DMA_2_CH0 254U > +#define SC_R_DMA_2_CH1 255U > +#define SC_R_DMA_2_CH2 256U > +#define SC_R_DMA_2_CH3 257U > +#define SC_R_DMA_2_CH4 258U > +#define SC_R_USB_0 259U > +#define SC_R_USB_1 260U > +#define SC_R_USB_0_PHY 261U > +#define SC_R_USB_2 262U > +#define SC_R_USB_2_PHY 263U > +#define SC_R_DTCP 264U > +#define SC_R_NAND 265U > +#define SC_R_LVDS_0 266U > +#define SC_R_LVDS_0_PWM_0 267U > +#define SC_R_LVDS_0_I2C_0 268U > +#define SC_R_LVDS_0_I2C_1 269U > +#define SC_R_LVDS_1 270U > +#define SC_R_LVDS_1_PWM_0 271U > +#define SC_R_LVDS_1_I2C_0 272U > +#define SC_R_LVDS_1_I2C_1 273U > +#define SC_R_LVDS_2 274U > +#define SC_R_LVDS_2_PWM_0 275U > +#define SC_R_LVDS_2_I2C_0 276U > +#define SC_R_LVDS_2_I2C_1 277U > +#define SC_R_M4_0_PID0 278U > +#define SC_R_M4_0_PID1 279U > +#define SC_R_M4_0_PID2 280U > +#define SC_R_M4_0_PID3 281U > +#define SC_R_M4_0_PID4 282U > +#define SC_R_M4_0_RGPIO 283U > +#define SC_R_M4_0_SEMA42 284U > +#define SC_R_M4_0_TPM 285U > +#define SC_R_M4_0_PIT 286U > +#define SC_R_M4_0_UART 287U > +#define SC_R_M4_0_I2C 288U > +#define SC_R_M4_0_INTMUX 289U > +#define SC_R_M4_0_SIM 290U > +#define SC_R_M4_0_WDOG 291U > +#define SC_R_M4_0_MU_0B 292U > +#define SC_R_M4_0_MU_0A0 293U > +#define SC_R_M4_0_MU_0A1 294U > +#define SC_R_M4_0_MU_0A2 295U > +#define SC_R_M4_0_MU_0A3 296U > +#define SC_R_M4_0_MU_1A 297U > +#define SC_R_M4_1_PID0 298U > +#define SC_R_M4_1_PID1 299U > +#define SC_R_M4_1_PID2 300U > +#define SC_R_M4_1_PID3 301U > +#define SC_R_M4_1_PID4 302U > +#define SC_R_M4_1_RGPIO 303U > +#define SC_R_M4_1_SEMA42 304U > +#define SC_R_M4_1_TPM 305U > +#define SC_R_M4_1_PIT 306U > +#define SC_R_M4_1_UART 307U > +#define SC_R_M4_1_I2C 308U > +#define SC_R_M4_1_INTMUX 309U > +#define SC_R_M4_1_SIM 310U > +#define SC_R_M4_1_WDOG 311U > +#define SC_R_M4_1_MU_0B 312U > +#define SC_R_M4_1_MU_0A0 313U > +#define SC_R_M4_1_MU_0A1 314U > +#define SC_R_M4_1_MU_0A2 315U > +#define SC_R_M4_1_MU_0A3 316U > +#define SC_R_M4_1_MU_1A 317U > +#define SC_R_SAI_0 318U > +#define SC_R_SAI_1 319U > +#define SC_R_SAI_2 320U > +#define SC_R_IRQSTR_SCU2 321U > +#define SC_R_IRQSTR_DSP 322U > +#define SC_R_UNUSED5 323U > +#define SC_R_OCRAM 324U > +#define SC_R_AUDIO_PLL_0 325U > +#define SC_R_PI_0 326U > +#define SC_R_PI_0_PWM_0 327U > +#define SC_R_PI_0_PWM_1 328U > +#define SC_R_PI_0_I2C_0 329U > +#define SC_R_PI_0_PLL 330U > +#define SC_R_PI_1 331U > +#define SC_R_PI_1_PWM_0 332U > +#define SC_R_PI_1_PWM_1 333U > +#define SC_R_PI_1_I2C_0 334U > +#define SC_R_PI_1_PLL 335U > +#define SC_R_SC_PID0 336U > +#define SC_R_SC_PID1 337U > +#define SC_R_SC_PID2 338U > +#define SC_R_SC_PID3 339U > +#define SC_R_SC_PID4 340U > +#define SC_R_SC_SEMA42 341U > +#define SC_R_SC_TPM 342U > +#define SC_R_SC_PIT 343U > +#define SC_R_SC_UART 344U > +#define SC_R_SC_I2C 345U > +#define SC_R_SC_MU_0B 346U > +#define SC_R_SC_MU_0A0 347U > +#define SC_R_SC_MU_0A1 348U > +#define SC_R_SC_MU_0A2 349U > +#define SC_R_SC_MU_0A3 350U > +#define SC_R_SC_MU_1A 351U > +#define SC_R_SYSCNT_RD 352U > +#define SC_R_SYSCNT_CMP 353U > +#define SC_R_DEBUG 354U > +#define SC_R_SYSTEM 355U > +#define SC_R_SNVS 356U > +#define SC_R_OTP 357U > +#define SC_R_VPU_PID0 358U > +#define SC_R_VPU_PID1 359U > +#define SC_R_VPU_PID2 360U > +#define SC_R_VPU_PID3 361U > +#define SC_R_VPU_PID4 362U > +#define SC_R_VPU_PID5 363U > +#define SC_R_VPU_PID6 364U > +#define SC_R_VPU_PID7 365U > +#define SC_R_VPU_UART 366U > +#define SC_R_VPUCORE 367U > +#define SC_R_VPUCORE_0 368U > +#define SC_R_VPUCORE_1 369U > +#define SC_R_VPUCORE_2 370U > +#define SC_R_VPUCORE_3 371U > +#define SC_R_DMA_4_CH0 372U > +#define SC_R_DMA_4_CH1 373U > +#define SC_R_DMA_4_CH2 374U > +#define SC_R_DMA_4_CH3 375U > +#define SC_R_DMA_4_CH4 376U > +#define SC_R_ISI_CH0 377U > +#define SC_R_ISI_CH1 378U > +#define SC_R_ISI_CH2 379U > +#define SC_R_ISI_CH3 380U > +#define SC_R_ISI_CH4 381U > +#define SC_R_ISI_CH5 382U > +#define SC_R_ISI_CH6 383U > +#define SC_R_ISI_CH7 384U > +#define SC_R_MJPEG_DEC_S0 385U > +#define SC_R_MJPEG_DEC_S1 386U > +#define SC_R_MJPEG_DEC_S2 387U > +#define SC_R_MJPEG_DEC_S3 388U > +#define SC_R_MJPEG_ENC_S0 389U > +#define SC_R_MJPEG_ENC_S1 390U > +#define SC_R_MJPEG_ENC_S2 391U > +#define SC_R_MJPEG_ENC_S3 392U > +#define SC_R_MIPI_0 393U > +#define SC_R_MIPI_0_PWM_0 394U > +#define SC_R_MIPI_0_I2C_0 395U > +#define SC_R_MIPI_0_I2C_1 396U > +#define SC_R_MIPI_1 397U > +#define SC_R_MIPI_1_PWM_0 398U > +#define SC_R_MIPI_1_I2C_0 399U > +#define SC_R_MIPI_1_I2C_1 400U > +#define SC_R_CSI_0 401U > +#define SC_R_CSI_0_PWM_0 402U > +#define SC_R_CSI_0_I2C_0 403U > +#define SC_R_CSI_1 404U > +#define SC_R_CSI_1_PWM_0 405U > +#define SC_R_CSI_1_I2C_0 406U > +#define SC_R_HDMI 407U > +#define SC_R_HDMI_I2S 408U > +#define SC_R_HDMI_I2C_0 409U > +#define SC_R_HDMI_PLL_0 410U > +#define SC_R_HDMI_RX 411U > +#define SC_R_HDMI_RX_BYPASS 412U > +#define SC_R_HDMI_RX_I2C_0 413U > +#define SC_R_ASRC_0 414U > +#define SC_R_ESAI_0 415U > +#define SC_R_SPDIF_0 416U > +#define SC_R_SPDIF_1 417U > +#define SC_R_SAI_3 418U > +#define SC_R_SAI_4 419U > +#define SC_R_SAI_5 420U > +#define SC_R_GPT_5 421U > +#define SC_R_GPT_6 422U > +#define SC_R_GPT_7 423U > +#define SC_R_GPT_8 424U > +#define SC_R_GPT_9 425U > +#define SC_R_GPT_10 426U > +#define SC_R_DMA_2_CH5 427U > +#define SC_R_DMA_2_CH6 428U > +#define SC_R_DMA_2_CH7 429U > +#define SC_R_DMA_2_CH8 430U > +#define SC_R_DMA_2_CH9 431U > +#define SC_R_DMA_2_CH10 432U > +#define SC_R_DMA_2_CH11 433U > +#define SC_R_DMA_2_CH12 434U > +#define SC_R_DMA_2_CH13 435U > +#define SC_R_DMA_2_CH14 436U > +#define SC_R_DMA_2_CH15 437U > +#define SC_R_DMA_2_CH16 438U > +#define SC_R_DMA_2_CH17 439U > +#define SC_R_DMA_2_CH18 440U > +#define SC_R_DMA_2_CH19 441U > +#define SC_R_DMA_2_CH20 442U > +#define SC_R_DMA_2_CH21 443U > +#define SC_R_DMA_2_CH22 444U > +#define SC_R_DMA_2_CH23 445U > +#define SC_R_DMA_2_CH24 446U > +#define SC_R_DMA_2_CH25 447U > +#define SC_R_DMA_2_CH26 448U > +#define SC_R_DMA_2_CH27 449U > +#define SC_R_DMA_2_CH28 450U > +#define SC_R_DMA_2_CH29 451U > +#define SC_R_DMA_2_CH30 452U > +#define SC_R_DMA_2_CH31 453U > +#define SC_R_ASRC_1 454U > +#define SC_R_ESAI_1 455U > +#define SC_R_SAI_6 456U > +#define SC_R_SAI_7 457U > +#define SC_R_AMIX 458U > +#define SC_R_MQS_0 459U > +#define SC_R_DMA_3_CH0 460U > +#define SC_R_DMA_3_CH1 461U > +#define SC_R_DMA_3_CH2 462U > +#define SC_R_DMA_3_CH3 463U > +#define SC_R_DMA_3_CH4 464U > +#define SC_R_DMA_3_CH5 465U > +#define SC_R_DMA_3_CH6 466U > +#define SC_R_DMA_3_CH7 467U > +#define SC_R_DMA_3_CH8 468U > +#define SC_R_DMA_3_CH9 469U > +#define SC_R_DMA_3_CH10 470U > +#define SC_R_DMA_3_CH11 471U > +#define SC_R_DMA_3_CH12 472U > +#define SC_R_DMA_3_CH13 473U > +#define SC_R_DMA_3_CH14 474U > +#define SC_R_DMA_3_CH15 475U > +#define SC_R_DMA_3_CH16 476U > +#define SC_R_DMA_3_CH17 477U > +#define SC_R_DMA_3_CH18 478U > +#define SC_R_DMA_3_CH19 479U > +#define SC_R_DMA_3_CH20 480U > +#define SC_R_DMA_3_CH21 481U > +#define SC_R_DMA_3_CH22 482U > +#define SC_R_DMA_3_CH23 483U > +#define SC_R_DMA_3_CH24 484U > +#define SC_R_DMA_3_CH25 485U > +#define SC_R_DMA_3_CH26 486U > +#define SC_R_DMA_3_CH27 487U > +#define SC_R_DMA_3_CH28 488U > +#define SC_R_DMA_3_CH29 489U > +#define SC_R_DMA_3_CH30 490U > +#define SC_R_DMA_3_CH31 491U > +#define SC_R_AUDIO_PLL_1 492U > +#define SC_R_AUDIO_CLK_0 493U > +#define SC_R_AUDIO_CLK_1 494U > +#define SC_R_MCLK_OUT_0 495U > +#define SC_R_MCLK_OUT_1 496U > +#define SC_R_PMIC_0 497U > +#define SC_R_PMIC_1 498U > +#define SC_R_SECO 499U > +#define SC_R_CAAM_JR1 500U > +#define SC_R_CAAM_JR2 501U > +#define SC_R_CAAM_JR3 502U > +#define SC_R_SECO_MU_2 503U > +#define SC_R_SECO_MU_3 504U > +#define SC_R_SECO_MU_4 505U > +#define SC_R_HDMI_RX_PWM_0 506U > +#define SC_R_A35 507U > +#define SC_R_A35_0 508U > +#define SC_R_A35_1 509U > +#define SC_R_A35_2 510U > +#define SC_R_A35_3 511U > +#define SC_R_DSP 512U > +#define SC_R_DSP_RAM 513U > +#define SC_R_CAAM_JR1_OUT 514U > +#define SC_R_CAAM_JR2_OUT 515U > +#define SC_R_CAAM_JR3_OUT 516U > +#define SC_R_VPU_DEC_0 517U > +#define SC_R_VPU_ENC_0 518U > +#define SC_R_CAAM_JR0 519U > +#define SC_R_CAAM_JR0_OUT 520U > +#define SC_R_PMIC_2 521U > +#define SC_R_DBLOGIC 522U > +#define SC_R_HDMI_PLL_1 523U > +#define SC_R_BOARD_R0 524U > +#define SC_R_BOARD_R1 525U > +#define SC_R_BOARD_R2 526U > +#define SC_R_BOARD_R3 527U > +#define SC_R_BOARD_R4 528U > +#define SC_R_BOARD_R5 529U > +#define SC_R_BOARD_R6 530U > +#define SC_R_BOARD_R7 531U > +#define SC_R_MJPEG_DEC_MP 532U > +#define SC_R_MJPEG_ENC_MP 533U > +#define SC_R_VPU_TS_0 534U > +#define SC_R_VPU_MU_0 535U > +#define SC_R_VPU_MU_1 536U > +#define SC_R_VPU_MU_2 537U > +#define SC_R_VPU_MU_3 538U > +#define SC_R_VPU_ENC_1 539U > +#define SC_R_VPU 540U > +#define SC_R_LAST 541U > +#define SC_R_ALL ((sc_rsrc_t) UINT16_MAX) /*!< All > resources */ > +/*@}*/ > + > +/* NOTE - please add by replacing some of the UNUSED from above! */ > + > +/*! > + * Defnes for sc_ctrl_t. > + */ > +#define SC_C_TEMP 0U > +#define SC_C_TEMP_HI 1U > +#define SC_C_TEMP_LOW 2U > +#define SC_C_PXL_LINK_MST1_ADDR 3U > +#define SC_C_PXL_LINK_MST2_ADDR 4U > +#define SC_C_PXL_LINK_MST_ENB 5U > +#define SC_C_PXL_LINK_MST1_ENB 6U > +#define SC_C_PXL_LINK_MST2_ENB 7U > +#define SC_C_PXL_LINK_SLV1_ADDR 8U > +#define SC_C_PXL_LINK_SLV2_ADDR 9U > +#define SC_C_PXL_LINK_MST_VLD 10U > +#define SC_C_PXL_LINK_MST1_VLD 11U > +#define SC_C_PXL_LINK_MST2_VLD 12U > +#define SC_C_SINGLE_MODE 13U > +#define SC_C_ID 14U > +#define SC_C_PXL_CLK_POLARITY 15U > +#define SC_C_LINESTATE 16U > +#define SC_C_PCIE_G_RST 17U > +#define SC_C_PCIE_BUTTON_RST 18U > +#define SC_C_PCIE_PERST 19U > +#define SC_C_PHY_RESET 20U > +#define SC_C_PXL_LINK_RATE_CORRECTION 21U > +#define SC_C_PANIC 22U > +#define SC_C_PRIORITY_GROUP 23U > +#define SC_C_TXCLK 24U > +#define SC_C_CLKDIV 25U > +#define SC_C_DISABLE_50 26U > +#define SC_C_DISABLE_125 27U > +#define SC_C_SEL_125 28U > +#define SC_C_MODE 29U > +#define SC_C_SYNC_CTRL0 30U > +#define SC_C_KACHUNK_CNT 31U > +#define SC_C_KACHUNK_SEL 32U > +#define SC_C_SYNC_CTRL1 33U > +#define SC_C_DPI_RESET 34U > +#define SC_C_MIPI_RESET 35U > +#define SC_C_DUAL_MODE 36U > +#define SC_C_VOLTAGE 37U > +#define SC_C_PXL_LINK_SEL 38U > +#define SC_C_OFS_SEL 39U > +#define SC_C_OFS_AUDIO 40U > +#define SC_C_OFS_PERIPH 41U > +#define SC_C_OFS_IRQ 42U > +#define SC_C_RST0 43U > +#define SC_C_RST1 44U > +#define SC_C_SEL0 45U > +#define SC_C_LAST 46U > + > +#define SC_P_ALL ((sc_pad_t) UINT16_MAX) /*!< All pads */ > + > +/* Types */ > + > +/*! > + * This type is used to store a boolean > + */ > +typedef uint8_t sc_bool_t; > + > +/*! > + * This type is used to store a system (full-size) address. > + */ > +typedef uint64_t sc_faddr_t; > + > +/*! > + * This type is used to indicate error response for most functions. > + */ > +typedef uint8_t sc_err_t; > + > +/*! > + * This type is used to indicate a resource. Resources include peripherals > + * and bus masters (but not memory regions). Note items from list should > + * never be changed or removed (only added to at the end of the list). > + */ > +typedef uint16_t sc_rsrc_t; > + > +/*! > + * This type is used to indicate a control. > + */ > +typedef uint8_t sc_ctrl_t; > + > +/*! > + * This type is used to indicate a pad. Valid values are SoC specific. > + * > + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. > + */ > +typedef uint16_t sc_pad_t; > + > +/* Extra documentation of standard types */ > + > +#ifdef DOXYGEN > + /*! > + * Type used to declare an 8-bit integer. > + */ > + typedef __INT8_TYPE__ int8_t; > + > + /*! > + * Type used to declare a 16-bit integer. > + */ > + typedef __INT16_TYPE__ int16_t; > + > + /*! > + * Type used to declare a 32-bit integer. > + */ > + typedef __INT32_TYPE__ int32_t; > + > + /*! > + * Type used to declare a 64-bit integer. > + */ > + typedef __INT64_TYPE__ int64_t; > + > + /*! > + * Type used to declare an 8-bit unsigned integer. > + */ > + typedef __UINT8_TYPE__ uint8_t; > + > + /*! > + * Type used to declare a 16-bit unsigned integer. > + */ > + typedef __UINT16_TYPE__ uint16_t; > + > + /*! > + * Type used to declare a 32-bit unsigned integer. > + */ > + typedef __UINT32_TYPE__ uint32_t; > + > + /*! > + * Type used to declare a 64-bit unsigned integer. > + */ > + typedef __UINT64_TYPE__ uint64_t; > +#endif > + > +#endif /* SC_TYPES_H */ > + > diff --git a/arch/arm/mach-imx/imx8/Makefile > b/arch/arm/mach-imx/imx8/Makefile > new file mode 100644 > index 0000000000..cfb7e34653 > --- /dev/null > +++ b/arch/arm/mach-imx/imx8/Makefile > @@ -0,0 +1,11 @@ > +# > +# Copyright 2018 NXP > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +obj-y += sci/svc/misc/rpc_clnt.o > +obj-y += sci/svc/pad/rpc_clnt.o > +obj-y += sci/svc/pm/rpc_clnt.o > +obj-y += sci/svc/rm/rpc_clnt.o > +obj-y += sci/svc/timer/rpc_clnt.o > diff --git a/arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h > b/arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h > new file mode 100644 > index 0000000000..ca0653d4da > --- /dev/null > +++ b/arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h > @@ -0,0 +1,54 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * Header file for the IRQ RPC implementation. > + * > + * @addtogroup IRQ_SVC > + * @{ > + */ > + > +#ifndef SC_IRQ_RPC_H > +#define SC_IRQ_RPC_H > + > +/* Includes */ > + > +/* Defines */ > + > +/*! > + * @name Defines for RPC IRQ function calls > + */ > +/*@{*/ > +#define IRQ_FUNC_UNKNOWN 0 /*!< Unknown function */ > +#define IRQ_FUNC_ENABLE 1U /*!< Index for irq_enable() RPC call */ > +#define IRQ_FUNC_STATUS 2U /*!< Index for irq_status() RPC call */ > +/*@}*/ > + > +/* Types */ > + > +/* Functions */ > + > +/*! > + * This function dispatches an incoming IRQ RPC request. > + * > + * @param[in] caller_pt caller partition > + * @param[in] msg pointer to RPC message > + */ > +void irq_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg); > + > +/*! > + * This function translates and dispatches an IRQ RPC request. > + * > + * @param[in] ipc IPC handle > + * @param[in] msg pointer to RPC message > + */ > +void irq_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg); > + > +#endif /* SC_IRQ_RPC_H */ > + > +/**@}*/ > + > diff --git a/arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c > b/arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c > new file mode 100644 > index 0000000000..8ecff72e21 > --- /dev/null > +++ b/arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c > @@ -0,0 +1,76 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * File containing client-side RPC functions for the IRQ service. These > + * functions are ported to clients that communicate to the SC. > + * > + * @addtogroup IRQ_SVC > + * @{ > + */ > + > +/* Includes */ > + > +#include <asm/arch/sci/types.h> > +#include <asm/arch/sci/svc/rm/api.h> > +#include <asm/arch/sci/svc/irq/api.h> > +#include <asm/arch/sci/rpc.h> > +#include "rpc.h" > + > +/* Local Defines */ > + > +/* Local Types */ > + > +/* Local Functions */ > + > +sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_irq_group_t group, uint32_t mask, sc_bool_t enable) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_IRQ; > + RPC_FUNC(&msg) = (uint8_t) IRQ_FUNC_ENABLE; > + RPC_U32(&msg, 0U) = (uint32_t) mask; > + RPC_U16(&msg, 4U) = (uint16_t) resource; > + RPC_U8(&msg, 6U) = (uint8_t) group; > + RPC_U8(&msg, 7U) = (uint8_t) enable; > + RPC_SIZE(&msg) = 3U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_irq_group_t group, uint32_t *status) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_IRQ; > + RPC_FUNC(&msg) = (uint8_t) IRQ_FUNC_STATUS; > + RPC_U16(&msg, 0U) = (uint16_t) resource; > + RPC_U8(&msg, 2U) = (uint8_t) group; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + if (status != NULL) > + { > + *status = RPC_U32(&msg, 0U); > + } > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +/**@}*/ > + > diff --git a/arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h > b/arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h > new file mode 100644 > index 0000000000..fee681d889 > --- /dev/null > +++ b/arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h > @@ -0,0 +1,76 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * Header file for the MISC RPC implementation. > + * > + * @addtogroup MISC_SVC > + * @{ > + */ > + > +#ifndef SC_MISC_RPC_H > +#define SC_MISC_RPC_H > + > +/* Includes */ > + > +/* Defines */ > + > +/*! > + * @name Defines for RPC MISC function calls > + */ > +/*@{*/ > +#define MISC_FUNC_UNKNOWN 0 /*!< Unknown function */ > +#define MISC_FUNC_SET_CONTROL 1U /*!< Index for misc_set_control() RPC > call */ > +#define MISC_FUNC_GET_CONTROL 2U /*!< Index for misc_get_control() RPC > call */ > +#define MISC_FUNC_SET_MAX_DMA_GROUP 4U /*!< Index for > misc_set_max_dma_group() RPC call */ > +#define MISC_FUNC_SET_DMA_GROUP 5U /*!< Index for > misc_set_dma_group() RPC call */ > +#define MISC_FUNC_SECO_IMAGE_LOAD 8U /*!< Index for > misc_seco_image_load() RPC call */ > +#define MISC_FUNC_SECO_AUTHENTICATE 9U /*!< Index for > misc_seco_authenticate() RPC call */ > +#define MISC_FUNC_SECO_FUSE_WRITE 20U /*!< Index for > misc_seco_fuse_write() RPC call */ > +#define MISC_FUNC_SECO_ENABLE_DEBUG 21U /*!< Index for > misc_seco_enable_debug() RPC call */ > +#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U /*!< Index for > misc_seco_forward_lifecycle() RPC call */ > +#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U /*!< Index for > misc_seco_return_lifecycle() RPC call */ > +#define MISC_FUNC_SECO_BUILD_INFO 24U /*!< Index for > misc_seco_build_info() RPC call */ > +#define MISC_FUNC_DEBUG_OUT 10U /*!< Index for misc_debug_out() RPC > call */ > +#define MISC_FUNC_WAVEFORM_CAPTURE 6U /*!< Index for > misc_waveform_capture() RPC call */ > +#define MISC_FUNC_BUILD_INFO 15U /*!< Index for misc_build_info() RPC call > */ > +#define MISC_FUNC_UNIQUE_ID 19U /*!< Index for misc_unique_id() RPC call > */ > +#define MISC_FUNC_SET_ARI 3U /*!< Index for misc_set_ari() RPC call */ > +#define MISC_FUNC_BOOT_STATUS 7U /*!< Index for misc_boot_status() RPC > call */ > +#define MISC_FUNC_BOOT_DONE 14U /*!< Index for misc_boot_done() RPC > call */ > +#define MISC_FUNC_OTP_FUSE_READ 11U /*!< Index for > misc_otp_fuse_read() RPC call */ > +#define MISC_FUNC_OTP_FUSE_WRITE 17U /*!< Index for > misc_otp_fuse_write() RPC call */ > +#define MISC_FUNC_SET_TEMP 12U /*!< Index for misc_set_temp() RPC call > */ > +#define MISC_FUNC_GET_TEMP 13U /*!< Index for misc_get_temp() RPC call > */ > +#define MISC_FUNC_GET_BOOT_DEV 16U /*!< Index for misc_get_boot_dev() > RPC call */ > +#define MISC_FUNC_GET_BUTTON_STATUS 18U /*!< Index for > misc_get_button_status() RPC call */ > +/*@}*/ > + > +/* Types */ > + > +/* Functions */ > + > +/*! > + * This function dispatches an incoming MISC RPC request. > + * > + * @param[in] caller_pt caller partition > + * @param[in] msg pointer to RPC message > + */ > +void misc_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg); > + > +/*! > + * This function translates and dispatches an MISC RPC request. > + * > + * @param[in] ipc IPC handle > + * @param[in] msg pointer to RPC message > + */ > +void misc_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg); > + > +#endif /* SC_MISC_RPC_H */ > + > +/**@}*/ > + > diff --git a/arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c > b/arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c > new file mode 100644 > index 0000000000..b4a9741986 > --- /dev/null > +++ b/arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c > @@ -0,0 +1,515 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * File containing client-side RPC functions for the MISC service. These > + * functions are ported to clients that communicate to the SC. > + * > + * @addtogroup MISC_SVC > + * @{ > + */ > + > +/* Includes */ > + > +#include <asm/arch/sci/types.h> > +#include <asm/arch/sci/svc/rm/api.h> > +#include <asm/arch/sci/svc/misc/api.h> > +#include <asm/arch/sci/rpc.h> > +#include "rpc.h" > + > +/* Local Defines */ > + > +/* Local Types */ > + > +/* Local Functions */ > + > +sc_err_t sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_ctrl_t ctrl, uint32_t val) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; > + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SET_CONTROL; > + RPC_U32(&msg, 0U) = (uint32_t) ctrl; > + RPC_U32(&msg, 4U) = (uint32_t) val; > + RPC_U16(&msg, 8U) = (uint16_t) resource; > + RPC_SIZE(&msg) = 4U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_ctrl_t ctrl, uint32_t *val) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; > + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_GET_CONTROL; > + RPC_U32(&msg, 0U) = (uint32_t) ctrl; > + RPC_U16(&msg, 4U) = (uint16_t) resource; > + RPC_SIZE(&msg) = 3U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + if (val != NULL) > + { > + *val = RPC_U32(&msg, 0U); > + } > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_misc_set_max_dma_group(sc_ipc_t ipc, sc_rm_pt_t pt, > + sc_misc_dma_group_t max) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; > + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SET_MAX_DMA_GROUP; > + RPC_U8(&msg, 0U) = (uint8_t) pt; > + RPC_U8(&msg, 1U) = (uint8_t) max; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_misc_set_dma_group(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_misc_dma_group_t group) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; > + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SET_DMA_GROUP; > + RPC_U16(&msg, 0U) = (uint16_t) resource; > + RPC_U8(&msg, 2U) = (uint8_t) group; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_misc_seco_image_load(sc_ipc_t ipc, sc_faddr_t addr_src, > + sc_faddr_t addr_dst, uint32_t len, sc_bool_t fw) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; > + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SECO_IMAGE_LOAD; > + RPC_U32(&msg, 0U) = (uint32_t) (addr_src >> 32U); > + RPC_U32(&msg, 4U) = (uint32_t) addr_src; > + RPC_U32(&msg, 8U) = (uint32_t) (addr_dst >> 32U); > + RPC_U32(&msg, 12U) = (uint32_t) addr_dst; > + RPC_U32(&msg, 16U) = (uint32_t) len; > + RPC_U8(&msg, 20U) = (uint8_t) fw; > + RPC_SIZE(&msg) = 7U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_misc_seco_authenticate(sc_ipc_t ipc, > + sc_misc_seco_auth_cmd_t cmd, sc_faddr_t addr) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; > + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SECO_AUTHENTICATE; > + RPC_U32(&msg, 0U) = (uint32_t) (addr >> 32U); > + RPC_U32(&msg, 4U) = (uint32_t) addr; > + RPC_U8(&msg, 8U) = (uint8_t) cmd; > + RPC_SIZE(&msg) = 4U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_misc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; > + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SECO_FUSE_WRITE; > + RPC_U32(&msg, 0U) = (uint32_t) (addr >> 32U); > + RPC_U32(&msg, 4U) = (uint32_t) addr; > + RPC_SIZE(&msg) = 3U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_misc_seco_enable_debug(sc_ipc_t ipc, sc_faddr_t addr) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; > + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SECO_ENABLE_DEBUG; > + RPC_U32(&msg, 0U) = (uint32_t) (addr >> 32U); > + RPC_U32(&msg, 4U) = (uint32_t) addr; > + RPC_SIZE(&msg) = 3U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_misc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t lifecycle) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; > + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SECO_FORWARD_LIFECYCLE; > + RPC_U32(&msg, 0U) = (uint32_t) lifecycle; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_misc_seco_return_lifecycle(sc_ipc_t ipc, sc_faddr_t addr) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; > + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SECO_RETURN_LIFECYCLE; > + RPC_U32(&msg, 0U) = (uint32_t) (addr >> 32U); > + RPC_U32(&msg, 4U) = (uint32_t) addr; > + RPC_SIZE(&msg) = 3U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +void sc_misc_seco_build_info(sc_ipc_t ipc, uint32_t *version, > + uint32_t *commit) > +{ > + sc_rpc_msg_t msg; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; > + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SECO_BUILD_INFO; > + RPC_SIZE(&msg) = 1U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + if (version != NULL) > + { > + *version = RPC_U32(&msg, 0U); > + } > + > + if (commit != NULL) > + { > + *commit = RPC_U32(&msg, 4U); > + } > + > + return; > +} > + > +void sc_misc_debug_out(sc_ipc_t ipc, uint8_t ch) > +{ > + sc_rpc_msg_t msg; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; > + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_DEBUG_OUT; > + RPC_U8(&msg, 0U) = (uint8_t) ch; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + return; > +} > + > +sc_err_t sc_misc_waveform_capture(sc_ipc_t ipc, sc_bool_t enable) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; > + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_WAVEFORM_CAPTURE; > + RPC_U8(&msg, 0U) = (uint8_t) enable; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +void sc_misc_build_info(sc_ipc_t ipc, uint32_t *build, > + uint32_t *commit) > +{ > + sc_rpc_msg_t msg; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; > + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_BUILD_INFO; > + RPC_SIZE(&msg) = 1U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + if (build != NULL) > + { > + *build = RPC_U32(&msg, 0U); > + } > + > + if (commit != NULL) > + { > + *commit = RPC_U32(&msg, 4U); > + } > + > + return; > +} > + > +void sc_misc_unique_id(sc_ipc_t ipc, uint32_t *id_l, > + uint32_t *id_h) > +{ > + sc_rpc_msg_t msg; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; > + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_UNIQUE_ID; > + RPC_SIZE(&msg) = 1U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + if (id_l != NULL) > + { > + *id_l = RPC_U32(&msg, 0U); > + } > + > + if (id_h != NULL) > + { > + *id_h = RPC_U32(&msg, 4U); > + } > + > + return; > +} > + > +sc_err_t sc_misc_set_ari(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_rsrc_t resource_mst, uint16_t ari, sc_bool_t enable) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; > + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SET_ARI; > + RPC_U16(&msg, 0U) = (uint16_t) resource; > + RPC_U16(&msg, 2U) = (uint16_t) resource_mst; > + RPC_U16(&msg, 4U) = (uint16_t) ari; > + RPC_U8(&msg, 6U) = (uint8_t) enable; > + RPC_SIZE(&msg) = 3U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status) > +{ > + sc_rpc_msg_t msg; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; > + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_BOOT_STATUS; > + RPC_U8(&msg, 0U) = (uint8_t) status; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_TRUE); > + > + return; > +} > + > +sc_err_t sc_misc_boot_done(sc_ipc_t ipc, sc_rsrc_t cpu) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; > + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_BOOT_DONE; > + RPC_U16(&msg, 0U) = (uint16_t) cpu; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_misc_otp_fuse_read(sc_ipc_t ipc, uint32_t word, uint32_t *val) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; > + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_OTP_FUSE_READ; > + RPC_U32(&msg, 0U) = (uint32_t) word; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + if (val != NULL) > + { > + *val = RPC_U32(&msg, 0U); > + } > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_misc_otp_fuse_write(sc_ipc_t ipc, uint32_t word, uint32_t val) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; > + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_OTP_FUSE_WRITE; > + RPC_U32(&msg, 0U) = (uint32_t) word; > + RPC_U32(&msg, 4U) = (uint32_t) val; > + RPC_SIZE(&msg) = 3U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_misc_set_temp(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_misc_temp_t temp, int16_t celsius, int8_t tenths) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; > + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SET_TEMP; > + RPC_U16(&msg, 0U) = (uint16_t) resource; > + RPC_I16(&msg, 2U) = (int16_t) celsius; > + RPC_U8(&msg, 4U) = (uint8_t) temp; > + RPC_I8(&msg, 5U) = (int8_t) tenths; > + RPC_SIZE(&msg) = 3U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_misc_temp_t temp, int16_t *celsius, int8_t *tenths) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; > + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_GET_TEMP; > + RPC_U16(&msg, 0U) = (uint16_t) resource; > + RPC_U8(&msg, 2U) = (uint8_t) temp; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + if (celsius != NULL) > + { > + *celsius = RPC_I16(&msg, 0U); > + } > + > + result = RPC_R8(&msg); > + if (tenths != NULL) > + { > + *tenths = RPC_I8(&msg, 2U); > + } > + > + return (sc_err_t) result; > +} > + > +void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *dev) > +{ > + sc_rpc_msg_t msg; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; > + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_GET_BOOT_DEV; > + RPC_SIZE(&msg) = 1U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + if (dev != NULL) > + { > + *dev = RPC_U16(&msg, 0U); > + } > + > + return; > +} > + > +void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status) > +{ > + sc_rpc_msg_t msg; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC; > + RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_GET_BUTTON_STATUS; > + RPC_SIZE(&msg) = 1U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + if (status != NULL) > + { > + *status = RPC_U8(&msg, 0U); > + } > + > + return; > +} > + > +/**@}*/ > + > diff --git a/arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h > b/arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h > new file mode 100644 > index 0000000000..b658dcc23d > --- /dev/null > +++ b/arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h > @@ -0,0 +1,68 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * Header file for the PAD RPC implementation. > + * > + * @addtogroup PAD_SVC > + * @{ > + */ > + > +#ifndef SC_PAD_RPC_H > +#define SC_PAD_RPC_H > + > +/* Includes */ > + > +/* Defines */ > + > +/*! > + * @name Defines for RPC PAD function calls > + */ > +/*@{*/ > +#define PAD_FUNC_UNKNOWN 0 /*!< Unknown function */ > +#define PAD_FUNC_SET_MUX 1U /*!< Index for pad_set_mux() RPC call */ > +#define PAD_FUNC_GET_MUX 6U /*!< Index for pad_get_mux() RPC call */ > +#define PAD_FUNC_SET_GP 2U /*!< Index for pad_set_gp() RPC call */ > +#define PAD_FUNC_GET_GP 7U /*!< Index for pad_get_gp() RPC call */ > +#define PAD_FUNC_SET_WAKEUP 4U /*!< Index for pad_set_wakeup() RPC > call */ > +#define PAD_FUNC_GET_WAKEUP 9U /*!< Index for pad_get_wakeup() RPC > call */ > +#define PAD_FUNC_SET_ALL 5U /*!< Index for pad_set_all() RPC call */ > +#define PAD_FUNC_GET_ALL 10U /*!< Index for pad_get_all() RPC call */ > +#define PAD_FUNC_SET 15U /*!< Index for pad_set() RPC call */ > +#define PAD_FUNC_GET 16U /*!< Index for pad_get() RPC call */ > +#define PAD_FUNC_SET_GP_28FDSOI 11U /*!< Index for pad_set_gp_28fdsoi() > RPC call */ > +#define PAD_FUNC_GET_GP_28FDSOI 12U /*!< Index for pad_get_gp_28fdsoi() > RPC call */ > +#define PAD_FUNC_SET_GP_28FDSOI_HSIC 3U /*!< Index for > pad_set_gp_28fdsoi_hsic() RPC call */ > +#define PAD_FUNC_GET_GP_28FDSOI_HSIC 8U /*!< Index for > pad_get_gp_28fdsoi_hsic() RPC call */ > +#define PAD_FUNC_SET_GP_28FDSOI_COMP 13U /*!< Index for > pad_set_gp_28fdsoi_comp() RPC call */ > +#define PAD_FUNC_GET_GP_28FDSOI_COMP 14U /*!< Index for > pad_get_gp_28fdsoi_comp() RPC call */ > +/*@}*/ > + > +/* Types */ > + > +/* Functions */ > + > +/*! > + * This function dispatches an incoming PAD RPC request. > + * > + * @param[in] caller_pt caller partition > + * @param[in] msg pointer to RPC message > + */ > +void pad_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg); > + > +/*! > + * This function translates and dispatches an PAD RPC request. > + * > + * @param[in] ipc IPC handle > + * @param[in] msg pointer to RPC message > + */ > +void pad_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg); > + > +#endif /* SC_PAD_RPC_H */ > + > +/**@}*/ > + > diff --git a/arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c > b/arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c > new file mode 100644 > index 0000000000..4a93c1a48e > --- /dev/null > +++ b/arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c > @@ -0,0 +1,475 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * File containing client-side RPC functions for the PAD service. These > + * functions are ported to clients that communicate to the SC. > + * > + * @addtogroup PAD_SVC > + * @{ > + */ > + > +/* Includes */ > + > +#include <asm/arch/sci/types.h> > +#include <asm/arch/sci/svc/rm/api.h> > +#include <asm/arch/sci/svc/pad/api.h> > +#include <asm/arch/sci/rpc.h> > +#include "rpc.h" > + > +/* Local Defines */ > + > +/* Local Types */ > + > +/* Local Functions */ > + > +sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad, > + uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; > + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_MUX; > + RPC_U16(&msg, 0U) = (uint16_t) pad; > + RPC_U8(&msg, 2U) = (uint8_t) mux; > + RPC_U8(&msg, 3U) = (uint8_t) config; > + RPC_U8(&msg, 4U) = (uint8_t) iso; > + RPC_SIZE(&msg) = 3U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pad_t pad, > + uint8_t *mux, sc_pad_config_t *config, sc_pad_iso_t *iso) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; > + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_MUX; > + RPC_U16(&msg, 0U) = (uint16_t) pad; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + if (mux != NULL) > + { > + *mux = RPC_U8(&msg, 0U); > + } > + > + if (config != NULL) > + { > + *config = RPC_U8(&msg, 1U); > + } > + > + if (iso != NULL) > + { > + *iso = RPC_U8(&msg, 2U); > + } > + > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t ctrl) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; > + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_GP; > + RPC_U32(&msg, 0U) = (uint32_t) ctrl; > + RPC_U16(&msg, 4U) = (uint16_t) pad; > + RPC_SIZE(&msg) = 3U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; > + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_GP; > + RPC_U16(&msg, 0U) = (uint16_t) pad; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + if (ctrl != NULL) > + { > + *ctrl = RPC_U32(&msg, 0U); > + } > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad, > + sc_pad_wakeup_t wakeup) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; > + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_WAKEUP; > + RPC_U16(&msg, 0U) = (uint16_t) pad; > + RPC_U8(&msg, 2U) = (uint8_t) wakeup; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad, > + sc_pad_wakeup_t *wakeup) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; > + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_WAKEUP; > + RPC_U16(&msg, 0U) = (uint16_t) pad; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + if (wakeup != NULL) > + { > + *wakeup = RPC_U8(&msg, 0U); > + } > + > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux, > + sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl, > + sc_pad_wakeup_t wakeup) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; > + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_ALL; > + RPC_U32(&msg, 0U) = (uint32_t) ctrl; > + RPC_U16(&msg, 4U) = (uint16_t) pad; > + RPC_U8(&msg, 6U) = (uint8_t) mux; > + RPC_U8(&msg, 7U) = (uint8_t) config; > + RPC_U8(&msg, 8U) = (uint8_t) iso; > + RPC_U8(&msg, 9U) = (uint8_t) wakeup; > + RPC_SIZE(&msg) = 4U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t *mux, > + sc_pad_config_t *config, sc_pad_iso_t *iso, uint32_t *ctrl, > + sc_pad_wakeup_t *wakeup) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; > + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_ALL; > + RPC_U16(&msg, 0U) = (uint16_t) pad; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + if (ctrl != NULL) > + { > + *ctrl = RPC_U32(&msg, 0U); > + } > + > + result = RPC_R8(&msg); > + if (mux != NULL) > + { > + *mux = RPC_U8(&msg, 4U); > + } > + > + if (config != NULL) > + { > + *config = RPC_U8(&msg, 5U); > + } > + > + if (iso != NULL) > + { > + *iso = RPC_U8(&msg, 6U); > + } > + > + if (wakeup != NULL) > + { > + *wakeup = RPC_U8(&msg, 7U); > + } > + > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, uint32_t val) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; > + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET; > + RPC_U32(&msg, 0U) = (uint32_t) val; > + RPC_U16(&msg, 4U) = (uint16_t) pad; > + RPC_SIZE(&msg) = 3U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; > + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET; > + RPC_U16(&msg, 0U) = (uint16_t) pad; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + if (val != NULL) > + { > + *val = RPC_U32(&msg, 0U); > + } > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad, > + sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; > + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_GP_28FDSOI; > + RPC_U16(&msg, 0U) = (uint16_t) pad; > + RPC_U8(&msg, 2U) = (uint8_t) dse; > + RPC_U8(&msg, 3U) = (uint8_t) ps; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad, > + sc_pad_28fdsoi_dse_t *dse, sc_pad_28fdsoi_ps_t *ps) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; > + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_GP_28FDSOI; > + RPC_U16(&msg, 0U) = (uint16_t) pad; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + if (dse != NULL) > + { > + *dse = RPC_U8(&msg, 0U); > + } > + > + if (ps != NULL) > + { > + *ps = RPC_U8(&msg, 1U); > + } > + > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad, > + sc_pad_28fdsoi_dse_t dse, sc_bool_t hys, sc_pad_28fdsoi_pus_t pus, > + sc_bool_t pke, sc_bool_t pue) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; > + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_GP_28FDSOI_HSIC; > + RPC_U16(&msg, 0U) = (uint16_t) pad; > + RPC_U8(&msg, 2U) = (uint8_t) dse; > + RPC_U8(&msg, 3U) = (uint8_t) pus; > + RPC_U8(&msg, 4U) = (uint8_t) hys; > + RPC_U8(&msg, 5U) = (uint8_t) pke; > + RPC_U8(&msg, 6U) = (uint8_t) pue; > + RPC_SIZE(&msg) = 3U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad, > + sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys, sc_pad_28fdsoi_pus_t *pus, > + sc_bool_t *pke, sc_bool_t *pue) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; > + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_GP_28FDSOI_HSIC; > + RPC_U16(&msg, 0U) = (uint16_t) pad; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + if (dse != NULL) > + { > + *dse = RPC_U8(&msg, 0U); > + } > + > + if (pus != NULL) > + { > + *pus = RPC_U8(&msg, 1U); > + } > + > + if (hys != NULL) > + { > + *hys = RPC_U8(&msg, 2U); > + } > + > + if (pke != NULL) > + { > + *pke = RPC_U8(&msg, 3U); > + } > + > + if (pue != NULL) > + { > + *pue = RPC_U8(&msg, 4U); > + } > + > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad, > + uint8_t compen, sc_bool_t fastfrz, uint8_t rasrcp, uint8_t rasrcn, > + sc_bool_t nasrc_sel, sc_bool_t psw_ovr) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; > + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_GP_28FDSOI_COMP; > + RPC_U16(&msg, 0U) = (uint16_t) pad; > + RPC_U8(&msg, 2U) = (uint8_t) compen; > + RPC_U8(&msg, 3U) = (uint8_t) rasrcp; > + RPC_U8(&msg, 4U) = (uint8_t) rasrcn; > + RPC_U8(&msg, 5U) = (uint8_t) fastfrz; > + RPC_U8(&msg, 6U) = (uint8_t) nasrc_sel; > + RPC_U8(&msg, 7U) = (uint8_t) psw_ovr; > + RPC_SIZE(&msg) = 3U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad, > + uint8_t *compen, sc_bool_t *fastfrz, uint8_t *rasrcp, uint8_t *rasrcn, > + sc_bool_t *nasrc_sel, sc_bool_t *compok, uint8_t *nasrc, sc_bool_t > *psw_ovr) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD; > + RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_GP_28FDSOI_COMP; > + RPC_U16(&msg, 0U) = (uint16_t) pad; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + if (compen != NULL) > + { > + *compen = RPC_U8(&msg, 0U); > + } > + > + if (rasrcp != NULL) > + { > + *rasrcp = RPC_U8(&msg, 1U); > + } > + > + if (rasrcn != NULL) > + { > + *rasrcn = RPC_U8(&msg, 2U); > + } > + > + if (nasrc != NULL) > + { > + *nasrc = RPC_U8(&msg, 3U); > + } > + > + if (fastfrz != NULL) > + { > + *fastfrz = RPC_U8(&msg, 4U); > + } > + > + if (nasrc_sel != NULL) > + { > + *nasrc_sel = RPC_U8(&msg, 5U); > + } > + > + if (compok != NULL) > + { > + *compok = RPC_U8(&msg, 6U); > + } > + > + if (psw_ovr != NULL) > + { > + *psw_ovr = RPC_U8(&msg, 7U); > + } > + > + return (sc_err_t) result; > +} > + > +/**@}*/ > + > diff --git a/arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h > b/arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h > new file mode 100644 > index 0000000000..49046c2ca7 > --- /dev/null > +++ b/arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h > @@ -0,0 +1,73 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * Header file for the PM RPC implementation. > + * > + * @addtogroup PM_SVC > + * @{ > + */ > + > +#ifndef SC_PM_RPC_H > +#define SC_PM_RPC_H > + > +/* Includes */ > + > +/* Defines */ > + > +/*! > + * @name Defines for RPC PM function calls > + */ > +/*@{*/ > +#define PM_FUNC_UNKNOWN 0 /*!< Unknown function */ > +#define PM_FUNC_SET_SYS_POWER_MODE 19U /*!< Index for > pm_set_sys_power_mode() RPC call */ > +#define PM_FUNC_SET_PARTITION_POWER_MODE 1U /*!< Index for > pm_set_partition_power_mode() RPC call */ > +#define PM_FUNC_GET_SYS_POWER_MODE 2U /*!< Index for > pm_get_sys_power_mode() RPC call */ > +#define PM_FUNC_SET_RESOURCE_POWER_MODE 3U /*!< Index for > pm_set_resource_power_mode() RPC call */ > +#define PM_FUNC_GET_RESOURCE_POWER_MODE 4U /*!< Index for > pm_get_resource_power_mode() RPC call */ > +#define PM_FUNC_REQ_LOW_POWER_MODE 16U /*!< Index for > pm_req_low_power_mode() RPC call */ > +#define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U /*!< Index for > pm_req_cpu_low_power_mode() RPC call */ > +#define PM_FUNC_SET_CPU_RESUME_ADDR 17U /*!< Index for > pm_set_cpu_resume_addr() RPC call */ > +#define PM_FUNC_SET_CPU_RESUME 21U /*!< Index for > pm_set_cpu_resume() RPC call */ > +#define PM_FUNC_REQ_SYS_IF_POWER_MODE 18U /*!< Index for > pm_req_sys_if_power_mode() RPC call */ > +#define PM_FUNC_SET_CLOCK_RATE 5U /*!< Index for pm_set_clock_rate() > RPC call */ > +#define PM_FUNC_GET_CLOCK_RATE 6U /*!< Index for pm_get_clock_rate() > RPC call */ > +#define PM_FUNC_CLOCK_ENABLE 7U /*!< Index for pm_clock_enable() RPC > call */ > +#define PM_FUNC_SET_CLOCK_PARENT 14U /*!< Index for > pm_set_clock_parent() RPC call */ > +#define PM_FUNC_GET_CLOCK_PARENT 15U /*!< Index for > pm_get_clock_parent() RPC call */ > +#define PM_FUNC_RESET 13U /*!< Index for pm_reset() RPC call */ > +#define PM_FUNC_RESET_REASON 10U /*!< Index for pm_reset_reason() RPC > call */ > +#define PM_FUNC_BOOT 8U /*!< Index for pm_boot() RPC call */ > +#define PM_FUNC_REBOOT 9U /*!< Index for pm_reboot() RPC call */ > +#define PM_FUNC_REBOOT_PARTITION 12U /*!< Index for > pm_reboot_partition() RPC call */ > +#define PM_FUNC_CPU_START 11U /*!< Index for pm_cpu_start() RPC call */ > +/*@}*/ > + > +/* Types */ > + > +/* Functions */ > + > +/*! > + * This function dispatches an incoming PM RPC request. > + * > + * @param[in] caller_pt caller partition > + * @param[in] msg pointer to RPC message > + */ > +void pm_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg); > + > +/*! > + * This function translates and dispatches an PM RPC request. > + * > + * @param[in] ipc IPC handle > + * @param[in] msg pointer to RPC message > + */ > +void pm_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg); > + > +#endif /* SC_PM_RPC_H */ > + > +/**@}*/ > + > diff --git a/arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c > b/arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c > new file mode 100644 > index 0000000000..6cad000354 > --- /dev/null > +++ b/arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c > @@ -0,0 +1,460 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * File containing client-side RPC functions for the PM service. These > + * functions are ported to clients that communicate to the SC. > + * > + * @addtogroup PM_SVC > + * @{ > + */ > + > +/* Includes */ > + > +#include <asm/arch/sci/types.h> > +#include <asm/arch/sci/svc/rm/api.h> > +#include <asm/arch/sci/svc/pm/api.h> > +#include <asm/arch/sci/rpc.h> > +#include "rpc.h" > + > +/* Local Defines */ > + > +/* Local Types */ > + > +/* Local Functions */ > + > +sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_pm_power_mode_t > mode) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; > + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_SYS_POWER_MODE; > + RPC_U8(&msg, 0U) = (uint8_t) mode; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, > + sc_pm_power_mode_t mode) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; > + RPC_FUNC(&msg) = (uint8_t) > PM_FUNC_SET_PARTITION_POWER_MODE; > + RPC_U8(&msg, 0U) = (uint8_t) pt; > + RPC_U8(&msg, 1U) = (uint8_t) mode; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, > + sc_pm_power_mode_t *mode) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; > + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_GET_SYS_POWER_MODE; > + RPC_U8(&msg, 0U) = (uint8_t) pt; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + if (mode != NULL) > + { > + *mode = RPC_U8(&msg, 0U); > + } > + > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_pm_power_mode_t mode) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; > + RPC_FUNC(&msg) = (uint8_t) > PM_FUNC_SET_RESOURCE_POWER_MODE; > + RPC_U16(&msg, 0U) = (uint16_t) resource; > + RPC_U8(&msg, 2U) = (uint8_t) mode; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_pm_power_mode_t *mode) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; > + RPC_FUNC(&msg) = (uint8_t) > PM_FUNC_GET_RESOURCE_POWER_MODE; > + RPC_U16(&msg, 0U) = (uint16_t) resource; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + if (mode != NULL) > + { > + *mode = RPC_U8(&msg, 0U); > + } > + > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_pm_power_mode_t mode) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; > + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_REQ_LOW_POWER_MODE; > + RPC_U16(&msg, 0U) = (uint16_t) resource; > + RPC_U8(&msg, 2U) = (uint8_t) mode; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pm_req_cpu_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_pm_power_mode_t mode, sc_pm_wake_src_t wake_src) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; > + RPC_FUNC(&msg) = (uint8_t) > PM_FUNC_REQ_CPU_LOW_POWER_MODE; > + RPC_U16(&msg, 0U) = (uint16_t) resource; > + RPC_U8(&msg, 2U) = (uint8_t) mode; > + RPC_U8(&msg, 3U) = (uint8_t) wake_src; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_faddr_t address) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; > + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_CPU_RESUME_ADDR; > + RPC_U32(&msg, 0U) = (uint32_t) (address >> 32U); > + RPC_U32(&msg, 4U) = (uint32_t) address; > + RPC_U16(&msg, 8U) = (uint16_t) resource; > + RPC_SIZE(&msg) = 4U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pm_set_cpu_resume(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_bool_t isPrimary, sc_faddr_t address) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; > + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_CPU_RESUME; > + RPC_U32(&msg, 0U) = (uint32_t) (address >> 32U); > + RPC_U32(&msg, 4U) = (uint32_t) address; > + RPC_U16(&msg, 8U) = (uint16_t) resource; > + RPC_U8(&msg, 10U) = (uint8_t) isPrimary; > + RPC_SIZE(&msg) = 4U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, > sc_pm_power_mode_t lpm) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; > + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_REQ_SYS_IF_POWER_MODE; > + RPC_U16(&msg, 0U) = (uint16_t) resource; > + RPC_U8(&msg, 2U) = (uint8_t) sys_if; > + RPC_U8(&msg, 3U) = (uint8_t) hpm; > + RPC_U8(&msg, 4U) = (uint8_t) lpm; > + RPC_SIZE(&msg) = 3U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_pm_clk_t clk, sc_pm_clock_rate_t *rate) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; > + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_CLOCK_RATE; > + RPC_U32(&msg, 0U) = *(uint32_t*) rate; > + RPC_U16(&msg, 4U) = (uint16_t) resource; > + RPC_U8(&msg, 6U) = (uint8_t) clk; > + RPC_SIZE(&msg) = 3U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + *rate = RPC_U32(&msg, 0U); > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_pm_clk_t clk, sc_pm_clock_rate_t *rate) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; > + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_GET_CLOCK_RATE; > + RPC_U16(&msg, 0U) = (uint16_t) resource; > + RPC_U8(&msg, 2U) = (uint8_t) clk; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + if (rate != NULL) > + { > + *rate = RPC_U32(&msg, 0U); > + } > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; > + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_CLOCK_ENABLE; > + RPC_U16(&msg, 0U) = (uint16_t) resource; > + RPC_U8(&msg, 2U) = (uint8_t) clk; > + RPC_U8(&msg, 3U) = (uint8_t) enable; > + RPC_U8(&msg, 4U) = (uint8_t) autog; > + RPC_SIZE(&msg) = 3U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_pm_clk_t clk, sc_pm_clk_parent_t parent) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; > + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_CLOCK_PARENT; > + RPC_U16(&msg, 0U) = (uint16_t) resource; > + RPC_U8(&msg, 2U) = (uint8_t) clk; > + RPC_U8(&msg, 3U) = (uint8_t) parent; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_pm_clk_t clk, sc_pm_clk_parent_t *parent) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; > + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_GET_CLOCK_PARENT; > + RPC_U16(&msg, 0U) = (uint16_t) resource; > + RPC_U8(&msg, 2U) = (uint8_t) clk; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + if (parent != NULL) > + { > + *parent = RPC_U8(&msg, 0U); > + } > + > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; > + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_RESET; > + RPC_U8(&msg, 0U) = (uint8_t) type; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; > + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_RESET_REASON; > + RPC_SIZE(&msg) = 1U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + if (reason != NULL) > + { > + *reason = RPC_U8(&msg, 0U); > + } > + > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt, > + sc_rsrc_t resource_cpu, sc_faddr_t boot_addr, > + sc_rsrc_t resource_mu, sc_rsrc_t resource_dev) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; > + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_BOOT; > + RPC_U32(&msg, 0U) = (uint32_t) (boot_addr >> 32U); > + RPC_U32(&msg, 4U) = (uint32_t) boot_addr; > + RPC_U16(&msg, 8U) = (uint16_t) resource_cpu; > + RPC_U16(&msg, 10U) = (uint16_t) resource_mu; > + RPC_U16(&msg, 12U) = (uint16_t) resource_dev; > + RPC_U8(&msg, 14U) = (uint8_t) pt; > + RPC_SIZE(&msg) = 5U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type) > +{ > + sc_rpc_msg_t msg; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; > + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_REBOOT; > + RPC_U8(&msg, 0U) = (uint8_t) type; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_TRUE); > + > + return; > +} > + > +sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt, > + sc_pm_reset_type_t type) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; > + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_REBOOT_PARTITION; > + RPC_U8(&msg, 0U) = (uint8_t) pt; > + RPC_U8(&msg, 1U) = (uint8_t) type; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, > + sc_faddr_t address) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM; > + RPC_FUNC(&msg) = (uint8_t) PM_FUNC_CPU_START; > + RPC_U32(&msg, 0U) = (uint32_t) (address >> 32U); > + RPC_U32(&msg, 4U) = (uint32_t) address; > + RPC_U16(&msg, 8U) = (uint16_t) resource; > + RPC_U8(&msg, 10U) = (uint8_t) enable; > + RPC_SIZE(&msg) = 4U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +/**@}*/ > + > diff --git a/arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h > b/arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h > new file mode 100644 > index 0000000000..196615e937 > --- /dev/null > +++ b/arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h > @@ -0,0 +1,83 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * Header file for the RM RPC implementation. > + * > + * @addtogroup RM_SVC > + * @{ > + */ > + > +#ifndef SC_RM_RPC_H > +#define SC_RM_RPC_H > + > +/* Includes */ > + > +/* Defines */ > + > +/*! > + * @name Defines for RPC RM function calls > + */ > +/*@{*/ > +#define RM_FUNC_UNKNOWN 0 /*!< Unknown function */ > +#define RM_FUNC_PARTITION_ALLOC 1U /*!< Index for rm_partition_alloc() > RPC call */ > +#define RM_FUNC_SET_CONFIDENTIAL 31U /*!< Index for > rm_set_confidential() RPC call */ > +#define RM_FUNC_PARTITION_FREE 2U /*!< Index for rm_partition_free() > RPC call */ > +#define RM_FUNC_GET_DID 26U /*!< Index for rm_get_did() RPC call */ > +#define RM_FUNC_PARTITION_STATIC 3U /*!< Index for rm_partition_static() > RPC call */ > +#define RM_FUNC_PARTITION_LOCK 4U /*!< Index for rm_partition_lock() > RPC call */ > +#define RM_FUNC_GET_PARTITION 5U /*!< Index for rm_get_partition() RPC > call */ > +#define RM_FUNC_SET_PARENT 6U /*!< Index for rm_set_parent() RPC call */ > +#define RM_FUNC_MOVE_ALL 7U /*!< Index for rm_move_all() RPC call */ > +#define RM_FUNC_ASSIGN_RESOURCE 8U /*!< Index for rm_assign_resource() > RPC call */ > +#define RM_FUNC_SET_RESOURCE_MOVABLE 9U /*!< Index for > rm_set_resource_movable() RPC call */ > +#define RM_FUNC_SET_SUBSYS_RSRC_MOVABLE 28U /*!< Index for > rm_set_subsys_rsrc_movable() RPC call */ > +#define RM_FUNC_SET_MASTER_ATTRIBUTES 10U /*!< Index for > rm_set_master_attributes() RPC call */ > +#define RM_FUNC_SET_MASTER_SID 11U /*!< Index for rm_set_master_sid() > RPC call */ > +#define RM_FUNC_SET_PERIPHERAL_PERMISSIONS 12U /*!< Index for > rm_set_peripheral_permissions() RPC call */ > +#define RM_FUNC_IS_RESOURCE_OWNED 13U /*!< Index for > rm_is_resource_owned() RPC call */ > +#define RM_FUNC_IS_RESOURCE_MASTER 14U /*!< Index for > rm_is_resource_master() RPC call */ > +#define RM_FUNC_IS_RESOURCE_PERIPHERAL 15U /*!< Index for > rm_is_resource_peripheral() RPC call */ > +#define RM_FUNC_GET_RESOURCE_INFO 16U /*!< Index for > rm_get_resource_info() RPC call */ > +#define RM_FUNC_MEMREG_ALLOC 17U /*!< Index for rm_memreg_alloc() > RPC call */ > +#define RM_FUNC_MEMREG_SPLIT 29U /*!< Index for rm_memreg_split() > RPC call */ > +#define RM_FUNC_MEMREG_FREE 18U /*!< Index for rm_memreg_free() > RPC call */ > +#define RM_FUNC_FIND_MEMREG 30U /*!< Index for rm_find_memreg() RPC > call */ > +#define RM_FUNC_ASSIGN_MEMREG 19U /*!< Index for rm_assign_memreg() > RPC call */ > +#define RM_FUNC_SET_MEMREG_PERMISSIONS 20U /*!< Index for > rm_set_memreg_permissions() RPC call */ > +#define RM_FUNC_IS_MEMREG_OWNED 21U /*!< Index for > rm_is_memreg_owned() RPC call */ > +#define RM_FUNC_GET_MEMREG_INFO 22U /*!< Index for > rm_get_memreg_info() RPC call */ > +#define RM_FUNC_ASSIGN_PAD 23U /*!< Index for rm_assign_pad() RPC call > */ > +#define RM_FUNC_SET_PAD_MOVABLE 24U /*!< Index for > rm_set_pad_movable() RPC call */ > +#define RM_FUNC_IS_PAD_OWNED 25U /*!< Index for rm_is_pad_owned() > RPC call */ > +#define RM_FUNC_DUMP 27U /*!< Index for rm_dump() RPC call */ > +/*@}*/ > + > +/* Types */ > + > +/* Functions */ > + > +/*! > + * This function dispatches an incoming RM RPC request. > + * > + * @param[in] caller_pt caller partition > + * @param[in] msg pointer to RPC message > + */ > +void rm_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg); > + > +/*! > + * This function translates and dispatches an RM RPC request. > + * > + * @param[in] ipc IPC handle > + * @param[in] msg pointer to RPC message > + */ > +void rm_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg); > + > +#endif /* SC_RM_RPC_H */ > + > +/**@}*/ > + > diff --git a/arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c > b/arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c > new file mode 100644 > index 0000000000..d1475cf643 > --- /dev/null > +++ b/arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c > @@ -0,0 +1,645 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * File containing client-side RPC functions for the RM service. These > + * functions are ported to clients that communicate to the SC. > + * > + * @addtogroup RM_SVC > + * @{ > + */ > + > +/* Includes */ > + > +#include <asm/arch/sci/types.h> > +#include <asm/arch/sci/svc/rm/api.h> > +#include <asm/arch/sci/rpc.h> > +#include "rpc.h" > + > +/* Local Defines */ > + > +/* Local Types */ > + > +/* Local Functions */ > + > +sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure, > + sc_bool_t isolated, sc_bool_t restricted, sc_bool_t grant, sc_bool_t > coherent) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_PARTITION_ALLOC; > + RPC_U8(&msg, 0U) = (uint8_t) secure; > + RPC_U8(&msg, 1U) = (uint8_t) isolated; > + RPC_U8(&msg, 2U) = (uint8_t) restricted; > + RPC_U8(&msg, 3U) = (uint8_t) grant; > + RPC_U8(&msg, 4U) = (uint8_t) coherent; > + RPC_SIZE(&msg) = 3U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + if (pt != NULL) > + { > + *pt = RPC_U8(&msg, 0U); > + } > + > + return (sc_err_t) result; > +} > + > +sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t retro) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_CONFIDENTIAL; > + RPC_U8(&msg, 0U) = (uint8_t) pt; > + RPC_U8(&msg, 1U) = (uint8_t) retro; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_PARTITION_FREE; > + RPC_U8(&msg, 0U) = (uint8_t) pt; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_rm_did_t sc_rm_get_did(sc_ipc_t ipc) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_GET_DID; > + RPC_SIZE(&msg) = 1U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_rm_did_t) result; > +} > + > +sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt, > + sc_rm_did_t did) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_PARTITION_STATIC; > + RPC_U8(&msg, 0U) = (uint8_t) pt; > + RPC_U8(&msg, 1U) = (uint8_t) did; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_rm_partition_lock(sc_ipc_t ipc, sc_rm_pt_t pt) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_PARTITION_LOCK; > + RPC_U8(&msg, 0U) = (uint8_t) pt; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_GET_PARTITION; > + RPC_SIZE(&msg) = 1U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + if (pt != NULL) > + { > + *pt = RPC_U8(&msg, 0U); > + } > + > + return (sc_err_t) result; > +} > + > +sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, > + sc_rm_pt_t pt_parent) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_PARENT; > + RPC_U8(&msg, 0U) = (uint8_t) pt; > + RPC_U8(&msg, 1U) = (uint8_t) pt_parent; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst, > + sc_bool_t move_rsrc, sc_bool_t move_pads) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_MOVE_ALL; > + RPC_U8(&msg, 0U) = (uint8_t) pt_src; > + RPC_U8(&msg, 1U) = (uint8_t) pt_dst; > + RPC_U8(&msg, 2U) = (uint8_t) move_rsrc; > + RPC_U8(&msg, 3U) = (uint8_t) move_pads; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, > + sc_rsrc_t resource) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_ASSIGN_RESOURCE; > + RPC_U16(&msg, 0U) = (uint16_t) resource; > + RPC_U8(&msg, 2U) = (uint8_t) pt; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst, > + sc_rsrc_t resource_lst, sc_bool_t movable) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_RESOURCE_MOVABLE; > + RPC_U16(&msg, 0U) = (uint16_t) resource_fst; > + RPC_U16(&msg, 2U) = (uint16_t) resource_lst; > + RPC_U8(&msg, 4U) = (uint8_t) movable; > + RPC_SIZE(&msg) = 3U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_bool_t movable) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_SUBSYS_RSRC_MOVABLE; > + RPC_U16(&msg, 0U) = (uint16_t) resource; > + RPC_U8(&msg, 2U) = (uint8_t) movable; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_rm_spa_t sa, sc_rm_spa_t pa, sc_bool_t smmu_bypass) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_MASTER_ATTRIBUTES; > + RPC_U16(&msg, 0U) = (uint16_t) resource; > + RPC_U8(&msg, 2U) = (uint8_t) sa; > + RPC_U8(&msg, 3U) = (uint8_t) pa; > + RPC_U8(&msg, 4U) = (uint8_t) smmu_bypass; > + RPC_SIZE(&msg) = 3U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_rm_sid_t sid) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_MASTER_SID; > + RPC_U16(&msg, 0U) = (uint16_t) resource; > + RPC_U16(&msg, 2U) = (uint16_t) sid; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_rm_pt_t pt, sc_rm_perm_t perm) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) > RM_FUNC_SET_PERIPHERAL_PERMISSIONS; > + RPC_U16(&msg, 0U) = (uint16_t) resource; > + RPC_U8(&msg, 2U) = (uint8_t) pt; > + RPC_U8(&msg, 3U) = (uint8_t) perm; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_IS_RESOURCE_OWNED; > + RPC_U16(&msg, 0U) = (uint16_t) resource; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_bool_t) result; > +} > + > +sc_bool_t sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_IS_RESOURCE_MASTER; > + RPC_U16(&msg, 0U) = (uint16_t) resource; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_bool_t) result; > +} > + > +sc_bool_t sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_IS_RESOURCE_PERIPHERAL; > + RPC_U16(&msg, 0U) = (uint16_t) resource; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_bool_t) result; > +} > + > +sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource, > + sc_rm_sid_t *sid) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_GET_RESOURCE_INFO; > + RPC_U16(&msg, 0U) = (uint16_t) resource; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + if (sid != NULL) > + { > + *sid = RPC_U16(&msg, 0U); > + } > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_rm_memreg_alloc(sc_ipc_t ipc, sc_rm_mr_t *mr, > + sc_faddr_t addr_start, sc_faddr_t addr_end) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_MEMREG_ALLOC; > + RPC_U32(&msg, 0U) = (uint32_t) (addr_start >> 32U); > + RPC_U32(&msg, 4U) = (uint32_t) addr_start; > + RPC_U32(&msg, 8U) = (uint32_t) (addr_end >> 32U); > + RPC_U32(&msg, 12U) = (uint32_t) addr_end; > + RPC_SIZE(&msg) = 5U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + if (mr != NULL) > + { > + *mr = RPC_U8(&msg, 0U); > + } > + > + return (sc_err_t) result; > +} > + > +sc_err_t sc_rm_memreg_split(sc_ipc_t ipc, sc_rm_mr_t mr, > + sc_rm_mr_t *mr_ret, sc_faddr_t addr_start, sc_faddr_t addr_end) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_MEMREG_SPLIT; > + RPC_U32(&msg, 0U) = (uint32_t) (addr_start >> 32U); > + RPC_U32(&msg, 4U) = (uint32_t) addr_start; > + RPC_U32(&msg, 8U) = (uint32_t) (addr_end >> 32U); > + RPC_U32(&msg, 12U) = (uint32_t) addr_end; > + RPC_U8(&msg, 16U) = (uint8_t) mr; > + RPC_SIZE(&msg) = 6U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + if (mr_ret != NULL) > + { > + *mr_ret = RPC_U8(&msg, 0U); > + } > + > + return (sc_err_t) result; > +} > + > +sc_err_t sc_rm_memreg_free(sc_ipc_t ipc, sc_rm_mr_t mr) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_MEMREG_FREE; > + RPC_U8(&msg, 0U) = (uint8_t) mr; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, > + sc_faddr_t addr_start, sc_faddr_t addr_end) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_FIND_MEMREG; > + RPC_U32(&msg, 0U) = (uint32_t) (addr_start >> 32U); > + RPC_U32(&msg, 4U) = (uint32_t) addr_start; > + RPC_U32(&msg, 8U) = (uint32_t) (addr_end >> 32U); > + RPC_U32(&msg, 12U) = (uint32_t) addr_end; > + RPC_SIZE(&msg) = 5U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + if (mr != NULL) > + { > + *mr = RPC_U8(&msg, 0U); > + } > + > + return (sc_err_t) result; > +} > + > +sc_err_t sc_rm_assign_memreg(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_mr_t mr) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_ASSIGN_MEMREG; > + RPC_U8(&msg, 0U) = (uint8_t) pt; > + RPC_U8(&msg, 1U) = (uint8_t) mr; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr, > + sc_rm_pt_t pt, sc_rm_perm_t perm) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_MEMREG_PERMISSIONS; > + RPC_U8(&msg, 0U) = (uint8_t) mr; > + RPC_U8(&msg, 1U) = (uint8_t) pt; > + RPC_U8(&msg, 2U) = (uint8_t) perm; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_IS_MEMREG_OWNED; > + RPC_U8(&msg, 0U) = (uint8_t) mr; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_bool_t) result; > +} > + > +sc_err_t sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, > + sc_faddr_t *addr_start, sc_faddr_t *addr_end) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_GET_MEMREG_INFO; > + RPC_U8(&msg, 0U) = (uint8_t) mr; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + if (addr_start != NULL) > + { > + *addr_start = ((uint64_t) RPC_U32(&msg, 0U) << 32U) | > RPC_U32(&msg, 4U); > + } > + > + if (addr_end != NULL) > + { > + *addr_end = ((uint64_t) RPC_U32(&msg, 8U) << 32U) | > RPC_U32(&msg, 12U); > + } > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_ASSIGN_PAD; > + RPC_U16(&msg, 0U) = (uint16_t) pad; > + RPC_U8(&msg, 2U) = (uint8_t) pt; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst, > + sc_pad_t pad_lst, sc_bool_t movable) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_PAD_MOVABLE; > + RPC_U16(&msg, 0U) = (uint16_t) pad_fst; > + RPC_U16(&msg, 2U) = (uint16_t) pad_lst; > + RPC_U8(&msg, 4U) = (uint8_t) movable; > + RPC_SIZE(&msg) = 3U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_IS_PAD_OWNED; > + RPC_U8(&msg, 0U) = (uint8_t) pad; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_bool_t) result; > +} > + > +void sc_rm_dump(sc_ipc_t ipc) > +{ > + sc_rpc_msg_t msg; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM; > + RPC_FUNC(&msg) = (uint8_t) RM_FUNC_DUMP; > + RPC_SIZE(&msg) = 1U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + return; > +} > + > +/**@}*/ > + > diff --git a/arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h > b/arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h > new file mode 100644 > index 0000000000..0c498e97f0 > --- /dev/null > +++ b/arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h > @@ -0,0 +1,67 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * Header file for the TIMER RPC implementation. > + * > + * @addtogroup TIMER_SVC > + * @{ > + */ > + > +#ifndef SC_TIMER_RPC_H > +#define SC_TIMER_RPC_H > + > +/* Includes */ > + > +/* Defines */ > + > +/*! > + * @name Defines for RPC TIMER function calls > + */ > +/*@{*/ > +#define TIMER_FUNC_UNKNOWN 0 /*!< Unknown function */ > +#define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /*!< Index for > timer_set_wdog_timeout() RPC call */ > +#define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /*!< Index for > timer_set_wdog_pre_timeout() RPC call */ > +#define TIMER_FUNC_START_WDOG 2U /*!< Index for timer_start_wdog() > RPC call */ > +#define TIMER_FUNC_STOP_WDOG 3U /*!< Index for timer_stop_wdog() RPC > call */ > +#define TIMER_FUNC_PING_WDOG 4U /*!< Index for timer_ping_wdog() RPC > call */ > +#define TIMER_FUNC_GET_WDOG_STATUS 5U /*!< Index for > timer_get_wdog_status() RPC call */ > +#define TIMER_FUNC_PT_GET_WDOG_STATUS 13U /*!< Index for > timer_pt_get_wdog_status() RPC call */ > +#define TIMER_FUNC_SET_WDOG_ACTION 10U /*!< Index for > timer_set_wdog_action() RPC call */ > +#define TIMER_FUNC_SET_RTC_TIME 6U /*!< Index for timer_set_rtc_time() > RPC call */ > +#define TIMER_FUNC_GET_RTC_TIME 7U /*!< Index for timer_get_rtc_time() > RPC call */ > +#define TIMER_FUNC_GET_RTC_SEC1970 9U /*!< Index for > timer_get_rtc_sec1970() RPC call */ > +#define TIMER_FUNC_SET_RTC_ALARM 8U /*!< Index for > timer_set_rtc_alarm() RPC call */ > +#define TIMER_FUNC_SET_RTC_PERIODIC_ALARM 14U /*!< Index for > timer_set_rtc_periodic_alarm() RPC call */ > +#define TIMER_FUNC_CANCEL_RTC_ALARM 15U /*!< Index for > timer_cancel_rtc_alarm() RPC call */ > +#define TIMER_FUNC_SET_RTC_CALB 11U /*!< Index for timer_set_rtc_calb() > RPC call */ > +/*@}*/ > + > +/* Types */ > + > +/* Functions */ > + > +/*! > + * This function dispatches an incoming TIMER RPC request. > + * > + * @param[in] caller_pt caller partition > + * @param[in] msg pointer to RPC message > + */ > +void timer_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg); > + > +/*! > + * This function translates and dispatches an TIMER RPC request. > + * > + * @param[in] ipc IPC handle > + * @param[in] msg pointer to RPC message > + */ > +void timer_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg); > + > +#endif /* SC_TIMER_RPC_H */ > + > +/**@}*/ > + > diff --git a/arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c > b/arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c > new file mode 100644 > index 0000000000..abdf433b5c > --- /dev/null > +++ b/arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c > @@ -0,0 +1,365 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * File containing client-side RPC functions for the TIMER service. These > + * functions are ported to clients that communicate to the SC. > + * > + * @addtogroup TIMER_SVC > + * @{ > + */ > + > +/* Includes */ > + > +#include <asm/arch/sci/types.h> > +#include <asm/arch/sci/svc/rm/api.h> > +#include <asm/arch/sci/svc/timer/api.h> > +#include <asm/arch/sci/rpc.h> > +#include "rpc.h" > + > +/* Local Defines */ > + > +/* Local Types */ > + > +/* Local Functions */ > + > +sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc, > + sc_timer_wdog_time_t timeout) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; > + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_WDOG_TIMEOUT; > + RPC_U32(&msg, 0U) = (uint32_t) timeout; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_timer_set_wdog_pre_timeout(sc_ipc_t ipc, > + sc_timer_wdog_time_t pre_timeout) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; > + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_WDOG_PRE_TIMEOUT; > + RPC_U32(&msg, 0U) = (uint32_t) pre_timeout; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_timer_start_wdog(sc_ipc_t ipc, sc_bool_t lock) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; > + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_START_WDOG; > + RPC_U8(&msg, 0U) = (uint8_t) lock; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_timer_stop_wdog(sc_ipc_t ipc) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; > + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_STOP_WDOG; > + RPC_SIZE(&msg) = 1U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_timer_ping_wdog(sc_ipc_t ipc) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; > + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_PING_WDOG; > + RPC_SIZE(&msg) = 1U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_timer_get_wdog_status(sc_ipc_t ipc, > + sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *max_timeout, > + sc_timer_wdog_time_t *remaining_time) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; > + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_GET_WDOG_STATUS; > + RPC_SIZE(&msg) = 1U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + if (timeout != NULL) > + { > + *timeout = RPC_U32(&msg, 0U); > + } > + > + if (max_timeout != NULL) > + { > + *max_timeout = RPC_U32(&msg, 4U); > + } > + > + if (remaining_time != NULL) > + { > + *remaining_time = RPC_U32(&msg, 8U); > + } > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t > *enb, > + sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t > *remaining_time) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; > + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_PT_GET_WDOG_STATUS; > + RPC_U8(&msg, 0U) = (uint8_t) pt; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + if (timeout != NULL) > + { > + *timeout = RPC_U32(&msg, 0U); > + } > + > + if (remaining_time != NULL) > + { > + *remaining_time = RPC_U32(&msg, 4U); > + } > + > + result = RPC_R8(&msg); > + if (enb != NULL) > + { > + *enb = RPC_U8(&msg, 8U); > + } > + > + return (sc_err_t) result; > +} > + > +sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc, > + sc_rm_pt_t pt, sc_timer_wdog_action_t action) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; > + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_WDOG_ACTION; > + RPC_U8(&msg, 0U) = (uint8_t) pt; > + RPC_U8(&msg, 1U) = (uint8_t) action; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_timer_set_rtc_time(sc_ipc_t ipc, uint16_t year, uint8_t mon, > + uint8_t day, uint8_t hour, uint8_t min, uint8_t sec) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; > + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_RTC_TIME; > + RPC_U16(&msg, 0U) = (uint16_t) year; > + RPC_U8(&msg, 2U) = (uint8_t) mon; > + RPC_U8(&msg, 3U) = (uint8_t) day; > + RPC_U8(&msg, 4U) = (uint8_t) hour; > + RPC_U8(&msg, 5U) = (uint8_t) min; > + RPC_U8(&msg, 6U) = (uint8_t) sec; > + RPC_SIZE(&msg) = 3U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_timer_get_rtc_time(sc_ipc_t ipc, uint16_t *year, uint8_t *mon, > + uint8_t *day, uint8_t *hour, uint8_t *min, uint8_t *sec) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; > + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_GET_RTC_TIME; > + RPC_SIZE(&msg) = 1U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + if (year != NULL) > + { > + *year = RPC_U16(&msg, 0U); > + } > + > + result = RPC_R8(&msg); > + if (mon != NULL) > + { > + *mon = RPC_U8(&msg, 2U); > + } > + > + if (day != NULL) > + { > + *day = RPC_U8(&msg, 3U); > + } > + > + if (hour != NULL) > + { > + *hour = RPC_U8(&msg, 4U); > + } > + > + if (min != NULL) > + { > + *min = RPC_U8(&msg, 5U); > + } > + > + if (sec != NULL) > + { > + *sec = RPC_U8(&msg, 6U); > + } > + > + return (sc_err_t) result; > +} > + > +sc_err_t sc_timer_get_rtc_sec1970(sc_ipc_t ipc, uint32_t *sec) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; > + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_GET_RTC_SEC1970; > + RPC_SIZE(&msg) = 1U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + if (sec != NULL) > + { > + *sec = RPC_U32(&msg, 0U); > + } > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_timer_set_rtc_alarm(sc_ipc_t ipc, uint16_t year, uint8_t mon, > + uint8_t day, uint8_t hour, uint8_t min, uint8_t sec) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; > + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_RTC_ALARM; > + RPC_U16(&msg, 0U) = (uint16_t) year; > + RPC_U8(&msg, 2U) = (uint8_t) mon; > + RPC_U8(&msg, 3U) = (uint8_t) day; > + RPC_U8(&msg, 4U) = (uint8_t) hour; > + RPC_U8(&msg, 5U) = (uint8_t) min; > + RPC_U8(&msg, 6U) = (uint8_t) sec; > + RPC_SIZE(&msg) = 3U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_timer_set_rtc_periodic_alarm(sc_ipc_t ipc, uint32_t sec) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; > + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_RTC_PERIODIC_ALARM; > + RPC_U32(&msg, 0U) = (uint32_t) sec; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_timer_cancel_rtc_alarm(sc_ipc_t ipc) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; > + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_CANCEL_RTC_ALARM; > + RPC_SIZE(&msg) = 1U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +sc_err_t sc_timer_set_rtc_calb(sc_ipc_t ipc, int8_t count) > +{ > + sc_rpc_msg_t msg; > + uint8_t result; > + > + RPC_VER(&msg) = SC_RPC_VERSION; > + RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER; > + RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_RTC_CALB; > + RPC_I8(&msg, 0U) = (int8_t) count; > + RPC_SIZE(&msg) = 2U; > + > + sc_call_rpc(ipc, &msg, SC_FALSE); > + > + result = RPC_R8(&msg); > + return (sc_err_t) result; > +} > + > +/**@}*/ > + > diff --git a/include/dt-bindings/pinctrl/pads-imx8qm.h > b/include/dt-bindings/pinctrl/pads-imx8qm.h > new file mode 100644 > index 0000000000..ba75ecb7a5 > --- /dev/null > +++ b/include/dt-bindings/pinctrl/pads-imx8qm.h > @@ -0,0 +1,975 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * Header file used to configure SoC pad list. > + */ > + > +#ifndef SC_PADS_H > +#define SC_PADS_H > + > +/* Includes */ > + > +/* Defines */ > + > +/*! > + * @name Pad Definitions > + */ > +/*@{*/ > +#define SC_P_SIM0_CLK 0 /*!< > DMA.SIM0.CLK, LSIO.GPIO0.IO00 */ > +#define SC_P_SIM0_RST 1 /*!< > DMA.SIM0.RST, LSIO.GPIO0.IO01 */ > +#define SC_P_SIM0_IO 2 /*!< > DMA.SIM0.IO, LSIO.GPIO0.IO02 */ > +#define SC_P_SIM0_PD 3 /*!< > DMA.SIM0.PD, DMA.I2C3.SCL, LSIO.GPIO0.IO03 */ > +#define SC_P_SIM0_POWER_EN 4 /*!< > DMA.SIM0.POWER_EN, DMA.I2C3.SDA, LSIO.GPIO0.IO04 */ > +#define SC_P_SIM0_GPIO0_00 5 /*!< > DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM 6 /*!< */ > +#define SC_P_M40_I2C0_SCL 7 /*!< > M40.I2C0.SCL, M40.UART0.RX, M40.GPIO0.IO02, LSIO.GPIO0.IO06 */ > +#define SC_P_M40_I2C0_SDA 8 /*!< > M40.I2C0.SDA, M40.UART0.TX, M40.GPIO0.IO03, LSIO.GPIO0.IO07 */ > +#define SC_P_M40_GPIO0_00 9 /*!< > M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */ > +#define SC_P_M40_GPIO0_01 10 /*!< > M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */ > +#define SC_P_M41_I2C0_SCL 11 /*!< > M41.I2C0.SCL, M41.UART0.RX, M41.GPIO0.IO02, LSIO.GPIO0.IO10 */ > +#define SC_P_M41_I2C0_SDA 12 /*!< > M41.I2C0.SDA, M41.UART0.TX, M41.GPIO0.IO03, LSIO.GPIO0.IO11 */ > +#define SC_P_M41_GPIO0_00 13 /*!< > M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */ > +#define SC_P_M41_GPIO0_01 14 /*!< > M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */ > +#define SC_P_GPT0_CLK 15 /*!< > LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */ > +#define SC_P_GPT0_CAPTURE 16 /*!< > LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */ > +#define SC_P_GPT0_COMPARE 17 /*!< > LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */ > +#define SC_P_GPT1_CLK 18 /*!< > LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */ > +#define SC_P_GPT1_CAPTURE 19 /*!< > LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */ > +#define SC_P_GPT1_COMPARE 20 /*!< > LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */ > +#define SC_P_UART0_RX 21 /*!< > DMA.UART0.RX, SCU.UART0.RX, LSIO.GPIO0.IO20 */ > +#define SC_P_UART0_TX 22 /*!< > DMA.UART0.TX, SCU.UART0.TX, LSIO.GPIO0.IO21 */ > +#define SC_P_UART0_RTS_B 23 /*!< > DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */ > +#define SC_P_UART0_CTS_B 24 /*!< > DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */ > +#define SC_P_UART1_TX 25 /*!< > DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */ > +#define SC_P_UART1_RX 26 /*!< > DMA.UART1.RX, DMA.SPI3.SDO, LSIO.GPIO0.IO25 */ > +#define SC_P_UART1_RTS_B 27 /*!< > DMA.UART1.RTS_B, DMA.SPI3.SDI, DMA.UART1.CTS_B, LSIO.GPIO0.IO26 */ > +#define SC_P_UART1_CTS_B 28 /*!< > DMA.UART1.CTS_B, DMA.SPI3.CS0, DMA.UART1.RTS_B, LSIO.GPIO0.IO27 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 29 /*!< */ > +#define SC_P_SCU_PMIC_MEMC_ON 30 /*!< > SCU.GPIO0.IOXX_PMIC_MEMC_ON */ > +#define SC_P_SCU_WDOG_OUT 31 /*!< > SCU.WDOG0.WDOG_OUT */ > +#define SC_P_PMIC_I2C_SDA 32 /*!< > SCU.PMIC_I2C.SDA */ > +#define SC_P_PMIC_I2C_SCL 33 /*!< > SCU.PMIC_I2C.SCL */ > +#define SC_P_PMIC_EARLY_WARNING 34 /*!< > SCU.PMIC_EARLY_WARNING */ > +#define SC_P_PMIC_INT_B 35 /*!< > SCU.DSC.PMIC_INT_B */ > +#define SC_P_SCU_GPIO0_00 36 /*!< > SCU.GPIO0.IO00, SCU.UART0.RX, LSIO.GPIO0.IO28 */ > +#define SC_P_SCU_GPIO0_01 37 /*!< > SCU.GPIO0.IO01, SCU.UART0.TX, LSIO.GPIO0.IO29 */ > +#define SC_P_SCU_GPIO0_02 38 /*!< > SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */ > +#define SC_P_SCU_GPIO0_03 39 /*!< > SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */ > +#define SC_P_SCU_GPIO0_04 40 /*!< > SCU.GPIO0.IO04, SCU.GPIO0.IOXX_PMIC_A72_ON, LSIO.GPIO1.IO00 */ > +#define SC_P_SCU_GPIO0_05 41 /*!< > SCU.GPIO0.IO05, SCU.GPIO0.IOXX_PMIC_A53_ON, LSIO.GPIO1.IO01 */ > +#define SC_P_SCU_GPIO0_06 42 /*!< > SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */ > +#define SC_P_SCU_GPIO0_07 43 /*!< > SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, > LSIO.GPIO1.IO03 */ > +#define SC_P_SCU_BOOT_MODE0 44 /*!< > SCU.DSC.BOOT_MODE0 */ > +#define SC_P_SCU_BOOT_MODE1 45 /*!< > SCU.DSC.BOOT_MODE1 */ > +#define SC_P_SCU_BOOT_MODE2 46 /*!< > SCU.DSC.BOOT_MODE2 */ > +#define SC_P_SCU_BOOT_MODE3 47 /*!< > SCU.DSC.BOOT_MODE3 */ > +#define SC_P_SCU_BOOT_MODE4 48 /*!< > SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */ > +#define SC_P_SCU_BOOT_MODE5 49 /*!< > SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */ > +#define SC_P_LVDS0_GPIO00 50 /*!< > LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */ > +#define SC_P_LVDS0_GPIO01 51 /*!< > LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */ > +#define SC_P_LVDS0_I2C0_SCL 52 /*!< > LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */ > +#define SC_P_LVDS0_I2C0_SDA 53 /*!< > LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */ > +#define SC_P_LVDS0_I2C1_SCL 54 /*!< > LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */ > +#define SC_P_LVDS0_I2C1_SDA 55 /*!< > LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */ > +#define SC_P_LVDS1_GPIO00 56 /*!< > LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */ > +#define SC_P_LVDS1_GPIO01 57 /*!< > LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */ > +#define SC_P_LVDS1_I2C0_SCL 58 /*!< > LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */ > +#define SC_P_LVDS1_I2C0_SDA 59 /*!< > LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */ > +#define SC_P_LVDS1_I2C1_SCL 60 /*!< > LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */ > +#define SC_P_LVDS1_I2C1_SDA 61 /*!< > LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62 /*!< */ > +#define SC_P_MIPI_DSI0_I2C0_SCL 63 /*!< > MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */ > +#define SC_P_MIPI_DSI0_I2C0_SDA 64 /*!< > MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */ > +#define SC_P_MIPI_DSI0_GPIO0_00 65 /*!< > MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 */ > +#define SC_P_MIPI_DSI0_GPIO0_01 66 /*!< > MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */ > +#define SC_P_MIPI_DSI1_I2C0_SCL 67 /*!< > MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */ > +#define SC_P_MIPI_DSI1_I2C0_SDA 68 /*!< > MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */ > +#define SC_P_MIPI_DSI1_GPIO0_00 69 /*!< > MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 */ > +#define SC_P_MIPI_DSI1_GPIO0_01 70 /*!< > MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 71 /*!< */ > +#define SC_P_MIPI_CSI0_MCLK_OUT 72 /*!< > MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */ > +#define SC_P_MIPI_CSI0_I2C0_SCL 73 /*!< > MIPI_CSI0.I2C0.SCL, LSIO.GPIO1.IO25 */ > +#define SC_P_MIPI_CSI0_I2C0_SDA 74 /*!< > MIPI_CSI0.I2C0.SDA, LSIO.GPIO1.IO26 */ > +#define SC_P_MIPI_CSI0_GPIO0_00 75 /*!< > MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, MIPI_CSI1.I2C0.SCL, LSIO.GPIO1.IO27 */ > +#define SC_P_MIPI_CSI0_GPIO0_01 76 /*!< > MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, MIPI_CSI1.I2C0.SDA, LSIO.GPIO1.IO28 > */ > +#define SC_P_MIPI_CSI1_MCLK_OUT 77 /*!< > MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */ > +#define SC_P_MIPI_CSI1_GPIO0_00 78 /*!< > MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */ > +#define SC_P_MIPI_CSI1_GPIO0_01 79 /*!< > MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */ > +#define SC_P_MIPI_CSI1_I2C0_SCL 80 /*!< > MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */ > +#define SC_P_MIPI_CSI1_I2C0_SDA 81 /*!< > MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */ > +#define SC_P_HDMI_TX0_TS_SCL 82 /*!< > HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */ > +#define SC_P_HDMI_TX0_TS_SDA 83 /*!< > HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */ > +#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 84 /*!< */ > +#define SC_P_ESAI1_FSR 85 /*!< > AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */ > +#define SC_P_ESAI1_FST 86 /*!< > AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */ > +#define SC_P_ESAI1_SCKR 87 /*!< > AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */ > +#define SC_P_ESAI1_SCKT 88 /*!< > AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 */ > +#define SC_P_ESAI1_TX0 89 /*!< > AUD.ESAI1.TX0, AUD.SAI2.RXD, AUD.SPDIF0.RX, LSIO.GPIO2.IO08 */ > +#define SC_P_ESAI1_TX1 90 /*!< > AUD.ESAI1.TX1, AUD.SAI2.RXFS, AUD.SPDIF0.TX, LSIO.GPIO2.IO09 */ > +#define SC_P_ESAI1_TX2_RX3 91 /*!< > AUD.ESAI1.TX2_RX3, AUD.SPDIF0.RX, LSIO.GPIO2.IO10 */ > +#define SC_P_ESAI1_TX3_RX2 92 /*!< > AUD.ESAI1.TX3_RX2, AUD.SPDIF0.TX, LSIO.GPIO2.IO11 */ > +#define SC_P_ESAI1_TX4_RX1 93 /*!< > AUD.ESAI1.TX4_RX1, LSIO.GPIO2.IO12 */ > +#define SC_P_ESAI1_TX5_RX0 94 /*!< > AUD.ESAI1.TX5_RX0, LSIO.GPIO2.IO13 */ > +#define SC_P_SPDIF0_RX 95 /*!< > AUD.SPDIF0.RX, AUD.MQS.R, AUD.ACM.MCLK_IN1, LSIO.GPIO2.IO14 */ > +#define SC_P_SPDIF0_TX 96 /*!< > AUD.SPDIF0.TX, AUD.MQS.L, AUD.ACM.MCLK_OUT1, LSIO.GPIO2.IO15 */ > +#define SC_P_SPDIF0_EXT_CLK 97 /*!< > AUD.SPDIF0.EXT_CLK, DMA.DMA0.REQ_IN0, LSIO.GPIO2.IO16 */ > +#define SC_P_SPI3_SCK 98 /*!< > DMA.SPI3.SCK, LSIO.GPIO2.IO17 */ > +#define SC_P_SPI3_SDO 99 /*!< > DMA.SPI3.SDO, DMA.FTM.CH0, LSIO.GPIO2.IO18 */ > +#define SC_P_SPI3_SDI 100 /*!< > DMA.SPI3.SDI, DMA.FTM.CH1, LSIO.GPIO2.IO19 */ > +#define SC_P_SPI3_CS0 101 /*!< > DMA.SPI3.CS0, DMA.FTM.CH2, LSIO.GPIO2.IO20 */ > +#define SC_P_SPI3_CS1 102 /*!< > DMA.SPI3.CS1, LSIO.GPIO2.IO21 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 103 /*!< */ > +#define SC_P_ESAI0_FSR 104 /*!< > AUD.ESAI0.FSR, LSIO.GPIO2.IO22 */ > +#define SC_P_ESAI0_FST 105 /*!< > AUD.ESAI0.FST, LSIO.GPIO2.IO23 */ > +#define SC_P_ESAI0_SCKR 106 /*!< > AUD.ESAI0.SCKR, LSIO.GPIO2.IO24 */ > +#define SC_P_ESAI0_SCKT 107 /*!< > AUD.ESAI0.SCKT, LSIO.GPIO2.IO25 */ > +#define SC_P_ESAI0_TX0 108 /*!< > AUD.ESAI0.TX0, LSIO.GPIO2.IO26 */ > +#define SC_P_ESAI0_TX1 109 /*!< > AUD.ESAI0.TX1, LSIO.GPIO2.IO27 */ > +#define SC_P_ESAI0_TX2_RX3 110 /*!< > AUD.ESAI0.TX2_RX3, LSIO.GPIO2.IO28 */ > +#define SC_P_ESAI0_TX3_RX2 111 /*!< > AUD.ESAI0.TX3_RX2, LSIO.GPIO2.IO29 */ > +#define SC_P_ESAI0_TX4_RX1 112 /*!< > AUD.ESAI0.TX4_RX1, LSIO.GPIO2.IO30 */ > +#define SC_P_ESAI0_TX5_RX0 113 /*!< > AUD.ESAI0.TX5_RX0, LSIO.GPIO2.IO31 */ > +#define SC_P_MCLK_IN0 114 /*!< > AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, AUD.ESAI1.RX_HF_CLK, > LSIO.GPIO3.IO00 */ > +#define SC_P_MCLK_OUT0 115 /*!< > AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, AUD.ESAI1.TX_HF_CLK, > LSIO.GPIO3.IO01 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC 116 /*!< */ > +#define SC_P_SPI0_SCK 117 /*!< > DMA.SPI0.SCK, AUD.SAI0.RXC, LSIO.GPIO3.IO02 */ > +#define SC_P_SPI0_SDO 118 /*!< > DMA.SPI0.SDO, AUD.SAI0.TXD, LSIO.GPIO3.IO03 */ > +#define SC_P_SPI0_SDI 119 /*!< > DMA.SPI0.SDI, AUD.SAI0.RXD, LSIO.GPIO3.IO04 */ > +#define SC_P_SPI0_CS0 120 /*!< > DMA.SPI0.CS0, AUD.SAI0.RXFS, LSIO.GPIO3.IO05 */ > +#define SC_P_SPI0_CS1 121 /*!< > DMA.SPI0.CS1, AUD.SAI0.TXC, LSIO.GPIO3.IO06 */ > +#define SC_P_SPI2_SCK 122 /*!< > DMA.SPI2.SCK, LSIO.GPIO3.IO07 */ > +#define SC_P_SPI2_SDO 123 /*!< > DMA.SPI2.SDO, LSIO.GPIO3.IO08 */ > +#define SC_P_SPI2_SDI 124 /*!< > DMA.SPI2.SDI, LSIO.GPIO3.IO09 */ > +#define SC_P_SPI2_CS0 125 /*!< > DMA.SPI2.CS0, LSIO.GPIO3.IO10 */ > +#define SC_P_SPI2_CS1 126 /*!< > DMA.SPI2.CS1, AUD.SAI0.TXFS, LSIO.GPIO3.IO11 */ > +#define SC_P_SAI1_RXC 127 /*!< > AUD.SAI1.RXC, AUD.SAI0.TXD, LSIO.GPIO3.IO12 */ > +#define SC_P_SAI1_RXD 128 /*!< > AUD.SAI1.RXD, AUD.SAI0.TXFS, LSIO.GPIO3.IO13 */ > +#define SC_P_SAI1_RXFS 129 /*!< > AUD.SAI1.RXFS, AUD.SAI0.RXD, LSIO.GPIO3.IO14 */ > +#define SC_P_SAI1_TXC 130 /*!< > AUD.SAI1.TXC, AUD.SAI0.TXC, LSIO.GPIO3.IO15 */ > +#define SC_P_SAI1_TXD 131 /*!< > AUD.SAI1.TXD, AUD.SAI1.RXC, LSIO.GPIO3.IO16 */ > +#define SC_P_SAI1_TXFS 132 /*!< > AUD.SAI1.TXFS, AUD.SAI1.RXFS, LSIO.GPIO3.IO17 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 133 /*!< */ > +#define SC_P_ADC_IN7 134 /*!< > DMA.ADC1.IN3, DMA.SPI1.CS1, LSIO.KPP0.ROW3, LSIO.GPIO3.IO25 */ > +#define SC_P_ADC_IN6 135 /*!< > DMA.ADC1.IN2, DMA.SPI1.CS0, LSIO.KPP0.ROW2, LSIO.GPIO3.IO24 */ > +#define SC_P_ADC_IN5 136 /*!< > DMA.ADC1.IN1, DMA.SPI1.SDI, LSIO.KPP0.ROW1, LSIO.GPIO3.IO23 */ > +#define SC_P_ADC_IN4 137 /*!< > DMA.ADC1.IN0, DMA.SPI1.SDO, LSIO.KPP0.ROW0, LSIO.GPIO3.IO22 */ > +#define SC_P_ADC_IN3 138 /*!< > DMA.ADC0.IN3, DMA.SPI1.SCK, LSIO.KPP0.COL3, LSIO.GPIO3.IO21 */ > +#define SC_P_ADC_IN2 139 /*!< > DMA.ADC0.IN2, LSIO.KPP0.COL2, LSIO.GPIO3.IO20 */ > +#define SC_P_ADC_IN1 140 /*!< > DMA.ADC0.IN1, LSIO.KPP0.COL1, LSIO.GPIO3.IO19 */ > +#define SC_P_ADC_IN0 141 /*!< > DMA.ADC0.IN0, LSIO.KPP0.COL0, LSIO.GPIO3.IO18 */ > +#define SC_P_MLB_SIG 142 /*!< > CONN.MLB.SIG, AUD.SAI3.RXC, LSIO.GPIO3.IO26 */ > +#define SC_P_MLB_CLK 143 /*!< > CONN.MLB.CLK, AUD.SAI3.RXFS, LSIO.GPIO3.IO27 */ > +#define SC_P_MLB_DATA 144 /*!< > CONN.MLB.DATA, AUD.SAI3.RXD, LSIO.GPIO3.IO28 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 145 /*!< */ > +#define SC_P_FLEXCAN0_RX 146 /*!< > DMA.FLEXCAN0.RX, LSIO.GPIO3.IO29 */ > +#define SC_P_FLEXCAN0_TX 147 /*!< > DMA.FLEXCAN0.TX, LSIO.GPIO3.IO30 */ > +#define SC_P_FLEXCAN1_RX 148 /*!< > DMA.FLEXCAN1.RX, LSIO.GPIO3.IO31 */ > +#define SC_P_FLEXCAN1_TX 149 /*!< > DMA.FLEXCAN1.TX, LSIO.GPIO4.IO00 */ > +#define SC_P_FLEXCAN2_RX 150 /*!< > DMA.FLEXCAN2.RX, LSIO.GPIO4.IO01 */ > +#define SC_P_FLEXCAN2_TX 151 /*!< > DMA.FLEXCAN2.TX, LSIO.GPIO4.IO02 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 152 /*!< */ > +#define SC_P_USB_SS3_TC0 153 /*!< > DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO4.IO03 */ > +#define SC_P_USB_SS3_TC1 154 /*!< > DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */ > +#define SC_P_USB_SS3_TC2 155 /*!< > DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO05 */ > +#define SC_P_USB_SS3_TC3 156 /*!< > DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */ > +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 157 /*!< */ > +#define SC_P_USDHC1_RESET_B 158 /*!< > CONN.USDHC1.RESET_B, LSIO.GPIO4.IO07 */ > +#define SC_P_USDHC1_VSELECT 159 /*!< > CONN.USDHC1.VSELECT, LSIO.GPIO4.IO08 */ > +#define SC_P_USDHC2_RESET_B 160 /*!< > CONN.USDHC2.RESET_B, LSIO.GPIO4.IO09 */ > +#define SC_P_USDHC2_VSELECT 161 /*!< > CONN.USDHC2.VSELECT, LSIO.GPIO4.IO10 */ > +#define SC_P_USDHC2_WP 162 /*!< > CONN.USDHC2.WP, LSIO.GPIO4.IO11 */ > +#define SC_P_USDHC2_CD_B 163 /*!< > CONN.USDHC2.CD_B, LSIO.GPIO4.IO12 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 164 /*!< */ > +#define SC_P_ENET0_MDIO 165 /*!< > CONN.ENET0.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO13 */ > +#define SC_P_ENET0_MDC 166 /*!< > CONN.ENET0.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO14 */ > +#define SC_P_ENET0_REFCLK_125M_25M 167 /*!< > CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, LSIO.GPIO4.IO15 */ > +#define SC_P_ENET1_REFCLK_125M_25M 168 /*!< > CONN.ENET1.REFCLK_125M_25M, CONN.ENET1.PPS, LSIO.GPIO4.IO16 */ > +#define SC_P_ENET1_MDIO 169 /*!< > CONN.ENET1.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO17 */ > +#define SC_P_ENET1_MDC 170 /*!< > CONN.ENET1.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO18 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 171 /*!< */ > +#define SC_P_QSPI1A_SS0_B 172 /*!< > LSIO.QSPI1A.SS0_B, LSIO.GPIO4.IO19 */ > +#define SC_P_QSPI1A_SS1_B 173 /*!< > LSIO.QSPI1A.SS1_B, LSIO.QSPI1A.SCLK2, LSIO.GPIO4.IO20 */ > +#define SC_P_QSPI1A_SCLK 174 /*!< > LSIO.QSPI1A.SCLK, LSIO.GPIO4.IO21 */ > +#define SC_P_QSPI1A_DQS 175 /*!< > LSIO.QSPI1A.DQS, LSIO.GPIO4.IO22 */ > +#define SC_P_QSPI1A_DATA3 176 /*!< > LSIO.QSPI1A.DATA3, DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO23 */ > +#define SC_P_QSPI1A_DATA2 177 /*!< > LSIO.QSPI1A.DATA2, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO24 */ > +#define SC_P_QSPI1A_DATA1 178 /*!< > LSIO.QSPI1A.DATA1, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO25 */ > +#define SC_P_QSPI1A_DATA0 179 /*!< > LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1 180 /*!< */ > +#define SC_P_QSPI0A_DATA0 181 /*!< > LSIO.QSPI0A.DATA0 */ > +#define SC_P_QSPI0A_DATA1 182 /*!< > LSIO.QSPI0A.DATA1 */ > +#define SC_P_QSPI0A_DATA2 183 /*!< > LSIO.QSPI0A.DATA2 */ > +#define SC_P_QSPI0A_DATA3 184 /*!< > LSIO.QSPI0A.DATA3 */ > +#define SC_P_QSPI0A_DQS 185 /*!< > LSIO.QSPI0A.DQS */ > +#define SC_P_QSPI0A_SS0_B 186 /*!< > LSIO.QSPI0A.SS0_B */ > +#define SC_P_QSPI0A_SS1_B 187 /*!< > LSIO.QSPI0A.SS1_B, LSIO.QSPI0A.SCLK2 */ > +#define SC_P_QSPI0A_SCLK 188 /*!< > LSIO.QSPI0A.SCLK */ > +#define SC_P_QSPI0B_SCLK 189 /*!< > LSIO.QSPI0B.SCLK */ > +#define SC_P_QSPI0B_DATA0 190 /*!< > LSIO.QSPI0B.DATA0 */ > +#define SC_P_QSPI0B_DATA1 191 /*!< > LSIO.QSPI0B.DATA1 */ > +#define SC_P_QSPI0B_DATA2 192 /*!< > LSIO.QSPI0B.DATA2 */ > +#define SC_P_QSPI0B_DATA3 193 /*!< > LSIO.QSPI0B.DATA3 */ > +#define SC_P_QSPI0B_DQS 194 /*!< > LSIO.QSPI0B.DQS */ > +#define SC_P_QSPI0B_SS0_B 195 /*!< > LSIO.QSPI0B.SS0_B */ > +#define SC_P_QSPI0B_SS1_B 196 /*!< > LSIO.QSPI0B.SS1_B, LSIO.QSPI0B.SCLK2 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 197 /*!< */ > +#define SC_P_PCIE_CTRL0_CLKREQ_B 198 /*!< > HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO27 */ > +#define SC_P_PCIE_CTRL0_WAKE_B 199 /*!< > HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO28 */ > +#define SC_P_PCIE_CTRL0_PERST_B 200 /*!< > HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO29 */ > +#define SC_P_PCIE_CTRL1_CLKREQ_B 201 /*!< > HSIO.PCIE1.CLKREQ_B, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO30 > */ > +#define SC_P_PCIE_CTRL1_WAKE_B 202 /*!< > HSIO.PCIE1.WAKE_B, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO31 > */ > +#define SC_P_PCIE_CTRL1_PERST_B 203 /*!< > HSIO.PCIE1.PERST_B, DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO5.IO00 > */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 204 /*!< */ > +#define SC_P_USB_HSIC0_DATA 205 /*!< > CONN.USB_HSIC0.DATA, DMA.I2C1.SDA, LSIO.GPIO5.IO01 */ > +#define SC_P_USB_HSIC0_STROBE 206 /*!< > CONN.USB_HSIC0.STROBE, DMA.I2C1.SCL, LSIO.GPIO5.IO02 */ > +#define SC_P_CALIBRATION_0_HSIC 207 /*!< */ > +#define SC_P_CALIBRATION_1_HSIC 208 /*!< */ > +#define SC_P_EMMC0_CLK 209 /*!< > CONN.EMMC0.CLK, CONN.NAND.READY_B */ > +#define SC_P_EMMC0_CMD 210 /*!< > CONN.EMMC0.CMD, CONN.NAND.DQS, AUD.MQS.R, LSIO.GPIO5.IO03 */ > +#define SC_P_EMMC0_DATA0 211 /*!< > CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO5.IO04 */ > +#define SC_P_EMMC0_DATA1 212 /*!< > CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO5.IO05 */ > +#define SC_P_EMMC0_DATA2 213 /*!< > CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO5.IO06 */ > +#define SC_P_EMMC0_DATA3 214 /*!< > CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO5.IO07 */ > +#define SC_P_EMMC0_DATA4 215 /*!< > CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO5.IO08 */ > +#define SC_P_EMMC0_DATA5 216 /*!< > CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO5.IO09 */ > +#define SC_P_EMMC0_DATA6 217 /*!< > CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO5.IO10 */ > +#define SC_P_EMMC0_DATA7 218 /*!< > CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO5.IO11 */ > +#define SC_P_EMMC0_STROBE 219 /*!< > CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO5.IO12 */ > +#define SC_P_EMMC0_RESET_B 220 /*!< > CONN.EMMC0.RESET_B, CONN.NAND.WP_B, CONN.USDHC1.VSELECT, > LSIO.GPIO5.IO13 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 221 /*!< */ > +#define SC_P_USDHC1_CLK 222 /*!< > CONN.USDHC1.CLK, AUD.MQS.R */ > +#define SC_P_USDHC1_CMD 223 /*!< > CONN.USDHC1.CMD, AUD.MQS.L, LSIO.GPIO5.IO14 */ > +#define SC_P_USDHC1_DATA0 224 /*!< > CONN.USDHC1.DATA0, CONN.NAND.RE_N, LSIO.GPIO5.IO15 */ > +#define SC_P_USDHC1_DATA1 225 /*!< > CONN.USDHC1.DATA1, CONN.NAND.RE_P, LSIO.GPIO5.IO16 */ > +#define SC_P_CTL_NAND_RE_P_N 226 /*!< */ > +#define SC_P_USDHC1_DATA2 227 /*!< > CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */ > +#define SC_P_USDHC1_DATA3 228 /*!< > CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */ > +#define SC_P_CTL_NAND_DQS_P_N 229 /*!< */ > +#define SC_P_USDHC1_DATA4 230 /*!< > CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 */ > +#define SC_P_USDHC1_DATA5 231 /*!< > CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */ > +#define SC_P_USDHC1_DATA6 232 /*!< > CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 > */ > +#define SC_P_USDHC1_DATA7 233 /*!< > CONN.USDHC1.DATA7, CONN.NAND.ALE, CONN.USDHC1.CD_B, > LSIO.GPIO5.IO22 */ > +#define SC_P_USDHC1_STROBE 234 /*!< > CONN.USDHC1.STROBE, CONN.NAND.CE1_B, CONN.USDHC1.RESET_B, > LSIO.GPIO5.IO23 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2 235 /*!< */ > +#define SC_P_USDHC2_CLK 236 /*!< > CONN.USDHC2.CLK, AUD.MQS.R, LSIO.GPIO5.IO24 */ > +#define SC_P_USDHC2_CMD 237 /*!< > CONN.USDHC2.CMD, AUD.MQS.L, LSIO.GPIO5.IO25 */ > +#define SC_P_USDHC2_DATA0 238 /*!< > CONN.USDHC2.DATA0, DMA.UART4.RX, LSIO.GPIO5.IO26 */ > +#define SC_P_USDHC2_DATA1 239 /*!< > CONN.USDHC2.DATA1, DMA.UART4.TX, LSIO.GPIO5.IO27 */ > +#define SC_P_USDHC2_DATA2 240 /*!< > CONN.USDHC2.DATA2, DMA.UART4.CTS_B, LSIO.GPIO5.IO28 */ > +#define SC_P_USDHC2_DATA3 241 /*!< > CONN.USDHC2.DATA3, DMA.UART4.RTS_B, LSIO.GPIO5.IO29 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 242 /*!< */ > +#define SC_P_ENET0_RGMII_TXC 243 /*!< > CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, > CONN.ENET0.RCLK50M_IN, LSIO.GPIO5.IO30 */ > +#define SC_P_ENET0_RGMII_TX_CTL 244 /*!< > CONN.ENET0.RGMII_TX_CTL, LSIO.GPIO5.IO31 */ > +#define SC_P_ENET0_RGMII_TXD0 245 /*!< > CONN.ENET0.RGMII_TXD0, LSIO.GPIO6.IO00 */ > +#define SC_P_ENET0_RGMII_TXD1 246 /*!< > CONN.ENET0.RGMII_TXD1, LSIO.GPIO6.IO01 */ > +#define SC_P_ENET0_RGMII_TXD2 247 /*!< > CONN.ENET0.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO02 > */ > +#define SC_P_ENET0_RGMII_TXD3 248 /*!< > CONN.ENET0.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, > LSIO.GPIO6.IO03 */ > +#define SC_P_ENET0_RGMII_RXC 249 /*!< > CONN.ENET0.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, > LSIO.GPIO6.IO04 */ > +#define SC_P_ENET0_RGMII_RX_CTL 250 /*!< > CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 */ > +#define SC_P_ENET0_RGMII_RXD0 251 /*!< > CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */ > +#define SC_P_ENET0_RGMII_RXD1 252 /*!< > CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */ > +#define SC_P_ENET0_RGMII_RXD2 253 /*!< > CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, VPU.TSI_S0.CLK, > LSIO.GPIO6.IO08 */ > +#define SC_P_ENET0_RGMII_RXD3 254 /*!< > CONN.ENET0.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO09 > */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 255 /*!< */ > +#define SC_P_ENET1_RGMII_TXC 256 /*!< > CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_OUT, > CONN.ENET1.RCLK50M_IN, LSIO.GPIO6.IO10 */ > +#define SC_P_ENET1_RGMII_TX_CTL 257 /*!< > CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO6.IO11 */ > +#define SC_P_ENET1_RGMII_TXD0 258 /*!< > CONN.ENET1.RGMII_TXD0, LSIO.GPIO6.IO12 */ > +#define SC_P_ENET1_RGMII_TXD1 259 /*!< > CONN.ENET1.RGMII_TXD1, LSIO.GPIO6.IO13 */ > +#define SC_P_ENET1_RGMII_TXD2 260 /*!< > CONN.ENET1.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO14 > */ > +#define SC_P_ENET1_RGMII_TXD3 261 /*!< > CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, > LSIO.GPIO6.IO15 */ > +#define SC_P_ENET1_RGMII_RXC 262 /*!< > CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, > LSIO.GPIO6.IO16 */ > +#define SC_P_ENET1_RGMII_RX_CTL 263 /*!< > CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 */ > +#define SC_P_ENET1_RGMII_RXD0 264 /*!< > CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */ > +#define SC_P_ENET1_RGMII_RXD1 265 /*!< > CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */ > +#define SC_P_ENET1_RGMII_RXD2 266 /*!< > CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, > LSIO.GPIO6.IO20 */ > +#define SC_P_ENET1_RGMII_RXD3 267 /*!< > CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 > */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 268 /*!< */ > +/*@}*/ > + > +/*! > + * @name Pad Mux Definitions > + * format: name padid padmux > + */ > +/*@{*/ > +#define SC_P_SIM0_CLK_DMA_SIM0_CLK > SC_P_SIM0_CLK 0 > +#define SC_P_SIM0_CLK_LSIO_GPIO0_IO00 > SC_P_SIM0_CLK 3 > +#define SC_P_SIM0_RST_DMA_SIM0_RST > SC_P_SIM0_RST 0 > +#define SC_P_SIM0_RST_LSIO_GPIO0_IO01 > SC_P_SIM0_RST 3 > +#define SC_P_SIM0_IO_DMA_SIM0_IO > SC_P_SIM0_IO 0 > +#define SC_P_SIM0_IO_LSIO_GPIO0_IO02 > SC_P_SIM0_IO 3 > +#define SC_P_SIM0_PD_DMA_SIM0_PD > SC_P_SIM0_PD 0 > +#define SC_P_SIM0_PD_DMA_I2C3_SCL > SC_P_SIM0_PD 1 > +#define SC_P_SIM0_PD_LSIO_GPIO0_IO03 > SC_P_SIM0_PD 3 > +#define SC_P_SIM0_POWER_EN_DMA_SIM0_POWER_EN > SC_P_SIM0_POWER_EN 0 > +#define SC_P_SIM0_POWER_EN_DMA_I2C3_SDA > SC_P_SIM0_POWER_EN 1 > +#define SC_P_SIM0_POWER_EN_LSIO_GPIO0_IO04 > SC_P_SIM0_POWER_EN 3 > +#define SC_P_SIM0_GPIO0_00_DMA_SIM0_POWER_EN > SC_P_SIM0_GPIO0_00 0 > +#define SC_P_SIM0_GPIO0_00_LSIO_GPIO0_IO05 > SC_P_SIM0_GPIO0_00 3 > +#define SC_P_M40_I2C0_SCL_M40_I2C0_SCL > SC_P_M40_I2C0_SCL 0 > +#define SC_P_M40_I2C0_SCL_M40_UART0_RX > SC_P_M40_I2C0_SCL 1 > +#define SC_P_M40_I2C0_SCL_M40_GPIO0_IO02 > SC_P_M40_I2C0_SCL 2 > +#define SC_P_M40_I2C0_SCL_LSIO_GPIO0_IO06 > SC_P_M40_I2C0_SCL 3 > +#define SC_P_M40_I2C0_SDA_M40_I2C0_SDA > SC_P_M40_I2C0_SDA 0 > +#define SC_P_M40_I2C0_SDA_M40_UART0_TX > SC_P_M40_I2C0_SDA 1 > +#define SC_P_M40_I2C0_SDA_M40_GPIO0_IO03 > SC_P_M40_I2C0_SDA 2 > +#define SC_P_M40_I2C0_SDA_LSIO_GPIO0_IO07 > SC_P_M40_I2C0_SDA 3 > +#define SC_P_M40_GPIO0_00_M40_GPIO0_IO00 > SC_P_M40_GPIO0_00 0 > +#define SC_P_M40_GPIO0_00_M40_TPM0_CH0 > SC_P_M40_GPIO0_00 1 > +#define SC_P_M40_GPIO0_00_DMA_UART4_RX > SC_P_M40_GPIO0_00 2 > +#define SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08 > SC_P_M40_GPIO0_00 3 > +#define SC_P_M40_GPIO0_01_M40_GPIO0_IO01 > SC_P_M40_GPIO0_01 0 > +#define SC_P_M40_GPIO0_01_M40_TPM0_CH1 > SC_P_M40_GPIO0_01 1 > +#define SC_P_M40_GPIO0_01_DMA_UART4_TX > SC_P_M40_GPIO0_01 2 > +#define SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09 > SC_P_M40_GPIO0_01 3 > +#define SC_P_M41_I2C0_SCL_M41_I2C0_SCL > SC_P_M41_I2C0_SCL 0 > +#define SC_P_M41_I2C0_SCL_M41_UART0_RX > SC_P_M41_I2C0_SCL 1 > +#define SC_P_M41_I2C0_SCL_M41_GPIO0_IO02 > SC_P_M41_I2C0_SCL 2 > +#define SC_P_M41_I2C0_SCL_LSIO_GPIO0_IO10 > SC_P_M41_I2C0_SCL 3 > +#define SC_P_M41_I2C0_SDA_M41_I2C0_SDA > SC_P_M41_I2C0_SDA 0 > +#define SC_P_M41_I2C0_SDA_M41_UART0_TX > SC_P_M41_I2C0_SDA 1 > +#define SC_P_M41_I2C0_SDA_M41_GPIO0_IO03 > SC_P_M41_I2C0_SDA 2 > +#define SC_P_M41_I2C0_SDA_LSIO_GPIO0_IO11 > SC_P_M41_I2C0_SDA 3 > +#define SC_P_M41_GPIO0_00_M41_GPIO0_IO00 > SC_P_M41_GPIO0_00 0 > +#define SC_P_M41_GPIO0_00_M41_TPM0_CH0 > SC_P_M41_GPIO0_00 1 > +#define SC_P_M41_GPIO0_00_DMA_UART3_RX > SC_P_M41_GPIO0_00 2 > +#define SC_P_M41_GPIO0_00_LSIO_GPIO0_IO12 > SC_P_M41_GPIO0_00 3 > +#define SC_P_M41_GPIO0_01_M41_GPIO0_IO01 > SC_P_M41_GPIO0_01 0 > +#define SC_P_M41_GPIO0_01_M41_TPM0_CH1 > SC_P_M41_GPIO0_01 1 > +#define SC_P_M41_GPIO0_01_DMA_UART3_TX > SC_P_M41_GPIO0_01 2 > +#define SC_P_M41_GPIO0_01_LSIO_GPIO0_IO13 > SC_P_M41_GPIO0_01 3 > +#define SC_P_GPT0_CLK_LSIO_GPT0_CLK > SC_P_GPT0_CLK 0 > +#define SC_P_GPT0_CLK_DMA_I2C1_SCL > SC_P_GPT0_CLK 1 > +#define SC_P_GPT0_CLK_LSIO_KPP0_COL4 > SC_P_GPT0_CLK 2 > +#define SC_P_GPT0_CLK_LSIO_GPIO0_IO14 > SC_P_GPT0_CLK 3 > +#define SC_P_GPT0_CAPTURE_LSIO_GPT0_CAPTURE > SC_P_GPT0_CAPTURE 0 > +#define SC_P_GPT0_CAPTURE_DMA_I2C1_SDA > SC_P_GPT0_CAPTURE 1 > +#define SC_P_GPT0_CAPTURE_LSIO_KPP0_COL5 > SC_P_GPT0_CAPTURE 2 > +#define SC_P_GPT0_CAPTURE_LSIO_GPIO0_IO15 > SC_P_GPT0_CAPTURE 3 > +#define SC_P_GPT0_COMPARE_LSIO_GPT0_COMPARE > SC_P_GPT0_COMPARE 0 > +#define SC_P_GPT0_COMPARE_LSIO_PWM3_OUT > SC_P_GPT0_COMPARE 1 > +#define SC_P_GPT0_COMPARE_LSIO_KPP0_COL6 > SC_P_GPT0_COMPARE 2 > +#define SC_P_GPT0_COMPARE_LSIO_GPIO0_IO16 > SC_P_GPT0_COMPARE 3 > +#define SC_P_GPT1_CLK_LSIO_GPT1_CLK > SC_P_GPT1_CLK 0 > +#define SC_P_GPT1_CLK_DMA_I2C2_SCL > SC_P_GPT1_CLK 1 > +#define SC_P_GPT1_CLK_LSIO_KPP0_COL7 > SC_P_GPT1_CLK 2 > +#define SC_P_GPT1_CLK_LSIO_GPIO0_IO17 > SC_P_GPT1_CLK 3 > +#define SC_P_GPT1_CAPTURE_LSIO_GPT1_CAPTURE > SC_P_GPT1_CAPTURE 0 > +#define SC_P_GPT1_CAPTURE_DMA_I2C2_SDA > SC_P_GPT1_CAPTURE 1 > +#define SC_P_GPT1_CAPTURE_LSIO_KPP0_ROW4 > SC_P_GPT1_CAPTURE 2 > +#define SC_P_GPT1_CAPTURE_LSIO_GPIO0_IO18 > SC_P_GPT1_CAPTURE 3 > +#define SC_P_GPT1_COMPARE_LSIO_GPT1_COMPARE > SC_P_GPT1_COMPARE 0 > +#define SC_P_GPT1_COMPARE_LSIO_PWM2_OUT > SC_P_GPT1_COMPARE 1 > +#define SC_P_GPT1_COMPARE_LSIO_KPP0_ROW5 > SC_P_GPT1_COMPARE 2 > +#define SC_P_GPT1_COMPARE_LSIO_GPIO0_IO19 > SC_P_GPT1_COMPARE 3 > +#define SC_P_UART0_RX_DMA_UART0_RX > SC_P_UART0_RX 0 > +#define SC_P_UART0_RX_SCU_UART0_RX > SC_P_UART0_RX 1 > +#define SC_P_UART0_RX_LSIO_GPIO0_IO20 > SC_P_UART0_RX 3 > +#define SC_P_UART0_TX_DMA_UART0_TX > SC_P_UART0_TX 0 > +#define SC_P_UART0_TX_SCU_UART0_TX > SC_P_UART0_TX 1 > +#define SC_P_UART0_TX_LSIO_GPIO0_IO21 > SC_P_UART0_TX 3 > +#define SC_P_UART0_RTS_B_DMA_UART0_RTS_B > SC_P_UART0_RTS_B 0 > +#define SC_P_UART0_RTS_B_LSIO_PWM0_OUT > SC_P_UART0_RTS_B 1 > +#define SC_P_UART0_RTS_B_DMA_UART2_RX > SC_P_UART0_RTS_B 2 > +#define SC_P_UART0_RTS_B_LSIO_GPIO0_IO22 > SC_P_UART0_RTS_B 3 > +#define SC_P_UART0_CTS_B_DMA_UART0_CTS_B > SC_P_UART0_CTS_B 0 > +#define SC_P_UART0_CTS_B_LSIO_PWM1_OUT > SC_P_UART0_CTS_B 1 > +#define SC_P_UART0_CTS_B_DMA_UART2_TX > SC_P_UART0_CTS_B 2 > +#define SC_P_UART0_CTS_B_LSIO_GPIO0_IO23 > SC_P_UART0_CTS_B 3 > +#define SC_P_UART1_TX_DMA_UART1_TX > SC_P_UART1_TX 0 > +#define SC_P_UART1_TX_DMA_SPI3_SCK > SC_P_UART1_TX 1 > +#define SC_P_UART1_TX_LSIO_GPIO0_IO24 > SC_P_UART1_TX 3 > +#define SC_P_UART1_RX_DMA_UART1_RX > SC_P_UART1_RX 0 > +#define SC_P_UART1_RX_DMA_SPI3_SDO > SC_P_UART1_RX 1 > +#define SC_P_UART1_RX_LSIO_GPIO0_IO25 > SC_P_UART1_RX 3 > +#define SC_P_UART1_RTS_B_DMA_UART1_RTS_B > SC_P_UART1_RTS_B 0 > +#define SC_P_UART1_RTS_B_DMA_SPI3_SDI > SC_P_UART1_RTS_B 1 > +#define SC_P_UART1_RTS_B_DMA_UART1_CTS_B > SC_P_UART1_RTS_B 2 > +#define SC_P_UART1_RTS_B_LSIO_GPIO0_IO26 > SC_P_UART1_RTS_B 3 > +#define SC_P_UART1_CTS_B_DMA_UART1_CTS_B > SC_P_UART1_CTS_B 0 > +#define SC_P_UART1_CTS_B_DMA_SPI3_CS0 > SC_P_UART1_CTS_B 1 > +#define SC_P_UART1_CTS_B_DMA_UART1_RTS_B > SC_P_UART1_CTS_B 2 > +#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO27 > SC_P_UART1_CTS_B 3 > +#define SC_P_SCU_PMIC_MEMC_ON_SCU_GPIO0_IOXX_PMIC_MEMC_ON > SC_P_SCU_PMIC_MEMC_ON 0 > +#define SC_P_SCU_WDOG_OUT_SCU_WDOG0_WDOG_OUT > SC_P_SCU_WDOG_OUT 0 > +#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA > SC_P_PMIC_I2C_SDA 0 > +#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL > SC_P_PMIC_I2C_SCL 0 > +#define SC_P_PMIC_EARLY_WARNING_SCU_PMIC_EARLY_WARNING > SC_P_PMIC_EARLY_WARNING 0 > +#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B > SC_P_PMIC_INT_B 0 > +#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00 > SC_P_SCU_GPIO0_00 0 > +#define SC_P_SCU_GPIO0_00_SCU_UART0_RX > SC_P_SCU_GPIO0_00 1 > +#define SC_P_SCU_GPIO0_00_LSIO_GPIO0_IO28 > SC_P_SCU_GPIO0_00 3 > +#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01 > SC_P_SCU_GPIO0_01 0 > +#define SC_P_SCU_GPIO0_01_SCU_UART0_TX > SC_P_SCU_GPIO0_01 1 > +#define SC_P_SCU_GPIO0_01_LSIO_GPIO0_IO29 > SC_P_SCU_GPIO0_01 3 > +#define SC_P_SCU_GPIO0_02_SCU_GPIO0_IO02 > SC_P_SCU_GPIO0_02 0 > +#define SC_P_SCU_GPIO0_02_SCU_GPIO0_IOXX_PMIC_GPU0_ON > SC_P_SCU_GPIO0_02 1 > +#define SC_P_SCU_GPIO0_02_LSIO_GPIO0_IO30 > SC_P_SCU_GPIO0_02 3 > +#define SC_P_SCU_GPIO0_03_SCU_GPIO0_IO03 > SC_P_SCU_GPIO0_03 0 > +#define SC_P_SCU_GPIO0_03_SCU_GPIO0_IOXX_PMIC_GPU1_ON > SC_P_SCU_GPIO0_03 1 > +#define SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31 > SC_P_SCU_GPIO0_03 3 > +#define SC_P_SCU_GPIO0_04_SCU_GPIO0_IO04 > SC_P_SCU_GPIO0_04 0 > +#define SC_P_SCU_GPIO0_04_SCU_GPIO0_IOXX_PMIC_A72_ON > SC_P_SCU_GPIO0_04 1 > +#define SC_P_SCU_GPIO0_04_LSIO_GPIO1_IO00 > SC_P_SCU_GPIO0_04 3 > +#define SC_P_SCU_GPIO0_05_SCU_GPIO0_IO05 > SC_P_SCU_GPIO0_05 0 > +#define SC_P_SCU_GPIO0_05_SCU_GPIO0_IOXX_PMIC_A53_ON > SC_P_SCU_GPIO0_05 1 > +#define SC_P_SCU_GPIO0_05_LSIO_GPIO1_IO01 > SC_P_SCU_GPIO0_05 3 > +#define SC_P_SCU_GPIO0_06_SCU_GPIO0_IO06 > SC_P_SCU_GPIO0_06 0 > +#define SC_P_SCU_GPIO0_06_SCU_TPM0_CH0 > SC_P_SCU_GPIO0_06 1 > +#define SC_P_SCU_GPIO0_06_LSIO_GPIO1_IO02 > SC_P_SCU_GPIO0_06 3 > +#define SC_P_SCU_GPIO0_07_SCU_GPIO0_IO07 > SC_P_SCU_GPIO0_07 0 > +#define SC_P_SCU_GPIO0_07_SCU_TPM0_CH1 > SC_P_SCU_GPIO0_07 1 > +#define SC_P_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K > SC_P_SCU_GPIO0_07 2 > +#define SC_P_SCU_GPIO0_07_LSIO_GPIO1_IO03 > SC_P_SCU_GPIO0_07 3 > +#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 > SC_P_SCU_BOOT_MODE0 0 > +#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 > SC_P_SCU_BOOT_MODE1 0 > +#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 > SC_P_SCU_BOOT_MODE2 0 > +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 > SC_P_SCU_BOOT_MODE3 0 > +#define SC_P_SCU_BOOT_MODE4_SCU_DSC_BOOT_MODE4 > SC_P_SCU_BOOT_MODE4 0 > +#define SC_P_SCU_BOOT_MODE4_SCU_PMIC_I2C_SCL > SC_P_SCU_BOOT_MODE4 1 > +#define SC_P_SCU_BOOT_MODE5_SCU_DSC_BOOT_MODE5 > SC_P_SCU_BOOT_MODE5 0 > +#define SC_P_SCU_BOOT_MODE5_SCU_PMIC_I2C_SDA > SC_P_SCU_BOOT_MODE5 1 > +#define SC_P_LVDS0_GPIO00_LVDS0_GPIO0_IO00 > SC_P_LVDS0_GPIO00 0 > +#define SC_P_LVDS0_GPIO00_LVDS0_PWM0_OUT > SC_P_LVDS0_GPIO00 1 > +#define SC_P_LVDS0_GPIO00_LSIO_GPIO1_IO04 > SC_P_LVDS0_GPIO00 3 > +#define SC_P_LVDS0_GPIO01_LVDS0_GPIO0_IO01 > SC_P_LVDS0_GPIO01 0 > +#define SC_P_LVDS0_GPIO01_LSIO_GPIO1_IO05 > SC_P_LVDS0_GPIO01 3 > +#define SC_P_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL > SC_P_LVDS0_I2C0_SCL 0 > +#define SC_P_LVDS0_I2C0_SCL_LVDS0_GPIO0_IO02 > SC_P_LVDS0_I2C0_SCL 1 > +#define SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 > SC_P_LVDS0_I2C0_SCL 3 > +#define SC_P_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA > SC_P_LVDS0_I2C0_SDA 0 > +#define SC_P_LVDS0_I2C0_SDA_LVDS0_GPIO0_IO03 > SC_P_LVDS0_I2C0_SDA 1 > +#define SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 > SC_P_LVDS0_I2C0_SDA 3 > +#define SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL > SC_P_LVDS0_I2C1_SCL 0 > +#define SC_P_LVDS0_I2C1_SCL_DMA_UART2_TX > SC_P_LVDS0_I2C1_SCL 1 > +#define SC_P_LVDS0_I2C1_SCL_LSIO_GPIO1_IO08 > SC_P_LVDS0_I2C1_SCL 3 > +#define SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA > SC_P_LVDS0_I2C1_SDA 0 > +#define SC_P_LVDS0_I2C1_SDA_DMA_UART2_RX > SC_P_LVDS0_I2C1_SDA 1 > +#define SC_P_LVDS0_I2C1_SDA_LSIO_GPIO1_IO09 > SC_P_LVDS0_I2C1_SDA 3 > +#define SC_P_LVDS1_GPIO00_LVDS1_GPIO0_IO00 > SC_P_LVDS1_GPIO00 0 > +#define SC_P_LVDS1_GPIO00_LVDS1_PWM0_OUT > SC_P_LVDS1_GPIO00 1 > +#define SC_P_LVDS1_GPIO00_LSIO_GPIO1_IO10 > SC_P_LVDS1_GPIO00 3 > +#define SC_P_LVDS1_GPIO01_LVDS1_GPIO0_IO01 > SC_P_LVDS1_GPIO01 0 > +#define SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11 > SC_P_LVDS1_GPIO01 3 > +#define SC_P_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL > SC_P_LVDS1_I2C0_SCL 0 > +#define SC_P_LVDS1_I2C0_SCL_LVDS1_GPIO0_IO02 > SC_P_LVDS1_I2C0_SCL 1 > +#define SC_P_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 > SC_P_LVDS1_I2C0_SCL 3 > +#define SC_P_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA > SC_P_LVDS1_I2C0_SDA 0 > +#define SC_P_LVDS1_I2C0_SDA_LVDS1_GPIO0_IO03 > SC_P_LVDS1_I2C0_SDA 1 > +#define SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 > SC_P_LVDS1_I2C0_SDA 3 > +#define SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL > SC_P_LVDS1_I2C1_SCL 0 > +#define SC_P_LVDS1_I2C1_SCL_DMA_UART3_TX > SC_P_LVDS1_I2C1_SCL 1 > +#define SC_P_LVDS1_I2C1_SCL_LSIO_GPIO1_IO14 > SC_P_LVDS1_I2C1_SCL 3 > +#define SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA > SC_P_LVDS1_I2C1_SDA 0 > +#define SC_P_LVDS1_I2C1_SDA_DMA_UART3_RX > SC_P_LVDS1_I2C1_SDA 1 > +#define SC_P_LVDS1_I2C1_SDA_LSIO_GPIO1_IO15 > SC_P_LVDS1_I2C1_SDA 3 > +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL > SC_P_MIPI_DSI0_I2C0_SCL 0 > +#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO16 > SC_P_MIPI_DSI0_I2C0_SCL 3 > +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA > SC_P_MIPI_DSI0_I2C0_SDA 0 > +#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO17 > SC_P_MIPI_DSI0_I2C0_SDA 3 > +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 > SC_P_MIPI_DSI0_GPIO0_00 0 > +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT > SC_P_MIPI_DSI0_GPIO0_00 1 > +#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO18 > SC_P_MIPI_DSI0_GPIO0_00 3 > +#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 > SC_P_MIPI_DSI0_GPIO0_01 0 > +#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 > SC_P_MIPI_DSI0_GPIO0_01 3 > +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL > SC_P_MIPI_DSI1_I2C0_SCL 0 > +#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 > SC_P_MIPI_DSI1_I2C0_SCL 3 > +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA > SC_P_MIPI_DSI1_I2C0_SDA 0 > +#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 > SC_P_MIPI_DSI1_I2C0_SDA 3 > +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 > SC_P_MIPI_DSI1_GPIO0_00 0 > +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT > SC_P_MIPI_DSI1_GPIO0_00 1 > +#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 > SC_P_MIPI_DSI1_GPIO0_00 3 > +#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 > SC_P_MIPI_DSI1_GPIO0_01 0 > +#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 > SC_P_MIPI_DSI1_GPIO0_01 3 > +#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT > SC_P_MIPI_CSI0_MCLK_OUT 0 > +#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 > SC_P_MIPI_CSI0_MCLK_OUT 3 > +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL > SC_P_MIPI_CSI0_I2C0_SCL 0 > +#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO1_IO25 > SC_P_MIPI_CSI0_I2C0_SCL 3 > +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA > SC_P_MIPI_CSI0_I2C0_SDA 0 > +#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO1_IO26 > SC_P_MIPI_CSI0_I2C0_SDA 3 > +#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 > SC_P_MIPI_CSI0_GPIO0_00 0 > +#define SC_P_MIPI_CSI0_GPIO0_00_DMA_I2C0_SCL > SC_P_MIPI_CSI0_GPIO0_00 1 > +#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI1_I2C0_SCL > SC_P_MIPI_CSI0_GPIO0_00 2 > +#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 > SC_P_MIPI_CSI0_GPIO0_00 3 > +#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 > SC_P_MIPI_CSI0_GPIO0_01 0 > +#define SC_P_MIPI_CSI0_GPIO0_01_DMA_I2C0_SDA > SC_P_MIPI_CSI0_GPIO0_01 1 > +#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI1_I2C0_SDA > SC_P_MIPI_CSI0_GPIO0_01 2 > +#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 > SC_P_MIPI_CSI0_GPIO0_01 3 > +#define SC_P_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT > SC_P_MIPI_CSI1_MCLK_OUT 0 > +#define SC_P_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 > SC_P_MIPI_CSI1_MCLK_OUT 3 > +#define SC_P_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 > SC_P_MIPI_CSI1_GPIO0_00 0 > +#define SC_P_MIPI_CSI1_GPIO0_00_DMA_UART4_RX > SC_P_MIPI_CSI1_GPIO0_00 1 > +#define SC_P_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 > SC_P_MIPI_CSI1_GPIO0_00 3 > +#define SC_P_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 > SC_P_MIPI_CSI1_GPIO0_01 0 > +#define SC_P_MIPI_CSI1_GPIO0_01_DMA_UART4_TX > SC_P_MIPI_CSI1_GPIO0_01 1 > +#define SC_P_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 > SC_P_MIPI_CSI1_GPIO0_01 3 > +#define SC_P_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL > SC_P_MIPI_CSI1_I2C0_SCL 0 > +#define SC_P_MIPI_CSI1_I2C0_SCL_LSIO_GPIO2_IO00 > SC_P_MIPI_CSI1_I2C0_SCL 3 > +#define SC_P_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA > SC_P_MIPI_CSI1_I2C0_SDA 0 > +#define SC_P_MIPI_CSI1_I2C0_SDA_LSIO_GPIO2_IO01 > SC_P_MIPI_CSI1_I2C0_SDA 3 > +#define SC_P_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL > SC_P_HDMI_TX0_TS_SCL 0 > +#define SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL > SC_P_HDMI_TX0_TS_SCL 1 > +#define SC_P_HDMI_TX0_TS_SCL_LSIO_GPIO2_IO02 > SC_P_HDMI_TX0_TS_SCL 3 > +#define SC_P_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA > SC_P_HDMI_TX0_TS_SDA 0 > +#define SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA > SC_P_HDMI_TX0_TS_SDA 1 > +#define SC_P_HDMI_TX0_TS_SDA_LSIO_GPIO2_IO03 > SC_P_HDMI_TX0_TS_SDA 3 > +#define SC_P_ESAI1_FSR_AUD_ESAI1_FSR > SC_P_ESAI1_FSR 0 > +#define SC_P_ESAI1_FSR_LSIO_GPIO2_IO04 > SC_P_ESAI1_FSR 3 > +#define SC_P_ESAI1_FST_AUD_ESAI1_FST > SC_P_ESAI1_FST 0 > +#define SC_P_ESAI1_FST_AUD_SPDIF0_EXT_CLK > SC_P_ESAI1_FST 1 > +#define SC_P_ESAI1_FST_LSIO_GPIO2_IO05 > SC_P_ESAI1_FST 3 > +#define SC_P_ESAI1_SCKR_AUD_ESAI1_SCKR > SC_P_ESAI1_SCKR 0 > +#define SC_P_ESAI1_SCKR_LSIO_GPIO2_IO06 > SC_P_ESAI1_SCKR 3 > +#define SC_P_ESAI1_SCKT_AUD_ESAI1_SCKT > SC_P_ESAI1_SCKT 0 > +#define SC_P_ESAI1_SCKT_AUD_SAI2_RXC > SC_P_ESAI1_SCKT 1 > +#define SC_P_ESAI1_SCKT_AUD_SPDIF0_EXT_CLK > SC_P_ESAI1_SCKT 2 > +#define SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07 > SC_P_ESAI1_SCKT 3 > +#define SC_P_ESAI1_TX0_AUD_ESAI1_TX0 > SC_P_ESAI1_TX0 0 > +#define SC_P_ESAI1_TX0_AUD_SAI2_RXD > SC_P_ESAI1_TX0 1 > +#define SC_P_ESAI1_TX0_AUD_SPDIF0_RX > SC_P_ESAI1_TX0 2 > +#define SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 > SC_P_ESAI1_TX0 3 > +#define SC_P_ESAI1_TX1_AUD_ESAI1_TX1 > SC_P_ESAI1_TX1 0 > +#define SC_P_ESAI1_TX1_AUD_SAI2_RXFS > SC_P_ESAI1_TX1 1 > +#define SC_P_ESAI1_TX1_AUD_SPDIF0_TX > SC_P_ESAI1_TX1 2 > +#define SC_P_ESAI1_TX1_LSIO_GPIO2_IO09 > SC_P_ESAI1_TX1 3 > +#define SC_P_ESAI1_TX2_RX3_AUD_ESAI1_TX2_RX3 > SC_P_ESAI1_TX2_RX3 0 > +#define SC_P_ESAI1_TX2_RX3_AUD_SPDIF0_RX > SC_P_ESAI1_TX2_RX3 1 > +#define SC_P_ESAI1_TX2_RX3_LSIO_GPIO2_IO10 > SC_P_ESAI1_TX2_RX3 3 > +#define SC_P_ESAI1_TX3_RX2_AUD_ESAI1_TX3_RX2 > SC_P_ESAI1_TX3_RX2 0 > +#define SC_P_ESAI1_TX3_RX2_AUD_SPDIF0_TX > SC_P_ESAI1_TX3_RX2 1 > +#define SC_P_ESAI1_TX3_RX2_LSIO_GPIO2_IO11 > SC_P_ESAI1_TX3_RX2 3 > +#define SC_P_ESAI1_TX4_RX1_AUD_ESAI1_TX4_RX1 > SC_P_ESAI1_TX4_RX1 0 > +#define SC_P_ESAI1_TX4_RX1_LSIO_GPIO2_IO12 > SC_P_ESAI1_TX4_RX1 3 > +#define SC_P_ESAI1_TX5_RX0_AUD_ESAI1_TX5_RX0 > SC_P_ESAI1_TX5_RX0 0 > +#define SC_P_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 > SC_P_ESAI1_TX5_RX0 3 > +#define SC_P_SPDIF0_RX_AUD_SPDIF0_RX > SC_P_SPDIF0_RX 0 > +#define SC_P_SPDIF0_RX_AUD_MQS_R > SC_P_SPDIF0_RX 1 > +#define SC_P_SPDIF0_RX_AUD_ACM_MCLK_IN1 > SC_P_SPDIF0_RX 2 > +#define SC_P_SPDIF0_RX_LSIO_GPIO2_IO14 > SC_P_SPDIF0_RX 3 > +#define SC_P_SPDIF0_TX_AUD_SPDIF0_TX > SC_P_SPDIF0_TX 0 > +#define SC_P_SPDIF0_TX_AUD_MQS_L > SC_P_SPDIF0_TX 1 > +#define SC_P_SPDIF0_TX_AUD_ACM_MCLK_OUT1 > SC_P_SPDIF0_TX 2 > +#define SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 > SC_P_SPDIF0_TX 3 > +#define SC_P_SPDIF0_EXT_CLK_AUD_SPDIF0_EXT_CLK > SC_P_SPDIF0_EXT_CLK 0 > +#define SC_P_SPDIF0_EXT_CLK_DMA_DMA0_REQ_IN0 > SC_P_SPDIF0_EXT_CLK 1 > +#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16 > SC_P_SPDIF0_EXT_CLK 3 > +#define SC_P_SPI3_SCK_DMA_SPI3_SCK > SC_P_SPI3_SCK 0 > +#define SC_P_SPI3_SCK_LSIO_GPIO2_IO17 > SC_P_SPI3_SCK 3 > +#define SC_P_SPI3_SDO_DMA_SPI3_SDO > SC_P_SPI3_SDO 0 > +#define SC_P_SPI3_SDO_DMA_FTM_CH0 > SC_P_SPI3_SDO 1 > +#define SC_P_SPI3_SDO_LSIO_GPIO2_IO18 > SC_P_SPI3_SDO 3 > +#define SC_P_SPI3_SDI_DMA_SPI3_SDI > SC_P_SPI3_SDI 0 > +#define SC_P_SPI3_SDI_DMA_FTM_CH1 > SC_P_SPI3_SDI 1 > +#define SC_P_SPI3_SDI_LSIO_GPIO2_IO19 > SC_P_SPI3_SDI 3 > +#define SC_P_SPI3_CS0_DMA_SPI3_CS0 > SC_P_SPI3_CS0 0 > +#define SC_P_SPI3_CS0_DMA_FTM_CH2 > SC_P_SPI3_CS0 1 > +#define SC_P_SPI3_CS0_LSIO_GPIO2_IO20 > SC_P_SPI3_CS0 3 > +#define SC_P_SPI3_CS1_DMA_SPI3_CS1 > SC_P_SPI3_CS1 0 > +#define SC_P_SPI3_CS1_LSIO_GPIO2_IO21 > SC_P_SPI3_CS1 3 > +#define SC_P_ESAI0_FSR_AUD_ESAI0_FSR > SC_P_ESAI0_FSR 0 > +#define SC_P_ESAI0_FSR_LSIO_GPIO2_IO22 > SC_P_ESAI0_FSR 3 > +#define SC_P_ESAI0_FST_AUD_ESAI0_FST > SC_P_ESAI0_FST 0 > +#define SC_P_ESAI0_FST_LSIO_GPIO2_IO23 > SC_P_ESAI0_FST 3 > +#define SC_P_ESAI0_SCKR_AUD_ESAI0_SCKR > SC_P_ESAI0_SCKR 0 > +#define SC_P_ESAI0_SCKR_LSIO_GPIO2_IO24 > SC_P_ESAI0_SCKR 3 > +#define SC_P_ESAI0_SCKT_AUD_ESAI0_SCKT > SC_P_ESAI0_SCKT 0 > +#define SC_P_ESAI0_SCKT_LSIO_GPIO2_IO25 > SC_P_ESAI0_SCKT 3 > +#define SC_P_ESAI0_TX0_AUD_ESAI0_TX0 > SC_P_ESAI0_TX0 0 > +#define SC_P_ESAI0_TX0_LSIO_GPIO2_IO26 > SC_P_ESAI0_TX0 3 > +#define SC_P_ESAI0_TX1_AUD_ESAI0_TX1 > SC_P_ESAI0_TX1 0 > +#define SC_P_ESAI0_TX1_LSIO_GPIO2_IO27 > SC_P_ESAI0_TX1 3 > +#define SC_P_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 > SC_P_ESAI0_TX2_RX3 0 > +#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 > SC_P_ESAI0_TX2_RX3 3 > +#define SC_P_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 > SC_P_ESAI0_TX3_RX2 0 > +#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 > SC_P_ESAI0_TX3_RX2 3 > +#define SC_P_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 > SC_P_ESAI0_TX4_RX1 0 > +#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 > SC_P_ESAI0_TX4_RX1 3 > +#define SC_P_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 > SC_P_ESAI0_TX5_RX0 0 > +#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 > SC_P_ESAI0_TX5_RX0 3 > +#define SC_P_MCLK_IN0_AUD_ACM_MCLK_IN0 > SC_P_MCLK_IN0 0 > +#define SC_P_MCLK_IN0_AUD_ESAI0_RX_HF_CLK > SC_P_MCLK_IN0 1 > +#define SC_P_MCLK_IN0_AUD_ESAI1_RX_HF_CLK > SC_P_MCLK_IN0 2 > +#define SC_P_MCLK_IN0_LSIO_GPIO3_IO00 > SC_P_MCLK_IN0 3 > +#define SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 > SC_P_MCLK_OUT0 0 > +#define SC_P_MCLK_OUT0_AUD_ESAI0_TX_HF_CLK > SC_P_MCLK_OUT0 1 > +#define SC_P_MCLK_OUT0_AUD_ESAI1_TX_HF_CLK > SC_P_MCLK_OUT0 2 > +#define SC_P_MCLK_OUT0_LSIO_GPIO3_IO01 > SC_P_MCLK_OUT0 3 > +#define SC_P_SPI0_SCK_DMA_SPI0_SCK > SC_P_SPI0_SCK 0 > +#define SC_P_SPI0_SCK_AUD_SAI0_RXC > SC_P_SPI0_SCK 1 > +#define SC_P_SPI0_SCK_LSIO_GPIO3_IO02 > SC_P_SPI0_SCK 3 > +#define SC_P_SPI0_SDO_DMA_SPI0_SDO > SC_P_SPI0_SDO 0 > +#define SC_P_SPI0_SDO_AUD_SAI0_TXD > SC_P_SPI0_SDO 1 > +#define SC_P_SPI0_SDO_LSIO_GPIO3_IO03 > SC_P_SPI0_SDO 3 > +#define SC_P_SPI0_SDI_DMA_SPI0_SDI > SC_P_SPI0_SDI 0 > +#define SC_P_SPI0_SDI_AUD_SAI0_RXD > SC_P_SPI0_SDI 1 > +#define SC_P_SPI0_SDI_LSIO_GPIO3_IO04 > SC_P_SPI0_SDI 3 > +#define SC_P_SPI0_CS0_DMA_SPI0_CS0 > SC_P_SPI0_CS0 0 > +#define SC_P_SPI0_CS0_AUD_SAI0_RXFS > SC_P_SPI0_CS0 1 > +#define SC_P_SPI0_CS0_LSIO_GPIO3_IO05 > SC_P_SPI0_CS0 3 > +#define SC_P_SPI0_CS1_DMA_SPI0_CS1 > SC_P_SPI0_CS1 0 > +#define SC_P_SPI0_CS1_AUD_SAI0_TXC > SC_P_SPI0_CS1 1 > +#define SC_P_SPI0_CS1_LSIO_GPIO3_IO06 > SC_P_SPI0_CS1 3 > +#define SC_P_SPI2_SCK_DMA_SPI2_SCK > SC_P_SPI2_SCK 0 > +#define SC_P_SPI2_SCK_LSIO_GPIO3_IO07 > SC_P_SPI2_SCK 3 > +#define SC_P_SPI2_SDO_DMA_SPI2_SDO > SC_P_SPI2_SDO 0 > +#define SC_P_SPI2_SDO_LSIO_GPIO3_IO08 > SC_P_SPI2_SDO 3 > +#define SC_P_SPI2_SDI_DMA_SPI2_SDI > SC_P_SPI2_SDI 0 > +#define SC_P_SPI2_SDI_LSIO_GPIO3_IO09 > SC_P_SPI2_SDI 3 > +#define SC_P_SPI2_CS0_DMA_SPI2_CS0 > SC_P_SPI2_CS0 0 > +#define SC_P_SPI2_CS0_LSIO_GPIO3_IO10 > SC_P_SPI2_CS0 3 > +#define SC_P_SPI2_CS1_DMA_SPI2_CS1 > SC_P_SPI2_CS1 0 > +#define SC_P_SPI2_CS1_AUD_SAI0_TXFS > SC_P_SPI2_CS1 1 > +#define SC_P_SPI2_CS1_LSIO_GPIO3_IO11 > SC_P_SPI2_CS1 3 > +#define SC_P_SAI1_RXC_AUD_SAI1_RXC > SC_P_SAI1_RXC 0 > +#define SC_P_SAI1_RXC_AUD_SAI0_TXD > SC_P_SAI1_RXC 1 > +#define SC_P_SAI1_RXC_LSIO_GPIO3_IO12 > SC_P_SAI1_RXC 3 > +#define SC_P_SAI1_RXD_AUD_SAI1_RXD > SC_P_SAI1_RXD 0 > +#define SC_P_SAI1_RXD_AUD_SAI0_TXFS > SC_P_SAI1_RXD 1 > +#define SC_P_SAI1_RXD_LSIO_GPIO3_IO13 > SC_P_SAI1_RXD 3 > +#define SC_P_SAI1_RXFS_AUD_SAI1_RXFS > SC_P_SAI1_RXFS 0 > +#define SC_P_SAI1_RXFS_AUD_SAI0_RXD > SC_P_SAI1_RXFS 1 > +#define SC_P_SAI1_RXFS_LSIO_GPIO3_IO14 > SC_P_SAI1_RXFS 3 > +#define SC_P_SAI1_TXC_AUD_SAI1_TXC > SC_P_SAI1_TXC 0 > +#define SC_P_SAI1_TXC_AUD_SAI0_TXC > SC_P_SAI1_TXC 1 > +#define SC_P_SAI1_TXC_LSIO_GPIO3_IO15 > SC_P_SAI1_TXC 3 > +#define SC_P_SAI1_TXD_AUD_SAI1_TXD > SC_P_SAI1_TXD 0 > +#define SC_P_SAI1_TXD_AUD_SAI1_RXC > SC_P_SAI1_TXD 1 > +#define SC_P_SAI1_TXD_LSIO_GPIO3_IO16 > SC_P_SAI1_TXD 3 > +#define SC_P_SAI1_TXFS_AUD_SAI1_TXFS > SC_P_SAI1_TXFS 0 > +#define SC_P_SAI1_TXFS_AUD_SAI1_RXFS > SC_P_SAI1_TXFS 1 > +#define SC_P_SAI1_TXFS_LSIO_GPIO3_IO17 > SC_P_SAI1_TXFS 3 > +#define SC_P_ADC_IN7_DMA_ADC1_IN3 > SC_P_ADC_IN7 0 > +#define SC_P_ADC_IN7_DMA_SPI1_CS1 > SC_P_ADC_IN7 1 > +#define SC_P_ADC_IN7_LSIO_KPP0_ROW3 > SC_P_ADC_IN7 2 > +#define SC_P_ADC_IN7_LSIO_GPIO3_IO25 > SC_P_ADC_IN7 3 > +#define SC_P_ADC_IN6_DMA_ADC1_IN2 > SC_P_ADC_IN6 0 > +#define SC_P_ADC_IN6_DMA_SPI1_CS0 > SC_P_ADC_IN6 1 > +#define SC_P_ADC_IN6_LSIO_KPP0_ROW2 > SC_P_ADC_IN6 2 > +#define SC_P_ADC_IN6_LSIO_GPIO3_IO24 > SC_P_ADC_IN6 3 > +#define SC_P_ADC_IN5_DMA_ADC1_IN1 > SC_P_ADC_IN5 0 > +#define SC_P_ADC_IN5_DMA_SPI1_SDI > SC_P_ADC_IN5 1 > +#define SC_P_ADC_IN5_LSIO_KPP0_ROW1 > SC_P_ADC_IN5 2 > +#define SC_P_ADC_IN5_LSIO_GPIO3_IO23 > SC_P_ADC_IN5 3 > +#define SC_P_ADC_IN4_DMA_ADC1_IN0 > SC_P_ADC_IN4 0 > +#define SC_P_ADC_IN4_DMA_SPI1_SDO > SC_P_ADC_IN4 1 > +#define SC_P_ADC_IN4_LSIO_KPP0_ROW0 > SC_P_ADC_IN4 2 > +#define SC_P_ADC_IN4_LSIO_GPIO3_IO22 > SC_P_ADC_IN4 3 > +#define SC_P_ADC_IN3_DMA_ADC0_IN3 > SC_P_ADC_IN3 0 > +#define SC_P_ADC_IN3_DMA_SPI1_SCK > SC_P_ADC_IN3 1 > +#define SC_P_ADC_IN3_LSIO_KPP0_COL3 > SC_P_ADC_IN3 2 > +#define SC_P_ADC_IN3_LSIO_GPIO3_IO21 > SC_P_ADC_IN3 3 > +#define SC_P_ADC_IN2_DMA_ADC0_IN2 > SC_P_ADC_IN2 0 > +#define SC_P_ADC_IN2_LSIO_KPP0_COL2 > SC_P_ADC_IN2 2 > +#define SC_P_ADC_IN2_LSIO_GPIO3_IO20 > SC_P_ADC_IN2 3 > +#define SC_P_ADC_IN1_DMA_ADC0_IN1 > SC_P_ADC_IN1 0 > +#define SC_P_ADC_IN1_LSIO_KPP0_COL1 > SC_P_ADC_IN1 2 > +#define SC_P_ADC_IN1_LSIO_GPIO3_IO19 > SC_P_ADC_IN1 3 > +#define SC_P_ADC_IN0_DMA_ADC0_IN0 > SC_P_ADC_IN0 0 > +#define SC_P_ADC_IN0_LSIO_KPP0_COL0 > SC_P_ADC_IN0 2 > +#define SC_P_ADC_IN0_LSIO_GPIO3_IO18 > SC_P_ADC_IN0 3 > +#define SC_P_MLB_SIG_CONN_MLB_SIG > SC_P_MLB_SIG 0 > +#define SC_P_MLB_SIG_AUD_SAI3_RXC > SC_P_MLB_SIG 1 > +#define SC_P_MLB_SIG_LSIO_GPIO3_IO26 > SC_P_MLB_SIG 3 > +#define SC_P_MLB_CLK_CONN_MLB_CLK > SC_P_MLB_CLK 0 > +#define SC_P_MLB_CLK_AUD_SAI3_RXFS > SC_P_MLB_CLK 1 > +#define SC_P_MLB_CLK_LSIO_GPIO3_IO27 > SC_P_MLB_CLK 3 > +#define SC_P_MLB_DATA_CONN_MLB_DATA > SC_P_MLB_DATA 0 > +#define SC_P_MLB_DATA_AUD_SAI3_RXD > SC_P_MLB_DATA 1 > +#define SC_P_MLB_DATA_LSIO_GPIO3_IO28 > SC_P_MLB_DATA 3 > +#define SC_P_FLEXCAN0_RX_DMA_FLEXCAN0_RX > SC_P_FLEXCAN0_RX 0 > +#define SC_P_FLEXCAN0_RX_LSIO_GPIO3_IO29 > SC_P_FLEXCAN0_RX 3 > +#define SC_P_FLEXCAN0_TX_DMA_FLEXCAN0_TX > SC_P_FLEXCAN0_TX 0 > +#define SC_P_FLEXCAN0_TX_LSIO_GPIO3_IO30 > SC_P_FLEXCAN0_TX 3 > +#define SC_P_FLEXCAN1_RX_DMA_FLEXCAN1_RX > SC_P_FLEXCAN1_RX 0 > +#define SC_P_FLEXCAN1_RX_LSIO_GPIO3_IO31 > SC_P_FLEXCAN1_RX 3 > +#define SC_P_FLEXCAN1_TX_DMA_FLEXCAN1_TX > SC_P_FLEXCAN1_TX 0 > +#define SC_P_FLEXCAN1_TX_LSIO_GPIO4_IO00 > SC_P_FLEXCAN1_TX 3 > +#define SC_P_FLEXCAN2_RX_DMA_FLEXCAN2_RX > SC_P_FLEXCAN2_RX 0 > +#define SC_P_FLEXCAN2_RX_LSIO_GPIO4_IO01 > SC_P_FLEXCAN2_RX 3 > +#define SC_P_FLEXCAN2_TX_DMA_FLEXCAN2_TX > SC_P_FLEXCAN2_TX 0 > +#define SC_P_FLEXCAN2_TX_LSIO_GPIO4_IO02 > SC_P_FLEXCAN2_TX 3 > +#define SC_P_USB_SS3_TC0_DMA_I2C1_SCL > SC_P_USB_SS3_TC0 0 > +#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR > SC_P_USB_SS3_TC0 1 > +#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 > SC_P_USB_SS3_TC0 3 > +#define SC_P_USB_SS3_TC1_DMA_I2C1_SCL > SC_P_USB_SS3_TC1 0 > +#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR > SC_P_USB_SS3_TC1 1 > +#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 > SC_P_USB_SS3_TC1 3 > +#define SC_P_USB_SS3_TC2_DMA_I2C1_SDA > SC_P_USB_SS3_TC2 0 > +#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC > SC_P_USB_SS3_TC2 1 > +#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 > SC_P_USB_SS3_TC2 3 > +#define SC_P_USB_SS3_TC3_DMA_I2C1_SDA > SC_P_USB_SS3_TC3 0 > +#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC > SC_P_USB_SS3_TC3 1 > +#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 > SC_P_USB_SS3_TC3 3 > +#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B > SC_P_USDHC1_RESET_B 0 > +#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 > SC_P_USDHC1_RESET_B 3 > +#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT > SC_P_USDHC1_VSELECT 0 > +#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO08 > SC_P_USDHC1_VSELECT 3 > +#define SC_P_USDHC2_RESET_B_CONN_USDHC2_RESET_B > SC_P_USDHC2_RESET_B 0 > +#define SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 > SC_P_USDHC2_RESET_B 3 > +#define SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT > SC_P_USDHC2_VSELECT 0 > +#define SC_P_USDHC2_VSELECT_LSIO_GPIO4_IO10 > SC_P_USDHC2_VSELECT 3 > +#define SC_P_USDHC2_WP_CONN_USDHC2_WP > SC_P_USDHC2_WP 0 > +#define SC_P_USDHC2_WP_LSIO_GPIO4_IO11 > SC_P_USDHC2_WP 3 > +#define SC_P_USDHC2_CD_B_CONN_USDHC2_CD_B > SC_P_USDHC2_CD_B 0 > +#define SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 > SC_P_USDHC2_CD_B 3 > +#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO > SC_P_ENET0_MDIO 0 > +#define SC_P_ENET0_MDIO_DMA_I2C4_SDA > SC_P_ENET0_MDIO 1 > +#define SC_P_ENET0_MDIO_LSIO_GPIO4_IO13 > SC_P_ENET0_MDIO 3 > +#define SC_P_ENET0_MDC_CONN_ENET0_MDC > SC_P_ENET0_MDC 0 > +#define SC_P_ENET0_MDC_DMA_I2C4_SCL > SC_P_ENET0_MDC 1 > +#define SC_P_ENET0_MDC_LSIO_GPIO4_IO14 > SC_P_ENET0_MDC 3 > +#define > SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M > SC_P_ENET0_REFCLK_125M_25M 0 > +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS > SC_P_ENET0_REFCLK_125M_25M 1 > +#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 > SC_P_ENET0_REFCLK_125M_25M 3 > +#define > SC_P_ENET1_REFCLK_125M_25M_CONN_ENET1_REFCLK_125M_25M > SC_P_ENET1_REFCLK_125M_25M 0 > +#define SC_P_ENET1_REFCLK_125M_25M_CONN_ENET1_PPS > SC_P_ENET1_REFCLK_125M_25M 1 > +#define SC_P_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 > SC_P_ENET1_REFCLK_125M_25M 3 > +#define SC_P_ENET1_MDIO_CONN_ENET1_MDIO > SC_P_ENET1_MDIO 0 > +#define SC_P_ENET1_MDIO_DMA_I2C4_SDA > SC_P_ENET1_MDIO 1 > +#define SC_P_ENET1_MDIO_LSIO_GPIO4_IO17 > SC_P_ENET1_MDIO 3 > +#define SC_P_ENET1_MDC_CONN_ENET1_MDC > SC_P_ENET1_MDC 0 > +#define SC_P_ENET1_MDC_DMA_I2C4_SCL > SC_P_ENET1_MDC 1 > +#define SC_P_ENET1_MDC_LSIO_GPIO4_IO18 > SC_P_ENET1_MDC 3 > +#define SC_P_QSPI1A_SS0_B_LSIO_QSPI1A_SS0_B > SC_P_QSPI1A_SS0_B 0 > +#define SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 > SC_P_QSPI1A_SS0_B 3 > +#define SC_P_QSPI1A_SS1_B_LSIO_QSPI1A_SS1_B > SC_P_QSPI1A_SS1_B 0 > +#define SC_P_QSPI1A_SS1_B_LSIO_QSPI1A_SCLK2 > SC_P_QSPI1A_SS1_B 1 > +#define SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20 > SC_P_QSPI1A_SS1_B 3 > +#define SC_P_QSPI1A_SCLK_LSIO_QSPI1A_SCLK > SC_P_QSPI1A_SCLK 0 > +#define SC_P_QSPI1A_SCLK_LSIO_GPIO4_IO21 > SC_P_QSPI1A_SCLK 3 > +#define SC_P_QSPI1A_DQS_LSIO_QSPI1A_DQS > SC_P_QSPI1A_DQS 0 > +#define SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22 > SC_P_QSPI1A_DQS 3 > +#define SC_P_QSPI1A_DATA3_LSIO_QSPI1A_DATA3 > SC_P_QSPI1A_DATA3 0 > +#define SC_P_QSPI1A_DATA3_DMA_I2C1_SDA > SC_P_QSPI1A_DATA3 1 > +#define SC_P_QSPI1A_DATA3_CONN_USB_OTG1_OC > SC_P_QSPI1A_DATA3 2 > +#define SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23 > SC_P_QSPI1A_DATA3 3 > +#define SC_P_QSPI1A_DATA2_LSIO_QSPI1A_DATA2 > SC_P_QSPI1A_DATA2 0 > +#define SC_P_QSPI1A_DATA2_DMA_I2C1_SCL > SC_P_QSPI1A_DATA2 1 > +#define SC_P_QSPI1A_DATA2_CONN_USB_OTG2_PWR > SC_P_QSPI1A_DATA2 2 > +#define SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24 > SC_P_QSPI1A_DATA2 3 > +#define SC_P_QSPI1A_DATA1_LSIO_QSPI1A_DATA1 > SC_P_QSPI1A_DATA1 0 > +#define SC_P_QSPI1A_DATA1_DMA_I2C1_SDA > SC_P_QSPI1A_DATA1 1 > +#define SC_P_QSPI1A_DATA1_CONN_USB_OTG2_OC > SC_P_QSPI1A_DATA1 2 > +#define SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 > SC_P_QSPI1A_DATA1 3 > +#define SC_P_QSPI1A_DATA0_LSIO_QSPI1A_DATA0 > SC_P_QSPI1A_DATA0 0 > +#define SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 > SC_P_QSPI1A_DATA0 3 > +#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 > SC_P_QSPI0A_DATA0 0 > +#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 > SC_P_QSPI0A_DATA1 0 > +#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 > SC_P_QSPI0A_DATA2 0 > +#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 > SC_P_QSPI0A_DATA3 0 > +#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS > SC_P_QSPI0A_DQS 0 > +#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B > SC_P_QSPI0A_SS0_B 0 > +#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B > SC_P_QSPI0A_SS1_B 0 > +#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SCLK2 > SC_P_QSPI0A_SS1_B 1 > +#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK > SC_P_QSPI0A_SCLK 0 > +#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK > SC_P_QSPI0B_SCLK 0 > +#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 > SC_P_QSPI0B_DATA0 0 > +#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 > SC_P_QSPI0B_DATA1 0 > +#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 > SC_P_QSPI0B_DATA2 0 > +#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 > SC_P_QSPI0B_DATA3 0 > +#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS > SC_P_QSPI0B_DQS 0 > +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B > SC_P_QSPI0B_SS0_B 0 > +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B > SC_P_QSPI0B_SS1_B 0 > +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SCLK2 > SC_P_QSPI0B_SS1_B 1 > +#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B > SC_P_PCIE_CTRL0_CLKREQ_B 0 > +#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 > SC_P_PCIE_CTRL0_CLKREQ_B 3 > +#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B > SC_P_PCIE_CTRL0_WAKE_B 0 > +#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 > SC_P_PCIE_CTRL0_WAKE_B 3 > +#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B > SC_P_PCIE_CTRL0_PERST_B 0 > +#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 > SC_P_PCIE_CTRL0_PERST_B 3 > +#define SC_P_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B > SC_P_PCIE_CTRL1_CLKREQ_B 0 > +#define SC_P_PCIE_CTRL1_CLKREQ_B_DMA_I2C1_SDA > SC_P_PCIE_CTRL1_CLKREQ_B 1 > +#define SC_P_PCIE_CTRL1_CLKREQ_B_CONN_USB_OTG2_OC > SC_P_PCIE_CTRL1_CLKREQ_B 2 > +#define SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 > SC_P_PCIE_CTRL1_CLKREQ_B 3 > +#define SC_P_PCIE_CTRL1_WAKE_B_HSIO_PCIE1_WAKE_B > SC_P_PCIE_CTRL1_WAKE_B 0 > +#define SC_P_PCIE_CTRL1_WAKE_B_DMA_I2C1_SCL > SC_P_PCIE_CTRL1_WAKE_B 1 > +#define SC_P_PCIE_CTRL1_WAKE_B_CONN_USB_OTG2_PWR > SC_P_PCIE_CTRL1_WAKE_B 2 > +#define SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 > SC_P_PCIE_CTRL1_WAKE_B 3 > +#define SC_P_PCIE_CTRL1_PERST_B_HSIO_PCIE1_PERST_B > SC_P_PCIE_CTRL1_PERST_B 0 > +#define SC_P_PCIE_CTRL1_PERST_B_DMA_I2C1_SCL > SC_P_PCIE_CTRL1_PERST_B 1 > +#define SC_P_PCIE_CTRL1_PERST_B_CONN_USB_OTG1_PWR > SC_P_PCIE_CTRL1_PERST_B 2 > +#define SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 > SC_P_PCIE_CTRL1_PERST_B 3 > +#define SC_P_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA > SC_P_USB_HSIC0_DATA 0 > +#define SC_P_USB_HSIC0_DATA_DMA_I2C1_SDA > SC_P_USB_HSIC0_DATA 1 > +#define SC_P_USB_HSIC0_DATA_LSIO_GPIO5_IO01 > SC_P_USB_HSIC0_DATA 3 > +#define SC_P_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE > SC_P_USB_HSIC0_STROBE 0 > +#define SC_P_USB_HSIC0_STROBE_DMA_I2C1_SCL > SC_P_USB_HSIC0_STROBE 1 > +#define SC_P_USB_HSIC0_STROBE_LSIO_GPIO5_IO02 > SC_P_USB_HSIC0_STROBE 3 > +#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK > SC_P_EMMC0_CLK 0 > +#define SC_P_EMMC0_CLK_CONN_NAND_READY_B > SC_P_EMMC0_CLK 1 > +#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD > SC_P_EMMC0_CMD 0 > +#define SC_P_EMMC0_CMD_CONN_NAND_DQS > SC_P_EMMC0_CMD 1 > +#define SC_P_EMMC0_CMD_AUD_MQS_R > SC_P_EMMC0_CMD 2 > +#define SC_P_EMMC0_CMD_LSIO_GPIO5_IO03 > SC_P_EMMC0_CMD 3 > +#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 > SC_P_EMMC0_DATA0 0 > +#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00 > SC_P_EMMC0_DATA0 1 > +#define SC_P_EMMC0_DATA0_LSIO_GPIO5_IO04 > SC_P_EMMC0_DATA0 3 > +#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 > SC_P_EMMC0_DATA1 0 > +#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01 > SC_P_EMMC0_DATA1 1 > +#define SC_P_EMMC0_DATA1_LSIO_GPIO5_IO05 > SC_P_EMMC0_DATA1 3 > +#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 > SC_P_EMMC0_DATA2 0 > +#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02 > SC_P_EMMC0_DATA2 1 > +#define SC_P_EMMC0_DATA2_LSIO_GPIO5_IO06 > SC_P_EMMC0_DATA2 3 > +#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 > SC_P_EMMC0_DATA3 0 > +#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03 > SC_P_EMMC0_DATA3 1 > +#define SC_P_EMMC0_DATA3_LSIO_GPIO5_IO07 > SC_P_EMMC0_DATA3 3 > +#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 > SC_P_EMMC0_DATA4 0 > +#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04 > SC_P_EMMC0_DATA4 1 > +#define SC_P_EMMC0_DATA4_LSIO_GPIO5_IO08 > SC_P_EMMC0_DATA4 3 > +#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 > SC_P_EMMC0_DATA5 0 > +#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05 > SC_P_EMMC0_DATA5 1 > +#define SC_P_EMMC0_DATA5_LSIO_GPIO5_IO09 > SC_P_EMMC0_DATA5 3 > +#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 > SC_P_EMMC0_DATA6 0 > +#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06 > SC_P_EMMC0_DATA6 1 > +#define SC_P_EMMC0_DATA6_LSIO_GPIO5_IO10 > SC_P_EMMC0_DATA6 3 > +#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 > SC_P_EMMC0_DATA7 0 > +#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07 > SC_P_EMMC0_DATA7 1 > +#define SC_P_EMMC0_DATA7_LSIO_GPIO5_IO11 > SC_P_EMMC0_DATA7 3 > +#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE > SC_P_EMMC0_STROBE 0 > +#define SC_P_EMMC0_STROBE_CONN_NAND_CLE > SC_P_EMMC0_STROBE 1 > +#define SC_P_EMMC0_STROBE_LSIO_GPIO5_IO12 > SC_P_EMMC0_STROBE 3 > +#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B > SC_P_EMMC0_RESET_B 0 > +#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B > SC_P_EMMC0_RESET_B 1 > +#define SC_P_EMMC0_RESET_B_CONN_USDHC1_VSELECT > SC_P_EMMC0_RESET_B 2 > +#define SC_P_EMMC0_RESET_B_LSIO_GPIO5_IO13 > SC_P_EMMC0_RESET_B 3 > +#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK > SC_P_USDHC1_CLK 0 > +#define SC_P_USDHC1_CLK_AUD_MQS_R > SC_P_USDHC1_CLK 1 > +#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD > SC_P_USDHC1_CMD 0 > +#define SC_P_USDHC1_CMD_AUD_MQS_L > SC_P_USDHC1_CMD 1 > +#define SC_P_USDHC1_CMD_LSIO_GPIO5_IO14 > SC_P_USDHC1_CMD 3 > +#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 > SC_P_USDHC1_DATA0 0 > +#define SC_P_USDHC1_DATA0_CONN_NAND_RE_N > SC_P_USDHC1_DATA0 1 > +#define SC_P_USDHC1_DATA0_LSIO_GPIO5_IO15 > SC_P_USDHC1_DATA0 3 > +#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 > SC_P_USDHC1_DATA1 0 > +#define SC_P_USDHC1_DATA1_CONN_NAND_RE_P > SC_P_USDHC1_DATA1 1 > +#define SC_P_USDHC1_DATA1_LSIO_GPIO5_IO16 > SC_P_USDHC1_DATA1 3 > +#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 > SC_P_USDHC1_DATA2 0 > +#define SC_P_USDHC1_DATA2_CONN_NAND_DQS_N > SC_P_USDHC1_DATA2 1 > +#define SC_P_USDHC1_DATA2_LSIO_GPIO5_IO17 > SC_P_USDHC1_DATA2 3 > +#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 > SC_P_USDHC1_DATA3 0 > +#define SC_P_USDHC1_DATA3_CONN_NAND_DQS_P > SC_P_USDHC1_DATA3 1 > +#define SC_P_USDHC1_DATA3_LSIO_GPIO5_IO18 > SC_P_USDHC1_DATA3 3 > +#define SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4 > SC_P_USDHC1_DATA4 0 > +#define SC_P_USDHC1_DATA4_CONN_NAND_CE0_B > SC_P_USDHC1_DATA4 1 > +#define SC_P_USDHC1_DATA4_AUD_MQS_R > SC_P_USDHC1_DATA4 2 > +#define SC_P_USDHC1_DATA4_LSIO_GPIO5_IO19 > SC_P_USDHC1_DATA4 3 > +#define SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5 > SC_P_USDHC1_DATA5 0 > +#define SC_P_USDHC1_DATA5_CONN_NAND_RE_B > SC_P_USDHC1_DATA5 1 > +#define SC_P_USDHC1_DATA5_AUD_MQS_L > SC_P_USDHC1_DATA5 2 > +#define SC_P_USDHC1_DATA5_LSIO_GPIO5_IO20 > SC_P_USDHC1_DATA5 3 > +#define SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6 > SC_P_USDHC1_DATA6 0 > +#define SC_P_USDHC1_DATA6_CONN_NAND_WE_B > SC_P_USDHC1_DATA6 1 > +#define SC_P_USDHC1_DATA6_CONN_USDHC1_WP > SC_P_USDHC1_DATA6 2 > +#define SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 > SC_P_USDHC1_DATA6 3 > +#define SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7 > SC_P_USDHC1_DATA7 0 > +#define SC_P_USDHC1_DATA7_CONN_NAND_ALE > SC_P_USDHC1_DATA7 1 > +#define SC_P_USDHC1_DATA7_CONN_USDHC1_CD_B > SC_P_USDHC1_DATA7 2 > +#define SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 > SC_P_USDHC1_DATA7 3 > +#define SC_P_USDHC1_STROBE_CONN_USDHC1_STROBE > SC_P_USDHC1_STROBE 0 > +#define SC_P_USDHC1_STROBE_CONN_NAND_CE1_B > SC_P_USDHC1_STROBE 1 > +#define SC_P_USDHC1_STROBE_CONN_USDHC1_RESET_B > SC_P_USDHC1_STROBE 2 > +#define SC_P_USDHC1_STROBE_LSIO_GPIO5_IO23 > SC_P_USDHC1_STROBE 3 > +#define SC_P_USDHC2_CLK_CONN_USDHC2_CLK > SC_P_USDHC2_CLK 0 > +#define SC_P_USDHC2_CLK_AUD_MQS_R > SC_P_USDHC2_CLK 1 > +#define SC_P_USDHC2_CLK_LSIO_GPIO5_IO24 > SC_P_USDHC2_CLK 3 > +#define SC_P_USDHC2_CMD_CONN_USDHC2_CMD > SC_P_USDHC2_CMD 0 > +#define SC_P_USDHC2_CMD_AUD_MQS_L > SC_P_USDHC2_CMD 1 > +#define SC_P_USDHC2_CMD_LSIO_GPIO5_IO25 > SC_P_USDHC2_CMD 3 > +#define SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 > SC_P_USDHC2_DATA0 0 > +#define SC_P_USDHC2_DATA0_DMA_UART4_RX > SC_P_USDHC2_DATA0 1 > +#define SC_P_USDHC2_DATA0_LSIO_GPIO5_IO26 > SC_P_USDHC2_DATA0 3 > +#define SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 > SC_P_USDHC2_DATA1 0 > +#define SC_P_USDHC2_DATA1_DMA_UART4_TX > SC_P_USDHC2_DATA1 1 > +#define SC_P_USDHC2_DATA1_LSIO_GPIO5_IO27 > SC_P_USDHC2_DATA1 3 > +#define SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 > SC_P_USDHC2_DATA2 0 > +#define SC_P_USDHC2_DATA2_DMA_UART4_CTS_B > SC_P_USDHC2_DATA2 1 > +#define SC_P_USDHC2_DATA2_LSIO_GPIO5_IO28 > SC_P_USDHC2_DATA2 3 > +#define SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 > SC_P_USDHC2_DATA3 0 > +#define SC_P_USDHC2_DATA3_DMA_UART4_RTS_B > SC_P_USDHC2_DATA3 1 > +#define SC_P_USDHC2_DATA3_LSIO_GPIO5_IO29 > SC_P_USDHC2_DATA3 3 > +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC > SC_P_ENET0_RGMII_TXC 0 > +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT > SC_P_ENET0_RGMII_TXC 1 > +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN > SC_P_ENET0_RGMII_TXC 2 > +#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 > SC_P_ENET0_RGMII_TXC 3 > +#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL > SC_P_ENET0_RGMII_TX_CTL 0 > +#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 > SC_P_ENET0_RGMII_TX_CTL 3 > +#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 > SC_P_ENET0_RGMII_TXD0 0 > +#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 > SC_P_ENET0_RGMII_TXD0 3 > +#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 > SC_P_ENET0_RGMII_TXD1 0 > +#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 > SC_P_ENET0_RGMII_TXD1 3 > +#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 > SC_P_ENET0_RGMII_TXD2 0 > +#define SC_P_ENET0_RGMII_TXD2_DMA_UART3_TX > SC_P_ENET0_RGMII_TXD2 1 > +#define SC_P_ENET0_RGMII_TXD2_VPU_TSI_S1_VID > SC_P_ENET0_RGMII_TXD2 2 > +#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 > SC_P_ENET0_RGMII_TXD2 3 > +#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 > SC_P_ENET0_RGMII_TXD3 0 > +#define SC_P_ENET0_RGMII_TXD3_DMA_UART3_RTS_B > SC_P_ENET0_RGMII_TXD3 1 > +#define SC_P_ENET0_RGMII_TXD3_VPU_TSI_S1_SYNC > SC_P_ENET0_RGMII_TXD3 2 > +#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 > SC_P_ENET0_RGMII_TXD3 3 > +#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC > SC_P_ENET0_RGMII_RXC 0 > +#define SC_P_ENET0_RGMII_RXC_DMA_UART3_CTS_B > SC_P_ENET0_RGMII_RXC 1 > +#define SC_P_ENET0_RGMII_RXC_VPU_TSI_S1_DATA > SC_P_ENET0_RGMII_RXC 2 > +#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 > SC_P_ENET0_RGMII_RXC 3 > +#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL > SC_P_ENET0_RGMII_RX_CTL 0 > +#define SC_P_ENET0_RGMII_RX_CTL_VPU_TSI_S0_VID > SC_P_ENET0_RGMII_RX_CTL 2 > +#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 > SC_P_ENET0_RGMII_RX_CTL 3 > +#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 > SC_P_ENET0_RGMII_RXD0 0 > +#define SC_P_ENET0_RGMII_RXD0_VPU_TSI_S0_SYNC > SC_P_ENET0_RGMII_RXD0 2 > +#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 > SC_P_ENET0_RGMII_RXD0 3 > +#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 > SC_P_ENET0_RGMII_RXD1 0 > +#define SC_P_ENET0_RGMII_RXD1_VPU_TSI_S0_DATA > SC_P_ENET0_RGMII_RXD1 2 > +#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 > SC_P_ENET0_RGMII_RXD1 3 > +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 > SC_P_ENET0_RGMII_RXD2 0 > +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER > SC_P_ENET0_RGMII_RXD2 1 > +#define SC_P_ENET0_RGMII_RXD2_VPU_TSI_S0_CLK > SC_P_ENET0_RGMII_RXD2 2 > +#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 > SC_P_ENET0_RGMII_RXD2 3 > +#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 > SC_P_ENET0_RGMII_RXD3 0 > +#define SC_P_ENET0_RGMII_RXD3_DMA_UART3_RX > SC_P_ENET0_RGMII_RXD3 1 > +#define SC_P_ENET0_RGMII_RXD3_VPU_TSI_S1_CLK > SC_P_ENET0_RGMII_RXD3 2 > +#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 > SC_P_ENET0_RGMII_RXD3 3 > +#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC > SC_P_ENET1_RGMII_TXC 0 > +#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT > SC_P_ENET1_RGMII_TXC 1 > +#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_IN > SC_P_ENET1_RGMII_TXC 2 > +#define SC_P_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 > SC_P_ENET1_RGMII_TXC 3 > +#define SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL > SC_P_ENET1_RGMII_TX_CTL 0 > +#define SC_P_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 > SC_P_ENET1_RGMII_TX_CTL 3 > +#define SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 > SC_P_ENET1_RGMII_TXD0 0 > +#define SC_P_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 > SC_P_ENET1_RGMII_TXD0 3 > +#define SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 > SC_P_ENET1_RGMII_TXD1 0 > +#define SC_P_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 > SC_P_ENET1_RGMII_TXD1 3 > +#define SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 > SC_P_ENET1_RGMII_TXD2 0 > +#define SC_P_ENET1_RGMII_TXD2_DMA_UART3_TX > SC_P_ENET1_RGMII_TXD2 1 > +#define SC_P_ENET1_RGMII_TXD2_VPU_TSI_S1_VID > SC_P_ENET1_RGMII_TXD2 2 > +#define SC_P_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 > SC_P_ENET1_RGMII_TXD2 3 > +#define SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 > SC_P_ENET1_RGMII_TXD3 0 > +#define SC_P_ENET1_RGMII_TXD3_DMA_UART3_RTS_B > SC_P_ENET1_RGMII_TXD3 1 > +#define SC_P_ENET1_RGMII_TXD3_VPU_TSI_S1_SYNC > SC_P_ENET1_RGMII_TXD3 2 > +#define SC_P_ENET1_RGMII_TXD3_LSIO_GPIO6_IO15 > SC_P_ENET1_RGMII_TXD3 3 > +#define SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC > SC_P_ENET1_RGMII_RXC 0 > +#define SC_P_ENET1_RGMII_RXC_DMA_UART3_CTS_B > SC_P_ENET1_RGMII_RXC 1 > +#define SC_P_ENET1_RGMII_RXC_VPU_TSI_S1_DATA > SC_P_ENET1_RGMII_RXC 2 > +#define SC_P_ENET1_RGMII_RXC_LSIO_GPIO6_IO16 > SC_P_ENET1_RGMII_RXC 3 > +#define SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL > SC_P_ENET1_RGMII_RX_CTL 0 > +#define SC_P_ENET1_RGMII_RX_CTL_VPU_TSI_S0_VID > SC_P_ENET1_RGMII_RX_CTL 2 > +#define SC_P_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 > SC_P_ENET1_RGMII_RX_CTL 3 > +#define SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 > SC_P_ENET1_RGMII_RXD0 0 > +#define SC_P_ENET1_RGMII_RXD0_VPU_TSI_S0_SYNC > SC_P_ENET1_RGMII_RXD0 2 > +#define SC_P_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 > SC_P_ENET1_RGMII_RXD0 3 > +#define SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 > SC_P_ENET1_RGMII_RXD1 0 > +#define SC_P_ENET1_RGMII_RXD1_VPU_TSI_S0_DATA > SC_P_ENET1_RGMII_RXD1 2 > +#define SC_P_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 > SC_P_ENET1_RGMII_RXD1 3 > +#define SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 > SC_P_ENET1_RGMII_RXD2 0 > +#define SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER > SC_P_ENET1_RGMII_RXD2 1 > +#define SC_P_ENET1_RGMII_RXD2_VPU_TSI_S0_CLK > SC_P_ENET1_RGMII_RXD2 2 > +#define SC_P_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 > SC_P_ENET1_RGMII_RXD2 3 > +#define SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 > SC_P_ENET1_RGMII_RXD3 0 > +#define SC_P_ENET1_RGMII_RXD3_DMA_UART3_RX > SC_P_ENET1_RGMII_RXD3 1 > +#define SC_P_ENET1_RGMII_RXD3_VPU_TSI_S1_CLK > SC_P_ENET1_RGMII_RXD3 2 > +#define SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 > SC_P_ENET1_RGMII_RXD3 3 > +/*@}*/ > + > +#endif /* SC_PADS_H */ > + > diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h > b/include/dt-bindings/pinctrl/pads-imx8qxp.h > new file mode 100644 > index 0000000000..8049735841 > --- /dev/null > +++ b/include/dt-bindings/pinctrl/pads-imx8qxp.h > @@ -0,0 +1,770 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/*! > + * Header file used to configure SoC pad list. > + */ > + > +#ifndef SC_PADS_H > +#define SC_PADS_H > + > +/* Includes */ > + > +/* Defines */ > + > +/*! > + * @name Pad Definitions > + */ > +/*@{*/ > +#define SC_P_PCIE_CTRL0_PERST_B 0 /*!< > HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */ > +#define SC_P_PCIE_CTRL0_CLKREQ_B 1 /*!< > HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */ > +#define SC_P_PCIE_CTRL0_WAKE_B 2 /*!< > HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 /*!< */ > +#define SC_P_USB_SS3_TC0 4 /*!< > ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, > LSIO.GPIO4.IO03 */ > +#define SC_P_USB_SS3_TC1 5 /*!< > ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */ > +#define SC_P_USB_SS3_TC2 6 /*!< > ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 > */ > +#define SC_P_USB_SS3_TC3 7 /*!< > ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */ > +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8 /*!< */ > +#define SC_P_EMMC0_CLK 9 /*!< > CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */ > +#define SC_P_EMMC0_CMD 10 /*!< > CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */ > +#define SC_P_EMMC0_DATA0 11 /*!< > CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */ > +#define SC_P_EMMC0_DATA1 12 /*!< > CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */ > +#define SC_P_EMMC0_DATA2 13 /*!< > CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */ > +#define SC_P_EMMC0_DATA3 14 /*!< > CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15 /*!< */ > +#define SC_P_EMMC0_DATA4 16 /*!< > CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, > LSIO.GPIO4.IO13 */ > +#define SC_P_EMMC0_DATA5 17 /*!< > CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, > LSIO.GPIO4.IO14 */ > +#define SC_P_EMMC0_DATA6 18 /*!< > CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 > */ > +#define SC_P_EMMC0_DATA7 19 /*!< > CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 > */ > +#define SC_P_EMMC0_STROBE 20 /*!< > CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 > */ > +#define SC_P_EMMC0_RESET_B 21 /*!< > CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22 /*!< */ > +#define SC_P_USDHC1_RESET_B 23 /*!< > CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 > */ > +#define SC_P_USDHC1_VSELECT 24 /*!< > CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, > CONN.NAND.RE_B, LSIO.GPIO4.IO20 */ > +#define SC_P_CTL_NAND_RE_P_N 25 /*!< */ > +#define SC_P_USDHC1_WP 26 /*!< > CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */ > +#define SC_P_USDHC1_CD_B 27 /*!< > CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, > LSIO.GPIO4.IO22 */ > +#define SC_P_CTL_NAND_DQS_P_N 28 /*!< */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29 /*!< */ > +#define SC_P_USDHC1_CLK 30 /*!< > CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */ > +#define SC_P_USDHC1_CMD 31 /*!< > CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */ > +#define SC_P_USDHC1_DATA0 32 /*!< > CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */ > +#define SC_P_USDHC1_DATA1 33 /*!< > CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 > */ > +#define SC_P_USDHC1_DATA2 34 /*!< > CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, > LSIO.GPIO4.IO27 */ > +#define SC_P_USDHC1_DATA3 35 /*!< > CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, > LSIO.GPIO4.IO28 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36 /*!< */ > +#define SC_P_ENET0_RGMII_TXC 37 /*!< > CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, > CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */ > +#define SC_P_ENET0_RGMII_TX_CTL 38 /*!< > CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */ > +#define SC_P_ENET0_RGMII_TXD0 39 /*!< > CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 */ > +#define SC_P_ENET0_RGMII_TXD1 40 /*!< > CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */ > +#define SC_P_ENET0_RGMII_TXD2 41 /*!< > CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, > CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 */ > +#define SC_P_ENET0_RGMII_TXD3 42 /*!< > CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, > LSIO.GPIO5.IO02 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43 /*!< */ > +#define SC_P_ENET0_RGMII_RXC 44 /*!< > CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, > CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */ > +#define SC_P_ENET0_RGMII_RX_CTL 45 /*!< > CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */ > +#define SC_P_ENET0_RGMII_RXD0 46 /*!< > CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */ > +#define SC_P_ENET0_RGMII_RXD1 47 /*!< > CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */ > +#define SC_P_ENET0_RGMII_RXD2 48 /*!< > CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, > LSIO.GPIO5.IO07 */ > +#define SC_P_ENET0_RGMII_RXD3 49 /*!< > CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, > LSIO.GPIO5.IO08 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50 /*!< */ > +#define SC_P_ENET0_REFCLK_125M_25M 51 /*!< > CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, > LSIO.GPIO5.IO09 */ > +#define SC_P_ENET0_MDIO 52 /*!< > CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO5.IO10 */ > +#define SC_P_ENET0_MDC 53 /*!< > CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO5.IO11 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54 /*!< */ > +#define SC_P_ESAI0_FSR 55 /*!< > ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, > CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN */ > +#define SC_P_ESAI0_FST 56 /*!< > ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01, > CONN.ENET1.RGMII_TXD2, LSIO.GPIO0.IO01 */ > +#define SC_P_ESAI0_SCKR 57 /*!< > ADMA.ESAI0.SCKR, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TX_CTL, > LSIO.GPIO0.IO02 */ > +#define SC_P_ESAI0_SCKT 58 /*!< > ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D03, > CONN.ENET1.RGMII_TXD3, LSIO.GPIO0.IO03 */ > +#define SC_P_ESAI0_TX0 59 /*!< > ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D04, > CONN.ENET1.RGMII_RXC, LSIO.GPIO0.IO04 */ > +#define SC_P_ESAI0_TX1 60 /*!< > ADMA.ESAI0.TX1, ADMA.LCDIF.D05, CONN.ENET1.RGMII_RXD3, > LSIO.GPIO0.IO05 */ > +#define SC_P_ESAI0_TX2_RX3 61 /*!< > ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D06, > CONN.ENET1.RGMII_RXD2, LSIO.GPIO0.IO06 */ > +#define SC_P_ESAI0_TX3_RX2 62 /*!< > ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD1, > LSIO.GPIO0.IO07 */ > +#define SC_P_ESAI0_TX4_RX1 63 /*!< > ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D08, CONN.ENET1.RGMII_TXD0, > LSIO.GPIO0.IO08 */ > +#define SC_P_ESAI0_TX5_RX0 64 /*!< > ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D09, CONN.ENET1.RGMII_TXD1, > LSIO.GPIO0.IO09 */ > +#define SC_P_SPDIF0_RX 65 /*!< > ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, > LSIO.GPIO0.IO10 */ > +#define SC_P_SPDIF0_TX 66 /*!< > ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, > CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO0.IO11 */ > +#define SC_P_SPDIF0_EXT_CLK 67 /*!< > ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, > LSIO.GPIO0.IO12 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68 /*!< */ > +#define SC_P_SPI3_SCK 69 /*!< > ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */ > +#define SC_P_SPI3_SDO 70 /*!< > ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */ > +#define SC_P_SPI3_SDI 71 /*!< > ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */ > +#define SC_P_SPI3_CS0 72 /*!< > ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, > LSIO.GPIO0.IO16 */ > +#define SC_P_SPI3_CS1 73 /*!< > ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, > ADMA.LCDIF.D16 */ > +#define SC_P_MCLK_IN1 74 /*!< > ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, > ADMA.LCDIF.D17 */ > +#define SC_P_MCLK_IN0 75 /*!< > ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, > ADMA.SPI2.SDI, LSIO.GPIO0.IO19 */ > +#define SC_P_MCLK_OUT0 76 /*!< > ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, > ADMA.SPI2.SDO, LSIO.GPIO0.IO20 */ > +#define SC_P_UART1_TX 77 /*!< > ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21 */ > +#define SC_P_UART1_RX 78 /*!< > ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, > LSIO.GPIO0.IO22 */ > +#define SC_P_UART1_RTS_B 79 /*!< > ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, > LSIO.GPT0.CLK */ > +#define SC_P_UART1_CTS_B 80 /*!< > ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, > LSIO.GPIO0.IO24 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81 /*!< */ > +#define SC_P_SAI0_TXD 82 /*!< > ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, > LSIO.GPIO0.IO25 */ > +#define SC_P_SAI0_TXC 83 /*!< > ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, > LSIO.GPIO0.IO26 */ > +#define SC_P_SAI0_RXD 84 /*!< > ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, > LSIO.GPIO0.IO27 */ > +#define SC_P_SAI0_TXFS 85 /*!< > ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO0.IO28 */ > +#define SC_P_SAI1_RXD 86 /*!< > ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D21, > LSIO.GPIO0.IO29 */ > +#define SC_P_SAI1_RXC 87 /*!< > ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22, LSIO.GPIO0.IO30 */ > +#define SC_P_SAI1_RXFS 88 /*!< > ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO0.IO31 */ > +#define SC_P_SPI2_CS0 89 /*!< > ADMA.SPI2.CS0, LSIO.GPIO1.IO00 */ > +#define SC_P_SPI2_SDO 90 /*!< > ADMA.SPI2.SDO, LSIO.GPIO1.IO01 */ > +#define SC_P_SPI2_SDI 91 /*!< > ADMA.SPI2.SDI, LSIO.GPIO1.IO02 */ > +#define SC_P_SPI2_SCK 92 /*!< > ADMA.SPI2.SCK, LSIO.GPIO1.IO03 */ > +#define SC_P_SPI0_SCK 93 /*!< > ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, > LSIO.GPIO1.IO04 */ > +#define SC_P_SPI0_SDI 94 /*!< > ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, > LSIO.GPIO1.IO05 */ > +#define SC_P_SPI0_SDO 95 /*!< > ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, > LSIO.GPIO1.IO06 */ > +#define SC_P_SPI0_CS1 96 /*!< > ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, > LSIO.GPIO1.IO07 */ > +#define SC_P_SPI0_CS0 97 /*!< > ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, > LSIO.GPIO1.IO08 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98 /*!< */ > +#define SC_P_ADC_IN1 99 /*!< > ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO09 */ > +#define SC_P_ADC_IN0 100 /*!< > ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO10 */ > +#define SC_P_ADC_IN3 101 /*!< > ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, > LSIO.GPIO1.IO11 */ > +#define SC_P_ADC_IN2 102 /*!< > ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, > LSIO.GPIO1.IO12 */ > +#define SC_P_ADC_IN5 103 /*!< > ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO1.IO13 */ > +#define SC_P_ADC_IN4 104 /*!< > ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO1.IO14 */ > +#define SC_P_FLEXCAN0_RX 105 /*!< > ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, > LSIO.GPIO1.IO15 */ > +#define SC_P_FLEXCAN0_TX 106 /*!< > ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, > LSIO.GPIO1.IO16 */ > +#define SC_P_FLEXCAN1_RX 107 /*!< > ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, > LSIO.GPIO1.IO17 */ > +#define SC_P_FLEXCAN1_TX 108 /*!< > ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, > LSIO.GPIO1.IO18 */ > +#define SC_P_FLEXCAN2_RX 109 /*!< > ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, > LSIO.GPIO1.IO19 */ > +#define SC_P_FLEXCAN2_TX 110 /*!< > ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, > LSIO.GPIO1.IO20 */ > +#define SC_P_UART0_RX 111 /*!< > ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, SCU.UART0.RX, > LSIO.GPIO1.IO21 */ > +#define SC_P_UART0_TX 112 /*!< > ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, SCU.UART0.TX, > LSIO.GPIO1.IO22 */ > +#define SC_P_UART2_TX 113 /*!< > ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */ > +#define SC_P_UART2_RX 114 /*!< > ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115 /*!< */ > +#define SC_P_MIPI_DSI0_I2C0_SCL 116 /*!< > MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 */ > +#define SC_P_MIPI_DSI0_I2C0_SDA 117 /*!< > MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 */ > +#define SC_P_MIPI_DSI0_GPIO0_00 118 /*!< > MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, > LSIO.GPIO1.IO27 */ > +#define SC_P_MIPI_DSI0_GPIO0_01 119 /*!< > MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */ > +#define SC_P_MIPI_DSI1_I2C0_SCL 120 /*!< > MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 */ > +#define SC_P_MIPI_DSI1_I2C0_SDA 121 /*!< > MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 */ > +#define SC_P_MIPI_DSI1_GPIO0_00 122 /*!< > MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, > LSIO.GPIO1.IO31 */ > +#define SC_P_MIPI_DSI1_GPIO0_01 123 /*!< > MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124 /*!< */ > +#define SC_P_JTAG_TRST_B 125 /*!< > SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */ > +#define SC_P_PMIC_I2C_SCL 126 /*!< > SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */ > +#define SC_P_PMIC_I2C_SDA 127 /*!< > SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */ > +#define SC_P_PMIC_INT_B 128 /*!< > SCU.DSC.PMIC_INT_B */ > +#define SC_P_SCU_GPIO0_00 129 /*!< > SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, > LSIO.GPIO2.IO03 */ > +#define SC_P_SCU_GPIO0_01 130 /*!< > SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, > SCU.WDOG0.WDOG_OUT */ > +#define SC_P_SCU_PMIC_STANDBY 131 /*!< > SCU.DSC.PMIC_STANDBY */ > +#define SC_P_SCU_BOOT_MODE0 132 /*!< > SCU.DSC.BOOT_MODE0 */ > +#define SC_P_SCU_BOOT_MODE1 133 /*!< > SCU.DSC.BOOT_MODE1 */ > +#define SC_P_SCU_BOOT_MODE2 134 /*!< > SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA */ > +#define SC_P_SCU_BOOT_MODE3 135 /*!< > SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, > SCU.DSC.RTC_CLOCK_OUTPUT_32K */ > +#define SC_P_CSI_D00 136 /*!< > CI_PI.D02, ADMA.SAI0.RXC */ > +#define SC_P_CSI_D01 137 /*!< > CI_PI.D03, ADMA.SAI0.RXD */ > +#define SC_P_CSI_D02 138 /*!< > CI_PI.D04, ADMA.SAI0.RXFS */ > +#define SC_P_CSI_D03 139 /*!< > CI_PI.D05, ADMA.SAI2.RXC */ > +#define SC_P_CSI_D04 140 /*!< > CI_PI.D06, ADMA.SAI2.RXD */ > +#define SC_P_CSI_D05 141 /*!< > CI_PI.D07, ADMA.SAI2.RXFS */ > +#define SC_P_CSI_D06 142 /*!< > CI_PI.D08, ADMA.SAI3.RXC */ > +#define SC_P_CSI_D07 143 /*!< > CI_PI.D09, ADMA.SAI3.RXD */ > +#define SC_P_CSI_HSYNC 144 /*!< > CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS */ > +#define SC_P_CSI_VSYNC 145 /*!< > CI_PI.VSYNC, CI_PI.D01 */ > +#define SC_P_CSI_PCLK 146 /*!< > CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */ > +#define SC_P_CSI_MCLK 147 /*!< > CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */ > +#define SC_P_CSI_EN 148 /*!< CI_PI.EN, > CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */ > +#define SC_P_CSI_RESET 149 /*!< > CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 > */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150 /*!< */ > +#define SC_P_MIPI_CSI0_MCLK_OUT 151 /*!< > MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */ > +#define SC_P_MIPI_CSI0_I2C0_SCL 152 /*!< > MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 */ > +#define SC_P_MIPI_CSI0_I2C0_SDA 153 /*!< > MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 */ > +#define SC_P_MIPI_CSI0_GPIO0_01 154 /*!< > MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */ > +#define SC_P_MIPI_CSI0_GPIO0_00 155 /*!< > MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */ > +#define SC_P_QSPI0A_DATA0 156 /*!< > LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */ > +#define SC_P_QSPI0A_DATA1 157 /*!< > LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */ > +#define SC_P_QSPI0A_DATA2 158 /*!< > LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */ > +#define SC_P_QSPI0A_DATA3 159 /*!< > LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */ > +#define SC_P_QSPI0A_DQS 160 /*!< > LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */ > +#define SC_P_QSPI0A_SS0_B 161 /*!< > LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */ > +#define SC_P_QSPI0A_SS1_B 162 /*!< > LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */ > +#define SC_P_QSPI0A_SCLK 163 /*!< > LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164 /*!< */ > +#define SC_P_QSPI0B_SCLK 165 /*!< > LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */ > +#define SC_P_QSPI0B_DATA0 166 /*!< > LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO3.IO18 */ > +#define SC_P_QSPI0B_DATA1 167 /*!< > LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO3.IO19 */ > +#define SC_P_QSPI0B_DATA2 168 /*!< > LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */ > +#define SC_P_QSPI0B_DATA3 169 /*!< > LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */ > +#define SC_P_QSPI0B_DQS 170 /*!< > LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 */ > +#define SC_P_QSPI0B_SS0_B 171 /*!< > LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */ > +#define SC_P_QSPI0B_SS1_B 172 /*!< > LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO3.IO24 */ > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173 /*!< */ > +/*@}*/ > + > +/*! > + * @name Pad Mux Definitions > + * format: name padid padmux > + */ > +/*@{*/ > +#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B > SC_P_PCIE_CTRL0_PERST_B 0 > +#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 > SC_P_PCIE_CTRL0_PERST_B 4 > +#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B > SC_P_PCIE_CTRL0_CLKREQ_B 0 > +#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 > SC_P_PCIE_CTRL0_CLKREQ_B 4 > +#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B > SC_P_PCIE_CTRL0_WAKE_B 0 > +#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 > SC_P_PCIE_CTRL0_WAKE_B 4 > +#define SC_P_USB_SS3_TC0_ADMA_I2C1_SCL > SC_P_USB_SS3_TC0 0 > +#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR > SC_P_USB_SS3_TC0 1 > +#define SC_P_USB_SS3_TC0_CONN_USB_OTG2_PWR > SC_P_USB_SS3_TC0 2 > +#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 > SC_P_USB_SS3_TC0 4 > +#define SC_P_USB_SS3_TC1_ADMA_I2C1_SCL > SC_P_USB_SS3_TC1 0 > +#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR > SC_P_USB_SS3_TC1 1 > +#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 > SC_P_USB_SS3_TC1 4 > +#define SC_P_USB_SS3_TC2_ADMA_I2C1_SDA > SC_P_USB_SS3_TC2 0 > +#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC > SC_P_USB_SS3_TC2 1 > +#define SC_P_USB_SS3_TC2_CONN_USB_OTG2_OC > SC_P_USB_SS3_TC2 2 > +#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 > SC_P_USB_SS3_TC2 4 > +#define SC_P_USB_SS3_TC3_ADMA_I2C1_SDA > SC_P_USB_SS3_TC3 0 > +#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC > SC_P_USB_SS3_TC3 1 > +#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 > SC_P_USB_SS3_TC3 4 > +#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK > SC_P_EMMC0_CLK 0 > +#define SC_P_EMMC0_CLK_CONN_NAND_READY_B > SC_P_EMMC0_CLK 1 > +#define SC_P_EMMC0_CLK_LSIO_GPIO4_IO07 > SC_P_EMMC0_CLK 4 > +#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD > SC_P_EMMC0_CMD 0 > +#define SC_P_EMMC0_CMD_CONN_NAND_DQS > SC_P_EMMC0_CMD 1 > +#define SC_P_EMMC0_CMD_LSIO_GPIO4_IO08 > SC_P_EMMC0_CMD 4 > +#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 > SC_P_EMMC0_DATA0 0 > +#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00 > SC_P_EMMC0_DATA0 1 > +#define SC_P_EMMC0_DATA0_LSIO_GPIO4_IO09 > SC_P_EMMC0_DATA0 4 > +#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 > SC_P_EMMC0_DATA1 0 > +#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01 > SC_P_EMMC0_DATA1 1 > +#define SC_P_EMMC0_DATA1_LSIO_GPIO4_IO10 > SC_P_EMMC0_DATA1 4 > +#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 > SC_P_EMMC0_DATA2 0 > +#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02 > SC_P_EMMC0_DATA2 1 > +#define SC_P_EMMC0_DATA2_LSIO_GPIO4_IO11 > SC_P_EMMC0_DATA2 4 > +#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 > SC_P_EMMC0_DATA3 0 > +#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03 > SC_P_EMMC0_DATA3 1 > +#define SC_P_EMMC0_DATA3_LSIO_GPIO4_IO12 > SC_P_EMMC0_DATA3 4 > +#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 > SC_P_EMMC0_DATA4 0 > +#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04 > SC_P_EMMC0_DATA4 1 > +#define SC_P_EMMC0_DATA4_CONN_EMMC0_WP > SC_P_EMMC0_DATA4 3 > +#define SC_P_EMMC0_DATA4_LSIO_GPIO4_IO13 > SC_P_EMMC0_DATA4 4 > +#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 > SC_P_EMMC0_DATA5 0 > +#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05 > SC_P_EMMC0_DATA5 1 > +#define SC_P_EMMC0_DATA5_CONN_EMMC0_VSELECT > SC_P_EMMC0_DATA5 3 > +#define SC_P_EMMC0_DATA5_LSIO_GPIO4_IO14 > SC_P_EMMC0_DATA5 4 > +#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 > SC_P_EMMC0_DATA6 0 > +#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06 > SC_P_EMMC0_DATA6 1 > +#define SC_P_EMMC0_DATA6_CONN_MLB_CLK > SC_P_EMMC0_DATA6 3 > +#define SC_P_EMMC0_DATA6_LSIO_GPIO4_IO15 > SC_P_EMMC0_DATA6 4 > +#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 > SC_P_EMMC0_DATA7 0 > +#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07 > SC_P_EMMC0_DATA7 1 > +#define SC_P_EMMC0_DATA7_CONN_MLB_SIG > SC_P_EMMC0_DATA7 3 > +#define SC_P_EMMC0_DATA7_LSIO_GPIO4_IO16 > SC_P_EMMC0_DATA7 4 > +#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE > SC_P_EMMC0_STROBE 0 > +#define SC_P_EMMC0_STROBE_CONN_NAND_CLE > SC_P_EMMC0_STROBE 1 > +#define SC_P_EMMC0_STROBE_CONN_MLB_DATA > SC_P_EMMC0_STROBE 3 > +#define SC_P_EMMC0_STROBE_LSIO_GPIO4_IO17 > SC_P_EMMC0_STROBE 4 > +#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B > SC_P_EMMC0_RESET_B 0 > +#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B > SC_P_EMMC0_RESET_B 1 > +#define SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18 > SC_P_EMMC0_RESET_B 4 > +#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B > SC_P_USDHC1_RESET_B 0 > +#define SC_P_USDHC1_RESET_B_CONN_NAND_RE_N > SC_P_USDHC1_RESET_B 1 > +#define SC_P_USDHC1_RESET_B_ADMA_SPI2_SCK > SC_P_USDHC1_RESET_B 2 > +#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 > SC_P_USDHC1_RESET_B 4 > +#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT > SC_P_USDHC1_VSELECT 0 > +#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_P > SC_P_USDHC1_VSELECT 1 > +#define SC_P_USDHC1_VSELECT_ADMA_SPI2_SDO > SC_P_USDHC1_VSELECT 2 > +#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_B > SC_P_USDHC1_VSELECT 3 > +#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO20 > SC_P_USDHC1_VSELECT 4 > +#define SC_P_USDHC1_WP_CONN_USDHC1_WP > SC_P_USDHC1_WP 0 > +#define SC_P_USDHC1_WP_CONN_NAND_DQS_N > SC_P_USDHC1_WP 1 > +#define SC_P_USDHC1_WP_ADMA_SPI2_SDI > SC_P_USDHC1_WP 2 > +#define SC_P_USDHC1_WP_LSIO_GPIO4_IO21 > SC_P_USDHC1_WP 4 > +#define SC_P_USDHC1_CD_B_CONN_USDHC1_CD_B > SC_P_USDHC1_CD_B 0 > +#define SC_P_USDHC1_CD_B_CONN_NAND_DQS_P > SC_P_USDHC1_CD_B 1 > +#define SC_P_USDHC1_CD_B_ADMA_SPI2_CS0 > SC_P_USDHC1_CD_B 2 > +#define SC_P_USDHC1_CD_B_CONN_NAND_DQS > SC_P_USDHC1_CD_B 3 > +#define SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 > SC_P_USDHC1_CD_B 4 > +#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK > SC_P_USDHC1_CLK 0 > +#define SC_P_USDHC1_CLK_ADMA_UART3_RX > SC_P_USDHC1_CLK 2 > +#define SC_P_USDHC1_CLK_LSIO_GPIO4_IO23 > SC_P_USDHC1_CLK 4 > +#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD > SC_P_USDHC1_CMD 0 > +#define SC_P_USDHC1_CMD_CONN_NAND_CE0_B > SC_P_USDHC1_CMD 1 > +#define SC_P_USDHC1_CMD_ADMA_MQS_R > SC_P_USDHC1_CMD 2 > +#define SC_P_USDHC1_CMD_LSIO_GPIO4_IO24 > SC_P_USDHC1_CMD 4 > +#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 > SC_P_USDHC1_DATA0 0 > +#define SC_P_USDHC1_DATA0_CONN_NAND_CE1_B > SC_P_USDHC1_DATA0 1 > +#define SC_P_USDHC1_DATA0_ADMA_MQS_L > SC_P_USDHC1_DATA0 2 > +#define SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25 > SC_P_USDHC1_DATA0 4 > +#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 > SC_P_USDHC1_DATA1 0 > +#define SC_P_USDHC1_DATA1_CONN_NAND_RE_B > SC_P_USDHC1_DATA1 1 > +#define SC_P_USDHC1_DATA1_ADMA_UART3_TX > SC_P_USDHC1_DATA1 2 > +#define SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26 > SC_P_USDHC1_DATA1 4 > +#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 > SC_P_USDHC1_DATA2 0 > +#define SC_P_USDHC1_DATA2_CONN_NAND_WE_B > SC_P_USDHC1_DATA2 1 > +#define SC_P_USDHC1_DATA2_ADMA_UART3_CTS_B > SC_P_USDHC1_DATA2 2 > +#define SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27 > SC_P_USDHC1_DATA2 4 > +#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 > SC_P_USDHC1_DATA3 0 > +#define SC_P_USDHC1_DATA3_CONN_NAND_ALE > SC_P_USDHC1_DATA3 1 > +#define SC_P_USDHC1_DATA3_ADMA_UART3_RTS_B > SC_P_USDHC1_DATA3 2 > +#define SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28 > SC_P_USDHC1_DATA3 4 > +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC > SC_P_ENET0_RGMII_TXC 0 > +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT > SC_P_ENET0_RGMII_TXC 1 > +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN > SC_P_ENET0_RGMII_TXC 2 > +#define SC_P_ENET0_RGMII_TXC_CONN_NAND_CE1_B > SC_P_ENET0_RGMII_TXC 3 > +#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 > SC_P_ENET0_RGMII_TXC 4 > +#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL > SC_P_ENET0_RGMII_TX_CTL 0 > +#define SC_P_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B > SC_P_ENET0_RGMII_TX_CTL 3 > +#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 > SC_P_ENET0_RGMII_TX_CTL 4 > +#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 > SC_P_ENET0_RGMII_TXD0 0 > +#define SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT > SC_P_ENET0_RGMII_TXD0 3 > +#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 > SC_P_ENET0_RGMII_TXD0 4 > +#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 > SC_P_ENET0_RGMII_TXD1 0 > +#define SC_P_ENET0_RGMII_TXD1_CONN_USDHC1_WP > SC_P_ENET0_RGMII_TXD1 3 > +#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 > SC_P_ENET0_RGMII_TXD1 4 > +#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 > SC_P_ENET0_RGMII_TXD2 0 > +#define SC_P_ENET0_RGMII_TXD2_CONN_MLB_CLK > SC_P_ENET0_RGMII_TXD2 1 > +#define SC_P_ENET0_RGMII_TXD2_CONN_NAND_CE0_B > SC_P_ENET0_RGMII_TXD2 2 > +#define SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B > SC_P_ENET0_RGMII_TXD2 3 > +#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 > SC_P_ENET0_RGMII_TXD2 4 > +#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 > SC_P_ENET0_RGMII_TXD3 0 > +#define SC_P_ENET0_RGMII_TXD3_CONN_MLB_SIG > SC_P_ENET0_RGMII_TXD3 1 > +#define SC_P_ENET0_RGMII_TXD3_CONN_NAND_RE_B > SC_P_ENET0_RGMII_TXD3 2 > +#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 > SC_P_ENET0_RGMII_TXD3 4 > +#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC > SC_P_ENET0_RGMII_RXC 0 > +#define SC_P_ENET0_RGMII_RXC_CONN_MLB_DATA > SC_P_ENET0_RGMII_RXC 1 > +#define SC_P_ENET0_RGMII_RXC_CONN_NAND_WE_B > SC_P_ENET0_RGMII_RXC 2 > +#define SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK > SC_P_ENET0_RGMII_RXC 3 > +#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 > SC_P_ENET0_RGMII_RXC 4 > +#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL > SC_P_ENET0_RGMII_RX_CTL 0 > +#define SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD > SC_P_ENET0_RGMII_RX_CTL 3 > +#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 > SC_P_ENET0_RGMII_RX_CTL 4 > +#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 > SC_P_ENET0_RGMII_RXD0 0 > +#define SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 > SC_P_ENET0_RGMII_RXD0 3 > +#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 > SC_P_ENET0_RGMII_RXD0 4 > +#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 > SC_P_ENET0_RGMII_RXD1 0 > +#define SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 > SC_P_ENET0_RGMII_RXD1 3 > +#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 > SC_P_ENET0_RGMII_RXD1 4 > +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 > SC_P_ENET0_RGMII_RXD2 0 > +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER > SC_P_ENET0_RGMII_RXD2 1 > +#define SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 > SC_P_ENET0_RGMII_RXD2 3 > +#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 > SC_P_ENET0_RGMII_RXD2 4 > +#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 > SC_P_ENET0_RGMII_RXD3 0 > +#define SC_P_ENET0_RGMII_RXD3_CONN_NAND_ALE > SC_P_ENET0_RGMII_RXD3 2 > +#define SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 > SC_P_ENET0_RGMII_RXD3 3 > +#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 > SC_P_ENET0_RGMII_RXD3 4 > +#define > SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M > SC_P_ENET0_REFCLK_125M_25M 0 > +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS > SC_P_ENET0_REFCLK_125M_25M 1 > +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS > SC_P_ENET0_REFCLK_125M_25M 2 > +#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 > SC_P_ENET0_REFCLK_125M_25M 4 > +#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO > SC_P_ENET0_MDIO 0 > +#define SC_P_ENET0_MDIO_ADMA_I2C3_SDA > SC_P_ENET0_MDIO 1 > +#define SC_P_ENET0_MDIO_CONN_ENET1_MDIO > SC_P_ENET0_MDIO 2 > +#define SC_P_ENET0_MDIO_LSIO_GPIO5_IO10 > SC_P_ENET0_MDIO 4 > +#define SC_P_ENET0_MDC_CONN_ENET0_MDC > SC_P_ENET0_MDC 0 > +#define SC_P_ENET0_MDC_ADMA_I2C3_SCL > SC_P_ENET0_MDC 1 > +#define SC_P_ENET0_MDC_CONN_ENET1_MDC > SC_P_ENET0_MDC 2 > +#define SC_P_ENET0_MDC_LSIO_GPIO5_IO11 > SC_P_ENET0_MDC 4 > +#define SC_P_ESAI0_FSR_ADMA_ESAI0_FSR > SC_P_ESAI0_FSR 0 > +#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT > SC_P_ESAI0_FSR 1 > +#define SC_P_ESAI0_FSR_ADMA_LCDIF_D00 > SC_P_ESAI0_FSR 2 > +#define SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC > SC_P_ESAI0_FSR 3 > +#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN > SC_P_ESAI0_FSR 4 > +#define SC_P_ESAI0_FST_ADMA_ESAI0_FST > SC_P_ESAI0_FST 0 > +#define SC_P_ESAI0_FST_CONN_MLB_CLK > SC_P_ESAI0_FST 1 > +#define SC_P_ESAI0_FST_ADMA_LCDIF_D01 > SC_P_ESAI0_FST 2 > +#define SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 > SC_P_ESAI0_FST 3 > +#define SC_P_ESAI0_FST_LSIO_GPIO0_IO01 > SC_P_ESAI0_FST 4 > +#define SC_P_ESAI0_SCKR_ADMA_ESAI0_SCKR > SC_P_ESAI0_SCKR 0 > +#define SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 > SC_P_ESAI0_SCKR 2 > +#define SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL > SC_P_ESAI0_SCKR 3 > +#define SC_P_ESAI0_SCKR_LSIO_GPIO0_IO02 > SC_P_ESAI0_SCKR 4 > +#define SC_P_ESAI0_SCKT_ADMA_ESAI0_SCKT > SC_P_ESAI0_SCKT 0 > +#define SC_P_ESAI0_SCKT_CONN_MLB_SIG > SC_P_ESAI0_SCKT 1 > +#define SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 > SC_P_ESAI0_SCKT 2 > +#define SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 > SC_P_ESAI0_SCKT 3 > +#define SC_P_ESAI0_SCKT_LSIO_GPIO0_IO03 > SC_P_ESAI0_SCKT 4 > +#define SC_P_ESAI0_TX0_ADMA_ESAI0_TX0 > SC_P_ESAI0_TX0 0 > +#define SC_P_ESAI0_TX0_CONN_MLB_DATA > SC_P_ESAI0_TX0 1 > +#define SC_P_ESAI0_TX0_ADMA_LCDIF_D04 > SC_P_ESAI0_TX0 2 > +#define SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC > SC_P_ESAI0_TX0 3 > +#define SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 > SC_P_ESAI0_TX0 4 > +#define SC_P_ESAI0_TX1_ADMA_ESAI0_TX1 > SC_P_ESAI0_TX1 0 > +#define SC_P_ESAI0_TX1_ADMA_LCDIF_D05 > SC_P_ESAI0_TX1 2 > +#define SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 > SC_P_ESAI0_TX1 3 > +#define SC_P_ESAI0_TX1_LSIO_GPIO0_IO05 > SC_P_ESAI0_TX1 4 > +#define SC_P_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 > SC_P_ESAI0_TX2_RX3 0 > +#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER > SC_P_ESAI0_TX2_RX3 1 > +#define SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 > SC_P_ESAI0_TX2_RX3 2 > +#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 > SC_P_ESAI0_TX2_RX3 3 > +#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 > SC_P_ESAI0_TX2_RX3 4 > +#define SC_P_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 > SC_P_ESAI0_TX3_RX2 0 > +#define SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 > SC_P_ESAI0_TX3_RX2 2 > +#define SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 > SC_P_ESAI0_TX3_RX2 3 > +#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 > SC_P_ESAI0_TX3_RX2 4 > +#define SC_P_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 > SC_P_ESAI0_TX4_RX1 0 > +#define SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 > SC_P_ESAI0_TX4_RX1 2 > +#define SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 > SC_P_ESAI0_TX4_RX1 3 > +#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO0_IO08 > SC_P_ESAI0_TX4_RX1 4 > +#define SC_P_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 > SC_P_ESAI0_TX5_RX0 0 > +#define SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 > SC_P_ESAI0_TX5_RX0 2 > +#define SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 > SC_P_ESAI0_TX5_RX0 3 > +#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO0_IO09 > SC_P_ESAI0_TX5_RX0 4 > +#define SC_P_SPDIF0_RX_ADMA_SPDIF0_RX > SC_P_SPDIF0_RX 0 > +#define SC_P_SPDIF0_RX_ADMA_MQS_R > SC_P_SPDIF0_RX 1 > +#define SC_P_SPDIF0_RX_ADMA_LCDIF_D10 > SC_P_SPDIF0_RX 2 > +#define SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 > SC_P_SPDIF0_RX 3 > +#define SC_P_SPDIF0_RX_LSIO_GPIO0_IO10 > SC_P_SPDIF0_RX 4 > +#define SC_P_SPDIF0_TX_ADMA_SPDIF0_TX > SC_P_SPDIF0_TX 0 > +#define SC_P_SPDIF0_TX_ADMA_MQS_L > SC_P_SPDIF0_TX 1 > +#define SC_P_SPDIF0_TX_ADMA_LCDIF_D11 > SC_P_SPDIF0_TX 2 > +#define SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL > SC_P_SPDIF0_TX 3 > +#define SC_P_SPDIF0_TX_LSIO_GPIO0_IO11 > SC_P_SPDIF0_TX 4 > +#define SC_P_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK > SC_P_SPDIF0_EXT_CLK 0 > +#define SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 > SC_P_SPDIF0_EXT_CLK 2 > +#define SC_P_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M > SC_P_SPDIF0_EXT_CLK 3 > +#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 > SC_P_SPDIF0_EXT_CLK 4 > +#define SC_P_SPI3_SCK_ADMA_SPI3_SCK > SC_P_SPI3_SCK 0 > +#define SC_P_SPI3_SCK_ADMA_LCDIF_D13 > SC_P_SPI3_SCK 2 > +#define SC_P_SPI3_SCK_LSIO_GPIO0_IO13 > SC_P_SPI3_SCK 4 > +#define SC_P_SPI3_SDO_ADMA_SPI3_SDO > SC_P_SPI3_SDO 0 > +#define SC_P_SPI3_SDO_ADMA_LCDIF_D14 > SC_P_SPI3_SDO 2 > +#define SC_P_SPI3_SDO_LSIO_GPIO0_IO14 > SC_P_SPI3_SDO 4 > +#define SC_P_SPI3_SDI_ADMA_SPI3_SDI > SC_P_SPI3_SDI 0 > +#define SC_P_SPI3_SDI_ADMA_LCDIF_D15 > SC_P_SPI3_SDI 2 > +#define SC_P_SPI3_SDI_LSIO_GPIO0_IO15 > SC_P_SPI3_SDI 4 > +#define SC_P_SPI3_CS0_ADMA_SPI3_CS0 > SC_P_SPI3_CS0 0 > +#define SC_P_SPI3_CS0_ADMA_ACM_MCLK_OUT1 > SC_P_SPI3_CS0 1 > +#define SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC > SC_P_SPI3_CS0 2 > +#define SC_P_SPI3_CS0_LSIO_GPIO0_IO16 > SC_P_SPI3_CS0 4 > +#define SC_P_SPI3_CS1_ADMA_SPI3_CS1 > SC_P_SPI3_CS1 0 > +#define SC_P_SPI3_CS1_ADMA_I2C3_SCL > SC_P_SPI3_CS1 1 > +#define SC_P_SPI3_CS1_ADMA_LCDIF_RESET > SC_P_SPI3_CS1 2 > +#define SC_P_SPI3_CS1_ADMA_SPI2_CS0 > SC_P_SPI3_CS1 3 > +#define SC_P_SPI3_CS1_ADMA_LCDIF_D16 > SC_P_SPI3_CS1 4 > +#define SC_P_MCLK_IN1_ADMA_ACM_MCLK_IN1 > SC_P_MCLK_IN1 0 > +#define SC_P_MCLK_IN1_ADMA_I2C3_SDA > SC_P_MCLK_IN1 1 > +#define SC_P_MCLK_IN1_ADMA_LCDIF_EN > SC_P_MCLK_IN1 2 > +#define SC_P_MCLK_IN1_ADMA_SPI2_SCK > SC_P_MCLK_IN1 3 > +#define SC_P_MCLK_IN1_ADMA_LCDIF_D17 > SC_P_MCLK_IN1 4 > +#define SC_P_MCLK_IN0_ADMA_ACM_MCLK_IN0 > SC_P_MCLK_IN0 0 > +#define SC_P_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK > SC_P_MCLK_IN0 1 > +#define SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC > SC_P_MCLK_IN0 2 > +#define SC_P_MCLK_IN0_ADMA_SPI2_SDI > SC_P_MCLK_IN0 3 > +#define SC_P_MCLK_IN0_LSIO_GPIO0_IO19 > SC_P_MCLK_IN0 4 > +#define SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 > SC_P_MCLK_OUT0 0 > +#define SC_P_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK > SC_P_MCLK_OUT0 1 > +#define SC_P_MCLK_OUT0_ADMA_LCDIF_CLK > SC_P_MCLK_OUT0 2 > +#define SC_P_MCLK_OUT0_ADMA_SPI2_SDO > SC_P_MCLK_OUT0 3 > +#define SC_P_MCLK_OUT0_LSIO_GPIO0_IO20 > SC_P_MCLK_OUT0 4 > +#define SC_P_UART1_TX_ADMA_UART1_TX > SC_P_UART1_TX 0 > +#define SC_P_UART1_TX_LSIO_PWM0_OUT > SC_P_UART1_TX 1 > +#define SC_P_UART1_TX_LSIO_GPT0_CAPTURE > SC_P_UART1_TX 2 > +#define SC_P_UART1_TX_LSIO_GPIO0_IO21 > SC_P_UART1_TX 4 > +#define SC_P_UART1_RX_ADMA_UART1_RX > SC_P_UART1_RX 0 > +#define SC_P_UART1_RX_LSIO_PWM1_OUT > SC_P_UART1_RX 1 > +#define SC_P_UART1_RX_LSIO_GPT0_COMPARE > SC_P_UART1_RX 2 > +#define SC_P_UART1_RX_LSIO_GPT1_CLK > SC_P_UART1_RX 3 > +#define SC_P_UART1_RX_LSIO_GPIO0_IO22 > SC_P_UART1_RX 4 > +#define SC_P_UART1_RTS_B_ADMA_UART1_RTS_B > SC_P_UART1_RTS_B 0 > +#define SC_P_UART1_RTS_B_LSIO_PWM2_OUT > SC_P_UART1_RTS_B 1 > +#define SC_P_UART1_RTS_B_ADMA_LCDIF_D16 > SC_P_UART1_RTS_B 2 > +#define SC_P_UART1_RTS_B_LSIO_GPT1_CAPTURE > SC_P_UART1_RTS_B 3 > +#define SC_P_UART1_RTS_B_LSIO_GPT0_CLK > SC_P_UART1_RTS_B 4 > +#define SC_P_UART1_CTS_B_ADMA_UART1_CTS_B > SC_P_UART1_CTS_B 0 > +#define SC_P_UART1_CTS_B_LSIO_PWM3_OUT > SC_P_UART1_CTS_B 1 > +#define SC_P_UART1_CTS_B_ADMA_LCDIF_D17 > SC_P_UART1_CTS_B 2 > +#define SC_P_UART1_CTS_B_LSIO_GPT1_COMPARE > SC_P_UART1_CTS_B 3 > +#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO24 > SC_P_UART1_CTS_B 4 > +#define SC_P_SAI0_TXD_ADMA_SAI0_TXD > SC_P_SAI0_TXD 0 > +#define SC_P_SAI0_TXD_ADMA_SAI1_RXC > SC_P_SAI0_TXD 1 > +#define SC_P_SAI0_TXD_ADMA_SPI1_SDO > SC_P_SAI0_TXD 2 > +#define SC_P_SAI0_TXD_ADMA_LCDIF_D18 > SC_P_SAI0_TXD 3 > +#define SC_P_SAI0_TXD_LSIO_GPIO0_IO25 > SC_P_SAI0_TXD 4 > +#define SC_P_SAI0_TXC_ADMA_SAI0_TXC > SC_P_SAI0_TXC 0 > +#define SC_P_SAI0_TXC_ADMA_SAI1_TXD > SC_P_SAI0_TXC 1 > +#define SC_P_SAI0_TXC_ADMA_SPI1_SDI > SC_P_SAI0_TXC 2 > +#define SC_P_SAI0_TXC_ADMA_LCDIF_D19 > SC_P_SAI0_TXC 3 > +#define SC_P_SAI0_TXC_LSIO_GPIO0_IO26 > SC_P_SAI0_TXC 4 > +#define SC_P_SAI0_RXD_ADMA_SAI0_RXD > SC_P_SAI0_RXD 0 > +#define SC_P_SAI0_RXD_ADMA_SAI1_RXFS > SC_P_SAI0_RXD 1 > +#define SC_P_SAI0_RXD_ADMA_SPI1_CS0 > SC_P_SAI0_RXD 2 > +#define SC_P_SAI0_RXD_ADMA_LCDIF_D20 > SC_P_SAI0_RXD 3 > +#define SC_P_SAI0_RXD_LSIO_GPIO0_IO27 > SC_P_SAI0_RXD 4 > +#define SC_P_SAI0_TXFS_ADMA_SAI0_TXFS > SC_P_SAI0_TXFS 0 > +#define SC_P_SAI0_TXFS_ADMA_SPI2_CS1 > SC_P_SAI0_TXFS 1 > +#define SC_P_SAI0_TXFS_ADMA_SPI1_SCK > SC_P_SAI0_TXFS 2 > +#define SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 > SC_P_SAI0_TXFS 4 > +#define SC_P_SAI1_RXD_ADMA_SAI1_RXD > SC_P_SAI1_RXD 0 > +#define SC_P_SAI1_RXD_ADMA_SAI0_RXFS > SC_P_SAI1_RXD 1 > +#define SC_P_SAI1_RXD_ADMA_SPI1_CS1 > SC_P_SAI1_RXD 2 > +#define SC_P_SAI1_RXD_ADMA_LCDIF_D21 > SC_P_SAI1_RXD 3 > +#define SC_P_SAI1_RXD_LSIO_GPIO0_IO29 > SC_P_SAI1_RXD 4 > +#define SC_P_SAI1_RXC_ADMA_SAI1_RXC > SC_P_SAI1_RXC 0 > +#define SC_P_SAI1_RXC_ADMA_SAI1_TXC > SC_P_SAI1_RXC 1 > +#define SC_P_SAI1_RXC_ADMA_LCDIF_D22 > SC_P_SAI1_RXC 3 > +#define SC_P_SAI1_RXC_LSIO_GPIO0_IO30 > SC_P_SAI1_RXC 4 > +#define SC_P_SAI1_RXFS_ADMA_SAI1_RXFS > SC_P_SAI1_RXFS 0 > +#define SC_P_SAI1_RXFS_ADMA_SAI1_TXFS > SC_P_SAI1_RXFS 1 > +#define SC_P_SAI1_RXFS_ADMA_LCDIF_D23 > SC_P_SAI1_RXFS 3 > +#define SC_P_SAI1_RXFS_LSIO_GPIO0_IO31 > SC_P_SAI1_RXFS 4 > +#define SC_P_SPI2_CS0_ADMA_SPI2_CS0 > SC_P_SPI2_CS0 0 > +#define SC_P_SPI2_CS0_LSIO_GPIO1_IO00 > SC_P_SPI2_CS0 4 > +#define SC_P_SPI2_SDO_ADMA_SPI2_SDO > SC_P_SPI2_SDO 0 > +#define SC_P_SPI2_SDO_LSIO_GPIO1_IO01 > SC_P_SPI2_SDO 4 > +#define SC_P_SPI2_SDI_ADMA_SPI2_SDI > SC_P_SPI2_SDI 0 > +#define SC_P_SPI2_SDI_LSIO_GPIO1_IO02 > SC_P_SPI2_SDI 4 > +#define SC_P_SPI2_SCK_ADMA_SPI2_SCK > SC_P_SPI2_SCK 0 > +#define SC_P_SPI2_SCK_LSIO_GPIO1_IO03 > SC_P_SPI2_SCK 4 > +#define SC_P_SPI0_SCK_ADMA_SPI0_SCK > SC_P_SPI0_SCK 0 > +#define SC_P_SPI0_SCK_ADMA_SAI0_TXC > SC_P_SPI0_SCK 1 > +#define SC_P_SPI0_SCK_M40_I2C0_SCL > SC_P_SPI0_SCK 2 > +#define SC_P_SPI0_SCK_M40_GPIO0_IO00 > SC_P_SPI0_SCK 3 > +#define SC_P_SPI0_SCK_LSIO_GPIO1_IO04 > SC_P_SPI0_SCK 4 > +#define SC_P_SPI0_SDI_ADMA_SPI0_SDI > SC_P_SPI0_SDI 0 > +#define SC_P_SPI0_SDI_ADMA_SAI0_TXD > SC_P_SPI0_SDI 1 > +#define SC_P_SPI0_SDI_M40_TPM0_CH0 > SC_P_SPI0_SDI 2 > +#define SC_P_SPI0_SDI_M40_GPIO0_IO02 > SC_P_SPI0_SDI 3 > +#define SC_P_SPI0_SDI_LSIO_GPIO1_IO05 > SC_P_SPI0_SDI 4 > +#define SC_P_SPI0_SDO_ADMA_SPI0_SDO > SC_P_SPI0_SDO 0 > +#define SC_P_SPI0_SDO_ADMA_SAI0_TXFS > SC_P_SPI0_SDO 1 > +#define SC_P_SPI0_SDO_M40_I2C0_SDA > SC_P_SPI0_SDO 2 > +#define SC_P_SPI0_SDO_M40_GPIO0_IO01 > SC_P_SPI0_SDO 3 > +#define SC_P_SPI0_SDO_LSIO_GPIO1_IO06 > SC_P_SPI0_SDO 4 > +#define SC_P_SPI0_CS1_ADMA_SPI0_CS1 > SC_P_SPI0_CS1 0 > +#define SC_P_SPI0_CS1_ADMA_SAI0_RXC > SC_P_SPI0_CS1 1 > +#define SC_P_SPI0_CS1_ADMA_SAI1_TXD > SC_P_SPI0_CS1 2 > +#define SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT > SC_P_SPI0_CS1 3 > +#define SC_P_SPI0_CS1_LSIO_GPIO1_IO07 > SC_P_SPI0_CS1 4 > +#define SC_P_SPI0_CS0_ADMA_SPI0_CS0 > SC_P_SPI0_CS0 0 > +#define SC_P_SPI0_CS0_ADMA_SAI0_RXD > SC_P_SPI0_CS0 1 > +#define SC_P_SPI0_CS0_M40_TPM0_CH1 > SC_P_SPI0_CS0 2 > +#define SC_P_SPI0_CS0_M40_GPIO0_IO03 > SC_P_SPI0_CS0 3 > +#define SC_P_SPI0_CS0_LSIO_GPIO1_IO08 > SC_P_SPI0_CS0 4 > +#define SC_P_ADC_IN1_ADMA_ADC_IN1 > SC_P_ADC_IN1 0 > +#define SC_P_ADC_IN1_M40_I2C0_SDA > SC_P_ADC_IN1 1 > +#define SC_P_ADC_IN1_M40_GPIO0_IO01 > SC_P_ADC_IN1 2 > +#define SC_P_ADC_IN1_LSIO_GPIO1_IO09 > SC_P_ADC_IN1 4 > +#define SC_P_ADC_IN0_ADMA_ADC_IN0 > SC_P_ADC_IN0 0 > +#define SC_P_ADC_IN0_M40_I2C0_SCL > SC_P_ADC_IN0 1 > +#define SC_P_ADC_IN0_M40_GPIO0_IO00 > SC_P_ADC_IN0 2 > +#define SC_P_ADC_IN0_LSIO_GPIO1_IO10 > SC_P_ADC_IN0 4 > +#define SC_P_ADC_IN3_ADMA_ADC_IN3 > SC_P_ADC_IN3 0 > +#define SC_P_ADC_IN3_M40_UART0_TX > SC_P_ADC_IN3 1 > +#define SC_P_ADC_IN3_M40_GPIO0_IO03 > SC_P_ADC_IN3 2 > +#define SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0 > SC_P_ADC_IN3 3 > +#define SC_P_ADC_IN3_LSIO_GPIO1_IO11 > SC_P_ADC_IN3 4 > +#define SC_P_ADC_IN2_ADMA_ADC_IN2 > SC_P_ADC_IN2 0 > +#define SC_P_ADC_IN2_M40_UART0_RX > SC_P_ADC_IN2 1 > +#define SC_P_ADC_IN2_M40_GPIO0_IO02 > SC_P_ADC_IN2 2 > +#define SC_P_ADC_IN2_ADMA_ACM_MCLK_IN0 > SC_P_ADC_IN2 3 > +#define SC_P_ADC_IN2_LSIO_GPIO1_IO12 > SC_P_ADC_IN2 4 > +#define SC_P_ADC_IN5_ADMA_ADC_IN5 > SC_P_ADC_IN5 0 > +#define SC_P_ADC_IN5_M40_TPM0_CH1 > SC_P_ADC_IN5 1 > +#define SC_P_ADC_IN5_M40_GPIO0_IO05 > SC_P_ADC_IN5 2 > +#define SC_P_ADC_IN5_LSIO_GPIO1_IO13 > SC_P_ADC_IN5 4 > +#define SC_P_ADC_IN4_ADMA_ADC_IN4 > SC_P_ADC_IN4 0 > +#define SC_P_ADC_IN4_M40_TPM0_CH0 > SC_P_ADC_IN4 1 > +#define SC_P_ADC_IN4_M40_GPIO0_IO04 > SC_P_ADC_IN4 2 > +#define SC_P_ADC_IN4_LSIO_GPIO1_IO14 > SC_P_ADC_IN4 4 > +#define SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX > SC_P_FLEXCAN0_RX 0 > +#define SC_P_FLEXCAN0_RX_ADMA_SAI2_RXC > SC_P_FLEXCAN0_RX 1 > +#define SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B > SC_P_FLEXCAN0_RX 2 > +#define SC_P_FLEXCAN0_RX_ADMA_SAI1_TXC > SC_P_FLEXCAN0_RX 3 > +#define SC_P_FLEXCAN0_RX_LSIO_GPIO1_IO15 > SC_P_FLEXCAN0_RX 4 > +#define SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX > SC_P_FLEXCAN0_TX 0 > +#define SC_P_FLEXCAN0_TX_ADMA_SAI2_RXD > SC_P_FLEXCAN0_TX 1 > +#define SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B > SC_P_FLEXCAN0_TX 2 > +#define SC_P_FLEXCAN0_TX_ADMA_SAI1_TXFS > SC_P_FLEXCAN0_TX 3 > +#define SC_P_FLEXCAN0_TX_LSIO_GPIO1_IO16 > SC_P_FLEXCAN0_TX 4 > +#define SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX > SC_P_FLEXCAN1_RX 0 > +#define SC_P_FLEXCAN1_RX_ADMA_SAI2_RXFS > SC_P_FLEXCAN1_RX 1 > +#define SC_P_FLEXCAN1_RX_ADMA_FTM_CH2 > SC_P_FLEXCAN1_RX 2 > +#define SC_P_FLEXCAN1_RX_ADMA_SAI1_TXD > SC_P_FLEXCAN1_RX 3 > +#define SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 > SC_P_FLEXCAN1_RX 4 > +#define SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX > SC_P_FLEXCAN1_TX 0 > +#define SC_P_FLEXCAN1_TX_ADMA_SAI3_RXC > SC_P_FLEXCAN1_TX 1 > +#define SC_P_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 > SC_P_FLEXCAN1_TX 2 > +#define SC_P_FLEXCAN1_TX_ADMA_SAI1_RXD > SC_P_FLEXCAN1_TX 3 > +#define SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 > SC_P_FLEXCAN1_TX 4 > +#define SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX > SC_P_FLEXCAN2_RX 0 > +#define SC_P_FLEXCAN2_RX_ADMA_SAI3_RXD > SC_P_FLEXCAN2_RX 1 > +#define SC_P_FLEXCAN2_RX_ADMA_UART3_RX > SC_P_FLEXCAN2_RX 2 > +#define SC_P_FLEXCAN2_RX_ADMA_SAI1_RXFS > SC_P_FLEXCAN2_RX 3 > +#define SC_P_FLEXCAN2_RX_LSIO_GPIO1_IO19 > SC_P_FLEXCAN2_RX 4 > +#define SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX > SC_P_FLEXCAN2_TX 0 > +#define SC_P_FLEXCAN2_TX_ADMA_SAI3_RXFS > SC_P_FLEXCAN2_TX 1 > +#define SC_P_FLEXCAN2_TX_ADMA_UART3_TX > SC_P_FLEXCAN2_TX 2 > +#define SC_P_FLEXCAN2_TX_ADMA_SAI1_RXC > SC_P_FLEXCAN2_TX 3 > +#define SC_P_FLEXCAN2_TX_LSIO_GPIO1_IO20 > SC_P_FLEXCAN2_TX 4 > +#define SC_P_UART0_RX_ADMA_UART0_RX > SC_P_UART0_RX 0 > +#define SC_P_UART0_RX_ADMA_MQS_R > SC_P_UART0_RX 1 > +#define SC_P_UART0_RX_ADMA_FLEXCAN0_RX > SC_P_UART0_RX 2 > +#define SC_P_UART0_RX_SCU_UART0_RX > SC_P_UART0_RX 3 > +#define SC_P_UART0_RX_LSIO_GPIO1_IO21 > SC_P_UART0_RX 4 > +#define SC_P_UART0_TX_ADMA_UART0_TX > SC_P_UART0_TX 0 > +#define SC_P_UART0_TX_ADMA_MQS_L > SC_P_UART0_TX 1 > +#define SC_P_UART0_TX_ADMA_FLEXCAN0_TX > SC_P_UART0_TX 2 > +#define SC_P_UART0_TX_SCU_UART0_TX > SC_P_UART0_TX 3 > +#define SC_P_UART0_TX_LSIO_GPIO1_IO22 > SC_P_UART0_TX 4 > +#define SC_P_UART2_TX_ADMA_UART2_TX > SC_P_UART2_TX 0 > +#define SC_P_UART2_TX_ADMA_FTM_CH1 > SC_P_UART2_TX 1 > +#define SC_P_UART2_TX_ADMA_FLEXCAN1_TX > SC_P_UART2_TX 2 > +#define SC_P_UART2_TX_LSIO_GPIO1_IO23 > SC_P_UART2_TX 4 > +#define SC_P_UART2_RX_ADMA_UART2_RX > SC_P_UART2_RX 0 > +#define SC_P_UART2_RX_ADMA_FTM_CH0 > SC_P_UART2_RX 1 > +#define SC_P_UART2_RX_ADMA_FLEXCAN1_RX > SC_P_UART2_RX 2 > +#define SC_P_UART2_RX_LSIO_GPIO1_IO24 > SC_P_UART2_RX 4 > +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL > SC_P_MIPI_DSI0_I2C0_SCL 0 > +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02 > SC_P_MIPI_DSI0_I2C0_SCL 1 > +#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 > SC_P_MIPI_DSI0_I2C0_SCL 4 > +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA > SC_P_MIPI_DSI0_I2C0_SDA 0 > +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03 > SC_P_MIPI_DSI0_I2C0_SDA 1 > +#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 > SC_P_MIPI_DSI0_I2C0_SDA 4 > +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 > SC_P_MIPI_DSI0_GPIO0_00 0 > +#define SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL > SC_P_MIPI_DSI0_GPIO0_00 1 > +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT > SC_P_MIPI_DSI0_GPIO0_00 2 > +#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 > SC_P_MIPI_DSI0_GPIO0_00 4 > +#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 > SC_P_MIPI_DSI0_GPIO0_01 0 > +#define SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA > SC_P_MIPI_DSI0_GPIO0_01 1 > +#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 > SC_P_MIPI_DSI0_GPIO0_01 4 > +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL > SC_P_MIPI_DSI1_I2C0_SCL 0 > +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02 > SC_P_MIPI_DSI1_I2C0_SCL 1 > +#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29 > SC_P_MIPI_DSI1_I2C0_SCL 4 > +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA > SC_P_MIPI_DSI1_I2C0_SDA 0 > +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03 > SC_P_MIPI_DSI1_I2C0_SDA 1 > +#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 > SC_P_MIPI_DSI1_I2C0_SDA 4 > +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 > SC_P_MIPI_DSI1_GPIO0_00 0 > +#define SC_P_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL > SC_P_MIPI_DSI1_GPIO0_00 1 > +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT > SC_P_MIPI_DSI1_GPIO0_00 2 > +#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 > SC_P_MIPI_DSI1_GPIO0_00 4 > +#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 > SC_P_MIPI_DSI1_GPIO0_01 0 > +#define SC_P_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA > SC_P_MIPI_DSI1_GPIO0_01 1 > +#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 > SC_P_MIPI_DSI1_GPIO0_01 4 > +#define SC_P_JTAG_TRST_B_SCU_JTAG_TRST_B > SC_P_JTAG_TRST_B 0 > +#define SC_P_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT > SC_P_JTAG_TRST_B 1 > +#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL > SC_P_PMIC_I2C_SCL 0 > +#define SC_P_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON > SC_P_PMIC_I2C_SCL 1 > +#define SC_P_PMIC_I2C_SCL_LSIO_GPIO2_IO01 > SC_P_PMIC_I2C_SCL 4 > +#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA > SC_P_PMIC_I2C_SDA 0 > +#define SC_P_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON > SC_P_PMIC_I2C_SDA 1 > +#define SC_P_PMIC_I2C_SDA_LSIO_GPIO2_IO02 > SC_P_PMIC_I2C_SDA 4 > +#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B > SC_P_PMIC_INT_B 0 > +#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00 > SC_P_SCU_GPIO0_00 0 > +#define SC_P_SCU_GPIO0_00_SCU_UART0_RX > SC_P_SCU_GPIO0_00 1 > +#define SC_P_SCU_GPIO0_00_M40_UART0_RX > SC_P_SCU_GPIO0_00 2 > +#define SC_P_SCU_GPIO0_00_ADMA_UART3_RX > SC_P_SCU_GPIO0_00 3 > +#define SC_P_SCU_GPIO0_00_LSIO_GPIO2_IO03 > SC_P_SCU_GPIO0_00 4 > +#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01 > SC_P_SCU_GPIO0_01 0 > +#define SC_P_SCU_GPIO0_01_SCU_UART0_TX > SC_P_SCU_GPIO0_01 1 > +#define SC_P_SCU_GPIO0_01_M40_UART0_TX > SC_P_SCU_GPIO0_01 2 > +#define SC_P_SCU_GPIO0_01_ADMA_UART3_TX > SC_P_SCU_GPIO0_01 3 > +#define SC_P_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT > SC_P_SCU_GPIO0_01 4 > +#define SC_P_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY > SC_P_SCU_PMIC_STANDBY 0 > +#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 > SC_P_SCU_BOOT_MODE0 0 > +#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 > SC_P_SCU_BOOT_MODE1 0 > +#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 > SC_P_SCU_BOOT_MODE2 0 > +#define SC_P_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA > SC_P_SCU_BOOT_MODE2 1 > +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 > SC_P_SCU_BOOT_MODE3 0 > +#define SC_P_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL > SC_P_SCU_BOOT_MODE3 1 > +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K > SC_P_SCU_BOOT_MODE3 3 > +#define SC_P_CSI_D00_CI_PI_D02 > SC_P_CSI_D00 0 > +#define SC_P_CSI_D00_ADMA_SAI0_RXC > SC_P_CSI_D00 2 > +#define SC_P_CSI_D01_CI_PI_D03 > SC_P_CSI_D01 0 > +#define SC_P_CSI_D01_ADMA_SAI0_RXD > SC_P_CSI_D01 2 > +#define SC_P_CSI_D02_CI_PI_D04 > SC_P_CSI_D02 0 > +#define SC_P_CSI_D02_ADMA_SAI0_RXFS > SC_P_CSI_D02 2 > +#define SC_P_CSI_D03_CI_PI_D05 > SC_P_CSI_D03 0 > +#define SC_P_CSI_D03_ADMA_SAI2_RXC > SC_P_CSI_D03 2 > +#define SC_P_CSI_D04_CI_PI_D06 > SC_P_CSI_D04 0 > +#define SC_P_CSI_D04_ADMA_SAI2_RXD > SC_P_CSI_D04 2 > +#define SC_P_CSI_D05_CI_PI_D07 > SC_P_CSI_D05 0 > +#define SC_P_CSI_D05_ADMA_SAI2_RXFS > SC_P_CSI_D05 2 > +#define SC_P_CSI_D06_CI_PI_D08 > SC_P_CSI_D06 0 > +#define SC_P_CSI_D06_ADMA_SAI3_RXC > SC_P_CSI_D06 2 > +#define SC_P_CSI_D07_CI_PI_D09 > SC_P_CSI_D07 0 > +#define SC_P_CSI_D07_ADMA_SAI3_RXD > SC_P_CSI_D07 2 > +#define SC_P_CSI_HSYNC_CI_PI_HSYNC > SC_P_CSI_HSYNC 0 > +#define SC_P_CSI_HSYNC_CI_PI_D00 > SC_P_CSI_HSYNC 1 > +#define SC_P_CSI_HSYNC_ADMA_SAI3_RXFS > SC_P_CSI_HSYNC 2 > +#define SC_P_CSI_VSYNC_CI_PI_VSYNC > SC_P_CSI_VSYNC 0 > +#define SC_P_CSI_VSYNC_CI_PI_D01 > SC_P_CSI_VSYNC 1 > +#define SC_P_CSI_PCLK_CI_PI_PCLK > SC_P_CSI_PCLK 0 > +#define SC_P_CSI_PCLK_MIPI_CSI0_I2C0_SCL > SC_P_CSI_PCLK 1 > +#define SC_P_CSI_PCLK_ADMA_SPI1_SCK > SC_P_CSI_PCLK 3 > +#define SC_P_CSI_PCLK_LSIO_GPIO3_IO00 > SC_P_CSI_PCLK 4 > +#define SC_P_CSI_MCLK_CI_PI_MCLK > SC_P_CSI_MCLK 0 > +#define SC_P_CSI_MCLK_MIPI_CSI0_I2C0_SDA > SC_P_CSI_MCLK 1 > +#define SC_P_CSI_MCLK_ADMA_SPI1_SDO > SC_P_CSI_MCLK 3 > +#define SC_P_CSI_MCLK_LSIO_GPIO3_IO01 > SC_P_CSI_MCLK 4 > +#define SC_P_CSI_EN_CI_PI_EN > SC_P_CSI_EN 0 > +#define SC_P_CSI_EN_CI_PI_I2C_SCL > SC_P_CSI_EN 1 > +#define SC_P_CSI_EN_ADMA_I2C3_SCL > SC_P_CSI_EN 2 > +#define SC_P_CSI_EN_ADMA_SPI1_SDI > SC_P_CSI_EN 3 > +#define SC_P_CSI_EN_LSIO_GPIO3_IO02 > SC_P_CSI_EN 4 > +#define SC_P_CSI_RESET_CI_PI_RESET > SC_P_CSI_RESET 0 > +#define SC_P_CSI_RESET_CI_PI_I2C_SDA > SC_P_CSI_RESET 1 > +#define SC_P_CSI_RESET_ADMA_I2C3_SDA > SC_P_CSI_RESET 2 > +#define SC_P_CSI_RESET_ADMA_SPI1_CS0 > SC_P_CSI_RESET 3 > +#define SC_P_CSI_RESET_LSIO_GPIO3_IO03 > SC_P_CSI_RESET 4 > +#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT > SC_P_MIPI_CSI0_MCLK_OUT 0 > +#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 > SC_P_MIPI_CSI0_MCLK_OUT 4 > +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL > SC_P_MIPI_CSI0_I2C0_SCL 0 > +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02 > SC_P_MIPI_CSI0_I2C0_SCL 1 > +#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 > SC_P_MIPI_CSI0_I2C0_SCL 4 > +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA > SC_P_MIPI_CSI0_I2C0_SDA 0 > +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03 > SC_P_MIPI_CSI0_I2C0_SDA 1 > +#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 > SC_P_MIPI_CSI0_I2C0_SDA 4 > +#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 > SC_P_MIPI_CSI0_GPIO0_01 0 > +#define SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA > SC_P_MIPI_CSI0_GPIO0_01 1 > +#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 > SC_P_MIPI_CSI0_GPIO0_01 4 > +#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 > SC_P_MIPI_CSI0_GPIO0_00 0 > +#define SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL > SC_P_MIPI_CSI0_GPIO0_00 1 > +#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 > SC_P_MIPI_CSI0_GPIO0_00 4 > +#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 > SC_P_QSPI0A_DATA0 0 > +#define SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 > SC_P_QSPI0A_DATA0 4 > +#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 > SC_P_QSPI0A_DATA1 0 > +#define SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 > SC_P_QSPI0A_DATA1 4 > +#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 > SC_P_QSPI0A_DATA2 0 > +#define SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 > SC_P_QSPI0A_DATA2 4 > +#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 > SC_P_QSPI0A_DATA3 0 > +#define SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 > SC_P_QSPI0A_DATA3 4 > +#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS > SC_P_QSPI0A_DQS 0 > +#define SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 > SC_P_QSPI0A_DQS 4 > +#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B > SC_P_QSPI0A_SS0_B 0 > +#define SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 > SC_P_QSPI0A_SS0_B 4 > +#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B > SC_P_QSPI0A_SS1_B 0 > +#define SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 > SC_P_QSPI0A_SS1_B 4 > +#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK > SC_P_QSPI0A_SCLK 0 > +#define SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 > SC_P_QSPI0A_SCLK 4 > +#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK > SC_P_QSPI0B_SCLK 0 > +#define SC_P_QSPI0B_SCLK_LSIO_QSPI1A_SCLK > SC_P_QSPI0B_SCLK 1 > +#define SC_P_QSPI0B_SCLK_LSIO_KPP0_COL0 > SC_P_QSPI0B_SCLK 2 > +#define SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 > SC_P_QSPI0B_SCLK 4 > +#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 > SC_P_QSPI0B_DATA0 0 > +#define SC_P_QSPI0B_DATA0_LSIO_QSPI1A_DATA0 > SC_P_QSPI0B_DATA0 1 > +#define SC_P_QSPI0B_DATA0_LSIO_KPP0_COL1 > SC_P_QSPI0B_DATA0 2 > +#define SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 > SC_P_QSPI0B_DATA0 4 > +#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 > SC_P_QSPI0B_DATA1 0 > +#define SC_P_QSPI0B_DATA1_LSIO_QSPI1A_DATA1 > SC_P_QSPI0B_DATA1 1 > +#define SC_P_QSPI0B_DATA1_LSIO_KPP0_COL2 > SC_P_QSPI0B_DATA1 2 > +#define SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 > SC_P_QSPI0B_DATA1 4 > +#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 > SC_P_QSPI0B_DATA2 0 > +#define SC_P_QSPI0B_DATA2_LSIO_QSPI1A_DATA2 > SC_P_QSPI0B_DATA2 1 > +#define SC_P_QSPI0B_DATA2_LSIO_KPP0_COL3 > SC_P_QSPI0B_DATA2 2 > +#define SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 > SC_P_QSPI0B_DATA2 4 > +#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 > SC_P_QSPI0B_DATA3 0 > +#define SC_P_QSPI0B_DATA3_LSIO_QSPI1A_DATA3 > SC_P_QSPI0B_DATA3 1 > +#define SC_P_QSPI0B_DATA3_LSIO_KPP0_ROW0 > SC_P_QSPI0B_DATA3 2 > +#define SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 > SC_P_QSPI0B_DATA3 4 > +#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS > SC_P_QSPI0B_DQS 0 > +#define SC_P_QSPI0B_DQS_LSIO_QSPI1A_DQS > SC_P_QSPI0B_DQS 1 > +#define SC_P_QSPI0B_DQS_LSIO_KPP0_ROW1 > SC_P_QSPI0B_DQS 2 > +#define SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 > SC_P_QSPI0B_DQS 4 > +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B > SC_P_QSPI0B_SS0_B 0 > +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B > SC_P_QSPI0B_SS0_B 1 > +#define SC_P_QSPI0B_SS0_B_LSIO_KPP0_ROW2 > SC_P_QSPI0B_SS0_B 2 > +#define SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 > SC_P_QSPI0B_SS0_B 4 > +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B > SC_P_QSPI0B_SS1_B 0 > +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B > SC_P_QSPI0B_SS1_B 1 > +#define SC_P_QSPI0B_SS1_B_LSIO_KPP0_ROW3 > SC_P_QSPI0B_SS1_B 2 > +#define SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 > SC_P_QSPI0B_SS1_B 4 > +/*@}*/ > + > +#endif /* SC_PADS_H */ > + > diff --git a/include/dt-bindings/soc/imx_rsrc.h > b/include/dt-bindings/soc/imx_rsrc.h > new file mode 100644 > index 0000000000..b2154e9a94 > --- /dev/null > +++ b/include/dt-bindings/soc/imx_rsrc.h > @@ -0,0 +1,560 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef DT_BINDINGS_RSCRC_IMX_H > +#define DT_BINDINGS_RSCRC_IMX_H > + > +/*! > + * These defines are used to indicate a resource. Resources include peripherals > + * and bus masters (but not memory regions). Note items from list should > + * never be changed or removed (only added to at the end of the list). > + */ > +#define SC_R_A53 0 > +#define SC_R_A53_0 1 > +#define SC_R_A53_1 2 > +#define SC_R_A53_2 3 > +#define SC_R_A53_3 4 > +#define SC_R_A72 5 > +#define SC_R_A72_0 6 > +#define SC_R_A72_1 7 > +#define SC_R_A72_2 8 > +#define SC_R_A72_3 9 > +#define SC_R_CCI 10 > +#define SC_R_DB 11 > +#define SC_R_DRC_0 12 > +#define SC_R_DRC_1 13 > +#define SC_R_GIC_SMMU 14 > +#define SC_R_IRQSTR_M4_0 15 > +#define SC_R_IRQSTR_M4_1 16 > +#define SC_R_SMMU 17 > +#define SC_R_GIC 18 > +#define SC_R_DC_0_BLIT0 19 > +#define SC_R_DC_0_BLIT1 20 > +#define SC_R_DC_0_BLIT2 21 > +#define SC_R_DC_0_BLIT_OUT 22 > +#define SC_R_DC_0_CAPTURE0 23 > +#define SC_R_DC_0_CAPTURE1 24 > +#define SC_R_DC_0_WARP 25 > +#define SC_R_DC_0_INTEGRAL0 26 > +#define SC_R_DC_0_INTEGRAL1 27 > +#define SC_R_DC_0_VIDEO0 28 > +#define SC_R_DC_0_VIDEO1 29 > +#define SC_R_DC_0_FRAC0 30 > +#define SC_R_DC_0_FRAC1 31 > +#define SC_R_DC_0 32 > +#define SC_R_GPU_2_PID0 33 > +#define SC_R_DC_0_PLL_0 34 > +#define SC_R_DC_0_PLL_1 35 > +#define SC_R_DC_1_BLIT0 36 > +#define SC_R_DC_1_BLIT1 37 > +#define SC_R_DC_1_BLIT2 38 > +#define SC_R_DC_1_BLIT_OUT 39 > +#define SC_R_DC_1_CAPTURE0 40 > +#define SC_R_DC_1_CAPTURE1 41 > +#define SC_R_DC_1_WARP 42 > +#define SC_R_DC_1_INTEGRAL0 43 > +#define SC_R_DC_1_INTEGRAL1 44 > +#define SC_R_DC_1_VIDEO0 45 > +#define SC_R_DC_1_VIDEO1 46 > +#define SC_R_DC_1_FRAC0 47 > +#define SC_R_DC_1_FRAC1 48 > +#define SC_R_DC_1 49 > +#define SC_R_GPU_3_PID0 50 > +#define SC_R_DC_1_PLL_0 51 > +#define SC_R_DC_1_PLL_1 52 > +#define SC_R_SPI_0 53 > +#define SC_R_SPI_1 54 > +#define SC_R_SPI_2 55 > +#define SC_R_SPI_3 56 > +#define SC_R_UART_0 57 > +#define SC_R_UART_1 58 > +#define SC_R_UART_2 59 > +#define SC_R_UART_3 60 > +#define SC_R_UART_4 61 > +#define SC_R_EMVSIM_0 62 > +#define SC_R_EMVSIM_1 63 > +#define SC_R_DMA_0_CH0 64 > +#define SC_R_DMA_0_CH1 65 > +#define SC_R_DMA_0_CH2 66 > +#define SC_R_DMA_0_CH3 67 > +#define SC_R_DMA_0_CH4 68 > +#define SC_R_DMA_0_CH5 69 > +#define SC_R_DMA_0_CH6 70 > +#define SC_R_DMA_0_CH7 71 > +#define SC_R_DMA_0_CH8 72 > +#define SC_R_DMA_0_CH9 73 > +#define SC_R_DMA_0_CH10 74 > +#define SC_R_DMA_0_CH11 75 > +#define SC_R_DMA_0_CH12 76 > +#define SC_R_DMA_0_CH13 77 > +#define SC_R_DMA_0_CH14 78 > +#define SC_R_DMA_0_CH15 79 > +#define SC_R_DMA_0_CH16 80 > +#define SC_R_DMA_0_CH17 81 > +#define SC_R_DMA_0_CH18 82 > +#define SC_R_DMA_0_CH19 83 > +#define SC_R_DMA_0_CH20 84 > +#define SC_R_DMA_0_CH21 85 > +#define SC_R_DMA_0_CH22 86 > +#define SC_R_DMA_0_CH23 87 > +#define SC_R_DMA_0_CH24 88 > +#define SC_R_DMA_0_CH25 89 > +#define SC_R_DMA_0_CH26 90 > +#define SC_R_DMA_0_CH27 91 > +#define SC_R_DMA_0_CH28 92 > +#define SC_R_DMA_0_CH29 93 > +#define SC_R_DMA_0_CH30 94 > +#define SC_R_DMA_0_CH31 95 > +#define SC_R_I2C_0 96 > +#define SC_R_I2C_1 97 > +#define SC_R_I2C_2 98 > +#define SC_R_I2C_3 99 > +#define SC_R_I2C_4 100 > +#define SC_R_ADC_0 101 > +#define SC_R_ADC_1 102 > +#define SC_R_FTM_0 103 > +#define SC_R_FTM_1 104 > +#define SC_R_CAN_0 105 > +#define SC_R_CAN_1 106 > +#define SC_R_CAN_2 107 > +#define SC_R_DMA_1_CH0 108 > +#define SC_R_DMA_1_CH1 109 > +#define SC_R_DMA_1_CH2 110 > +#define SC_R_DMA_1_CH3 111 > +#define SC_R_DMA_1_CH4 112 > +#define SC_R_DMA_1_CH5 113 > +#define SC_R_DMA_1_CH6 114 > +#define SC_R_DMA_1_CH7 115 > +#define SC_R_DMA_1_CH8 116 > +#define SC_R_DMA_1_CH9 117 > +#define SC_R_DMA_1_CH10 118 > +#define SC_R_DMA_1_CH11 119 > +#define SC_R_DMA_1_CH12 120 > +#define SC_R_DMA_1_CH13 121 > +#define SC_R_DMA_1_CH14 122 > +#define SC_R_DMA_1_CH15 123 > +#define SC_R_DMA_1_CH16 124 > +#define SC_R_DMA_1_CH17 125 > +#define SC_R_DMA_1_CH18 126 > +#define SC_R_DMA_1_CH19 127 > +#define SC_R_DMA_1_CH20 128 > +#define SC_R_DMA_1_CH21 129 > +#define SC_R_DMA_1_CH22 130 > +#define SC_R_DMA_1_CH23 131 > +#define SC_R_DMA_1_CH24 132 > +#define SC_R_DMA_1_CH25 133 > +#define SC_R_DMA_1_CH26 134 > +#define SC_R_DMA_1_CH27 135 > +#define SC_R_DMA_1_CH28 136 > +#define SC_R_DMA_1_CH29 137 > +#define SC_R_DMA_1_CH30 138 > +#define SC_R_DMA_1_CH31 139 > +#define SC_R_UNUSED1 140 > +#define SC_R_UNUSED2 141 > +#define SC_R_UNUSED3 142 > +#define SC_R_UNUSED4 143 > +#define SC_R_GPU_0_PID0 144 > +#define SC_R_GPU_0_PID1 145 > +#define SC_R_GPU_0_PID2 146 > +#define SC_R_GPU_0_PID3 147 > +#define SC_R_GPU_1_PID0 148 > +#define SC_R_GPU_1_PID1 149 > +#define SC_R_GPU_1_PID2 150 > +#define SC_R_GPU_1_PID3 151 > +#define SC_R_PCIE_A 152 > +#define SC_R_SERDES_0 153 > +#define SC_R_MATCH_0 154 > +#define SC_R_MATCH_1 155 > +#define SC_R_MATCH_2 156 > +#define SC_R_MATCH_3 157 > +#define SC_R_MATCH_4 158 > +#define SC_R_MATCH_5 159 > +#define SC_R_MATCH_6 160 > +#define SC_R_MATCH_7 161 > +#define SC_R_MATCH_8 162 > +#define SC_R_MATCH_9 163 > +#define SC_R_MATCH_10 164 > +#define SC_R_MATCH_11 165 > +#define SC_R_MATCH_12 166 > +#define SC_R_MATCH_13 167 > +#define SC_R_MATCH_14 168 > +#define SC_R_PCIE_B 169 > +#define SC_R_SATA_0 170 > +#define SC_R_SERDES_1 171 > +#define SC_R_HSIO_GPIO 172 > +#define SC_R_MATCH_15 173 > +#define SC_R_MATCH_16 174 > +#define SC_R_MATCH_17 175 > +#define SC_R_MATCH_18 176 > +#define SC_R_MATCH_19 177 > +#define SC_R_MATCH_20 178 > +#define SC_R_MATCH_21 179 > +#define SC_R_MATCH_22 180 > +#define SC_R_MATCH_23 181 > +#define SC_R_MATCH_24 182 > +#define SC_R_MATCH_25 183 > +#define SC_R_MATCH_26 184 > +#define SC_R_MATCH_27 185 > +#define SC_R_MATCH_28 186 > +#define SC_R_LCD_0 187 > +#define SC_R_LCD_0_PWM_0 188 > +#define SC_R_LCD_0_I2C_0 189 > +#define SC_R_LCD_0_I2C_1 190 > +#define SC_R_PWM_0 191 > +#define SC_R_PWM_1 192 > +#define SC_R_PWM_2 193 > +#define SC_R_PWM_3 194 > +#define SC_R_PWM_4 195 > +#define SC_R_PWM_5 196 > +#define SC_R_PWM_6 197 > +#define SC_R_PWM_7 198 > +#define SC_R_GPIO_0 199 > +#define SC_R_GPIO_1 200 > +#define SC_R_GPIO_2 201 > +#define SC_R_GPIO_3 202 > +#define SC_R_GPIO_4 203 > +#define SC_R_GPIO_5 204 > +#define SC_R_GPIO_6 205 > +#define SC_R_GPIO_7 206 > +#define SC_R_GPT_0 207 > +#define SC_R_GPT_1 208 > +#define SC_R_GPT_2 209 > +#define SC_R_GPT_3 210 > +#define SC_R_GPT_4 211 > +#define SC_R_KPP 212 > +#define SC_R_MU_0A 213 > +#define SC_R_MU_1A 214 > +#define SC_R_MU_2A 215 > +#define SC_R_MU_3A 216 > +#define SC_R_MU_4A 217 > +#define SC_R_MU_5A 218 > +#define SC_R_MU_6A 219 > +#define SC_R_MU_7A 220 > +#define SC_R_MU_8A 221 > +#define SC_R_MU_9A 222 > +#define SC_R_MU_10A 223 > +#define SC_R_MU_11A 224 > +#define SC_R_MU_12A 225 > +#define SC_R_MU_13A 226 > +#define SC_R_MU_5B 227 > +#define SC_R_MU_6B 228 > +#define SC_R_MU_7B 229 > +#define SC_R_MU_8B 230 > +#define SC_R_MU_9B 231 > +#define SC_R_MU_10B 232 > +#define SC_R_MU_11B 233 > +#define SC_R_MU_12B 234 > +#define SC_R_MU_13B 235 > +#define SC_R_ROM_0 236 > +#define SC_R_FSPI_0 237 > +#define SC_R_FSPI_1 238 > +#define SC_R_IEE 239 > +#define SC_R_IEE_R0 240 > +#define SC_R_IEE_R1 241 > +#define SC_R_IEE_R2 242 > +#define SC_R_IEE_R3 243 > +#define SC_R_IEE_R4 244 > +#define SC_R_IEE_R5 245 > +#define SC_R_IEE_R6 246 > +#define SC_R_IEE_R7 247 > +#define SC_R_SDHC_0 248 > +#define SC_R_SDHC_1 249 > +#define SC_R_SDHC_2 250 > +#define SC_R_ENET_0 251 > +#define SC_R_ENET_1 252 > +#define SC_R_MLB_0 253 > +#define SC_R_DMA_2_CH0 254 > +#define SC_R_DMA_2_CH1 255 > +#define SC_R_DMA_2_CH2 256 > +#define SC_R_DMA_2_CH3 257 > +#define SC_R_DMA_2_CH4 258 > +#define SC_R_USB_0 259 > +#define SC_R_USB_1 260 > +#define SC_R_USB_0_PHY 261 > +#define SC_R_USB_2 262 > +#define SC_R_USB_2_PHY 263 > +#define SC_R_DTCP 264 > +#define SC_R_NAND 265 > +#define SC_R_LVDS_0 266 > +#define SC_R_LVDS_0_PWM_0 267 > +#define SC_R_LVDS_0_I2C_0 268 > +#define SC_R_LVDS_0_I2C_1 269 > +#define SC_R_LVDS_1 270 > +#define SC_R_LVDS_1_PWM_0 271 > +#define SC_R_LVDS_1_I2C_0 272 > +#define SC_R_LVDS_1_I2C_1 273 > +#define SC_R_LVDS_2 274 > +#define SC_R_LVDS_2_PWM_0 275 > +#define SC_R_LVDS_2_I2C_0 276 > +#define SC_R_LVDS_2_I2C_1 277 > +#define SC_R_M4_0_PID0 278 > +#define SC_R_M4_0_PID1 279 > +#define SC_R_M4_0_PID2 280 > +#define SC_R_M4_0_PID3 281 > +#define SC_R_M4_0_PID4 282 > +#define SC_R_M4_0_RGPIO 283 > +#define SC_R_M4_0_SEMA42 284 > +#define SC_R_M4_0_TPM 285 > +#define SC_R_M4_0_PIT 286 > +#define SC_R_M4_0_UART 287 > +#define SC_R_M4_0_I2C 288 > +#define SC_R_M4_0_INTMUX 289 > +#define SC_R_M4_0_SIM 290 > +#define SC_R_M4_0_WDOG 291 > +#define SC_R_M4_0_MU_0B 292 > +#define SC_R_M4_0_MU_0A0 293 > +#define SC_R_M4_0_MU_0A1 294 > +#define SC_R_M4_0_MU_0A2 295 > +#define SC_R_M4_0_MU_0A3 296 > +#define SC_R_M4_0_MU_1A 297 > +#define SC_R_M4_1_PID0 298 > +#define SC_R_M4_1_PID1 299 > +#define SC_R_M4_1_PID2 300 > +#define SC_R_M4_1_PID3 301 > +#define SC_R_M4_1_PID4 302 > +#define SC_R_M4_1_RGPIO 303 > +#define SC_R_M4_1_SEMA42 304 > +#define SC_R_M4_1_TPM 305 > +#define SC_R_M4_1_PIT 306 > +#define SC_R_M4_1_UART 307 > +#define SC_R_M4_1_I2C 308 > +#define SC_R_M4_1_INTMUX 309 > +#define SC_R_M4_1_SIM 310 > +#define SC_R_M4_1_WDOG 311 > +#define SC_R_M4_1_MU_0B 312 > +#define SC_R_M4_1_MU_0A0 313 > +#define SC_R_M4_1_MU_0A1 314 > +#define SC_R_M4_1_MU_0A2 315 > +#define SC_R_M4_1_MU_0A3 316 > +#define SC_R_M4_1_MU_1A 317 > +#define SC_R_SAI_0 318 > +#define SC_R_SAI_1 319 > +#define SC_R_SAI_2 320 > +#define SC_R_IRQSTR_SCU2 321 > +#define SC_R_IRQSTR_DSP 322 > +#define SC_R_UNUSED5 323 > +#define SC_R_OCRAM 324 > +#define SC_R_AUDIO_PLL_0 325 > +#define SC_R_PI_0 326 > +#define SC_R_PI_0_PWM_0 327 > +#define SC_R_PI_0_PWM_1 328 > +#define SC_R_PI_0_I2C_0 329 > +#define SC_R_PI_0_PLL 330 > +#define SC_R_PI_1 331 > +#define SC_R_PI_1_PWM_0 332 > +#define SC_R_PI_1_PWM_1 333 > +#define SC_R_PI_1_I2C_0 334 > +#define SC_R_PI_1_PLL 335 > +#define SC_R_SC_PID0 336 > +#define SC_R_SC_PID1 337 > +#define SC_R_SC_PID2 338 > +#define SC_R_SC_PID3 339 > +#define SC_R_SC_PID4 340 > +#define SC_R_SC_SEMA42 341 > +#define SC_R_SC_TPM 342 > +#define SC_R_SC_PIT 343 > +#define SC_R_SC_UART 344 > +#define SC_R_SC_I2C 345 > +#define SC_R_SC_MU_0B 346 > +#define SC_R_SC_MU_0A0 347 > +#define SC_R_SC_MU_0A1 348 > +#define SC_R_SC_MU_0A2 349 > +#define SC_R_SC_MU_0A3 350 > +#define SC_R_SC_MU_1A 351 > +#define SC_R_SYSCNT_RD 352 > +#define SC_R_SYSCNT_CMP 353 > +#define SC_R_DEBUG 354 > +#define SC_R_SYSTEM 355 > +#define SC_R_SNVS 356 > +#define SC_R_OTP 357 > +#define SC_R_VPU_PID0 358 > +#define SC_R_VPU_PID1 359 > +#define SC_R_VPU_PID2 360 > +#define SC_R_VPU_PID3 361 > +#define SC_R_VPU_PID4 362 > +#define SC_R_VPU_PID5 363 > +#define SC_R_VPU_PID6 364 > +#define SC_R_VPU_PID7 365 > +#define SC_R_VPU_UART 366 > +#define SC_R_VPUCORE 367 > +#define SC_R_VPUCORE_0 368 > +#define SC_R_VPUCORE_1 369 > +#define SC_R_VPUCORE_2 370 > +#define SC_R_VPUCORE_3 371 > +#define SC_R_DMA_4_CH0 372 > +#define SC_R_DMA_4_CH1 373 > +#define SC_R_DMA_4_CH2 374 > +#define SC_R_DMA_4_CH3 375 > +#define SC_R_DMA_4_CH4 376 > +#define SC_R_ISI_CH0 377 > +#define SC_R_ISI_CH1 378 > +#define SC_R_ISI_CH2 379 > +#define SC_R_ISI_CH3 380 > +#define SC_R_ISI_CH4 381 > +#define SC_R_ISI_CH5 382 > +#define SC_R_ISI_CH6 383 > +#define SC_R_ISI_CH7 384 > +#define SC_R_MJPEG_DEC_S0 385 > +#define SC_R_MJPEG_DEC_S1 386 > +#define SC_R_MJPEG_DEC_S2 387 > +#define SC_R_MJPEG_DEC_S3 388 > +#define SC_R_MJPEG_ENC_S0 389 > +#define SC_R_MJPEG_ENC_S1 390 > +#define SC_R_MJPEG_ENC_S2 391 > +#define SC_R_MJPEG_ENC_S3 392 > +#define SC_R_MIPI_0 393 > +#define SC_R_MIPI_0_PWM_0 394 > +#define SC_R_MIPI_0_I2C_0 395 > +#define SC_R_MIPI_0_I2C_1 396 > +#define SC_R_MIPI_1 397 > +#define SC_R_MIPI_1_PWM_0 398 > +#define SC_R_MIPI_1_I2C_0 399 > +#define SC_R_MIPI_1_I2C_1 400 > +#define SC_R_CSI_0 401 > +#define SC_R_CSI_0_PWM_0 402 > +#define SC_R_CSI_0_I2C_0 403 > +#define SC_R_CSI_1 404 > +#define SC_R_CSI_1_PWM_0 405 > +#define SC_R_CSI_1_I2C_0 406 > +#define SC_R_HDMI 407 > +#define SC_R_HDMI_I2S 408 > +#define SC_R_HDMI_I2C_0 409 > +#define SC_R_HDMI_PLL_0 410 > +#define SC_R_HDMI_RX 411 > +#define SC_R_HDMI_RX_BYPASS 412 > +#define SC_R_HDMI_RX_I2C_0 413 > +#define SC_R_ASRC_0 414 > +#define SC_R_ESAI_0 415 > +#define SC_R_SPDIF_0 416 > +#define SC_R_SPDIF_1 417 > +#define SC_R_SAI_3 418 > +#define SC_R_SAI_4 419 > +#define SC_R_SAI_5 420 > +#define SC_R_GPT_5 421 > +#define SC_R_GPT_6 422 > +#define SC_R_GPT_7 423 > +#define SC_R_GPT_8 424 > +#define SC_R_GPT_9 425 > +#define SC_R_GPT_10 426 > +#define SC_R_DMA_2_CH5 427 > +#define SC_R_DMA_2_CH6 428 > +#define SC_R_DMA_2_CH7 429 > +#define SC_R_DMA_2_CH8 430 > +#define SC_R_DMA_2_CH9 431 > +#define SC_R_DMA_2_CH10 432 > +#define SC_R_DMA_2_CH11 433 > +#define SC_R_DMA_2_CH12 434 > +#define SC_R_DMA_2_CH13 435 > +#define SC_R_DMA_2_CH14 436 > +#define SC_R_DMA_2_CH15 437 > +#define SC_R_DMA_2_CH16 438 > +#define SC_R_DMA_2_CH17 439 > +#define SC_R_DMA_2_CH18 440 > +#define SC_R_DMA_2_CH19 441 > +#define SC_R_DMA_2_CH20 442 > +#define SC_R_DMA_2_CH21 443 > +#define SC_R_DMA_2_CH22 444 > +#define SC_R_DMA_2_CH23 445 > +#define SC_R_DMA_2_CH24 446 > +#define SC_R_DMA_2_CH25 447 > +#define SC_R_DMA_2_CH26 448 > +#define SC_R_DMA_2_CH27 449 > +#define SC_R_DMA_2_CH28 450 > +#define SC_R_DMA_2_CH29 451 > +#define SC_R_DMA_2_CH30 452 > +#define SC_R_DMA_2_CH31 453 > +#define SC_R_ASRC_1 454 > +#define SC_R_ESAI_1 455 > +#define SC_R_SAI_6 456 > +#define SC_R_SAI_7 457 > +#define SC_R_AMIX 458 > +#define SC_R_MQS_0 459 > +#define SC_R_DMA_3_CH0 460 > +#define SC_R_DMA_3_CH1 461 > +#define SC_R_DMA_3_CH2 462 > +#define SC_R_DMA_3_CH3 463 > +#define SC_R_DMA_3_CH4 464 > +#define SC_R_DMA_3_CH5 465 > +#define SC_R_DMA_3_CH6 466 > +#define SC_R_DMA_3_CH7 467 > +#define SC_R_DMA_3_CH8 468 > +#define SC_R_DMA_3_CH9 469 > +#define SC_R_DMA_3_CH10 470 > +#define SC_R_DMA_3_CH11 471 > +#define SC_R_DMA_3_CH12 472 > +#define SC_R_DMA_3_CH13 473 > +#define SC_R_DMA_3_CH14 474 > +#define SC_R_DMA_3_CH15 475 > +#define SC_R_DMA_3_CH16 476 > +#define SC_R_DMA_3_CH17 477 > +#define SC_R_DMA_3_CH18 478 > +#define SC_R_DMA_3_CH19 479 > +#define SC_R_DMA_3_CH20 480 > +#define SC_R_DMA_3_CH21 481 > +#define SC_R_DMA_3_CH22 482 > +#define SC_R_DMA_3_CH23 483 > +#define SC_R_DMA_3_CH24 484 > +#define SC_R_DMA_3_CH25 485 > +#define SC_R_DMA_3_CH26 486 > +#define SC_R_DMA_3_CH27 487 > +#define SC_R_DMA_3_CH28 488 > +#define SC_R_DMA_3_CH29 489 > +#define SC_R_DMA_3_CH30 490 > +#define SC_R_DMA_3_CH31 491 > +#define SC_R_AUDIO_PLL_1 492 > +#define SC_R_AUDIO_CLK_0 493 > +#define SC_R_AUDIO_CLK_1 494 > +#define SC_R_MCLK_OUT_0 495 > +#define SC_R_MCLK_OUT_1 496 > +#define SC_R_PMIC_0 497 > +#define SC_R_PMIC_1 498 > +#define SC_R_SECO 499 > +#define SC_R_CAAM_JR1 500 > +#define SC_R_CAAM_JR2 501 > +#define SC_R_CAAM_JR3 502 > +#define SC_R_SECO_MU_2 503 > +#define SC_R_SECO_MU_3 504 > +#define SC_R_SECO_MU_4 505 > +#define SC_R_HDMI_RX_PWM_0 506 > +#define SC_R_A35 507 > +#define SC_R_A35_0 508 > +#define SC_R_A35_1 509 > +#define SC_R_A35_2 510 > +#define SC_R_A35_3 511 > +#define SC_R_DSP 512 > +#define SC_R_DSP_RAM 513 > +#define SC_R_CAAM_JR1_OUT 514 > +#define SC_R_CAAM_JR2_OUT 515 > +#define SC_R_CAAM_JR3_OUT 516 > +#define SC_R_VPU_DEC_0 517 > +#define SC_R_VPU_ENC_0 518 > +#define SC_R_CAAM_JR0 519 > +#define SC_R_CAAM_JR0_OUT 520 > +#define SC_R_PMIC_2 521 > +#define SC_R_DBLOGIC 522 > +#define SC_R_HDMI_PLL_1 523 > +#define SC_R_BOARD_R0 524 > +#define SC_R_BOARD_R1 525 > +#define SC_R_BOARD_R2 526 > +#define SC_R_BOARD_R3 527 > +#define SC_R_BOARD_R4 528 > +#define SC_R_BOARD_R5 529 > +#define SC_R_BOARD_R6 530 > +#define SC_R_BOARD_R7 531 > +#define SC_R_MJPEG_DEC_MP 532 > +#define SC_R_MJPEG_ENC_MP 533 > +#define SC_R_VPU_TS_0 534 > +#define SC_R_VPU_MU_0 535 > +#define SC_R_VPU_MU_1 536 > +#define SC_R_VPU_MU_2 537 > +#define SC_R_VPU_MU_3 538 > +#define SC_R_VPU_ENC_1 539 > +#define SC_R_VPU 540 > +#define SC_R_LAST 541 > + > +#endif /* DT_BINDINGS_RSCRC_IMX_H */ > + > -- > 2.14.1 ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 02/41] imx: add Kconfig entry for i.MX8 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 01/41] imx: import SCFW API Peng Fan @ 2018-05-28 12:24 ` Peng Fan 2018-06-27 8:19 ` Stefano Babic 2018-05-28 12:24 ` [U-Boot] [PATCH 03/41] arm: build mach-imx " Peng Fan ` (40 subsequent siblings) 42 siblings, 1 reply; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:24 UTC (permalink / raw) To: u-boot Add Kconfig entry for i.MX8 and i.MX8QXP Select HAVE_SC_FIRMWARE for i.MX8QXP Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/Kconfig | 8 ++++++++ arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/imx8/Kconfig | 13 +++++++++++++ 3 files changed, 22 insertions(+) create mode 100644 arch/arm/mach-imx/imx8/Kconfig diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3e05f79f63..0406c1dada 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -635,6 +635,12 @@ config ARCH_MESON targeted at media players and tablet computers. We currently support the S905 (GXBaby) 64-bit SoC. +config ARCH_IMX8 + bool "NXP i.MX8 platform" + select ARM64 + select DM + select OF_CONTROL + config ARCH_MX8M bool "NXP i.MX8M platform" select ARM64 @@ -1325,6 +1331,8 @@ source "arch/arm/mach-imx/mx7/Kconfig" source "arch/arm/mach-imx/mx7ulp/Kconfig" +source "arch/arm/mach-imx/imx8/Kconfig" + source "arch/arm/mach-imx/mx8m/Kconfig" source "arch/arm/mach-imx/mxs/Kconfig" diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 733c308670..375789efb2 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -141,3 +141,4 @@ obj-$(CONFIG_MX6) += mx6/ obj-$(CONFIG_MX7) += mx7/ obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/ obj-$(CONFIG_MX8M) += mx8m/ +obj-$(CONFIG_ARCH_IMX8) += imx8/ diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig new file mode 100644 index 0000000000..58cb19946f --- /dev/null +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -0,0 +1,13 @@ +if ARCH_IMX8 + +config IMX8 + bool + default y + +config IMX8QXP + bool + +config SYS_SOC + default "imx8" + +endif -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 02/41] imx: add Kconfig entry for i.MX8 2018-05-28 12:24 ` [U-Boot] [PATCH 02/41] imx: add Kconfig entry for i.MX8 Peng Fan @ 2018-06-27 8:19 ` Stefano Babic 2018-07-07 12:46 ` Peng Fan 0 siblings, 1 reply; 69+ messages in thread From: Stefano Babic @ 2018-06-27 8:19 UTC (permalink / raw) To: u-boot On 28/05/2018 14:24, Peng Fan wrote: > Add Kconfig entry for i.MX8 and i.MX8QXP > Select HAVE_SC_FIRMWARE for i.MX8QXP > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > arch/arm/Kconfig | 8 ++++++++ > arch/arm/mach-imx/Makefile | 1 + > arch/arm/mach-imx/imx8/Kconfig | 13 +++++++++++++ > 3 files changed, 22 insertions(+) > create mode 100644 arch/arm/mach-imx/imx8/Kconfig > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 3e05f79f63..0406c1dada 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -635,6 +635,12 @@ config ARCH_MESON > targeted at media players and tablet computers. We currently > support the S905 (GXBaby) 64-bit SoC. > > +config ARCH_IMX8 > + bool "NXP i.MX8 platform" > + select ARM64 > + select DM > + select OF_CONTROL > + > config ARCH_MX8M > bool "NXP i.MX8M platform" > select ARM64 > @@ -1325,6 +1331,8 @@ source "arch/arm/mach-imx/mx7/Kconfig" > > source "arch/arm/mach-imx/mx7ulp/Kconfig" > > +source "arch/arm/mach-imx/imx8/Kconfig" > + > source "arch/arm/mach-imx/mx8m/Kconfig" > > source "arch/arm/mach-imx/mxs/Kconfig" > diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile > index 733c308670..375789efb2 100644 > --- a/arch/arm/mach-imx/Makefile > +++ b/arch/arm/mach-imx/Makefile > @@ -141,3 +141,4 @@ obj-$(CONFIG_MX6) += mx6/ > obj-$(CONFIG_MX7) += mx7/ > obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/ > obj-$(CONFIG_MX8M) += mx8m/ > +obj-$(CONFIG_ARCH_IMX8) += imx8/ > diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig > new file mode 100644 > index 0000000000..58cb19946f > --- /dev/null > +++ b/arch/arm/mach-imx/imx8/Kconfig > @@ -0,0 +1,13 @@ > +if ARCH_IMX8 > + > +config IMX8 > + bool > + default y > + > +config IMX8QXP > + bool > + > +config SYS_SOC > + default "imx8" > + > +endif > Just to be sure. We introduce several switches: ARCH_IMX8 ==> architecture IMX8 ==> set for all SOC variants IMX8QXP ==> specific variant then we will have, as usual, a TARGET_ for the board. This reflects the MX6, yes (but why do you introduce a "I" in the name ? Shouldn't we use MX8 instead of IMX8 ?). Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 02/41] imx: add Kconfig entry for i.MX8 2018-06-27 8:19 ` Stefano Babic @ 2018-07-07 12:46 ` Peng Fan 0 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-07-07 12:46 UTC (permalink / raw) To: u-boot Hi Stefano, > -----Original Message----- > From: Stefano Babic [mailto:sbabic at denx.de] > Sent: 2018年6月27日 16:20 > To: Peng Fan <peng.fan@nxp.com>; sbabic at denx.de; Fabio Estevam > <fabio.estevam@nxp.com> > Cc: u-boot at lists.denx.de > Subject: Re: [PATCH 02/41] imx: add Kconfig entry for i.MX8 > > On 28/05/2018 14:24, Peng Fan wrote: > > Add Kconfig entry for i.MX8 and i.MX8QXP Select HAVE_SC_FIRMWARE for > > i.MX8QXP > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > > --- > > arch/arm/Kconfig | 8 ++++++++ > > arch/arm/mach-imx/Makefile | 1 + > > arch/arm/mach-imx/imx8/Kconfig | 13 +++++++++++++ > > 3 files changed, 22 insertions(+) > > create mode 100644 arch/arm/mach-imx/imx8/Kconfig > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index > > 3e05f79f63..0406c1dada 100644 > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -635,6 +635,12 @@ config ARCH_MESON > > targeted at media players and tablet computers. We currently > > support the S905 (GXBaby) 64-bit SoC. > > > > +config ARCH_IMX8 > > + bool "NXP i.MX8 platform" > > + select ARM64 > > + select DM > > + select OF_CONTROL > > + > > config ARCH_MX8M > > bool "NXP i.MX8M platform" > > select ARM64 > > @@ -1325,6 +1331,8 @@ source "arch/arm/mach-imx/mx7/Kconfig" > > > > source "arch/arm/mach-imx/mx7ulp/Kconfig" > > > > +source "arch/arm/mach-imx/imx8/Kconfig" > > + > > source "arch/arm/mach-imx/mx8m/Kconfig" > > > > source "arch/arm/mach-imx/mxs/Kconfig" > > diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile > > index 733c308670..375789efb2 100644 > > --- a/arch/arm/mach-imx/Makefile > > +++ b/arch/arm/mach-imx/Makefile > > @@ -141,3 +141,4 @@ obj-$(CONFIG_MX6) += mx6/ > > obj-$(CONFIG_MX7) += mx7/ > > obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/ > > obj-$(CONFIG_MX8M) += mx8m/ > > +obj-$(CONFIG_ARCH_IMX8) += imx8/ > > diff --git a/arch/arm/mach-imx/imx8/Kconfig > > b/arch/arm/mach-imx/imx8/Kconfig new file mode 100644 index > > 0000000000..58cb19946f > > --- /dev/null > > +++ b/arch/arm/mach-imx/imx8/Kconfig > > @@ -0,0 +1,13 @@ > > +if ARCH_IMX8 > > + > > +config IMX8 > > + bool > > + default y > > + > > +config IMX8QXP > > + bool > > + > > +config SYS_SOC > > + default "imx8" > > + > > +endif > > > > Just to be sure. We introduce several switches: > > ARCH_IMX8 ==> architecture > IMX8 ==> set for all SOC variants > IMX8QXP ==> specific variant > > then we will have, as usual, a TARGET_ for the board. This reflects the MX6, yes > (but why do you introduce a "I" in the name ? Shouldn't we use > MX8 instead of IMX8 ?). We are asked to use IMX8 to better reflect i.MX8 from marketing team. So we switch to use IMX8 for i.MX8 Family. Thanks, Peng. > > Best regards, > Stefano Babic > > -- > ================================================================ > ===== > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de > ================================================================ > ===== ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 03/41] arm: build mach-imx for i.MX8 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 01/41] imx: import SCFW API Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 02/41] imx: add Kconfig entry for i.MX8 Peng Fan @ 2018-05-28 12:24 ` Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 04/41] imx8: add IPC communication support between ACore and SCU Peng Fan ` (39 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:24 UTC (permalink / raw) To: u-boot Build mach-imx for i.MX8 Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 4d6d276137..9aadb7a49a 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -101,7 +101,7 @@ ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 libs-y += arch/arm/mach-imx/ endif else -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m vf610)) +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m imx8 vf610)) libs-y += arch/arm/mach-imx/ endif endif -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 04/41] imx8: add IPC communication support between ACore and SCU 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (2 preceding siblings ...) 2018-05-28 12:24 ` [U-Boot] [PATCH 03/41] arm: build mach-imx " Peng Fan @ 2018-05-28 12:24 ` Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 05/41] arm: global_data: introduce ipc_channel_handle Peng Fan ` (38 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:24 UTC (permalink / raw) To: u-boot The IPC communication is based on Message Unit(MU) between ACore and SCU. Add the lowlevel MU initialization, message send/receive code. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/include/asm/arch-imx8/fsl_mu_hal.h | 54 +++++++++++++++ arch/arm/include/asm/arch-imx8/sci/sci.h | 39 +++++++++++ arch/arm/mach-imx/imx8/Makefile | 1 + arch/arm/mach-imx/imx8/fsl_mu_hal.c | 28 ++++++++ arch/arm/mach-imx/imx8/sci/ipc.c | 100 ++++++++++++++++++++++++++++ 5 files changed, 222 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8/fsl_mu_hal.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/sci.h create mode 100644 arch/arm/mach-imx/imx8/fsl_mu_hal.c create mode 100644 arch/arm/mach-imx/imx8/sci/ipc.c diff --git a/arch/arm/include/asm/arch-imx8/fsl_mu_hal.h b/arch/arm/include/asm/arch-imx8/fsl_mu_hal.h new file mode 100644 index 0000000000..a7b9518604 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/fsl_mu_hal.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __FSL_MU_HAL_H__ +#define __FSL_MU_HAL_H__ + +#include <asm/io.h> +#include <linux/bitops.h> + +struct mu_type { + u32 tr[4]; + u32 rr[4]; + u32 sr; + u32 cr; +}; + +#define MU_SR_GIP0_MASK BIT(31) +#define MU_SR_RF0_MASK BIT(27) +#define MU_SR_TE0_MASK BIT(23) +#define MU_CR_GIE0_MASK BIT(31) +#define MU_CR_RIE0_MASK BIT(27) +#define MU_CR_TIE0_MASK BIT(23) +#define MU_CR_GIR0_MASK BIT(19) + +#define MU_CR_GIEn_MASK 0xF0000000u +#define MU_CR_RIEn_MASK 0x0F000000u +#define MU_CR_TIEn_MASK 0x00F00000u +#define MU_CR_GIRn_MASK 0x000F0000u +#define MU_CR_Fn_MASK 0x7u +#define MU_CR_NMI_MASK 0x8u + +#define MU_CR_GIRn_NMI_MASK (MU_CR_GIRn_MASK | MU_CR_NMI_MASK) + +#define MU_TR_COUNT 4 +#define MU_RR_COUNT 4 + +static inline void mu_hal_init(struct mu_type *base) +{ + /* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */ + clrbits_le32(&base->cr, MU_CR_GIEn_MASK | MU_CR_RIEn_MASK | + MU_CR_TIEn_MASK | MU_CR_GIRn_MASK | MU_CR_Fn_MASK); +} + +static inline void mu_hal_enablerxfullint(struct mu_type *base, u32 index) +{ + clrsetbits_le32(&base->cr, MU_CR_GIRn_NMI_MASK, + MU_CR_RIE0_MASK >> index); +} + +void mu_hal_sendmsg(struct mu_type *base, u32 regindex, u32 msg); +void mu_hal_receivemsg(struct mu_type *base, u32 regindex, u32 *msg); +#endif /* __FSL_MU_HAL_H__ */ diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h new file mode 100644 index 0000000000..589dba0653 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/sci.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef _SC_SCI_H +#define _SC_SCI_H + +/*! + * This type is used to declare a handle for an IPC communication + * channel. Its meaning is specific to the IPC implementation. + */ +typedef u64 sc_ipc_t; + +/*! + * This type is used to declare an ID for an IPC communication + * channel. Its meaning is specific to the IPC implementation. + */ +typedef u64 sc_ipc_id_t; + +#include <asm/arch/sci/types.h> +#include <asm/arch/sci/ipc.h> +#include <asm/arch/sci/svc/misc/api.h> +#include <asm/arch/sci/svc/pad/api.h> +#include <asm/arch/sci/svc/pm/api.h> +#include <asm/arch/sci/svc/rm/api.h> +#include <asm/arch/sci/svc/timer/api.h> + +#define MU_BASE_ADDR(id) (0x5D1B0000U + (id * 0x10000)) + +#define SC_IPC_AP_CH0 (MU_BASE_ADDR(0)) +#define SC_IPC_AP_CH1 (MU_BASE_ADDR(1)) +#define SC_IPC_AP_CH2 (MU_BASE_ADDR(2)) +#define SC_IPC_AP_CH3 (MU_BASE_ADDR(3)) +#define SC_IPC_AP_CH4 (MU_BASE_ADDR(4)) + +#define SC_IPC_CH SC_IPC_AP_CH1 + +#endif diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile index cfb7e34653..8ae0518c16 100644 --- a/arch/arm/mach-imx/imx8/Makefile +++ b/arch/arm/mach-imx/imx8/Makefile @@ -4,6 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-y += fsl_mu_hal.o sci/ipc.o obj-y += sci/svc/misc/rpc_clnt.o obj-y += sci/svc/pad/rpc_clnt.o obj-y += sci/svc/pm/rpc_clnt.o diff --git a/arch/arm/mach-imx/imx8/fsl_mu_hal.c b/arch/arm/mach-imx/imx8/fsl_mu_hal.c new file mode 100644 index 0000000000..87b8d5a355 --- /dev/null +++ b/arch/arm/mach-imx/imx8/fsl_mu_hal.c @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <log.h> +#include <asm/arch/fsl_mu_hal.h> + +void mu_hal_sendmsg(struct mu_type *base, u32 regindex, u32 msg) +{ + assert(regindex < MU_TR_COUNT); + u32 mask = MU_SR_TE0_MASK >> regindex; + /* Wait TX register to be empty. */ + while (!(readl(&base->sr) & mask)) + ; + writel(msg, &base->tr[regindex]); +} + +void mu_hal_receivemsg(struct mu_type *base, u32 regindex, u32 *msg) +{ + assert(regindex < MU_TR_COUNT); + u32 mask = MU_SR_RF0_MASK >> regindex; + + /* Wait RX register to be full. */ + while (!(readl(&base->sr) & mask)) + ; + *msg = readl(&base->rr[regindex]); +} diff --git a/arch/arm/mach-imx/imx8/sci/ipc.c b/arch/arm/mach-imx/imx8/sci/ipc.c new file mode 100644 index 0000000000..7af10de027 --- /dev/null +++ b/arch/arm/mach-imx/imx8/sci/ipc.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <asm/arch/fsl_mu_hal.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/sci/ipc.h> +#include <asm/arch/sci/rpc.h> + +void sc_ipc_read(sc_ipc_t ipc, void *data) +{ + struct mu_type *base = (struct mu_type *)ipc; + sc_rpc_msg_t *msg = (sc_rpc_msg_t *)data; + u8 count = 0; + + /* Check parms */ + if (!base || !msg) + return; + + /* Read first word */ + mu_hal_receivemsg(base, 0, (u32 *)msg); + count++; + + /* Check size */ + if (msg->size > SC_RPC_MAX_MSG) { + *((u32 *)msg) = 0; + return; + } + + /* Read remaining words */ + while (count < msg->size) { + mu_hal_receivemsg(base, count % MU_RR_COUNT, + &msg->DATA.u32[count - 1]); + count++; + } +} + +void sc_ipc_write(sc_ipc_t ipc, void *data) +{ + struct mu_type *base = (struct mu_type *)ipc; + sc_rpc_msg_t *msg = (sc_rpc_msg_t *)data; + u8 count = 0; + + /* Check parms */ + if (!base || !msg) + return; + + /* Check size */ + if (msg->size > SC_RPC_MAX_MSG) + return; + + /* Write first word */ + mu_hal_sendmsg(base, 0, *((u32 *)msg)); + count++; + + /* Write remaining words */ + while (count < msg->size) { + mu_hal_sendmsg(base, count % MU_TR_COUNT, + msg->DATA.u32[count - 1]); + count++; + } +} + +void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, sc_bool_t no_resp) +{ + sc_ipc_write(ipc, msg); + if (!no_resp) + sc_ipc_read(ipc, msg); +} + +sc_err_t sc_ipc_open(sc_ipc_t *ipc, sc_ipc_id_t id) +{ + struct mu_type *base = (struct mu_type *)id; + u32 i; + + /* Get MU base associated with IPC channel */ + if (!ipc || !base) + return SC_ERR_IPC; + + /* Init MU */ + mu_hal_init(base); + + /* Enable all RX interrupts */ + for (i = 0; i < MU_RR_COUNT; i++) + mu_hal_enablerxfullint(base, i); + + /* Return MU address as handle */ + *ipc = (sc_ipc_t)id; + + return SC_ERR_NONE; +} + +void sc_ipc_close(sc_ipc_t ipc) +{ + struct mu_type *base = (struct mu_type *)ipc; + + if (base) + mu_hal_init(base); +} -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 05/41] arm: global_data: introduce ipc_channel_handle 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (3 preceding siblings ...) 2018-05-28 12:24 ` [U-Boot] [PATCH 04/41] imx8: add IPC communication support between ACore and SCU Peng Fan @ 2018-05-28 12:24 ` Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 06/41] imx: boot_mode: Add FLEXSPI boot entry Peng Fan ` (37 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:24 UTC (permalink / raw) To: u-boot Introduce ipc_channel_handle holding the communication between Acore and SCU. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/include/asm/global_data.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 287a7bd5b1..4bdf1abaf4 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -74,6 +74,10 @@ struct arch_global_data { #if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_FSL_HAS_DP_DDR) unsigned long mem2_clk; #endif + +#ifdef CONFIG_ARCH_IMX8 + u64 ipc_channel_handle; +#endif }; #include <asm-generic/global_data.h> -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 06/41] imx: boot_mode: Add FLEXSPI boot entry 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (4 preceding siblings ...) 2018-05-28 12:24 ` [U-Boot] [PATCH 05/41] arm: global_data: introduce ipc_channel_handle Peng Fan @ 2018-05-28 12:24 ` Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 07/41] imx8: add imx-regs header file Peng Fan ` (36 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:24 UTC (permalink / raw) To: u-boot i.MX8 support FLEXSPI boot support. So add FLEXSPI boot entry. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/include/asm/mach-imx/boot_mode.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/mach-imx/boot_mode.h b/arch/arm/include/asm/mach-imx/boot_mode.h index 8766e9d180..3a483b6afa 100644 --- a/arch/arm/include/asm/mach-imx/boot_mode.h +++ b/arch/arm/include/asm/mach-imx/boot_mode.h @@ -25,6 +25,7 @@ enum boot_device { MMC4_BOOT, NAND_BOOT, QSPI_BOOT, + FLEXSPI_BOOT, USB_BOOT, UNKNOWN_BOOT, BOOT_DEV_NUM = UNKNOWN_BOOT, -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 07/41] imx8: add imx-regs header file 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (5 preceding siblings ...) 2018-05-28 12:24 ` [U-Boot] [PATCH 06/41] imx: boot_mode: Add FLEXSPI boot entry Peng Fan @ 2018-05-28 12:24 ` Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 08/41] imx8: pins: include i.MX8QXP pin header when CONFIG_IMX8QXP defined Peng Fan ` (35 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:24 UTC (permalink / raw) To: u-boot Add imx-regs header file to include the register base definition and usbphy_regs structure. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/include/asm/arch-imx8/imx-regs.h | 117 ++++++++++++++++++++++++++++++ 1 file changed, 117 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8/imx-regs.h diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h new file mode 100644 index 0000000000..bfba2daae2 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx-regs.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __ASM_ARCH_IMX_REGS_H__ +#define __ASM_ARCH_IMX_REGS_H__ + +#define LPUART_BASE 0x5A060000 + +#define GPT1_BASE_ADDR 0x5D140000 +#define SCU_LPUART_BASE 0x33220000 +#define GPIO1_BASE_ADDR 0x5D080000 +#define GPIO2_BASE_ADDR 0x5D090000 +#define GPIO3_BASE_ADDR 0x5D0A0000 +#define GPIO4_BASE_ADDR 0x5D0B0000 +#define GPIO5_BASE_ADDR 0x5D0C0000 +#define GPIO6_BASE_ADDR 0x5D0D0000 +#define GPIO7_BASE_ADDR 0x5D0E0000 +#define GPIO8_BASE_ADDR 0x5D0F0000 +#define LPI2C1_BASE_ADDR 0x5A800000 +#define LPI2C2_BASE_ADDR 0x5A810000 +#define LPI2C3_BASE_ADDR 0x5A820000 +#define LPI2C4_BASE_ADDR 0x5A830000 +#define LPI2C5_BASE_ADDR 0x5A840000 + +#ifdef CONFIG_IMX8QXP +#define LVDS0_PHYCTRL_BASE 0x56221000 +#define LVDS1_PHYCTRL_BASE 0x56241000 +#define MIPI0_SS_BASE 0x56220000 +#define MIPI1_SS_BASE 0x56240000 +#endif + +#define APBH_DMA_ARB_BASE_ADDR 0x5B810000 +#define APBH_DMA_ARB_END_ADDR 0x5B81FFFF +#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR + +#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) +#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) + +#define USB_BASE_ADDR 0x5b0d0000 +#define USB_PHY0_BASE_ADDR 0x5b100000 + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/types.h> +#include <stdbool.h> + +struct usbphy_regs { + u32 usbphy_pwd; /* 0x000 */ + u32 usbphy_pwd_set; /* 0x004 */ + u32 usbphy_pwd_clr; /* 0x008 */ + u32 usbphy_pwd_tog; /* 0x00c */ + u32 usbphy_tx; /* 0x010 */ + u32 usbphy_tx_set; /* 0x014 */ + u32 usbphy_tx_clr; /* 0x018 */ + u32 usbphy_tx_tog; /* 0x01c */ + u32 usbphy_rx; /* 0x020 */ + u32 usbphy_rx_set; /* 0x024 */ + u32 usbphy_rx_clr; /* 0x028 */ + u32 usbphy_rx_tog; /* 0x02c */ + u32 usbphy_ctrl; /* 0x030 */ + u32 usbphy_ctrl_set; /* 0x034 */ + u32 usbphy_ctrl_clr; /* 0x038 */ + u32 usbphy_ctrl_tog; /* 0x03c */ + u32 usbphy_status; /* 0x040 */ + u32 reserved0[3]; + u32 usbphy_debug0; /* 0x050 */ + u32 usbphy_debug0_set; /* 0x054 */ + u32 usbphy_debug0_clr; /* 0x058 */ + u32 usbphy_debug0_tog; /* 0x05c */ + u32 reserved1[4]; + u32 usbphy_debug1; /* 0x070 */ + u32 usbphy_debug1_set; /* 0x074 */ + u32 usbphy_debug1_clr; /* 0x078 */ + u32 usbphy_debug1_tog; /* 0x07c */ + u32 usbphy_version; /* 0x080 */ + u32 reserved2[7]; + u32 usb1_pll_480_ctrl; /* 0x0a0 */ + u32 usb1_pll_480_ctrl_set; /* 0x0a4 */ + u32 usb1_pll_480_ctrl_clr; /* 0x0a8 */ + u32 usb1_pll_480_ctrl_tog; /* 0x0ac */ + u32 reserved3[4]; + u32 usb1_vbus_detect; /* 0xc0 */ + u32 usb1_vbus_detect_set; /* 0xc4 */ + u32 usb1_vbus_detect_clr; /* 0xc8 */ + u32 usb1_vbus_detect_tog; /* 0xcc */ + u32 usb1_vbus_det_stat; /* 0xd0 */ + u32 reserved4[3]; + u32 usb1_chrg_detect; /* 0xe0 */ + u32 usb1_chrg_detect_set; /* 0xe4 */ + u32 usb1_chrg_detect_clr; /* 0xe8 */ + u32 usb1_chrg_detect_tog; /* 0xec */ + u32 usb1_chrg_det_stat; /* 0xf0 */ + u32 reserved5[3]; + u32 usbphy_anactrl; /* 0x100 */ + u32 usbphy_anactrl_set; /* 0x104 */ + u32 usbphy_anactrl_clr; /* 0x108 */ + u32 usbphy_anactrl_tog; /* 0x10c */ + u32 usb1_loopback; /* 0x110 */ + u32 usb1_loopback_set; /* 0x114 */ + u32 usb1_loopback_clr; /* 0x118 */ + u32 usb1_loopback_tog; /* 0x11c */ + u32 usb1_loopback_hsfscnt; /* 0x120 */ + u32 usb1_loopback_hsfscnt_set; /* 0x124 */ + u32 usb1_loopback_hsfscnt_clr; /* 0x128 */ + u32 usb1_loopback_hsfscnt_tog; /* 0x12c */ + u32 usphy_trim_override_en; /* 0x130 */ + u32 usphy_trim_override_en_set; /* 0x134 */ + u32 usphy_trim_override_en_clr; /* 0x138 */ + u32 usphy_trim_override_en_tog; /* 0x13c */ + u32 usb1_pfda_ctrl1; /* 0x140 */ + u32 usb1_pfda_ctrl1_set; /* 0x144 */ + u32 usb1_pfda_ctrl1_clr; /* 0x148 */ + u32 usb1_pfda_ctrl1_tog; /* 0x14c */ +}; +#endif +#endif /* __ASM_ARCH_IMX_REGS_H__ */ -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 08/41] imx8: pins: include i.MX8QXP pin header when CONFIG_IMX8QXP defined 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (6 preceding siblings ...) 2018-05-28 12:24 ` [U-Boot] [PATCH 07/41] imx8: add imx-regs header file Peng Fan @ 2018-05-28 12:24 ` Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 09/41] imx: add i.MX8 cpu type Peng Fan ` (34 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:24 UTC (permalink / raw) To: u-boot Include i.MX8QXP pin header when CONFIG_IMX8QXP defined, if no SoC macro defined, report error. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/include/asm/arch-imx8/imx8-pins.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8/imx8-pins.h diff --git a/arch/arm/include/asm/arch-imx8/imx8-pins.h b/arch/arm/include/asm/arch-imx8/imx8-pins.h new file mode 100644 index 0000000000..60b5831473 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx8-pins.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __ASM_ARCH_IMX8_PINS_H__ +#define __ASM_ARCH_IMX8_PINS_H__ + +#if defined(CONFIG_IMX8QXP) +#include "imx8qxp_pads.h" +#else +#error "No pin header" +#endif + +#endif /* __ASM_ARCH_IMX8_PINS_H__ */ -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 09/41] imx: add i.MX8 cpu type 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (7 preceding siblings ...) 2018-05-28 12:24 ` [U-Boot] [PATCH 08/41] imx8: pins: include i.MX8QXP pin header when CONFIG_IMX8QXP defined Peng Fan @ 2018-05-28 12:24 ` Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 10/41] imx8: add basic cpu support Peng Fan ` (33 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:24 UTC (permalink / raw) To: u-boot Add i.MX8 cpu type and is_imx8/is_imx8qxp help macros. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/include/asm/arch-imx/cpu.h | 5 +++++ arch/arm/include/asm/mach-imx/sys_proto.h | 3 +++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 62df1b9ad2..cf6303c3f5 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -25,12 +25,14 @@ #define MXC_CPU_MX7S 0x71 /* dummy ID */ #define MXC_CPU_MX7D 0x72 #define MXC_CPU_MX8MQ 0x82 +#define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ #define MXC_SOC_MX6 0x60 #define MXC_SOC_MX7 0x70 #define MXC_SOC_MX8M 0x80 +#define MXC_SOC_IMX8 0x90 /* dummy */ #define MXC_SOC_MX7ULP 0xE0 /* dummy */ #define CHIP_REV_1_0 0x10 @@ -41,6 +43,9 @@ #define CHIP_REV_2_5 0x25 #define CHIP_REV_3_0 0x30 +#define CHIP_REV_A 0x0 +#define CHIP_REV_B 0x1 + #define BOARD_REV_1_0 0x0 #define BOARD_REV_2_0 0x1 #define BOARD_VER_OFFSET 0x8 diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index d1d6cbc462..f8890b57da 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -27,6 +27,7 @@ #define is_mx6() (is_soc_type(MXC_SOC_MX6)) #define is_mx7() (is_soc_type(MXC_SOC_MX7)) #define is_mx8m() (is_soc_type(MXC_SOC_MX8M)) +#define is_imx8() (is_soc_type(MXC_SOC_IMX8)) #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) @@ -41,6 +42,8 @@ #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP)) +#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) + #ifdef CONFIG_MX6 #define IMX6_SRC_GPR10_BMODE BIT(28) -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 10/41] imx8: add basic cpu support 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (8 preceding siblings ...) 2018-05-28 12:24 ` [U-Boot] [PATCH 09/41] imx: add i.MX8 cpu type Peng Fan @ 2018-05-28 12:24 ` Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 11/41] imx8: add boot device detection Peng Fan ` (32 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:24 UTC (permalink / raw) To: u-boot Add basic cpu support, including cpu revision, cpu type, cpu core detection. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/include/asm/arch-imx8/cpu.h | 26 ++++++++++++ arch/arm/mach-imx/imx8/Makefile | 1 + arch/arm/mach-imx/imx8/cpu.c | 79 ++++++++++++++++++++++++++++++++++++ 3 files changed, 106 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8/cpu.h create mode 100644 arch/arm/mach-imx/imx8/cpu.c diff --git a/arch/arm/include/asm/arch-imx8/cpu.h b/arch/arm/include/asm/arch-imx8/cpu.h new file mode 100644 index 0000000000..9dfffc09bc --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/cpu.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#define MIDR_PARTNUM_CORTEX_A35 0xD04 +#define MIDR_PARTNUM_CORTEX_A53 0xD03 +#define MIDR_PARTNUM_CORTEX_A72 0xD08 +#define MIDR_PARTNUM_SHIFT 0x4 +#define MIDR_PARTNUM_MASK (0xFFF << 0x4) + +static inline unsigned int read_midr(void) +{ + unsigned long val; + + asm volatile("mrs %0, midr_el1" : "=r" (val)); + + return val; +} + +#define is_cortex_a35() (((read_midr() & MIDR_PARTNUM_MASK) >> \ + MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35) +#define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> \ + MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53) +#define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >>\ + MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72) diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile index 8ae0518c16..9545fd8d03 100644 --- a/arch/arm/mach-imx/imx8/Makefile +++ b/arch/arm/mach-imx/imx8/Makefile @@ -4,6 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-y += cpu.o obj-y += fsl_mu_hal.o sci/ipc.o obj-y += sci/svc/misc/rpc_clnt.o obj-y += sci/svc/pad/rpc_clnt.o diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c new file mode 100644 index 0000000000..eed92d9963 --- /dev/null +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <errno.h> +#include <asm/arch/cpu.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/clock.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch-imx/cpu.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 get_cpu_rev(void) +{ + sc_ipc_t ipchndl; + u32 id = 0, rev = 0; + sc_err_t err; + + ipchndl = gd->arch.ipc_channel_handle; + + err = sc_misc_get_control(ipchndl, SC_R_SYSTEM, SC_C_ID, &id); + if (err != SC_ERR_NONE) + return 0; + + rev = (id >> 5) & 0xf; + id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */ + + return (id << 12) | rev; +} + +#ifdef CONFIG_DISPLAY_CPUINFO +const char *get_imx8_type(u32 imxtype) +{ + switch (imxtype) { + case MXC_CPU_IMX8QXP: + return "8QXP"; + default: + return "??"; + } +} + +const char *get_imx8_rev(u32 rev) +{ + switch (rev) { + case CHIP_REV_A: + return "A"; + case CHIP_REV_B: + return "B"; + default: + return "?"; + } +} + +const char *get_core_name(void) +{ + if (is_cortex_a35()) + return "A35"; + else + return "?"; +} + +int print_cpuinfo(void) +{ + u32 cpurev; + + cpurev = get_cpu_rev(); + + printf("CPU: Freescale i.MX%s rev%s %s@%d MHz\n", + get_imx8_type((cpurev & 0xFF000) >> 12), + get_imx8_rev((cpurev & 0xFFF)), + get_core_name(), + mxc_get_clock(MXC_ARM_CLK) / 1000000); + + return 0; +} +#endif -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 11/41] imx8: add boot device detection 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (9 preceding siblings ...) 2018-05-28 12:24 ` [U-Boot] [PATCH 10/41] imx8: add basic cpu support Peng Fan @ 2018-05-28 12:24 ` Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 12/41] imx8: implement mmc_get_env_dev Peng Fan ` (31 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:24 UTC (permalink / raw) To: u-boot Add get_boot_device to detect boot device. Add print_bootinfo to print the boot device info. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/include/asm/arch-imx8/sys_proto.h | 10 ++++ arch/arm/mach-imx/imx8/cpu.c | 88 +++++++++++++++++++++++++++++- 2 files changed, 97 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-imx8/sys_proto.h diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h b/arch/arm/include/asm/arch-imx8/sys_proto.h new file mode 100644 index 0000000000..f9a3016132 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sys_proto.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#include <asm/mach-imx/sys_proto.h> +#include <linux/types.h> + +enum boot_device get_boot_device(void); +int print_bootinfo(void); diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index eed92d9963..7aecaac356 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -6,10 +6,11 @@ #include <common.h> #include <errno.h> #include <asm/arch/cpu.h> -#include <asm/arch/sys_proto.h> #include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> #include <asm/arch/sci/sci.h> #include <asm/arch-imx/cpu.h> +#include <asm/mach-imx/boot_mode.h> DECLARE_GLOBAL_DATA_PTR; @@ -77,3 +78,88 @@ int print_cpuinfo(void) return 0; } #endif + +int print_bootinfo(void) +{ + enum boot_device bt_dev = get_boot_device(); + + puts("Boot: "); + switch (bt_dev) { + case SD1_BOOT: + puts("SD0\n"); + break; + case SD2_BOOT: + puts("SD1\n"); + break; + case SD3_BOOT: + puts("SD2\n"); + break; + case MMC1_BOOT: + puts("MMC0\n"); + break; + case MMC2_BOOT: + puts("MMC1\n"); + break; + case MMC3_BOOT: + puts("MMC2\n"); + break; + case FLEXSPI_BOOT: + puts("FLEXSPI\n"); + break; + case SATA_BOOT: + puts("SATA\n"); + break; + case NAND_BOOT: + puts("NAND\n"); + break; + case USB_BOOT: + puts("USB\n"); + break; + default: + printf("Unknown device %u\n", bt_dev); + break; + } + + return 0; +} + +enum boot_device get_boot_device(void) +{ + enum boot_device boot_dev = SD1_BOOT; + + sc_ipc_t ipchndl = 0; + sc_rsrc_t dev_rsrc; + + ipchndl = gd->arch.ipc_channel_handle; + sc_misc_get_boot_dev(ipchndl, &dev_rsrc); + + switch (dev_rsrc) { + case SC_R_SDHC_0: + boot_dev = MMC1_BOOT; + break; + case SC_R_SDHC_1: + boot_dev = SD2_BOOT; + break; + case SC_R_SDHC_2: + boot_dev = SD3_BOOT; + break; + case SC_R_NAND: + boot_dev = NAND_BOOT; + break; + case SC_R_FSPI_0: + boot_dev = FLEXSPI_BOOT; + break; + case SC_R_SATA_0: + boot_dev = SATA_BOOT; + break; + case SC_R_USB_0: + case SC_R_USB_1: + case SC_R_USB_2: + boot_dev = USB_BOOT; + break; + default: + break; + } + + return boot_dev; +} -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 12/41] imx8: implement mmc_get_env_dev 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (10 preceding siblings ...) 2018-05-28 12:24 ` [U-Boot] [PATCH 11/41] imx8: add boot device detection Peng Fan @ 2018-05-28 12:24 ` Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 13/41] imx8: implement imx_get_mac_from_fuse Peng Fan ` (30 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:24 UTC (permalink / raw) To: u-boot Implement mmc_get_env_dev for i.MX8. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/mach-imx/imx8/cpu.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 7aecaac356..fa32a9362c 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -163,3 +163,37 @@ enum boot_device get_boot_device(void) return boot_dev; } + +#ifdef CONFIG_ENV_IS_IN_MMC +__weak int board_mmc_get_env_dev(int devno) +{ + return CONFIG_SYS_MMC_ENV_DEV; +} + +int mmc_get_env_dev(void) +{ + sc_ipc_t ipchndl; + sc_rsrc_t dev_rsrc; + int devno; + + ipchndl = gd->arch.ipc_channel_handle; + sc_misc_get_boot_dev(ipchndl, &dev_rsrc); + + switch (dev_rsrc) { + case SC_R_SDHC_0: + devno = 0; + break; + case SC_R_SDHC_1: + devno = 1; + break; + case SC_R_SDHC_2: + devno = 2; + break; + default: + /* If not boot from sd/mmc, use default value */ + return CONFIG_SYS_MMC_ENV_DEV; + } + + return board_mmc_get_env_dev(devno); +} +#endif -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 13/41] imx8: implement imx_get_mac_from_fuse 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (11 preceding siblings ...) 2018-05-28 12:24 ` [U-Boot] [PATCH 12/41] imx8: implement mmc_get_env_dev Peng Fan @ 2018-05-28 12:24 ` Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 14/41] imx8: implement get_board_serial Peng Fan ` (29 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:24 UTC (permalink / raw) To: u-boot Implement imx_get_mac_from_fuse for i.MX8, this will be used by fec_mxc driver to get the mac address. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/mach-imx/imx8/cpu.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index fa32a9362c..2b58f510b4 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -79,6 +79,50 @@ int print_cpuinfo(void) } #endif +#if defined(CONFIG_IMX8QXP) +#define FUSE_MAC0_WORD0 708 +#define FUSE_MAC0_WORD1 709 +#define FUSE_MAC1_WORD0 710 +#define FUSE_MAC1_WORD1 711 +#endif + +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + sc_err_t err; + sc_ipc_t ipc; + u32 val1 = 0, val2 = 0; + u32 word1, word2; + + ipc = gd->arch.ipc_channel_handle; + + if (dev_id == 0) { + word1 = FUSE_MAC0_WORD0; + word2 = FUSE_MAC0_WORD1; + } else { + word1 = FUSE_MAC1_WORD0; + word2 = FUSE_MAC1_WORD1; + } + + err = sc_misc_otp_fuse_read(ipc, word1, &val1); + if (err != SC_ERR_NONE) { + printf("%s fuse %d read error: %d\n", __func__, word1, err); + return; + } + + err = sc_misc_otp_fuse_read(ipc, word2, &val2); + if (err != SC_ERR_NONE) { + printf("%s fuse %d read error: %d\n", __func__, word2, err); + return; + } + + mac[0] = val1; + mac[1] = val1 >> 8; + mac[2] = val1 >> 16; + mac[3] = val1 >> 24; + mac[4] = val2; + mac[5] = val2 >> 8; +} + int print_bootinfo(void) { enum boot_device bt_dev = get_boot_device(); -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 14/41] imx8: implement get_board_serial 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (12 preceding siblings ...) 2018-05-28 12:24 ` [U-Boot] [PATCH 13/41] imx8: implement imx_get_mac_from_fuse Peng Fan @ 2018-05-28 12:24 ` Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 15/41] imx8: add mmu and dram related functiions Peng Fan ` (28 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:24 UTC (permalink / raw) To: u-boot Implement get_board_serial Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/mach-imx/imx8/cpu.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 2b58f510b4..f24ae6ecb8 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -11,6 +11,7 @@ #include <asm/arch/sci/sci.h> #include <asm/arch-imx/cpu.h> #include <asm/mach-imx/boot_mode.h> +#include <asm/setup.h> DECLARE_GLOBAL_DATA_PTR; @@ -208,6 +209,37 @@ enum boot_device get_boot_device(void) return boot_dev; } +#ifdef CONFIG_SERIAL_TAG +#define FUSE_UNIQUE_ID_WORD0 16 +#define FUSE_UNIQUE_ID_WORD1 17 +void get_board_serial(struct tag_serialnr *serialnr) +{ + sc_err_t err; + sc_ipc_t ipc; + u32 val1 = 0, val2 = 0; + u32 word1, word2; + + ipc = gd->arch.ipc_channel_handle; + + word1 = FUSE_UNIQUE_ID_WORD0; + word2 = FUSE_UNIQUE_ID_WORD1; + + err = sc_misc_otp_fuse_read(ipc, word1, &val1); + if (err != SC_ERR_NONE) { + printf("%s fuse %d read error: %d\n", __func__, word1, err); + return; + } + + err = sc_misc_otp_fuse_read(ipc, word2, &val2); + if (err != SC_ERR_NONE) { + printf("%s fuse %d read error: %d\n", __func__, word2, err); + return; + } + serialnr->low = val1; + serialnr->high = val2; +} +#endif /*CONFIG_SERIAL_TAG*/ + #ifdef CONFIG_ENV_IS_IN_MMC __weak int board_mmc_get_env_dev(int devno) { -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 15/41] imx8: add mmu and dram related functiions 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (13 preceding siblings ...) 2018-05-28 12:24 ` [U-Boot] [PATCH 14/41] imx8: implement get_board_serial Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 16/41] imx8: add bootaux support Peng Fan ` (27 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot Add mmu memmap, some memory regions are reserved by M4, Arm Trusted Firmware, so need to get memreg using SCFW API and setup the memmap. Add dram_init, dram_init_banksize, get_effective_memsize functions, according to the memreg. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/mach-imx/imx8/cpu.c | 289 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 289 insertions(+) diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index f24ae6ecb8..c2508c2600 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -10,6 +10,7 @@ #include <asm/arch/sys_proto.h> #include <asm/arch/sci/sci.h> #include <asm/arch-imx/cpu.h> +#include <asm/armv8/mmu.h> #include <asm/mach-imx/boot_mode.h> #include <asm/setup.h> @@ -273,3 +274,291 @@ int mmc_get_env_dev(void) return board_mmc_get_env_dev(devno); } #endif + +#define MEMSTART_ALIGNMENT SZ_2M /* Align the memory start with 2MB */ + +static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start, + sc_faddr_t *addr_end) +{ + sc_ipc_t ipchndl; + sc_err_t scierr; + bool owned; + sc_faddr_t start, end; + + ipchndl = gd->arch.ipc_channel_handle; + + if (ipchndl) { + owned = sc_rm_is_memreg_owned(ipchndl, mr); + if (owned) { + scierr = sc_rm_get_memreg_info(ipchndl, mr, &start, + &end); + if (scierr != SC_ERR_NONE) { + printf("Memreg get info failed, %d\n", scierr); + return -EINVAL; + } + debug("0x%llx -- 0x%llx\n", start, end); + *addr_start = start; + *addr_end = end; + + return 0; + } + } + + return -EINVAL; +} + +phys_size_t get_effective_memsize(void) +{ + sc_rm_mr_t mr; + sc_faddr_t start, end, end1; + int err; + + end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; + + for (mr = 0; mr < 64; mr++) { + err = get_owned_memreg(mr, &start, &end); + if (!err) { + start = roundup(start, MEMSTART_ALIGNMENT); + /* Too small memory region, not use it */ + if (start > end) + continue; + + /* Find the memory region runs the u-boot */ + if (start >= PHYS_SDRAM_1 && start <= end1 && + (start <= CONFIG_SYS_TEXT_BASE && + end >= CONFIG_SYS_TEXT_BASE)) { + if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 + + PHYS_SDRAM_1_SIZE)) + return (end - PHYS_SDRAM_1 + 1); + else + return PHYS_SDRAM_1_SIZE; + } + } + } + + return PHYS_SDRAM_1_SIZE; +} + +int dram_init(void) +{ + sc_rm_mr_t mr; + sc_faddr_t start, end, end1, end2; + int err; + + end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; + end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE; + for (mr = 0; mr < 64; mr++) { + err = get_owned_memreg(mr, &start, &end); + if (!err) { + start = roundup(start, MEMSTART_ALIGNMENT); + /* Too small memory region, not use it */ + if (start > end) + continue; + + if (start >= PHYS_SDRAM_1 && start <= end1) { + if ((end + 1) <= end1) + gd->ram_size += end - start + 1; + else + gd->ram_size += end1 - start; + } else if (start >= PHYS_SDRAM_2 && start <= end2) { + if ((end + 1) <= end2) + gd->ram_size += end - start + 1; + else + gd->ram_size += end2 - start; + } + } + } + + /* If error, set to the default value */ + if (!gd->ram_size) { + gd->ram_size = PHYS_SDRAM_1_SIZE; + gd->ram_size += PHYS_SDRAM_2_SIZE; + } + return 0; +} + +static void dram_bank_sort(int current_bank) +{ + phys_addr_t start; + phys_size_t size; + + while (current_bank > 0) { + if (gd->bd->bi_dram[current_bank - 1].start > + gd->bd->bi_dram[current_bank].start) { + start = gd->bd->bi_dram[current_bank - 1].start; + size = gd->bd->bi_dram[current_bank - 1].size; + + gd->bd->bi_dram[current_bank - 1].start = + gd->bd->bi_dram[current_bank].start; + gd->bd->bi_dram[current_bank - 1].size = + gd->bd->bi_dram[current_bank].size; + + gd->bd->bi_dram[current_bank].start = start; + gd->bd->bi_dram[current_bank].size = size; + } + current_bank--; + } +} + +int dram_init_banksize(void) +{ + sc_rm_mr_t mr; + sc_faddr_t start, end, end1, end2; + int i = 0; + int err; + + end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; + end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE; + + for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) { + err = get_owned_memreg(mr, &start, &end); + if (!err) { + start = roundup(start, MEMSTART_ALIGNMENT); + if (start > end) /* Small memory region, no use it */ + continue; + + if (start >= PHYS_SDRAM_1 && start <= end1) { + gd->bd->bi_dram[i].start = start; + + if ((end + 1) <= end1) + gd->bd->bi_dram[i].size = + end - start + 1; + else + gd->bd->bi_dram[i].size = end1 - start; + + dram_bank_sort(i); + i++; + } else if (start >= PHYS_SDRAM_2 && start <= end2) { + gd->bd->bi_dram[i].start = start; + + if ((end + 1) <= end2) + gd->bd->bi_dram[i].size = + end - start + 1; + else + gd->bd->bi_dram[i].size = end2 - start; + + dram_bank_sort(i); + i++; + } + } + } + + /* If error, set to the default value */ + if (!i) { + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + } + + return 0; +} + +static u64 get_block_attrs(sc_faddr_t addr_start) +{ + u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN; + + if ((addr_start >= PHYS_SDRAM_1 && + addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) || + (addr_start >= PHYS_SDRAM_2 && + addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE))) + return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE); + + return attr; +} + +static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end) +{ + sc_faddr_t end1, end2; + + end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; + end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE; + + if (addr_start >= PHYS_SDRAM_1 && addr_start <= end1) { + if ((addr_end + 1) > end1) + return end1 - addr_start; + } else if (addr_start >= PHYS_SDRAM_2 && addr_start <= end2) { + if ((addr_end + 1) > end2) + return end2 - addr_start; + } + + return (addr_end - addr_start + 1); +} + +#define MAX_PTE_ENTRIES 512 +#define MAX_MEM_MAP_REGIONS 16 + +static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS]; +struct mm_region *mem_map = imx8_mem_map; + +void enable_caches(void) +{ + sc_rm_mr_t mr; + sc_faddr_t start, end; + int err, i; + + /* Create map for registers access from 0x1c000000 to 0x80000000*/ + imx8_mem_map[0].virt = 0x1c000000UL; + imx8_mem_map[0].phys = 0x1c000000UL; + imx8_mem_map[0].size = 0x64000000UL; + imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; + + i = 1; + for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) { + err = get_owned_memreg(mr, &start, &end); + if (!err) { + imx8_mem_map[i].virt = start; + imx8_mem_map[i].phys = start; + imx8_mem_map[i].size = get_block_size(start, end); + imx8_mem_map[i].attrs = get_block_attrs(start); + i++; + } + } + + if (i < MAX_MEM_MAP_REGIONS) { + imx8_mem_map[i].size = 0; + imx8_mem_map[i].attrs = 0; + } else { + puts("Error, need more MEM MAP REGIONS reserved\n"); + icache_enable(); + return; + } + + for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) { + debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n", i, + imx8_mem_map[i].virt, imx8_mem_map[i].phys, imx8_mem_map[i].size, imx8_mem_map[i].attrs); + } + + icache_enable(); + dcache_enable(); +} + +#ifndef CONFIG_SYS_DCACHE_OFF +u64 get_page_table_size(void) +{ + u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64); + u64 size = 0; + + /* + * For each memory region, the max table size: + * 2 level 3 tables + 2 level 2 tables + 1 level 1 table + */ + size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt; + + /* + * We need to duplicate our page table once to have an emergency pt to + * resort to when splitting page tables later on + */ + size *= 2; + + /* + * We may need to split page tables later on if dcache settings change, + * so reserve up to 4 (random pick) page tables for that. + */ + size += one_pt * 4; + + return size; +} +#endif -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 16/41] imx8: add bootaux support 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (14 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 15/41] imx8: add mmu and dram related functiions Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 17/41] imx8: add arch_cpu_init Peng Fan ` (26 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot There is a M4 Core for genernal purpose and a DSP core for audio, add bootaux function in U-Boot to startup the core. The DSP image is an ELF image. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/mach-imx/imx8/cpu.c | 179 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 179 insertions(+) diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index c2508c2600..5223726b59 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -13,6 +13,7 @@ #include <asm/armv8/mmu.h> #include <asm/mach-imx/boot_mode.h> #include <asm/setup.h> +#include <elf.h> DECLARE_GLOBAL_DATA_PTR; @@ -125,6 +126,184 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) mac[5] = val2 >> 8; } +#ifdef CONFIG_IMX_BOOTAUX +#ifdef CONFIG_IMX8QXP +static unsigned long load_elf_image_shdr(unsigned long addr) +{ + /* Elf header structure pointer */ + Elf32_Ehdr *ehdr; + /* Section header structure pointer */ + Elf32_Shdr *shdr; + /* String table pointer */ + unsigned char *strtab = NULL; + /* Binary image pointer */ + unsigned char *image; + /* Loop counter */ + int i; + + ehdr = (Elf32_Ehdr *)addr; + + /* Find the section header string table for output info */ + shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff + + (ehdr->e_shstrndx * sizeof(Elf32_Shdr))); + + if (shdr->sh_type == SHT_STRTAB) + strtab = (unsigned char *)(addr + shdr->sh_offset); + + /* Load each appropriate section */ + for (i = 0; i < ehdr->e_shnum; ++i) { + shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff + + (i * sizeof(Elf32_Shdr))); + + if (!(shdr->sh_flags & SHF_ALLOC) || + shdr->sh_addr == 0 || shdr->sh_size == 0) { + continue; + } + + if (strtab) { + debug("%sing %s @ 0x%08lx (%ld bytes)\n", + (shdr->sh_type == SHT_NOBITS) ? "Clear" : "Load", + &strtab[shdr->sh_name], + (unsigned long)shdr->sh_addr, + (long)shdr->sh_size); + } + + if (shdr->sh_type == SHT_NOBITS) { + memset((void *)(uintptr_t)shdr->sh_addr, 0, + shdr->sh_size); + } else { + image = (unsigned char *)addr + shdr->sh_offset; + memcpy((void *)(uintptr_t)shdr->sh_addr, + (const void *)image, shdr->sh_size); + } + flush_cache(shdr->sh_addr, shdr->sh_size); + } + + return ehdr->e_entry; +} + +int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) +{ + sc_ipc_t ipchndl; + sc_rsrc_t core_rsrc, mu_rsrc = -1; + sc_faddr_t aux_core_ram; + u32 size; + ulong addr; + + ipchndl = gd->arch.ipc_channel_handle; + + switch (core_id) { + case 0: + core_rsrc = SC_R_M4_0_PID0; + aux_core_ram = 0x34FE0000; + mu_rsrc = SC_R_M4_0_MU_1A; + size = SZ_128K; + break; + case 1: + core_rsrc = SC_R_DSP; + aux_core_ram = 0x596f8000; + size = SZ_2K; + break; + default: + printf("Not support this core boot up, ID:%u\n", core_id); + return -EINVAL; + } + + addr = (sc_faddr_t)boot_private_data; + + if (addr >= aux_core_ram && addr <= aux_core_ram + size) { + printf("Wrong image address 0x%lx, should not in aux core ram\n", addr); + return -EINVAL; + } + + printf("Power on aux core %d\n", core_id); + + if (sc_pm_set_resource_power_mode(ipchndl, core_rsrc, + SC_PM_PW_MODE_ON) != SC_ERR_NONE) + return -EIO; + + if (mu_rsrc != -1) { + if (sc_pm_set_resource_power_mode(ipchndl, mu_rsrc, + SC_PM_PW_MODE_ON) != + SC_ERR_NONE) + return -EIO; + } + + if (core_id == 1) { + struct power_domain pd; + + if (sc_pm_clock_enable(ipchndl, core_rsrc, SC_PM_CLK_PER, + true, false) != SC_ERR_NONE) { + printf("Error enable clock\n"); + return -EIO; + } + + if (!power_domain_lookup_name("audio_sai0", &pd)) { + if (power_domain_on(&pd)) { + printf("Error power on SAI0\n"); + return -EIO; + } + } + + if (!power_domain_lookup_name("audio_ocram", &pd)) { + if (power_domain_on(&pd)) { + printf("Error power on HIFI RAM\n"); + return -EIO; + } + } + } + + printf("Copy image from 0x%lx to 0x%lx\n", addr, (ulong)aux_core_ram); + if (core_id == 0) { + /* M4 use bin file */ + memcpy((void *)aux_core_ram, (void *)addr, size); + } else { + /* HIFI use elf file */ + if (!valid_elf_image(addr)) + return -1; + addr = load_elf_image_shdr(addr); + } + + printf("Start %s\n", core_id == 0 ? "M4" : "HIFI"); + + if (sc_pm_cpu_start(ipcHndl, core_rsrc, true, aux_core_ram) != + SC_ERR_NONE) + return -EIO; + + puts("bootaux complete\n"); + + return 0; +} +#endif + +int arch_auxiliary_core_check_up(u32 core_id) +{ + sc_rsrc_t core_rsrc; + sc_pm_power_mode_t power_mode; + sc_ipc_t ipchndl; + + ipchndl = gd->arch.ipc_channel_handle; + + switch (core_id) { + case 0: + core_rsrc = SC_R_M4_0_PID0; + break; + default: + printf("Not support this core, ID:%u\n", core_id); + return 0; + } + + if (sc_pm_get_resource_power_mode(ipchndl, core_rsrc, &power_mode) != + SC_ERR_NONE) + return 0; + + if (power_mode != SC_PM_PW_MODE_OFF) + return 1; + + return 0; +} +#endif + int print_bootinfo(void) { enum boot_device bt_dev = get_boot_device(); -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 17/41] imx8: add arch_cpu_init 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (15 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 16/41] imx8: add bootaux support Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 18/41] imx8: add clock driver Peng Fan ` (25 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot Add arch_cpu_init mainly to open the channel between ACore and SCU. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/include/asm/arch-imx8/imx-regs.h | 2 ++ arch/arm/include/asm/arch-imx8/sys_proto.h | 9 +++++++ arch/arm/mach-imx/imx8/cpu.c | 40 ++++++++++++++++++++++++++++++ 3 files changed, 51 insertions(+) diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h index bfba2daae2..8a92275ae7 100644 --- a/arch/arm/include/asm/arch-imx8/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8/imx-regs.h @@ -38,6 +38,8 @@ #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) +#define PASS_OVER_INFO_ADDR 0x0010fe00 + #define USB_BASE_ADDR 0x5b0d0000 #define USB_PHY0_BASE_ADDR 0x5b100000 diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h b/arch/arm/include/asm/arch-imx8/sys_proto.h index f9a3016132..73ffaba7d5 100644 --- a/arch/arm/include/asm/arch-imx8/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8/sys_proto.h @@ -6,5 +6,14 @@ #include <asm/mach-imx/sys_proto.h> #include <linux/types.h> +struct pass_over_info_t { + u16 barker; + u16 len; + u32 g_bt_cfg_shadow; + u32 card_address_mode; + u32 bad_block_count_met; + u32 g_ap_mu; +}; + enum boot_device get_boot_device(void); int print_bootinfo(void); diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 5223726b59..9ea90f1215 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -82,6 +82,46 @@ int print_cpuinfo(void) } #endif +#define BT_PASSOVER_TAG 0x504F +struct pass_over_info_t *get_pass_over_info(void) +{ + struct pass_over_info_t *p = + (struct pass_over_info_t *)PASS_OVER_INFO_ADDR; + + if (p->barker != BT_PASSOVER_TAG || + p->len != sizeof(struct pass_over_info_t)) + return NULL; + + return p; +} + +int arch_cpu_init(void) +{ + sc_ipc_t ipchndl; + sc_err_t scierr; + struct pass_over_info_t *pass_over; + + gd->arch.ipc_channel_handle = 0; + + /* Open IPC channel */ + scierr = sc_ipc_open(&ipchndl, SC_IPC_CH); + if (scierr != SC_ERR_NONE) + return -EPERM; + + gd->arch.ipc_channel_handle = ipchndl; + + pass_over = get_pass_over_info(); + if (pass_over && pass_over->g_ap_mu == 0) { + /* + * When ap_mu is 0, means the u-boot is boot + * from first container + */ + sc_misc_boot_status(ipchndl, SC_MISC_BOOT_STATUS_SUCCESS); + } + + return 0; +} + #if defined(CONFIG_IMX8QXP) #define FUSE_MAC0_WORD0 708 #define FUSE_MAC0_WORD1 709 -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 18/41] imx8: add clock driver 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (16 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 17/41] imx8: add arch_cpu_init Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 19/41] imx8: add iomux configuration code Peng Fan ` (24 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot Add clock driver for i.MX8, including get arm core clock, peripheral's clock, configure I2C/flexspi/enet/gpmi-nand/usb clock. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/include/asm/arch-imx8/clock.h | 36 ++++ arch/arm/include/asm/arch-imx8/i2c.h | 34 ++++ arch/arm/mach-imx/imx8/Makefile | 2 +- arch/arm/mach-imx/imx8/clock.c | 361 +++++++++++++++++++++++++++++++++ 4 files changed, 432 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-imx8/clock.h create mode 100644 arch/arm/include/asm/arch-imx8/i2c.h create mode 100644 arch/arm/mach-imx/imx8/clock.c diff --git a/arch/arm/include/asm/arch-imx8/clock.h b/arch/arm/include/asm/arch-imx8/clock.h new file mode 100644 index 0000000000..ff98324b1c --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/clock.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __ASM_ARCH_IMX8_CLOCK_H__ +#define __ASM_ARCH_IMX8_CLOCK_H__ + +/* Mainly for compatible to imx common code. */ +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_UART_CLK, + MXC_CSPI_CLK, + MXC_AXI_CLK, + MXC_DDR_CLK, + MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, + MXC_ESDHC3_CLK, + MXC_I2C_CLK, + MXC_FEC_CLK, +}; + +u32 mxc_get_clock(enum mxc_clock clk); +u32 get_lpuart_clk(void); +int enable_i2c_clk(u8 enable, u32 i2c_num); +u32 imx_get_i2cclk(u32 i2c_num); +void enable_usboh3_clk(bool enable); +int set_clk_qspi(void); +u32 imx_get_fecclk(void); +void init_clk_usdhc(u32 index); +void init_clk_gpmi_nand(void); +void init_clk_usb3(int index); + +#endif /* __ASM_ARCH_IMX8_CLOCK_H__ */ diff --git a/arch/arm/include/asm/arch-imx8/i2c.h b/arch/arm/include/asm/arch-imx8/i2c.h new file mode 100644 index 0000000000..b20db5eb1e --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/i2c.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 NXP + */ +#ifndef __ASM_ARCH_IMX8_I2C_H__ +#define __ASM_ARCH_IMX8_I2C_H__ + +#include <asm/arch/sci/sci.h> + +struct imx_i2c_map { + int index; + sc_rsrc_t rsrc; +}; + +static struct imx_i2c_map imx_i2c_desc[] = { + {0, SC_R_I2C_0}, + {1, SC_R_I2C_1}, + {2, SC_R_I2C_2}, + {3, SC_R_I2C_3}, + {4, SC_R_I2C_4}, + {5, SC_R_LVDS_0_I2C_0}, /* lvds0 i2c0 */ + {6, SC_R_LVDS_0_I2C_0}, /* lvds0 i2c1 */ + {7, SC_R_LVDS_1_I2C_0}, /* lvds1 i2c0 */ + {8, SC_R_LVDS_1_I2C_0}, /* lvds1 i2c1 */ + {9, SC_R_CSI_0_I2C_0}, + {10, SC_R_CSI_1_I2C_0}, + {11, SC_R_HDMI_I2C_0}, + {12, SC_R_HDMI_RX_I2C_0}, + {13, SC_R_MIPI_0_I2C_0}, + {14, SC_R_MIPI_0_I2C_1}, + {15, SC_R_MIPI_1_I2C_0}, + {16, SC_R_MIPI_1_I2C_1}, +}; +#endif /* __ASM_ARCH_IMX8_I2C_H__ */ diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile index 9545fd8d03..2921d18f9f 100644 --- a/arch/arm/mach-imx/imx8/Makefile +++ b/arch/arm/mach-imx/imx8/Makefile @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += cpu.o +obj-y += cpu.o clock.o obj-y += fsl_mu_hal.o sci/ipc.o obj-y += sci/svc/misc/rpc_clnt.o obj-y += sci/svc/pad/rpc_clnt.o diff --git a/arch/arm/mach-imx/imx8/clock.c b/arch/arm/mach-imx/imx8/clock.c new file mode 100644 index 0000000000..a12bfea633 --- /dev/null +++ b/arch/arm/mach-imx/imx8/clock.c @@ -0,0 +1,361 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2018 NXP + */ + +#include <common.h> +#include <linux/errno.h> +#include <asm/arch/clock.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/imx8-pins.h> +#include <asm/arch/i2c.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/cpu.h> + +DECLARE_GLOBAL_DATA_PTR; + +static u32 get_arm_main_clk(void) +{ + sc_err_t err; + sc_pm_clock_rate_t clkrate; + sc_ipc_t ipchandle = (sc_ipc_t)gd->arch.ipc_channel_handle; + + if (is_cortex_a35()) + err = sc_pm_get_clock_rate(ipchandle, SC_R_A35, SC_PM_CLK_CPU, + &clkrate); + else + err = SC_ERR_UNAVAILABLE; + + if (err != SC_ERR_NONE) { + printf("sc get ARM clk failed! err=%d\n", err); + return 0; + } + + return clkrate; +} + +u32 get_lpuart_clk(void) +{ + return mxc_get_clock(MXC_UART_CLK); +} + +u32 mxc_get_clock(enum mxc_clock clk) +{ + sc_err_t err; + sc_pm_clock_rate_t clkrate; + sc_ipc_t ipchandle = (sc_ipc_t)gd->arch.ipc_channel_handle; + + switch (clk) { + case MXC_UART_CLK: + err = sc_pm_get_clock_rate(ipchandle, SC_R_UART_0, 2, &clkrate); + if (err != SC_ERR_NONE) { + printf("sc get UART clk failed! err=%d\n", err); + return 0; + } + return clkrate; + case MXC_ESDHC_CLK: + err = sc_pm_get_clock_rate(ipchandle, SC_R_SDHC_0, 2, &clkrate); + if (err != SC_ERR_NONE) { + printf("sc get uSDHC1 clk failed! err=%d\n", err); + return 0; + } + return clkrate; + case MXC_ESDHC2_CLK: + err = sc_pm_get_clock_rate(ipchandle, SC_R_SDHC_1, 2, &clkrate); + if (err != SC_ERR_NONE) { + printf("sc get uSDHC2 clk failed! err=%d\n", err); + return 0; + } + return clkrate; + case MXC_ESDHC3_CLK: + err = sc_pm_get_clock_rate(ipchandle, SC_R_SDHC_2, 2, &clkrate); + if (err != SC_ERR_NONE) { + printf("sc get uSDHC3 clk failed! err=%d\n", err); + return 0; + } + return clkrate; + case MXC_FEC_CLK: + err = sc_pm_get_clock_rate(ipchandle, SC_R_ENET_0, 2, &clkrate); + if (err != SC_ERR_NONE) { + printf("sc get ENET clk failed! err=%d\n", err); + return 0; + } + return clkrate; + case MXC_ARM_CLK: + return get_arm_main_clk(); + default: + printf("Unsupported mxc_clock %d\n", clk); + break; + } + + return 0; +} + +u32 imx_get_fecclk(void) +{ + return mxc_get_clock(MXC_FEC_CLK); +} + +int enable_i2c_clk(u8 enable, u32 i2c_num) +{ + sc_ipc_t ipc; + sc_err_t err; + + if (i2c_num >= ARRAY_SIZE(imx_i2c_desc)) + return -EINVAL; + + ipc = gd->arch.ipc_channel_handle; + + if (enable) + err = sc_pm_clock_enable(ipc, imx_i2c_desc[i2c_num].rsrc, 2, + true, false); + else + err = sc_pm_clock_enable(ipc, imx_i2c_desc[i2c_num].rsrc, 2, + false, false); + + if (err != SC_ERR_NONE) { + printf("i2c clock error %d\n", err); + return -EPERM; + } + + return 0; +} + +u32 imx_get_i2cclk(u32 i2c_num) +{ + sc_err_t err; + sc_ipc_t ipc; + u32 clock_rate; + + if (i2c_num >= ARRAY_SIZE(imx_i2c_desc)) + return 0; + + ipc = gd->arch.ipc_channel_handle; + err = sc_pm_get_clock_rate(ipc, imx_i2c_desc[i2c_num].rsrc, 2, + &clock_rate); + if (err != SC_ERR_NONE) + return 0; + + return clock_rate; +} + +void init_clk_fspi(int index) +{ + sc_err_t scierr; + sc_pm_clock_rate_t rate; + sc_ipc_t ipchndl = gd->arch.ipc_channel_handle; + + /* Set FSPI0 clock root to 29 MHz */ + rate = 29000000; + scierr = sc_pm_set_clock_rate(ipchndl, SC_R_FSPI_0, SC_PM_CLK_PER, + &rate); + if (scierr != SC_ERR_NONE) { + puts("FSPI0 setrate failed\n"); + return; + } + + /* Enable FSPI0 clock root */ + scierr = sc_pm_clock_enable(ipchndl, SC_R_FSPI_0, SC_PM_CLK_PER, true, + false); + if (scierr != SC_ERR_NONE) { + puts("FSPI0 enable clock failed\n"); + return; + } +} + +void init_clk_gpmi_nand(void) +{ + sc_err_t scierr = 0; + sc_pm_clock_rate_t rate; + sc_ipc_t ipchndl = gd->arch.ipc_channel_handle; + + /* Set NAND BCH clock root to 50 MHz */ + rate = 50000000; + scierr = sc_pm_set_clock_rate(ipchndl, SC_R_NAND, SC_PM_CLK_PER, &rate); + if (scierr != SC_ERR_NONE) { + puts("NAND BCH set rate failed\n"); + return; + } + + /* Enable NAND BCH clock root */ + scierr = sc_pm_clock_enable(ipchndl, SC_R_NAND, SC_PM_CLK_PER, true, + false); + if (scierr != SC_ERR_NONE) { + puts("NAND BCH enable clock failed\n"); + return; + } + + /* Set NAND GPMI clock root to 50 MHz */ + rate = 50000000; + scierr = sc_pm_set_clock_rate(ipchndl, SC_R_NAND, SC_PM_CLK_MST_BUS, + &rate); + if (scierr != SC_ERR_NONE) { + puts("NAND GPMI set rate failed\n"); + return; + } + + /* Enable NAND GPMI clock root */ + scierr = sc_pm_clock_enable(ipchndl, SC_R_NAND, SC_PM_CLK_MST_BUS, + true, false); + if (scierr != SC_ERR_NONE) { + puts("NAND GPMI enable clock failed\n"); + return; + } +} + +void enable_usboh3_clk(bool enable) +{ + /* Dummy function */ +} + +void init_clk_usb3(int index) +{ + sc_err_t err; + sc_ipc_t ipc; + + ipc = gd->arch.ipc_channel_handle; + + err = sc_pm_clock_enable(ipc, SC_R_USB_2, SC_PM_CLK_MISC, true, false); + if (err != SC_ERR_NONE) + printf("USB3 set clock failed!, line=%d (error = %d)\n", + __LINE__, err); + + err = sc_pm_clock_enable(ipc, SC_R_USB_2, SC_PM_CLK_MST_BUS, true, + false); + if (err != SC_ERR_NONE) + printf("USB3 set clock failed!, line=%d (error = %d)\n", + __LINE__, err); + + err = sc_pm_clock_enable(ipc, SC_R_USB_2, SC_PM_CLK_PER, true, false); + if (err != SC_ERR_NONE) + printf("USB3 set clock failed!, line=%d (error = %d)\n", + __LINE__, err); +} + +int cdns3_enable_clks(int index) +{ + init_clk_usb3(index); + + return 0; +} + +int cdns3_disable_clks(int index) +{ + sc_err_t err; + sc_ipc_t ipc; + + ipc = gd->arch.ipc_channel_handle; + + err = sc_pm_clock_enable(ipc, SC_R_USB_2, SC_PM_CLK_MISC, false, false); + if (err != SC_ERR_NONE) + printf("USB3 disable clock failed!, line=%d (error = %d)\n", + __LINE__, err); + + err = sc_pm_clock_enable(ipc, SC_R_USB_2, SC_PM_CLK_MST_BUS, false, + false); + if (err != SC_ERR_NONE) + printf("USB3 disable clock failed!, line=%d (error = %d)\n", + __LINE__, err); + + err = sc_pm_clock_enable(ipc, SC_R_USB_2, SC_PM_CLK_PER, false, false); + if (err != SC_ERR_NONE) + printf("USB3 disable clock failed!, line=%d (error = %d)\n", + __LINE__, err); + + return 0; +} + +void init_clk_usdhc(u32 index) +{ +#ifdef CONFIG_IMX8QXP + sc_rsrc_t usdhcs[] = {SC_R_SDHC_0, SC_R_SDHC_1}; + u32 instances = 2; +#endif + + sc_err_t err; + sc_ipc_t ipc; + sc_pm_clock_rate_t actual = 400000000; + + ipc = gd->arch.ipc_channel_handle; + + if (index >= instances) + return; + + /* + * IMX8QXP USDHC_CLK_ROOT default source from DPLL, but this DPLL + * do not stable, will cause usdhc data transfer crc error. So here + * is a workaround, let USDHC_CLK_ROOT source from AVPLL. Due to + * AVPLL is fixed to 1000MHz, so here config USDHC1_CLK_ROOT to 333MHz, + * USDHC2_CLK_ROOT to 200MHz, make eMMC HS400ES work at 166MHz, and SD + * SDR104 work at 200MHz. + */ +#ifdef CONFIG_IMX8QXP + err = sc_pm_set_clock_parent(ipc, usdhcs[index], 2, SC_PM_PARENT_PLL1); + if (err != SC_ERR_NONE) + printf("SDHC_%d set clock parent failed!(error = %d)\n", + index, err); + + if (index == 1) + actual = 200000000; +#endif + + err = sc_pm_set_clock_rate(ipc, usdhcs[index], 2, &actual); + if (err != SC_ERR_NONE) { + printf("SDHC_%d set clock failed! (error = %d)\n", index, err); + return; + } + + if (actual != 400000000) + printf("Actual rate for SDHC_%d is %d\n", index, actual); + + err = sc_pm_clock_enable(ipc, usdhcs[index], SC_PM_CLK_PER, true, + false); + if (err != SC_ERR_NONE) { + printf("SDHC_%d per clk enable failed!\n", index); + return; + } +} + +void init_clk_fec(int index) +{ + sc_err_t err; + sc_ipc_t ipc; + sc_pm_clock_rate_t rate = 24000000; + sc_rsrc_t enet[2] = {SC_R_ENET_0, SC_R_ENET_1}; + + if (index > 1) + return; + + if (index == -1) + index = 0; + + ipc = gd->arch.ipc_channel_handle; + + /* Disable SC_R_ENET_0 clock root */ + err = sc_pm_clock_enable(ipc, enet[index], 0, false, false); + err |= sc_pm_clock_enable(ipc, enet[index], 2, false, false); + err |= sc_pm_clock_enable(ipc, enet[index], 4, false, false); + if (err != SC_ERR_NONE) { + printf("SC_R_ENET_0 disable clock failed! (error = %d)\n", err); + return; + } + + /* Set SC_R_ENET_0 clock root to 125 MHz */ + rate = 125000000; + + /* div = 8 clk_source = PLL_1 ss_slice #7 in verfication codes */ + err = sc_pm_set_clock_rate(ipc, enet[index], 2, &rate); + if (err != SC_ERR_NONE) { + printf("SC_R_ENET_0 set ref clock failed! (err = %d)\n", err); + return; + } + + /* Enable SC_R_ENET_0 clock root */ + err = sc_pm_clock_enable(ipc, enet[index], 0, true, true); + err |= sc_pm_clock_enable(ipc, enet[index], 2, true, true); + err |= sc_pm_clock_enable(ipc, enet[index], 4, true, true); + if (err != SC_ERR_NONE) { + printf("SC_R_ENET_0 enable clock failed! (error = %d)\n", err); + return; + } +} -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 19/41] imx8: add iomux configuration code 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (17 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 18/41] imx8: add clock driver Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 20/41] fsl_esdhc: Update usdhc driver to support i.MX8 Peng Fan ` (23 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot The pads are controlled by SCU, so we could not reuse the code as i.MX6/7/8M, so use dedicated iomux code to invoke the SCFW API to configure the pads. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/include/asm/arch-imx8/iomux.h | 40 +++++++++++++++++++++++++++++ arch/arm/mach-imx/imx8/Makefile | 2 +- arch/arm/mach-imx/imx8/iomux.c | 47 ++++++++++++++++++++++++++++++++++ 3 files changed, 88 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-imx8/iomux.h create mode 100644 arch/arm/mach-imx/imx8/iomux.c diff --git a/arch/arm/include/asm/arch-imx8/iomux.h b/arch/arm/include/asm/arch-imx8/iomux.h new file mode 100644 index 0000000000..bedd01bfd8 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/iomux.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __ASM_ARCH_IMX8_IOMUX_H__ +#define __ASM_ARCH_IMX8_IOMUX_H__ + +/* + * We use 64bits value for iomux settings. + * High 32bits are used for padring register value, + * low 16bits are used for pin index. + */ +typedef u64 iomux_cfg_t; + +#define PADRING_IFMUX_EN_SHIFT 31 +#define PADRING_IFMUX_EN_MASK BIT(31) +#define PADRING_GP_EN_SHIFT 30 +#define PADRING_GP_EN_MASK BIT(30) +#define PADRING_IFMUX_SHIFT 27 +#define PADRING_IFMUX_MASK GENMASK(29, 27) +#define PADRING_CONFIG_SHIFT 25 +#define PADRING_LPCONFIG_SHIFT 23 +#define PADRING_PULL_SHIFT 5 +#define PADRING_DSE_SHIFT 0 + +#define MUX_PAD_CTRL_SHIFT 32 +#define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0xFFFFFFFF << MUX_PAD_CTRL_SHIFT) +#define MUX_PAD_CTRL(x) ((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) +#define MUX_MODE_SHIFT (PADRING_IFMUX_SHIFT + MUX_PAD_CTRL_SHIFT) +#define MUX_MODE_MASK ((iomux_cfg_t)0x7 << MUX_MODE_SHIFT) +#define PIN_ID_MASK ((iomux_cfg_t)0xFFFF) + +/* Valid mux alt0 to alt7 */ +#define MUX_MODE_ALT(x) (((iomux_cfg_t)(x) << MUX_MODE_SHIFT) & \ + MUX_MODE_MASK) + +void imx8_iomux_setup_pad(iomux_cfg_t pad); +void imx8_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, u32 count); +#endif /* __ASM_ARCH_IMX8_IOMUX_H__ */ diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile index 2921d18f9f..17ecf57ffa 100644 --- a/arch/arm/mach-imx/imx8/Makefile +++ b/arch/arm/mach-imx/imx8/Makefile @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += cpu.o clock.o +obj-y += cpu.o clock.o iomux.o obj-y += fsl_mu_hal.o sci/ipc.o obj-y += sci/svc/misc/rpc_clnt.o obj-y += sci/svc/pad/rpc_clnt.o diff --git a/arch/arm/mach-imx/imx8/iomux.c b/arch/arm/mach-imx/imx8/iomux.c new file mode 100644 index 0000000000..a33a322b4f --- /dev/null +++ b/arch/arm/mach-imx/imx8/iomux.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sci/sci.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * configures a single pad in the iomuxer + */ +void imx8_iomux_setup_pad(iomux_cfg_t pad) +{ + sc_err_t err; + sc_ipc_t ipc; + + sc_pad_t pin_id = pad & PIN_ID_MASK; + + u32 val = (u32)((pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT); + + ipc = gd->arch.ipc_channel_handle; + + val |= PADRING_IFMUX_EN_MASK; + val |= PADRING_GP_EN_MASK; + + err = sc_pad_set(ipc, pin_id, val); + if (err != SC_ERR_NONE) + printf("sc_pad_set failed!, pin: %u, val: 0x%x\n", pin_id, val); + + debug("iomux: pin %d, val = 0x%x\n", pin_id, val); +} + +/* configures a list of pads within declared with IOMUX_PADS macro */ +void imx8_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, u32 count) +{ + iomux_cfg_t const *p = pad_list; + int i; + + for (i = 0; i < count; i++) { + imx8_iomux_setup_pad(*p); + p++; + } +} -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 20/41] fsl_esdhc: Update usdhc driver to support i.MX8 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (18 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 19/41] imx8: add iomux configuration code Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 21/41] serial_lpuart: Update lpuart " Peng Fan ` (22 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot From: Ye Li <ye.li@nxp.com> Add CONFIG_IMX8 to use the 64bits support in usdhc driver. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> --- drivers/mmc/fsl_esdhc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 4528345c67..1b062ff06d 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -257,7 +257,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, int timeout; struct fsl_esdhc *regs = priv->esdhc_regs; #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ - defined(CONFIG_MX8M) + defined(CONFIG_IMX8) || defined(CONFIG_MX8M) dma_addr_t addr; #endif uint wml_value; @@ -271,7 +271,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ - defined(CONFIG_MX8M) + defined(CONFIG_IMX8) || defined(CONFIG_MX8M) addr = virt_to_phys((void *)(data->dest)); if (upper_32_bits(addr)) printf("Error found for upper 32 bits\n"); @@ -301,7 +301,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, wml_value << 16); #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ - defined(CONFIG_MX8M) + defined(CONFIG_IMX8) || defined(CONFIG_MX8M) addr = virt_to_phys((void *)(data->src)); if (upper_32_bits(addr)) printf("Error found for upper 32 bits\n"); @@ -367,7 +367,7 @@ static void check_and_invalidate_dcache_range unsigned size = roundup(ARCH_DMA_MINALIGN, data->blocks*data->blocksize); #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ - defined(CONFIG_MX8M) + defined(CONFIG_IMX8) || defined(CONFIG_MX8M) dma_addr_t addr; addr = virt_to_phys((void *)(data->dest)); -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 21/41] serial_lpuart: Update lpuart driver to support i.MX8 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (19 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 20/41] fsl_esdhc: Update usdhc driver to support i.MX8 Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 22/41] serial: lpuart: Enable RX and TX FIFO Peng Fan ` (21 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot Add i.MX8 compatible string and cpu type support to lpuart driver, to use little endian 32 bits configurations. Also, accroding to RM, the Receive FIFO Enable (RXFE) field in LPUART FIFO register is bit 3, so the definition should change to 0x08 not 0x40 for i.MX8, otherwise the Receive FIFO is not disabled. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> --- drivers/serial/serial_lpuart.c | 15 ++++++++++++--- include/fsl_lpuart.h | 2 +- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 1212b72676..a5a2f65c77 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -41,7 +41,11 @@ #define CTRL_RE (1 << 18) #define FIFO_TXFE 0x80 +#ifdef CONFIG_IMX8 +#define FIFO_RXFE 0x08 +#else #define FIFO_RXFE 0x40 +#endif #define WATER_TXWATER_OFF 1 #define WATER_RXWATER_OFF 16 @@ -54,7 +58,8 @@ DECLARE_GLOBAL_DATA_PTR; enum lpuart_devtype { DEV_VF610 = 1, DEV_LS1021A, - DEV_MX7ULP + DEV_MX7ULP, + DEV_IMX8 }; struct lpuart_serial_platdata { @@ -325,7 +330,7 @@ static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat) lpuart_write32(plat->flags, &base->match, 0); - if (plat->devtype == DEV_MX7ULP) { + if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8) { _lpuart32_serial_setbrg_7ulp(plat, gd->baudrate); } else { /* provide data bits, parity, stop bit, etc */ @@ -342,7 +347,7 @@ static int lpuart_serial_setbrg(struct udevice *dev, int baudrate) struct lpuart_serial_platdata *plat = dev->platdata; if (is_lpuart32(dev)) { - if (plat->devtype == DEV_MX7ULP) + if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8) _lpuart32_serial_setbrg_7ulp(plat, baudrate); else _lpuart32_serial_setbrg(plat, baudrate); @@ -427,6 +432,8 @@ static int lpuart_serial_ofdata_to_platdata(struct udevice *dev) plat->devtype = DEV_MX7ULP; else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart")) plat->devtype = DEV_VF610; + else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart")) + plat->devtype = DEV_IMX8; return 0; } @@ -444,6 +451,8 @@ static const struct udevice_id lpuart_serial_ids[] = { { .compatible = "fsl,imx7ulp-lpuart", .data = LPUART_FLAG_REGMAP_32BIT_REG }, { .compatible = "fsl,vf610-lpuart"}, + { .compatible = "fsl,imx8qm-lpuart", + .data = LPUART_FLAG_REGMAP_32BIT_REG }, { } }; diff --git a/include/fsl_lpuart.h b/include/fsl_lpuart.h index 02ebfefc74..7a8231ec19 100644 --- a/include/fsl_lpuart.h +++ b/include/fsl_lpuart.h @@ -4,7 +4,7 @@ * */ -#ifdef CONFIG_ARCH_MX7ULP +#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_IMX8) struct lpuart_fsl_reg32 { u32 verid; u32 param; -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 22/41] serial: lpuart: Enable RX and TX FIFO 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (20 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 21/41] serial_lpuart: Update lpuart " Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 23/41] imx_lpi2c: Update lpi2c driver to support imx8 Peng Fan ` (20 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot From: Ye Li <ye.li@nxp.com> Enable the RX and TX FIFO in LPUART driver to avoid the input lost during u-boot boot up. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> --- drivers/serial/serial_lpuart.c | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index a5a2f65c77..e99a49d0d9 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -40,6 +40,12 @@ #define CTRL_TE (1 << 19) #define CTRL_RE (1 << 18) +#define FIFO_RXFLUSH (1 << 14) +#define FIFO_TXFLUSH (1 << 15) +#define FIFO_TXSIZE_MASK 0x70 +#define FIFO_TXSIZE_OFF 4 +#define FIFO_RXSIZE_MASK 0x7 +#define FIFO_RXSIZE_OFF 0 #define FIFO_TXFE 0x80 #ifdef CONFIG_IMX8 #define FIFO_RXFE 0x08 @@ -47,7 +53,7 @@ #define FIFO_RXFE 0x40 #endif -#define WATER_TXWATER_OFF 1 +#define WATER_TXWATER_OFF 0 #define WATER_RXWATER_OFF 16 DECLARE_GLOBAL_DATA_PTR; @@ -318,15 +324,28 @@ static int _lpuart32_serial_tstc(struct lpuart_serial_platdata *plat) static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat) { struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg; - u32 ctrl; + u32 val, tx_fifo_size; - lpuart_read32(plat->flags, &base->ctrl, &ctrl); - ctrl &= ~CTRL_RE; - ctrl &= ~CTRL_TE; - lpuart_write32(plat->flags, &base->ctrl, ctrl); + lpuart_read32(plat->flags, &base->ctrl, &val); + val &= ~CTRL_RE; + val &= ~CTRL_TE; + lpuart_write32(plat->flags, &base->ctrl, val); lpuart_write32(plat->flags, &base->modir, 0); - lpuart_write32(plat->flags, &base->fifo, ~(FIFO_TXFE | FIFO_RXFE)); + + lpuart_read32(plat->flags, &base->fifo, &val); + tx_fifo_size = (val & FIFO_TXSIZE_MASK) >> FIFO_TXSIZE_OFF; + /* Set the TX water to half of FIFO size */ + if (tx_fifo_size > 1) + tx_fifo_size = tx_fifo_size >> 1; + + /* Set RX water to 0, to be triggered by any receive data */ + lpuart_write32(plat->flags, &base->water, + (tx_fifo_size << WATER_TXWATER_OFF)); + + /* Enable TX and RX FIFO */ + val |= (FIFO_TXFE | FIFO_RXFE | FIFO_TXFLUSH | FIFO_RXFLUSH); + lpuart_write32(plat->flags, &base->fifo, val); lpuart_write32(plat->flags, &base->match, 0); -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 23/41] imx_lpi2c: Update lpi2c driver to support imx8 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (21 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 22/41] serial: lpuart: Enable RX and TX FIFO Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-05-29 3:40 ` Heiko Schocher 2018-05-28 12:25 ` [U-Boot] [PATCH 24/41] imx: lpi2c: fix clock issue when NACK detected Peng Fan ` (19 subsequent siblings) 42 siblings, 1 reply; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot From: Ye Li <ye.li@nxp.com> Add compatible string for i.MX8 and move imx_lpi2c.h from mx7ulp directory to u-boot include directory as a common header file. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Heiko Schocher <hs@denx.de> --- drivers/i2c/imx_lpi2c.c | 3 ++- {arch/arm/include/asm/arch-mx7ulp => include}/imx_lpi2c.h | 0 2 files changed, 2 insertions(+), 1 deletion(-) rename {arch/arm/include/asm/arch-mx7ulp => include}/imx_lpi2c.h (100%) diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c index 8d3e0555a1..a6e41c5c91 100644 --- a/drivers/i2c/imx_lpi2c.c +++ b/drivers/i2c/imx_lpi2c.c @@ -8,7 +8,7 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> -#include <asm/arch/imx_lpi2c.h> +#include <imx_lpi2c.h> #include <asm/arch/sys_proto.h> #include <dm.h> #include <fdtdec.h> @@ -447,6 +447,7 @@ static const struct dm_i2c_ops imx_lpi2c_ops = { static const struct udevice_id imx_lpi2c_ids[] = { { .compatible = "fsl,imx7ulp-lpi2c", }, + { .compatible = "fsl,imx8qm-lpi2c", }, {} }; diff --git a/arch/arm/include/asm/arch-mx7ulp/imx_lpi2c.h b/include/imx_lpi2c.h similarity index 100% rename from arch/arm/include/asm/arch-mx7ulp/imx_lpi2c.h rename to include/imx_lpi2c.h -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 23/41] imx_lpi2c: Update lpi2c driver to support imx8 2018-05-28 12:25 ` [U-Boot] [PATCH 23/41] imx_lpi2c: Update lpi2c driver to support imx8 Peng Fan @ 2018-05-29 3:40 ` Heiko Schocher 0 siblings, 0 replies; 69+ messages in thread From: Heiko Schocher @ 2018-05-29 3:40 UTC (permalink / raw) To: u-boot Hello Peng, Am 28.05.2018 um 14:25 schrieb Peng Fan: > From: Ye Li <ye.li@nxp.com> > > Add compatible string for i.MX8 and move imx_lpi2c.h from mx7ulp directory > to u-boot include directory as a common header file. > > Signed-off-by: Ye Li <ye.li@nxp.com> > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Cc: Heiko Schocher <hs@denx.de> > --- > drivers/i2c/imx_lpi2c.c | 3 ++- > {arch/arm/include/asm/arch-mx7ulp => include}/imx_lpi2c.h | 0 > 2 files changed, 2 insertions(+), 1 deletion(-) > rename {arch/arm/include/asm/arch-mx7ulp => include}/imx_lpi2c.h (100%) Reviewed-by: Heiko Schocher <hs@denx.de> bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: hs at denx.de ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 24/41] imx: lpi2c: fix clock issue when NACK detected 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (22 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 23/41] imx_lpi2c: Update lpi2c driver to support imx8 Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-05-29 3:52 ` Heiko Schocher 2018-05-28 12:25 ` [U-Boot] [PATCH 25/41] lpi2c: Fix bus stop problem in xfer Peng Fan ` (18 subsequent siblings) 42 siblings, 1 reply; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot From: Gao Pan <pandy.gao@nxp.com> For LPI2C IP, NACK is detected by the rising edge of the ninth clock. In current uboot driver, once NACK is detected, it will reset and then disable LPI2C master. As a result, we can never see the falling edge of the ninth clock. Signed-off-by: Gao Pan <pandy.gao@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Heiko Schocher <hs@denx.de> --- drivers/i2c/imx_lpi2c.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c index a6e41c5c91..d2e11b411b 100644 --- a/drivers/i2c/imx_lpi2c.c +++ b/drivers/i2c/imx_lpi2c.c @@ -15,6 +15,7 @@ #include <i2c.h> #define LPI2C_FIFO_SIZE 4 +#define LPI2C_NACK_TOUT_MS 1 #define LPI2C_TIMEOUT_MS 100 /* Weak linked function for overridden by some SoC power function */ @@ -184,6 +185,7 @@ static int bus_i2c_stop(struct imx_lpi2c_reg *regs) { lpi2c_status_t result; u32 status; + ulong start_time; result = bus_i2c_wait_for_tx_ready(regs); if (result) { @@ -194,7 +196,8 @@ static int bus_i2c_stop(struct imx_lpi2c_reg *regs) /* send stop command */ writel(LPI2C_MTDR_CMD(0x2), ®s->mtdr); - while (result == LPI2C_SUCESS) { + start_time = get_timer(0); + while (1) { status = readl(®s->msr); result = imx_lpci2c_check_clear_error(regs); /* stop detect flag */ @@ -204,6 +207,11 @@ static int bus_i2c_stop(struct imx_lpi2c_reg *regs) writel(status, ®s->msr); break; } + + if (get_timer(start_time) > LPI2C_NACK_TOUT_MS) { + debug("stop timeout\n"); + return -ETIMEDOUT; + } } return result; @@ -363,10 +371,8 @@ static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip, } result = bus_i2c_stop(regs); - if (result) { + if (result) bus_i2c_init(bus, 100000); - return -result; - } return result; } -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 24/41] imx: lpi2c: fix clock issue when NACK detected 2018-05-28 12:25 ` [U-Boot] [PATCH 24/41] imx: lpi2c: fix clock issue when NACK detected Peng Fan @ 2018-05-29 3:52 ` Heiko Schocher 0 siblings, 0 replies; 69+ messages in thread From: Heiko Schocher @ 2018-05-29 3:52 UTC (permalink / raw) To: u-boot Hello Peng, Am 28.05.2018 um 14:25 schrieb Peng Fan: > From: Gao Pan <pandy.gao@nxp.com> > > For LPI2C IP, NACK is detected by the rising edge of the ninth clock. > In current uboot driver, once NACK is detected, it will reset and then > disable LPI2C master. As a result, we can never see the falling edge > of the ninth clock. > > Signed-off-by: Gao Pan <pandy.gao@nxp.com> > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Cc: Heiko Schocher <hs@denx.de> > --- > drivers/i2c/imx_lpi2c.c | 14 ++++++++++---- > 1 file changed, 10 insertions(+), 4 deletions(-) Thanks! Reviewed-by: Heiko Schocher <hs@denx.de> bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: hs at denx.de ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 25/41] lpi2c: Fix bus stop problem in xfer 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (23 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 24/41] imx: lpi2c: fix clock issue when NACK detected Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-05-29 3:55 ` Heiko Schocher 2018-05-28 12:25 ` [U-Boot] [PATCH 26/41] lpi2c: Add bus busy error handling Peng Fan ` (17 subsequent siblings) 42 siblings, 1 reply; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot From: Ye Li <ye.li@nxp.com> In xfer function, both bus_i2c_read and bus_i2c_write will send a STOP command. This causes a problem when reading register data from i2c device. Generally two operations comprise the register data reading: 1. Write the register address to i2c device. START | chip_addr | W | ACK | register_addr | ACK | 2. Read the Data from i2c device. START | chip_addr | R | ACK | DATA | NACK | STOP The STOP command should happen at the end of the transfer, otherwise we will always get data from register address 0 Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Cc: Heiko Schocher <hs@denx.de> --- drivers/i2c/imx_lpi2c.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c index d2e11b411b..585787a35c 100644 --- a/drivers/i2c/imx_lpi2c.c +++ b/drivers/i2c/imx_lpi2c.c @@ -225,9 +225,6 @@ static int bus_i2c_read(struct imx_lpi2c_reg *regs, u32 chip, u8 *buf, int len) if (result) return result; result = bus_i2c_receive(regs, buf, len); - if (result) - return result; - result = bus_i2c_stop(regs); if (result) return result; @@ -242,9 +239,6 @@ static int bus_i2c_write(struct imx_lpi2c_reg *regs, u32 chip, u8 *buf, int len) if (result) return result; result = bus_i2c_send(regs, buf, len); - if (result) - return result; - result = bus_i2c_stop(regs); if (result) return result; @@ -380,7 +374,7 @@ static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip, static int imx_lpi2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) { struct imx_lpi2c_reg *regs; - int ret = 0; + int ret = 0, ret_stop; regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus); for (; nmsgs > 0; nmsgs--, msg++) { @@ -398,6 +392,12 @@ static int imx_lpi2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) if (ret) debug("i2c_write: error sending\n"); + ret_stop = bus_i2c_stop(regs); + if (ret_stop) + debug("i2c_xfer: stop bus error\n"); + + ret |= ret_stop; + return ret; } -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 25/41] lpi2c: Fix bus stop problem in xfer 2018-05-28 12:25 ` [U-Boot] [PATCH 25/41] lpi2c: Fix bus stop problem in xfer Peng Fan @ 2018-05-29 3:55 ` Heiko Schocher 0 siblings, 0 replies; 69+ messages in thread From: Heiko Schocher @ 2018-05-29 3:55 UTC (permalink / raw) To: u-boot Hello Peng, Am 28.05.2018 um 14:25 schrieb Peng Fan: > From: Ye Li <ye.li@nxp.com> > > In xfer function, both bus_i2c_read and bus_i2c_write will > send a STOP command. This causes a problem when reading register > data from i2c device. > > Generally two operations comprise the register data reading: > 1. Write the register address to i2c device. > START | chip_addr | W | ACK | register_addr | ACK | > > 2. Read the Data from i2c device. > START | chip_addr | R | ACK | DATA | NACK | STOP > > The STOP command should happen at the end of the transfer, otherwise > we will always get data from register address 0 > > Signed-off-by: Ye Li <ye.li@nxp.com> > Acked-by: Peng Fan <peng.fan@nxp.com> > Cc: Heiko Schocher <hs@denx.de> > --- > drivers/i2c/imx_lpi2c.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) Good catch. Reviewed-by: Heiko Schocher <hs@denx.de> bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: hs at denx.de ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 26/41] lpi2c: Add bus busy error handling 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (24 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 25/41] lpi2c: Fix bus stop problem in xfer Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-05-29 3:59 ` Heiko Schocher 2018-05-28 12:25 ` [U-Boot] [PATCH 27/41] net: fec: do not access reserved register for i.MX8 Peng Fan ` (16 subsequent siblings) 42 siblings, 1 reply; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot From: Ye Li <ye.li@nxp.com> When doing "i2c dev 4; i2c probe" with ENET daughter card connected on iMX8QXP MEK board, we met a i2c bus busy issue, that the BBF of lpi2c always show busy, but the master is idle, and stop is detected (SDF set). This patch addes a handling to re-init the lpi2c master for this case. Then the issue can be worked around. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Cc: Heiko Schocher <hs@denx.de> --- drivers/i2c/imx_lpi2c.c | 53 +++++++++++++++++++++++++++++-------------------- 1 file changed, 32 insertions(+), 21 deletions(-) diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c index 585787a35c..ff07ca34aa 100644 --- a/drivers/i2c/imx_lpi2c.c +++ b/drivers/i2c/imx_lpi2c.c @@ -18,6 +18,8 @@ #define LPI2C_NACK_TOUT_MS 1 #define LPI2C_TIMEOUT_MS 100 +static int bus_i2c_init(struct udevice *bus, int speed); + /* Weak linked function for overridden by some SoC power function */ int __weak init_i2c_power(unsigned i2c_num) { @@ -91,8 +93,9 @@ static int bus_i2c_wait_for_tx_ready(struct imx_lpi2c_reg *regs) return result; } -static int bus_i2c_send(struct imx_lpi2c_reg *regs, u8 *txbuf, int len) +static int bus_i2c_send(struct udevice *bus, u8 *txbuf, int len) { + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus); lpi2c_status_t result = LPI2C_SUCESS; /* empty tx */ @@ -111,8 +114,9 @@ static int bus_i2c_send(struct imx_lpi2c_reg *regs, u8 *txbuf, int len) return result; } -static int bus_i2c_receive(struct imx_lpi2c_reg *regs, u8 *rxbuf, int len) +static int bus_i2c_receive(struct udevice *bus, u8 *rxbuf, int len) { + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus); lpi2c_status_t result = LPI2C_SUCESS; u32 val; ulong start_time = get_timer(0); @@ -153,15 +157,24 @@ static int bus_i2c_receive(struct imx_lpi2c_reg *regs, u8 *rxbuf, int len) return result; } -static int bus_i2c_start(struct imx_lpi2c_reg *regs, u8 addr, u8 dir) +static int bus_i2c_start(struct udevice *bus, u8 addr, u8 dir) { lpi2c_status_t result; + struct imx_lpi2c_reg *regs = + (struct imx_lpi2c_reg *)devfdt_get_addr(bus); u32 val; result = imx_lpci2c_check_busy_bus(regs); if (result) { debug("i2c: start check busy bus: 0x%x\n", result); - return result; + + /* Try to init the lpi2c then check the bus busy again */ + bus_i2c_init(bus, 100000); + result = imx_lpci2c_check_busy_bus(regs); + if (result) { + printf("i2c: Error check busy bus: 0x%x\n", result); + return result; + } } /* clear all status flags */ writel(0x7f00, ®s->msr); @@ -181,9 +194,11 @@ static int bus_i2c_start(struct imx_lpi2c_reg *regs, u8 addr, u8 dir) return result; } -static int bus_i2c_stop(struct imx_lpi2c_reg *regs) +static int bus_i2c_stop(struct udevice *bus) { lpi2c_status_t result; + struct imx_lpi2c_reg *regs = + (struct imx_lpi2c_reg *)devfdt_get_addr(bus); u32 status; ulong start_time; @@ -217,28 +232,28 @@ static int bus_i2c_stop(struct imx_lpi2c_reg *regs) return result; } -static int bus_i2c_read(struct imx_lpi2c_reg *regs, u32 chip, u8 *buf, int len) +static int bus_i2c_read(struct udevice *bus, u32 chip, u8 *buf, int len) { lpi2c_status_t result; - result = bus_i2c_start(regs, chip, 1); + result = bus_i2c_start(bus, chip, 1); if (result) return result; - result = bus_i2c_receive(regs, buf, len); + result = bus_i2c_receive(bus, buf, len); if (result) return result; return result; } -static int bus_i2c_write(struct imx_lpi2c_reg *regs, u32 chip, u8 *buf, int len) +static int bus_i2c_write(struct udevice *bus, u32 chip, u8 *buf, int len) { lpi2c_status_t result; - result = bus_i2c_start(regs, chip, 0); + result = bus_i2c_start(bus, chip, 0); if (result) return result; - result = bus_i2c_send(regs, buf, len); + result = bus_i2c_send(bus, buf, len); if (result) return result; @@ -353,18 +368,16 @@ static int bus_i2c_init(struct udevice *bus, int speed) static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip, u32 chip_flags) { - struct imx_lpi2c_reg *regs; lpi2c_status_t result; - regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus); - result = bus_i2c_start(regs, chip, 0); + result = bus_i2c_start(bus, chip, 0); if (result) { - bus_i2c_stop(regs); + bus_i2c_stop(bus); bus_i2c_init(bus, 100000); return result; } - result = bus_i2c_stop(regs); + result = bus_i2c_stop(bus); if (result) bus_i2c_init(bus, 100000); @@ -373,16 +386,14 @@ static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip, static int imx_lpi2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) { - struct imx_lpi2c_reg *regs; int ret = 0, ret_stop; - regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus); for (; nmsgs > 0; nmsgs--, msg++) { debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); if (msg->flags & I2C_M_RD) - ret = bus_i2c_read(regs, msg->addr, msg->buf, msg->len); + ret = bus_i2c_read(bus, msg->addr, msg->buf, msg->len); else { - ret = bus_i2c_write(regs, msg->addr, msg->buf, + ret = bus_i2c_write(bus, msg->addr, msg->buf, msg->len); if (ret) break; @@ -392,7 +403,7 @@ static int imx_lpi2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) if (ret) debug("i2c_write: error sending\n"); - ret_stop = bus_i2c_stop(regs); + ret_stop = bus_i2c_stop(bus); if (ret_stop) debug("i2c_xfer: stop bus error\n"); -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 26/41] lpi2c: Add bus busy error handling 2018-05-28 12:25 ` [U-Boot] [PATCH 26/41] lpi2c: Add bus busy error handling Peng Fan @ 2018-05-29 3:59 ` Heiko Schocher 0 siblings, 0 replies; 69+ messages in thread From: Heiko Schocher @ 2018-05-29 3:59 UTC (permalink / raw) To: u-boot Hello Peng, Am 28.05.2018 um 14:25 schrieb Peng Fan: > From: Ye Li <ye.li@nxp.com> > > When doing "i2c dev 4; i2c probe" with ENET daughter card connected > on iMX8QXP MEK board, we met a i2c bus busy issue, that the BBF of > lpi2c always show busy, but the master is idle, and stop is detected > (SDF set). > > This patch addes a handling to re-init the lpi2c master for this > case. Then the issue can be worked around. > > Signed-off-by: Ye Li <ye.li@nxp.com> > Acked-by: Peng Fan <peng.fan@nxp.com> > Cc: Heiko Schocher <hs@denx.de> > --- > drivers/i2c/imx_lpi2c.c | 53 +++++++++++++++++++++++++++++-------------------- > 1 file changed, 32 insertions(+), 21 deletions(-) I have no such hardware, but the question is why is this bus busy shown? Nevertheless, trying to re init a busy bus, before ginving up, seems a good attempt to me. Reviewed-by: Heiko Schocher <hs@denx.de> bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: hs at denx.de ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 27/41] net: fec: do not access reserved register for i.MX8 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (25 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 26/41] lpi2c: Add bus busy error handling Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-06-12 18:26 ` Joe Hershberger 2018-10-18 13:38 ` Anatolij Gustschin 2018-05-28 12:25 ` [U-Boot] [PATCH 28/41] net: fec_mxc: Add the init_clk_fec function Peng Fan ` (15 subsequent siblings) 42 siblings, 2 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot The MIB RAM and FIFO receive start register does not exist on i.MX8. Accessing these register will cause SERROR. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Joe Hershberger <joe.hershberger@ni.com> --- drivers/net/fec_mxc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 694a0b2f7e..b512a71c0c 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -564,7 +564,7 @@ static int fec_init(struct eth_device *dev, bd_t *bd) writel(0x00000000, &fec->eth->gaddr2); /* Do not access reserved register */ - if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) { + if (!is_mx6ul() && !is_mx6ull() && !is_mx8m() && !is_imx8()) { /* clear MIB RAM */ for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) writel(0, i); -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 27/41] net: fec: do not access reserved register for i.MX8 2018-05-28 12:25 ` [U-Boot] [PATCH 27/41] net: fec: do not access reserved register for i.MX8 Peng Fan @ 2018-06-12 18:26 ` Joe Hershberger 2018-10-18 13:38 ` Anatolij Gustschin 1 sibling, 0 replies; 69+ messages in thread From: Joe Hershberger @ 2018-06-12 18:26 UTC (permalink / raw) To: u-boot On Mon, May 28, 2018 at 7:25 AM, Peng Fan <peng.fan@nxp.com> wrote: > The MIB RAM and FIFO receive start register does not exist on > i.MX8. Accessing these register will cause SERROR. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 27/41] net: fec: do not access reserved register for i.MX8 2018-05-28 12:25 ` [U-Boot] [PATCH 27/41] net: fec: do not access reserved register for i.MX8 Peng Fan 2018-06-12 18:26 ` Joe Hershberger @ 2018-10-18 13:38 ` Anatolij Gustschin 1 sibling, 0 replies; 69+ messages in thread From: Anatolij Gustschin @ 2018-10-18 13:38 UTC (permalink / raw) To: u-boot Hi Peng, On Mon, 28 May 2018 20:25:12 +0800 Peng Fan peng.fan at nxp.com wrote: > The MIB RAM and FIFO receive start register does not exist on > i.MX8. Accessing these register will cause SERROR. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Cc: Joe Hershberger <joe.hershberger@ni.com> > --- > drivers/net/fec_mxc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) This should be merged for v2018.11, so applied to u-boot-staging/agust at denx.de, thanks! -- Anatolij ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 28/41] net: fec_mxc: Add the init_clk_fec function 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (26 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 27/41] net: fec: do not access reserved register for i.MX8 Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-06-12 18:27 ` Joe Hershberger 2018-05-28 12:25 ` [U-Boot] [PATCH 29/41] sata: Add i.MX8 SATA support Peng Fan ` (14 subsequent siblings) 42 siblings, 1 reply; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot From: Ye Li <ye.li@nxp.com> When the power domain driver is enabled, we need to enable clocks after power domain on. So the clock settings can't set in board_init, needs to set them when the device is probed. Add this weak function in driver, that SoC codes can implement the clock settings. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Joe Hershberger <joe.hershberger@ni.com> --- drivers/net/fec_mxc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index b512a71c0c..d4e5a2a776 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1037,6 +1037,10 @@ struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id) return bus; } +__weak void init_clk_fec(int index) +{ +} + #ifndef CONFIG_DM_ETH #ifdef CONFIG_PHYLIB int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, @@ -1154,6 +1158,7 @@ int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) #else base_mii = addr; #endif + init_clk_fec(dev_id); debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); bus = fec_get_miibus(base_mii, dev_id); if (!bus) @@ -1253,6 +1258,8 @@ static int fecmxc_probe(struct udevice *dev) uint32_t start; int ret; + init_clk_fec(dev->seq); + ret = fec_alloc_descs(priv); if (ret) return ret; -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 28/41] net: fec_mxc: Add the init_clk_fec function 2018-05-28 12:25 ` [U-Boot] [PATCH 28/41] net: fec_mxc: Add the init_clk_fec function Peng Fan @ 2018-06-12 18:27 ` Joe Hershberger 2018-06-13 1:26 ` Simon Glass 0 siblings, 1 reply; 69+ messages in thread From: Joe Hershberger @ 2018-06-12 18:27 UTC (permalink / raw) To: u-boot Hi Peng, On Mon, May 28, 2018 at 7:25 AM, Peng Fan <peng.fan@nxp.com> wrote: > From: Ye Li <ye.li@nxp.com> > > When the power domain driver is enabled, we need to enable clocks after power > domain on. So the clock settings can't set in board_init, needs to set them > when the device is probed. Add this weak function in driver, that SoC codes > can implement the clock settings. Can you not use clock infrastructure in DM to handle this. We don't really want these direct calls out of drivers like this. Simon? Thanks, -Joe > Reviewed-by: Peng Fan <peng.fan@nxp.com> > Signed-off-by: Ye Li <ye.li@nxp.com> > Cc: Joe Hershberger <joe.hershberger@ni.com> > --- > drivers/net/fec_mxc.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c > index b512a71c0c..d4e5a2a776 100644 > --- a/drivers/net/fec_mxc.c > +++ b/drivers/net/fec_mxc.c > @@ -1037,6 +1037,10 @@ struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id) > return bus; > } > > +__weak void init_clk_fec(int index) > +{ > +} > + > #ifndef CONFIG_DM_ETH > #ifdef CONFIG_PHYLIB > int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, > @@ -1154,6 +1158,7 @@ int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) > #else > base_mii = addr; > #endif > + init_clk_fec(dev_id); > debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); > bus = fec_get_miibus(base_mii, dev_id); > if (!bus) > @@ -1253,6 +1258,8 @@ static int fecmxc_probe(struct udevice *dev) > uint32_t start; > int ret; > > + init_clk_fec(dev->seq); > + > ret = fec_alloc_descs(priv); > if (ret) > return ret; > -- > 2.14.1 > > _______________________________________________ > U-Boot mailing list > U-Boot at lists.denx.de > https://lists.denx.de/listinfo/u-boot ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 28/41] net: fec_mxc: Add the init_clk_fec function 2018-06-12 18:27 ` Joe Hershberger @ 2018-06-13 1:26 ` Simon Glass 2018-06-15 6:46 ` Peng Fan 0 siblings, 1 reply; 69+ messages in thread From: Simon Glass @ 2018-06-13 1:26 UTC (permalink / raw) To: u-boot Hi, On 12 June 2018 at 12:27, Joe Hershberger <joe.hershberger@ni.com> wrote: > > Hi Peng, > > On Mon, May 28, 2018 at 7:25 AM, Peng Fan <peng.fan@nxp.com> wrote: > > From: Ye Li <ye.li@nxp.com> > > > > When the power domain driver is enabled, we need to enable clocks after power > > domain on. So the clock settings can't set in board_init, needs to set them > > when the device is probed. Add this weak function in driver, that SoC codes > > can implement the clock settings. > > Can you not use clock infrastructure in DM to handle this. We don't > really want these direct calls out of drivers like this. Simon? > Yes that is definitely bad. Probably the easiest option is to add a clock driver. Regards, Simon ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 28/41] net: fec_mxc: Add the init_clk_fec function 2018-06-13 1:26 ` Simon Glass @ 2018-06-15 6:46 ` Peng Fan 0 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-06-15 6:46 UTC (permalink / raw) To: u-boot Hi Joe, Simon, > -----Original Message----- > From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass > Sent: 2018年6月13日 9:26 > To: Joe Hershberger <joe.hershberger@ni.com> > Cc: Peng Fan <peng.fan@nxp.com>; Stefano Babic <sbabic@denx.de>; Fabio > Estevam <fabio.estevam@nxp.com>; u-boot <u-boot@lists.denx.de> > Subject: Re: [U-Boot] [PATCH 28/41] net: fec_mxc: Add the init_clk_fec function > > Hi, > > On 12 June 2018 at 12:27, Joe Hershberger <joe.hershberger@ni.com> wrote: > > > > Hi Peng, > > > > On Mon, May 28, 2018 at 7:25 AM, Peng Fan <peng.fan@nxp.com> wrote: > > > From: Ye Li <ye.li@nxp.com> > > > > > > When the power domain driver is enabled, we need to enable clocks > > > after power domain on. So the clock settings can't set in > > > board_init, needs to set them when the device is probed. Add this > > > weak function in driver, that SoC codes can implement the clock settings. > > > > Can you not use clock infrastructure in DM to handle this. We don't > > really want these direct calls out of drivers like this. Simon? > > > > Yes that is definitely bad. > > Probably the easiest option is to add a clock driver. I'll give a try to add a clock DM driver. Thanks, Peng. > > Regards, > Simon ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 29/41] sata: Add i.MX8 SATA support 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (27 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 28/41] net: fec_mxc: Add the init_clk_fec function Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 30/41] gpio: mxc_gpio: add support for i.MX8 Peng Fan ` (13 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot From: Ye Li <ye.li@nxp.com> - some delay is required between SATA_CTRL0 RST SET and CLR. Otherwise, sata phy link would be down. - specific the ahci modification by imx8qm platform. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> --- drivers/ata/Kconfig | 6 +++++ drivers/ata/Makefile | 1 + drivers/ata/ahci.c | 25 ++++++++++++++++++++ drivers/ata/sata_imx.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 96 insertions(+) create mode 100644 drivers/ata/sata_imx.c diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 86ec628104..30fa9a2f02 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -79,6 +79,12 @@ config MVSATA_IDE Enable this driver to support the SATA controller found in some Marvell SoCs, running in IDE compatibility mode using PIO. +config SATA_IMX + bool "Enable SATA driver support for i.MX8QM" + select LIBATA + help + Enable this driver to support the SATA controller found in i.MX8QM SoCs. + config SATA_MV bool "Enable Marvell SATA controller driver support" select LIBATA diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index 02f02c8e8d..da2634c3a4 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_LIBATA) += libata.o obj-$(CONFIG_MVSATA_IDE) += mvsata_ide.o obj-$(CONFIG_SATA) += sata.o obj-$(CONFIG_SATA_CEVA) += sata_ceva.o +obj-$(CONFIG_SATA_IMX) += sata_imx.o obj-$(CONFIG_SATA_MV) += sata_mv.o obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o obj-$(CONFIG_SATA_SIL) += sata_sil.o diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index c35912bd33..39ae494c34 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -26,6 +26,16 @@ #include <dm/device-internal.h> #include <dm/lists.h> +#ifdef CONFIG_SCSI_AHCI_PLAT +#ifdef CONFIG_FSL_HSIO +#define HW_PP2C 0xAC +#define HW_PP3C 0xB0 +#define HW_PP4C 0xB4 +#define HW_PP5C 0xB8 +#define HW_PAXIC 0xC0 +#endif +#endif + static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port); #ifndef CONFIG_DM_SCSI @@ -191,6 +201,16 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv) debug("ahci_host_init: start\n"); +#ifdef CONFIG_SCSI_AHCI_PLAT +#ifdef CONFIG_FSL_HSIO + writel((1 << 28) | (1 << 24) | readl(mmio + HW_PAXIC), mmio + HW_PAXIC); + writel(0x2718461C, mmio + HW_PP2C); + writel(0x0D081907, mmio + HW_PP3C); + writel(0x06000815, mmio + HW_PP4C); + writel(0x800C96A4, mmio + HW_PP5C); +#endif +#endif + cap_save = readl(mmio + HOST_CAP); cap_save &= ((1 << 28) | (1 << 17)); cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */ @@ -270,6 +290,11 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv) ret = ahci_link_up(uc_priv, i); if (ret) { printf("SATA link %d timeout.\n", i); +#ifdef CONFIG_SCSI_AHCI_PLAT +#ifdef CONFIG_FSL_HSIO + return -ENODEV; +#endif +#endif continue; } else { debug("SATA link ok.\n"); diff --git a/drivers/ata/sata_imx.c b/drivers/ata/sata_imx.c new file mode 100644 index 0000000000..90293a6e49 --- /dev/null +++ b/drivers/ata/sata_imx.c @@ -0,0 +1,64 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <linux/errno.h> +#include <asm/io.h> +#include <asm/mach-imx/sci/sci.h> +#include <ahci.h> +#include <scsi.h> +#include <imx8_hsio.h> + +int sata_init(void) +{ + int ret; + u32 val, i = 0; + + printf("start sata init\n"); + writel(0x22222222, GPR_LPCG_PHYX2APB_0_APB); + writel(0x22222222, GPR_LPCG_PHYX1_APB); + + setbits_le32(0x5F130008, BIT(21)); + setbits_le32(0x5F130008, BIT(23)); + + /* PHY_MODE to SATA100Mhz ref clk */ + setbits_le32(HW_PHYX1_CTRL0_ADDR, BIT(19)); + + /* + * bit 0 rx ena, bit 1 tx ena, bit 11 fast_init, + * bit12 PHY_X1_EPCS_SEL 1. + */ + setbits_le32(HW_MISC_CTRL0_ADDR, HW_MISC_CTRL0_IOB_RXENA + | HW_MISC_CTRL0_PHY_X1_EPCS_SEL); + + clrbits_le32(HW_SATA_CTRL0_ADDR, HW_SATA_CTRL0_PHY_RESET); + setbits_le32(HW_SATA_CTRL0_ADDR, HW_SATA_CTRL0_PHY_RESET); + setbits_le32(HW_SATA_CTRL0_ADDR, HW_SATA_CTRL0_RESET); + udelay(1); + clrbits_le32(HW_SATA_CTRL0_ADDR, HW_SATA_CTRL0_RESET); + setbits_le32(HW_SATA_CTRL0_ADDR, HW_SATA_CTRL0_RESET); + + setbits_le32(HW_PHYX1_CTRL0_ADDR, HW_PHYX1_CTRL0_APB_RSTN); + + for (i = 0; i < 100; i++) { + val = readl(HW_PHYX1_STTS0_ADDR); + val &= HW_PHYX1_STTS0_LANE0_TX_PLL_LOCK; + if (val == HW_PHYX1_STTS0_LANE0_TX_PLL_LOCK) + break; + udelay(1); + } + + if (val != HW_PHYX1_STTS0_LANE0_TX_PLL_LOCK) { + printf("TX PLL is not locked.\n"); + return -ENODEV; + } + + ret = ahci_init((void __iomem *)AHCI_BASE_ADDR); + if (ret) + return ret; + scsi_scan(1); + + return 0; +} -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 30/41] gpio: mxc_gpio: add support for i.MX8 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (28 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 29/41] sata: Add i.MX8 SATA support Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 31/41] pinctrl: Add pinctrl driver " Peng Fan ` (12 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot Add i.MX8 support, there are 8 GPIO banks. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/include/asm/arch-imx8/gpio.h | 22 ++++++++++++++++++++++ drivers/gpio/mxc_gpio.c | 30 +++++++++++++++++++++--------- 2 files changed, 43 insertions(+), 9 deletions(-) create mode 100644 arch/arm/include/asm/arch-imx8/gpio.h diff --git a/arch/arm/include/asm/arch-imx8/gpio.h b/arch/arm/include/asm/arch-imx8/gpio.h new file mode 100644 index 0000000000..a342e6004d --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/gpio.h @@ -0,0 +1,22 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_IMX8_GPIO_H +#define __ASM_ARCH_IMX8_GPIO_H + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +/* GPIO registers */ +struct gpio_regs { + u32 gpio_dr; /* data */ + u32 gpio_dir; /* direction */ + u32 gpio_psr; /* pad satus */ +}; +#endif + +/* IMX8 the GPIO index is from 0 not 1 */ +#define IMX_GPIO_NR(port, index) (((port) * 32)+((index) & 31)) + +#endif /* __ASM_ARCH_IMX8_GPIO_H */ diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index d8e72ada19..dc1b4fb4a6 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -40,21 +40,27 @@ static unsigned long gpio_ports[] = { [2] = GPIO3_BASE_ADDR, #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX7) || defined(CONFIG_MX8M) + defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \ + defined(CONFIG_IMX8) [3] = GPIO4_BASE_ADDR, #endif #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX7) || defined(CONFIG_MX8M) + defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \ + defined(CONFIG_IMX8) [4] = GPIO5_BASE_ADDR, #if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX8M)) [5] = GPIO6_BASE_ADDR, #endif #endif -#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7) +#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ + defined(CONFIG_IMX8) #if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) [6] = GPIO7_BASE_ADDR, #endif #endif +#if defined(CONFIG_IMX8) + [7] = GPIO8_BASE_ADDR, +#endif }; static int mxc_gpio_direction(unsigned int gpio, @@ -347,19 +353,22 @@ static const struct mxc_gpio_plat mxc_plat[] = { { 2, (struct gpio_regs *)GPIO3_BASE_ADDR }, #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) + defined(CONFIG_MX8M) || defined(CONFIG_IMX8) { 3, (struct gpio_regs *)GPIO4_BASE_ADDR }, #endif #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) + defined(CONFIG_MX8M) || defined(CONFIG_IMX8) { 4, (struct gpio_regs *)GPIO5_BASE_ADDR }, #ifndef CONFIG_MX8M { 5, (struct gpio_regs *)GPIO6_BASE_ADDR }, #endif #endif -#if defined(CONFIG_MX53) || defined(CONFIG_MX6) +#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_IMX8) { 6, (struct gpio_regs *)GPIO7_BASE_ADDR }, #endif +#if defined(CONFIG_IMX8) + { 7, (struct gpio_regs *)GPIO8_BASE_ADDR }, +#endif }; U_BOOT_DEVICES(mxc_gpios) = { @@ -368,19 +377,22 @@ U_BOOT_DEVICES(mxc_gpios) = { { "gpio_mxc", &mxc_plat[2] }, #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) + defined(CONFIG_MX8M) || defined(CONFIG_IMX8) { "gpio_mxc", &mxc_plat[3] }, #endif #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) + defined(CONFIG_MX8M) || defined(CONFIG_IMX8) { "gpio_mxc", &mxc_plat[4] }, #ifndef CONFIG_MX8M { "gpio_mxc", &mxc_plat[5] }, #endif #endif -#if defined(CONFIG_MX53) || defined(CONFIG_MX6) +#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_IMX8) { "gpio_mxc", &mxc_plat[6] }, #endif +#if defined(CONFIG_IMX8) + { "gpio_mxc", &mxc_plat[7] }, +#endif }; #endif #endif -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 31/41] pinctrl: Add pinctrl driver for i.MX8 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (29 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 30/41] gpio: mxc_gpio: add support for i.MX8 Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 32/41] power: Add power domain " Peng Fan ` (11 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot Add pinctrl driver for i.MX8. The pads configuration is controlled by SCU, so need to ask SCU to configure pads through scfw API. Add pinctrl-scu to invoke sc_pad_set to configue pads. Add a new flag IMX8_USE_SCU to differentiate i.MX8 from other platforms which could directly configure pads from Acore side. Add CONFIG_PINCTRL_IMX8 as the built gate. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> --- drivers/pinctrl/nxp/Kconfig | 18 ++++ drivers/pinctrl/nxp/Makefile | 2 + drivers/pinctrl/nxp/pinctrl-imx.c | 209 ++++++++++++++++++++----------------- drivers/pinctrl/nxp/pinctrl-imx.h | 16 +++ drivers/pinctrl/nxp/pinctrl-imx8.c | 42 ++++++++ drivers/pinctrl/nxp/pinctrl-scu.c | 72 +++++++++++++ 6 files changed, 266 insertions(+), 93 deletions(-) create mode 100644 drivers/pinctrl/nxp/pinctrl-imx8.c create mode 100644 drivers/pinctrl/nxp/pinctrl-scu.c diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig index b668359a0b..449ad47ebc 100644 --- a/drivers/pinctrl/nxp/Kconfig +++ b/drivers/pinctrl/nxp/Kconfig @@ -1,6 +1,9 @@ config PINCTRL_IMX bool +config PINCTRL_IMX_SCU + bool + config PINCTRL_IMX5 bool "IMX5 pinctrl driver" depends on ARCH_MX5 && PINCTRL_FULL @@ -56,3 +59,18 @@ config PINCTRL_IMX7ULP is different from the linux one, this is a simple implementation, only parses the 'fsl,pins' property and configure related registers. + +config PINCTRL_IMX8 + bool "IMX8 pinctrl driver" + depends on ARCH_IMX8 && PINCTRL_FULL + select DEVRES + select PINCTRL_IMX + select PINCTRL_IMX_SCU + help + Say Y here to enable the imx8 pinctrl driver + + This provides a simple pinctrl driver for i.MX8 SoC familiy. + This feature depends on device tree configuration. This driver + is different from the linux one, this is a simple implementation, + only parses the 'fsl,pins' property and configure related + registers. diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile index c763948376..310b3b3a2e 100644 --- a/drivers/pinctrl/nxp/Makefile +++ b/drivers/pinctrl/nxp/Makefile @@ -3,3 +3,5 @@ obj-$(CONFIG_PINCTRL_IMX5) += pinctrl-imx5.o obj-$(CONFIG_PINCTRL_IMX6) += pinctrl-imx6.o obj-$(CONFIG_PINCTRL_IMX7) += pinctrl-imx7.o obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o +obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o +obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c index 36e1e8983c..04ea82aba5 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx.c +++ b/drivers/pinctrl/nxp/pinctrl-imx.c @@ -28,7 +28,9 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) dev_dbg(dev, "%s: %s\n", __func__, config->name); - if (info->flags & SHARE_MUX_CONF_REG) + if (info->flags & IMX8_USE_SCU) + pin_size = SHARE_IMX8_PIN_SIZE; + else if (info->flags & SHARE_MUX_CONF_REG) pin_size = SHARE_FSL_PIN_SIZE; else pin_size = FSL_PIN_SIZE; @@ -58,112 +60,127 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) npins = size / pin_size; - /* - * Refer to linux documentation for details: - * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt - */ - for (i = 0; i < npins; i++) { - mux_reg = pin_data[j++]; - - if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) - mux_reg = -1; - - if (info->flags & SHARE_MUX_CONF_REG) { - conf_reg = mux_reg; - } else { - conf_reg = pin_data[j++]; - if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg) - conf_reg = -1; - } + if (info->flags & IMX8_USE_SCU) { + imx_pinctrl_scu_conf_pins(info, pin_data, npins); + } else { + /* + * Refer to linux documentation for details: + * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt + */ + for (i = 0; i < npins; i++) { + mux_reg = pin_data[j++]; - if ((mux_reg == -1) || (conf_reg == -1)) { - dev_err(dev, "Error mux_reg or conf_reg\n"); - devm_kfree(dev, pin_data); - return -EINVAL; - } + if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) + mux_reg = -1; - input_reg = pin_data[j++]; - mux_mode = pin_data[j++]; - input_val = pin_data[j++]; - config_val = pin_data[j++]; + if (info->flags & SHARE_MUX_CONF_REG) { + conf_reg = mux_reg; + } else { + conf_reg = pin_data[j++]; + if (!(info->flags & ZERO_OFFSET_VALID) && + !conf_reg) + conf_reg = -1; + } - dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, input_reg 0x%x, " - "mux_mode 0x%x, input_val 0x%x, config_val 0x%x\n", - mux_reg, conf_reg, input_reg, mux_mode, input_val, - config_val); + if ((mux_reg == -1) || (conf_reg == -1)) { + dev_err(dev, "Error mux_reg or conf_reg\n"); + devm_kfree(dev, pin_data); + return -EINVAL; + } - if (config_val & IMX_PAD_SION) - mux_mode |= IOMUXC_CONFIG_SION; + input_reg = pin_data[j++]; + mux_mode = pin_data[j++]; + input_val = pin_data[j++]; + config_val = pin_data[j++]; - config_val &= ~IMX_PAD_SION; + dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, " + "input_reg 0x%x, mux_mode 0x%x, " + "input_val 0x%x, config_val 0x%x\n", + mux_reg, conf_reg, input_reg, mux_mode, + input_val, config_val); - /* Set Mux */ - if (info->flags & SHARE_MUX_CONF_REG) { - clrsetbits_le32(info->base + mux_reg, info->mux_mask, - mux_mode << mux_shift); - } else { - writel(mux_mode, info->base + mux_reg); - } + if (config_val & IMX_PAD_SION) + mux_mode |= IOMUXC_CONFIG_SION; - dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n", mux_reg, - mux_mode); + config_val &= ~IMX_PAD_SION; - /* - * Set select input - * - * If the select input value begins with 0xff, it's a quirky - * select input and the value should be interpreted as below. - * 31 23 15 7 0 - * | 0xff | shift | width | select | - * It's used to work around the problem that the select - * input for some pin is not implemented in the select - * input register but in some general purpose register. - * We encode the select input value, width and shift of - * the bit field into input_val cell of pin function ID - * in device tree, and then decode them here for setting - * up the select input bits in general purpose register. - */ + /* Set Mux */ + if (info->flags & SHARE_MUX_CONF_REG) { + clrsetbits_le32(info->base + mux_reg, + info->mux_mask, + mux_mode << mux_shift); + } else { + writel(mux_mode, info->base + mux_reg); + } + + dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n", + mux_reg, mux_mode); - if (input_val >> 24 == 0xff) { - u32 val = input_val; - u8 select = val & 0xff; - u8 width = (val >> 8) & 0xff; - u8 shift = (val >> 16) & 0xff; - u32 mask = ((1 << width) - 1) << shift; - /* - * The input_reg[i] here is actually some IOMUXC general - * purpose register, not regular select input register. - */ - val = readl(info->base + input_reg); - val &= ~mask; - val |= select << shift; - writel(val, info->base + input_reg); - } else if (input_reg) { /* - * Regular select input register can never be at offset - * 0, and we only print register value for regular case. + * Set select input + * + * If the select input value begins with 0xff, + * it's a quirky select input and the value should + * be interpreted as below. + * 31 23 15 7 0 + * | 0xff | shift | width | select | + * It's used to work around the problem that the + * select input for some pin is not implemented in + * the select input register but in some general + * purpose register. We encode the select input + * value, width and shift of the bit field into + * input_val cell of pin function ID in device tree, + * and then decode them here for setting up the select + * input bits in general purpose register. */ - if (info->input_sel_base) - writel(input_val, info->input_sel_base + - input_reg); - else - writel(input_val, info->base + input_reg); - - dev_dbg(dev, "select_input: offset 0x%x val 0x%x\n", - input_reg, input_val); - } - /* Set config */ - if (!(config_val & IMX_NO_PAD_CTL)) { - if (info->flags & SHARE_MUX_CONF_REG) { - clrsetbits_le32(info->base + conf_reg, - ~info->mux_mask, config_val); - } else { - writel(config_val, info->base + conf_reg); + if (input_val >> 24 == 0xff) { + u32 val = input_val; + u8 select = val & 0xff; + u8 width = (val >> 8) & 0xff; + u8 shift = (val >> 16) & 0xff; + u32 mask = ((1 << width) - 1) << shift; + /* + * The input_reg[i] here is actually some + * IOMUXC general purpose register, not + * regular select input register. + */ + val = readl(info->base + input_reg); + val &= ~mask; + val |= select << shift; + writel(val, info->base + input_reg); + } else if (input_reg) { + /* + * Regular select input register can never be + * at offset 0, and we only print register + * value for regular case. + */ + if (info->input_sel_base) + writel(input_val, + info->input_sel_base + + input_reg); + else + writel(input_val, + info->base + input_reg); + + dev_dbg(dev, "select_input: offset 0x%x val " + "0x%x\n", input_reg, input_val); } - dev_dbg(dev, "write config: offset 0x%x val 0x%x\n", - conf_reg, config_val); + /* Set config */ + if (!(config_val & IMX_NO_PAD_CTL)) { + if (info->flags & SHARE_MUX_CONF_REG) { + clrsetbits_le32(info->base + conf_reg, + ~info->mux_mask, + config_val); + } else { + writel(config_val, + info->base + conf_reg); + } + + dev_dbg(dev, "write config: offset 0x%x val " + "0x%x\n", conf_reg, config_val); + } } } @@ -193,6 +210,9 @@ int imx_pinctrl_probe(struct udevice *dev, priv->dev = dev; priv->info = info; + if (info->flags & IMX8_USE_SCU) + return 0; + addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg", &size); @@ -238,6 +258,9 @@ int imx_pinctrl_remove(struct udevice *dev) struct imx_pinctrl_priv *priv = dev_get_priv(dev); struct imx_pinctrl_soc_info *info = priv->info; + if (info->flags & IMX8_USE_SCU) + return 0; + if (info->input_sel_base) unmap_sysmem(info->input_sel_base); if (info->base) diff --git a/drivers/pinctrl/nxp/pinctrl-imx.h b/drivers/pinctrl/nxp/pinctrl-imx.h index b0032455b7..947975ee72 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx.h +++ b/drivers/pinctrl/nxp/pinctrl-imx.h @@ -40,13 +40,29 @@ extern const struct pinctrl_ops imx_pinctrl_ops; #define FSL_PIN_SIZE 24 #define SHARE_FSL_PIN_SIZE 20 +/* Each pin on imx8qm/qxp consists of 2 u32 PIN_FUNC_ID and 1 u32 CONFIG */ +#define SHARE_IMX8_PIN_SIZE 12 + #define SHARE_MUX_CONF_REG 0x1 #define ZERO_OFFSET_VALID 0x2 #define CONFIG_IBE_OBE 0x4 +#define IMX8_USE_SCU 0x8 #define IOMUXC_CONFIG_SION (0x1 << 4) int imx_pinctrl_probe(struct udevice *dev, struct imx_pinctrl_soc_info *info); int imx_pinctrl_remove(struct udevice *dev); + +#ifdef CONFIG_PINCTRL_IMX_SCU +int imx_pinctrl_scu_conf_pins(struct imx_pinctrl_soc_info *info, + u32 *pin_data, int npins); +#else +static inline int imx_pinctrl_scu_conf_pins(struct imx_pinctrl_soc_info *info, + u32 *pin_data, int npins) +{ + return 0; +} +#endif + #endif /* __DRIVERS_PINCTRL_IMX_H */ diff --git a/drivers/pinctrl/nxp/pinctrl-imx8.c b/drivers/pinctrl/nxp/pinctrl-imx8.c new file mode 100644 index 0000000000..26bc160318 --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imx8.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <dm/device.h> +#include <dm/pinctrl.h> + +#include "pinctrl-imx.h" + +DECLARE_GLOBAL_DATA_PTR; + +static struct imx_pinctrl_soc_info imx8_pinctrl_soc_info = { + .flags = IMX8_USE_SCU, +}; + +static int imx8_pinctrl_probe(struct udevice *dev) +{ + struct imx_pinctrl_soc_info *info = + (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); + + info->base = (void *)gd->arch.ipc_channel_handle; + + return imx_pinctrl_probe(dev, info); +} + +static const struct udevice_id imx8_pinctrl_match[] = { + { .compatible = "fsl,imx8qxp-iomuxc", .data = (ulong)&imx8_pinctrl_soc_info }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(imx8_pinctrl) = { + .name = "imx8_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(imx8_pinctrl_match), + .probe = imx8_pinctrl_probe, + .remove = imx_pinctrl_remove, + .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), + .ops = &imx_pinctrl_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/pinctrl/nxp/pinctrl-scu.c b/drivers/pinctrl/nxp/pinctrl-scu.c new file mode 100644 index 0000000000..ca9222feeb --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-scu.c @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <errno.h> +#include <linux/bitops.h> +#include <asm/io.h> +#include <asm/arch/sci/sci.h> + +#include "pinctrl-imx.h" + +#define PADRING_IFMUX_EN_SHIFT 31 +#define PADRING_IFMUX_EN_MASK BIT(31) +#define PADRING_GP_EN_SHIFT 30 +#define PADRING_GP_EN_MASK BIT(30) +#define PADRING_IFMUX_SHIFT 27 +#define PADRING_IFMUX_MASK GENMASK(29, 27) + +static int imx_pinconf_scu_set(struct imx_pinctrl_soc_info *info, u32 pin_id, + u32 mux, u32 val) +{ + sc_err_t err; + sc_ipc_t ipchndl = (sc_ipc_t)info->base; + + /* + * Mux should be done in pmx set, but we do not have a good api + * to handle that in scfw, so config it in pad conf func + */ + + if (ipchndl == 0) { + puts("IPC handle not initialized!\n"); + return -EIO; + } + + val |= PADRING_IFMUX_EN_MASK; + val |= PADRING_GP_EN_MASK; + val |= (mux << PADRING_IFMUX_SHIFT) & PADRING_IFMUX_MASK; + + err = sc_pad_set(ipchndl, pin_id, val); + + if (err != SC_ERR_NONE) + return -EIO; + + return 0; +} + +int imx_pinctrl_scu_conf_pins(struct imx_pinctrl_soc_info *info, u32 *pin_data, + int npins) +{ + int pin_id, mux, config_val; + int i, j = 0; + int ret; + + /* + * Refer to linux documentation for details: + * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt + */ + for (i = 0; i < npins; i++) { + pin_id = pin_data[j++]; + mux = pin_data[j++]; + config_val = pin_data[j++]; + + ret = imx_pinconf_scu_set(info, pin_id, mux, config_val); + if (ret) + printf("Set pin %d, mux %d, val %d, error\n", pin_id, + mux, config_val); + } + + return 0; +} -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 32/41] power: Add power domain driver for i.MX8 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (30 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 31/41] pinctrl: Add pinctrl driver " Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 33/41] power: Add PD device lookup interface to power domain uclass Peng Fan ` (10 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot Add the power domain DM driver for i.MX8, that it depends on the DTB power domain trees to generate the power domain provider devices. Users needs add power domain trees with property "compatible = "nxp,imx8-pd";" When power on one PD device, the driver will power on its ancestor PD devices in power domain tree. When power off on PD device, the driver will check its child PD devices first, only all child PD devices are off, then power off the current PD device. Then the driver checks sibling PD devices. If sibling PD devices are off, then it will power off parent PD device. There is no counter maintained in this driver, but a state to hold current on/off state. So the request and free functions are empty. The power domain implementation in i.MX8 DTB set the "#power-domain-cells" to 0, so there is no ID binding with each PD device. We don't use "id" variable in struct power_domain. At same time, we have to set of_xlate to empty to bypass standard of_xlate in uclass driver. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> --- arch/arm/include/asm/arch-imx8/power-domain.h | 15 ++ drivers/power/domain/Kconfig | 6 + drivers/power/domain/Makefile | 1 + drivers/power/domain/imx8-power-domain.c | 315 ++++++++++++++++++++++++++ 4 files changed, 337 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8/power-domain.h create mode 100644 drivers/power/domain/imx8-power-domain.c diff --git a/arch/arm/include/asm/arch-imx8/power-domain.h b/arch/arm/include/asm/arch-imx8/power-domain.h new file mode 100644 index 0000000000..1396008877 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/power-domain.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 NXP + */ + +#ifndef _ASM_ARCH_IMX8_POWER_DOMAIN_H +#define _ASM_ARCH_IMX8_POWER_DOMAIN_H + +#include <asm/arch/sci/types.h> + +struct imx8_power_domain_platdata { + sc_rsrc_t resource_id; +}; + +#endif diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig index 7cfa761498..2a72642a26 100644 --- a/drivers/power/domain/Kconfig +++ b/drivers/power/domain/Kconfig @@ -31,4 +31,10 @@ config TEGRA186_POWER_DOMAIN Enable support for manipulating Tegra's on-SoC power domains via IPC requests to the BPMP (Boot and Power Management Processor). +config IMX8_POWER_DOMAIN + bool "Enable i.MX8 power domain driver" + depends on ARCH_IMX8 + help + Enable support for manipulating NXP i.MX8 on-SoC power domains via IPC + requests to the SCU. endmenu diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile index c7d7644402..c6ad7ff447 100644 --- a/drivers/power/domain/Makefile +++ b/drivers/power/domain/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o +obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain.o diff --git a/drivers/power/domain/imx8-power-domain.c b/drivers/power/domain/imx8-power-domain.c new file mode 100644 index 0000000000..057119ca70 --- /dev/null +++ b/drivers/power/domain/imx8-power-domain.c @@ -0,0 +1,315 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2017 NXP + */ + +#include <common.h> +#include <dm.h> +#include <power-domain-uclass.h> +#include <asm/io.h> +#include <asm/arch/power-domain.h> +#include <dm/device-internal.h> +#include <dm/device.h> +#include <asm/arch/sci/sci.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct imx8_power_domain_priv { + bool state_on; +}; + +static int imx8_power_domain_request(struct power_domain *power_domain) +{ + debug("%s(power_domain=%p)\n", __func__, power_domain); + + return 0; +} + +static int imx8_power_domain_free(struct power_domain *power_domain) +{ + debug("%s(power_domain=%p)\n", __func__, power_domain); + + return 0; +} + +static int imx8_power_domain_on(struct power_domain *power_domain) +{ + struct udevice *dev = power_domain->dev; + struct imx8_power_domain_platdata *pdata; + struct imx8_power_domain_priv *ppriv; + sc_ipc_t ipchndl = gd->arch.ipc_channel_handle; + sc_err_t ret; + + struct power_domain parent_domain; + struct udevice *parent = dev_get_parent(dev); + + /* Need to power on parent node first */ + if (device_get_uclass_id(parent) == UCLASS_POWER_DOMAIN) { + parent_domain.dev = parent; + imx8_power_domain_on(&parent_domain); + } + + pdata = (struct imx8_power_domain_platdata *)dev_get_platdata(dev); + ppriv = (struct imx8_power_domain_priv *)dev_get_priv(dev); + + debug("%s(power_domain=%s) resource_id %d\n", __func__, dev->name, + pdata->resource_id); + + /* Already powered on */ + if (ppriv->state_on) + return 0; + + if (pdata->resource_id != SC_R_LAST) { + ret = sc_pm_set_resource_power_mode(ipchndl, + pdata->resource_id, + SC_PM_PW_MODE_ON); + if (ret) { + printf("Error: %s Power up failed! (error = %d)\n", + dev->name, ret); + return -EIO; + } + } + + ppriv->state_on = true; + debug("%s is powered on\n", dev->name); + + return 0; +} + +static int imx8_power_domain_off_node(struct power_domain *power_domain) +{ + struct udevice *dev = power_domain->dev; + struct udevice *child; + struct imx8_power_domain_priv *ppriv; + struct imx8_power_domain_priv *child_ppriv; + struct imx8_power_domain_platdata *pdata; + sc_ipc_t ipchndl = gd->arch.ipc_channel_handle; + sc_err_t ret; + + ppriv = (struct imx8_power_domain_priv *)dev_get_priv(dev); + pdata = (struct imx8_power_domain_platdata *)dev_get_platdata(dev); + + debug("%s, %s, state_on %d\n", __func__, dev->name, ppriv->state_on); + + /* Already powered off */ + if (!ppriv->state_on) + return 0; + + /* Check if all subnodes are off */ + for (device_find_first_child(dev, &child); + child; + device_find_next_child(&child)) { + if (device_active(child)) { + child_ppriv = (struct imx8_power_domain_priv *)dev_get_priv(child); + if (child_ppriv->state_on) + return -EPERM; + } + } + + if (pdata->resource_id != SC_R_LAST) { + if (!sc_rm_is_resource_owned(ipchndl, pdata->resource_id)) { + printf("%s not owned by curr partition\n", dev->name); + return 0; + } + ret = sc_pm_set_resource_power_mode(ipchndl, + pdata->resource_id, + SC_PM_PW_MODE_OFF); + if (ret) { + printf("Error: %s Power off failed! (error = %d)\n", + dev->name, ret); + return -EIO; + } + } + + ppriv->state_on = false; + debug("%s is powered off\n", dev->name); + + return 0; +} + +static int imx8_power_domain_off_parentnodes(struct power_domain *power_domain) +{ + struct udevice *dev = power_domain->dev; + struct udevice *parent = dev_get_parent(dev); + struct udevice *child; + struct imx8_power_domain_priv *ppriv; + struct imx8_power_domain_priv *child_ppriv; + struct imx8_power_domain_platdata *pdata; + sc_ipc_t ipchndl = gd->arch.ipc_channel_handle; + sc_err_t ret; + struct power_domain parent_pd; + + if (device_get_uclass_id(parent) == UCLASS_POWER_DOMAIN) { + pdata = + (struct imx8_power_domain_platdata *)dev_get_platdata(parent); + ppriv = (struct imx8_power_domain_priv *)dev_get_priv(parent); + + debug("%s, %s, state_on %d\n", __func__, parent->name, + ppriv->state_on); + + /* Already powered off */ + if (!ppriv->state_on) + return 0; + + /* + * Check if all sibling nodes are off. If yes, + * power off parent + */ + for (device_find_first_child(parent, &child); child; + device_find_next_child(&child)) { + if (device_active(child)) { + child_ppriv = (struct imx8_power_domain_priv *)dev_get_priv(child); + /* Find a power on sibling */ + if (child_ppriv->state_on) { + debug("sibling %s, state_on %d\n", + child->name, + child_ppriv->state_on); + return 0; + } + } + } + + /* power off parent */ + if (pdata->resource_id != SC_R_LAST) { + ret = sc_pm_set_resource_power_mode(ipchndl, + pdata->resource_id, + SC_PM_PW_MODE_OFF); + if (ret) { + printf("%s Power off failed! (error = %d)\n", + parent->name, ret); + return -EIO; + } + } + + ppriv->state_on = false; + debug("%s is powered off\n", parent->name); + + parent_pd.dev = parent; + imx8_power_domain_off_parentnodes(&parent_pd); + } + + return 0; +} + +static int imx8_power_domain_off(struct power_domain *power_domain) +{ + int ret; + + debug("%s(power_domain=%p)\n", __func__, power_domain); + + /* Turn off the node */ + ret = imx8_power_domain_off_node(power_domain); + if (ret) { + debug("Can't power off the node of dev %s, ret = %d\n", + power_domain->dev->name, ret); + return ret; + } + + /* Turn off parent nodes, if sibling nodes are all off */ + ret = imx8_power_domain_off_parentnodes(power_domain); + if (ret) { + printf("Failed to power off parent nodes of dev %s, ret = %d\n", + power_domain->dev->name, ret); + return ret; + } + + return 0; +} + +static int imx8_power_domain_of_xlate(struct power_domain *power_domain, + struct ofnode_phandle_args *args) +{ + debug("%s(power_domain=%p)\n", __func__, power_domain); + + /* Do nothing to the xlate, since we don't have args used */ + + return 0; +} + +static int imx8_power_domain_bind(struct udevice *dev) +{ + int offset; + const char *name; + int ret = 0; + + debug("%s(dev=%p)\n", __func__, dev); + + offset = dev_of_offset(dev); + for (offset = fdt_first_subnode(gd->fdt_blob, offset); offset > 0; + offset = fdt_next_subnode(gd->fdt_blob, offset)) { + /* Bind the subnode to this driver */ + name = fdt_get_name(gd->fdt_blob, offset, NULL); + + ret = device_bind_with_driver_data(dev, dev->driver, name, + dev->driver_data, + offset_to_ofnode(offset), + NULL); + + if (ret == -ENODEV) + printf("Driver '%s' refuses to bind\n", + dev->driver->name); + + if (ret) + printf("Error binding driver '%s': %d\n", + dev->driver->name, ret); + } + + return 0; +} + +static int imx8_power_domain_probe(struct udevice *dev) +{ + struct imx8_power_domain_priv *ppriv; + + debug("%s(dev=%s)\n", __func__, dev->name); + + ppriv = (struct imx8_power_domain_priv *)dev_get_priv(dev); + + /* Set default to power off */ + if (ppriv) + ppriv->state_on = false; + + return 0; +} + +static int imx8_power_domain_ofdata_to_platdata(struct udevice *dev) +{ + int reg; + struct imx8_power_domain_platdata *pdata = dev_get_platdata(dev); + + reg = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1); + if (reg == -1) { + debug("%s: Invalid resource id %d\n", __func__, reg); + return -EINVAL; + } + pdata->resource_id = (sc_rsrc_t)reg; + + debug("%s resource_id %d\n", __func__, pdata->resource_id); + + return 0; +} + +static const struct udevice_id imx8_power_domain_ids[] = { + { .compatible = "nxp,imx8-pd" }, + { } +}; + +struct power_domain_ops imx8_power_domain_ops = { + .request = imx8_power_domain_request, + .free = imx8_power_domain_free, + .on = imx8_power_domain_on, + .off = imx8_power_domain_off, + .of_xlate = imx8_power_domain_of_xlate, +}; + +U_BOOT_DRIVER(imx8_power_domain) = { + .name = "imx8_power_domain", + .id = UCLASS_POWER_DOMAIN, + .of_match = imx8_power_domain_ids, + .bind = imx8_power_domain_bind, + .probe = imx8_power_domain_probe, + .ofdata_to_platdata = imx8_power_domain_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct imx8_power_domain_platdata), + .priv_auto_alloc_size = sizeof(struct imx8_power_domain_priv), + .ops = &imx8_power_domain_ops, +}; -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 33/41] power: Add PD device lookup interface to power domain uclass 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (31 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 32/41] power: Add power domain " Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-05-30 19:18 ` Simon Glass 2018-05-28 12:25 ` [U-Boot] [PATCH 34/41] power-domain: add dummy functions when CONFIG_POWER_DOMAIN not defined Peng Fan ` (9 subsequent siblings) 42 siblings, 1 reply; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot Add power_domain_lookup_name interface to power domain uclass to find a power domain device by its DTB node name, not using its associated client device. Through this interface, we can operate the power domain devices directly. This is needed for non-DM drivers. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> --- drivers/power/domain/power-domain-uclass.c | 42 ++++++++++++++++++++++++++++++ include/power-domain.h | 15 +++++++++++ 2 files changed, 57 insertions(+) diff --git a/drivers/power/domain/power-domain-uclass.c b/drivers/power/domain/power-domain-uclass.c index 9e9ec4f419..4e9bcbdfae 100644 --- a/drivers/power/domain/power-domain-uclass.c +++ b/drivers/power/domain/power-domain-uclass.c @@ -7,6 +7,8 @@ #include <dm.h> #include <power-domain.h> #include <power-domain-uclass.h> +#include <dm/uclass-internal.h> +#include <dm/device-internal.h> static inline struct power_domain_ops *power_domain_dev_ops(struct udevice *dev) { @@ -28,6 +30,46 @@ static int power_domain_of_xlate_default(struct power_domain *power_domain, return 0; } +int power_domain_lookup_name(const char *name, + struct power_domain *power_domain) +{ + struct udevice *dev; + struct power_domain_ops *ops; + int ret; + + debug("%s(power_domain=%p name=%s)\n", __func__, power_domain, name); + + ret = uclass_find_device_by_name(UCLASS_POWER_DOMAIN, name, &dev); + if (!ret) { + /* Probe the dev */ + device_probe(dev); + ops = power_domain_dev_ops(dev); + + power_domain->dev = dev; + if (ops->of_xlate) + ret = ops->of_xlate(power_domain, NULL); + else + ret = power_domain_of_xlate_default(power_domain, NULL); + if (ret) { + debug("of_xlate() failed: %d\n", ret); + return ret; + } + + ret = ops->request(power_domain); + if (ret) { + debug("ops->request() failed: %d\n", ret); + return ret; + } + + debug("%s ok: %s\n", __func__, dev->name); + + return 0; + } + + printf("%s fail: %s, ret = %d\n", __func__, name, ret); + return -EINVAL; +} + int power_domain_get(struct udevice *dev, struct power_domain *power_domain) { struct ofnode_phandle_args args; diff --git a/include/power-domain.h b/include/power-domain.h index aba8c0f65c..9060b174c0 100644 --- a/include/power-domain.h +++ b/include/power-domain.h @@ -74,6 +74,21 @@ struct power_domain { unsigned long id; }; +/** + * power_domain_lookup_name - Lookup the power domain device by name. + * + * This looks up and requests a provider power domain by using its + * device name. This skip the associated client device, but directly + * get the power domain device. + * + * @name: The power domain device's name. + * @power_domain A pointer to a power domain struct to initialize. + * @return 0 if OK, or a negative error code. + */ + +int power_domain_lookup_name(const char *name, + struct power_domain *power_domain); + /** * power_domain_get - Get/request the power domain for a device. * -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 33/41] power: Add PD device lookup interface to power domain uclass 2018-05-28 12:25 ` [U-Boot] [PATCH 33/41] power: Add PD device lookup interface to power domain uclass Peng Fan @ 2018-05-30 19:18 ` Simon Glass 0 siblings, 0 replies; 69+ messages in thread From: Simon Glass @ 2018-05-30 19:18 UTC (permalink / raw) To: u-boot Hi Peng, On 28 May 2018 at 06:25, Peng Fan <peng.fan@nxp.com> wrote: > Add power_domain_lookup_name interface to power domain uclass to find > a power domain device by its DTB node name, not using its associated > client device. > > Through this interface, we can operate the power domain devices directly. > This is needed for non-DM drivers. > > Signed-off-by: Ye Li <ye.li@nxp.com> > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Cc: Simon Glass <sjg@chromium.org> > --- > drivers/power/domain/power-domain-uclass.c | 42 ++++++++++++++++++++++++++++++ > include/power-domain.h | 15 +++++++++++ > 2 files changed, 57 insertions(+) > Please add a test to test/dm/power-domain.c for your newe function. Regards, Simon ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 34/41] power-domain: add dummy functions when CONFIG_POWER_DOMAIN not defined 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (32 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 33/41] power: Add PD device lookup interface to power domain uclass Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-05-30 19:18 ` Simon Glass 2018-05-28 12:25 ` [U-Boot] [PATCH 35/41] dm: core: device: enable power domain in probe Peng Fan ` (8 subsequent siblings) 42 siblings, 1 reply; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot Add dummy functions when CONFIG_POWER_DOMAIN not defined. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> --- include/power-domain.h | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/include/power-domain.h b/include/power-domain.h index 9060b174c0..a990479d03 100644 --- a/include/power-domain.h +++ b/include/power-domain.h @@ -86,8 +86,16 @@ struct power_domain { * @return 0 if OK, or a negative error code. */ +#ifdef CONFIG_POWER_DOMAIN int power_domain_lookup_name(const char *name, struct power_domain *power_domain); +#else +static inline int power_domain_lookup_name(const char *name, + struct power_domain *power_domain) +{ + return -EINVAL; +} +#endif /** * power_domain_get - Get/request the power domain for a device. @@ -102,7 +110,15 @@ int power_domain_lookup_name(const char *name, * @power_domain A pointer to a power domain struct to initialize. * @return 0 if OK, or a negative error code. */ +#ifdef CONFIG_POWER_DOMAIN int power_domain_get(struct udevice *dev, struct power_domain *power_domain); +#else +static inline int power_domain_get(struct udevice *dev, + struct power_domain *power_domain) +{ + return -EINVAL; +} +#endif /** * power_domain_free - Free a previously requested power domain. @@ -111,7 +127,14 @@ int power_domain_get(struct udevice *dev, struct power_domain *power_domain); * requested by power_domain_get(). * @return 0 if OK, or a negative error code. */ +#ifdef CONFIG_POWER_DOMAIN int power_domain_free(struct power_domain *power_domain); +#else +static inline int power_domain_free(struct power_domain *power_domain) +{ + return -EINVAL; +} +#endif /** * power_domain_on - Enable power to a power domain. @@ -120,7 +143,14 @@ int power_domain_free(struct power_domain *power_domain); * requested by power_domain_get(). * @return 0 if OK, or a negative error code. */ +#ifdef CONFIG_POWER_DOMAIN int power_domain_on(struct power_domain *power_domain); +#else +static inline int power_domain_on(struct power_domain *power_domain); +{ + return -EINVAL; +} +#endif /** * power_domain_off - Disable power ot a power domain. @@ -129,6 +159,13 @@ int power_domain_on(struct power_domain *power_domain); * requested by power_domain_get(). * @return 0 if OK, or a negative error code. */ +#ifdef CONFIG_POWER_DOMAIN int power_domain_off(struct power_domain *power_domain); +#else +static inline int power_domain_off(struct power_domain *power_domain) +{ + return -EINVAL; +} +#endif #endif -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 34/41] power-domain: add dummy functions when CONFIG_POWER_DOMAIN not defined 2018-05-28 12:25 ` [U-Boot] [PATCH 34/41] power-domain: add dummy functions when CONFIG_POWER_DOMAIN not defined Peng Fan @ 2018-05-30 19:18 ` Simon Glass 0 siblings, 0 replies; 69+ messages in thread From: Simon Glass @ 2018-05-30 19:18 UTC (permalink / raw) To: u-boot On 28 May 2018 at 06:25, Peng Fan <peng.fan@nxp.com> wrote: > Add dummy functions when CONFIG_POWER_DOMAIN not defined. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Cc: Simon Glass <sjg@chromium.org> > --- > include/power-domain.h | 37 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) Reviewed-by: Simon Glass <sjg@chromium.org> ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 35/41] dm: core: device: enable power domain in probe 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (33 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 34/41] power-domain: add dummy functions when CONFIG_POWER_DOMAIN not defined Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-05-30 19:18 ` Simon Glass 2018-05-28 12:25 ` [U-Boot] [PATCH 36/41] drivers: regulator: fixed: add off-on-delay-us Peng Fan ` (7 subsequent siblings) 42 siblings, 1 reply; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot Enable power domain associated with the device when probe. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> --- drivers/core/device.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/core/device.c b/drivers/core/device.c index e048e1a659..b6950d9dbb 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -26,6 +26,7 @@ #include <dm/util.h> #include <linux/err.h> #include <linux/list.h> +#include <power-domain.h> DECLARE_GLOBAL_DATA_PTR; @@ -296,6 +297,7 @@ static void *alloc_priv(int size, uint flags) int device_probe(struct udevice *dev) { + struct power_domain pd; const struct driver *drv; int size = 0; int ret; @@ -375,6 +377,11 @@ int device_probe(struct udevice *dev) if (dev->parent && device_get_uclass_id(dev) != UCLASS_PINCTRL) pinctrl_select_state(dev, "default"); + if (dev->parent && device_get_uclass_id(dev) != UCLASS_POWER_DOMAIN) { + if (!power_domain_get(dev, &pd)) + power_domain_on(&pd); + } + ret = uclass_pre_probe_device(dev); if (ret) goto fail; -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 35/41] dm: core: device: enable power domain in probe 2018-05-28 12:25 ` [U-Boot] [PATCH 35/41] dm: core: device: enable power domain in probe Peng Fan @ 2018-05-30 19:18 ` Simon Glass 2018-07-18 12:56 ` Peng Fan 0 siblings, 1 reply; 69+ messages in thread From: Simon Glass @ 2018-05-30 19:18 UTC (permalink / raw) To: u-boot On 28 May 2018 at 06:25, Peng Fan <peng.fan@nxp.com> wrote: > Enable power domain associated with the device when probe. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Cc: Simon Glass <sjg@chromium.org> > --- > drivers/core/device.c | 7 +++++++ > 1 file changed, 7 insertions(+) > How is this feature tested at present? Can you add something to the power-domain test? ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 35/41] dm: core: device: enable power domain in probe 2018-05-30 19:18 ` Simon Glass @ 2018-07-18 12:56 ` Peng Fan 2018-07-19 1:32 ` Simon Glass 0 siblings, 1 reply; 69+ messages in thread From: Peng Fan @ 2018-07-18 12:56 UTC (permalink / raw) To: u-boot Hi Simon > -----Original Message----- > From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass > Sent: 2018年5月31日 3:19 > To: Peng Fan <peng.fan@nxp.com> > Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam > <fabio.estevam@nxp.com>; U-Boot Mailing List <u-boot@lists.denx.de> > Subject: Re: [PATCH 35/41] dm: core: device: enable power domain in probe > > On 28 May 2018 at 06:25, Peng Fan <peng.fan@nxp.com> wrote: > > Enable power domain associated with the device when probe. > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > > Cc: Simon Glass <sjg@chromium.org> > > --- > > drivers/core/device.c | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > How is this feature tested at present? Can you add something to the > power-domain test? Sorry for late reply. Do you mean add code to test/dm/power-domain.c? And the test is run test/run? Thanks, Peng. ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 35/41] dm: core: device: enable power domain in probe 2018-07-18 12:56 ` Peng Fan @ 2018-07-19 1:32 ` Simon Glass 0 siblings, 0 replies; 69+ messages in thread From: Simon Glass @ 2018-07-19 1:32 UTC (permalink / raw) To: u-boot Hi Peng, On 18 July 2018 at 06:56, Peng Fan <peng.fan@nxp.com> wrote: > Hi Simon > >> -----Original Message----- >> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass >> Sent: 2018年5月31日 3:19 >> To: Peng Fan <peng.fan@nxp.com> >> Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam >> <fabio.estevam@nxp.com>; U-Boot Mailing List <u-boot@lists.denx.de> >> Subject: Re: [PATCH 35/41] dm: core: device: enable power domain in probe >> >> On 28 May 2018 at 06:25, Peng Fan <peng.fan@nxp.com> wrote: >> > Enable power domain associated with the device when probe. >> > >> > Signed-off-by: Peng Fan <peng.fan@nxp.com> >> > Cc: Simon Glass <sjg@chromium.org> >> > --- >> > drivers/core/device.c | 7 +++++++ >> > 1 file changed, 7 insertions(+) >> > >> >> How is this feature tested at present? Can you add something to the >> power-domain test? > > Sorry for late reply. > Do you mean add code to test/dm/power-domain.c? > And the test is run test/run? Yes and yes - or 'make tests'. We really should have a 'make check' target. Regards, Simon ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 36/41] drivers: regulator: fixed: add off-on-delay-us 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (34 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 35/41] dm: core: device: enable power domain in probe Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-05-30 19:18 ` Simon Glass 2018-05-28 12:25 ` [U-Boot] [PATCH 37/41] mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue Peng Fan ` (6 subsequent siblings) 42 siblings, 1 reply; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot Add off-on-delay-us for fixed regulator. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> --- drivers/power/regulator/fixed.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/power/regulator/fixed.c b/drivers/power/regulator/fixed.c index 0be5b7bd51..b72ad98cb8 100644 --- a/drivers/power/regulator/fixed.c +++ b/drivers/power/regulator/fixed.c @@ -16,6 +16,7 @@ struct fixed_regulator_platdata { struct gpio_desc gpio; /* GPIO for regulator enable control */ unsigned int startup_delay_us; + unsigned int off_on_delay_us; }; static int fixed_regulator_ofdata_to_platdata(struct udevice *dev) @@ -50,6 +51,8 @@ static int fixed_regulator_ofdata_to_platdata(struct udevice *dev) /* Get optional ramp up delay */ dev_pdata->startup_delay_us = dev_read_u32_default(dev, "startup-delay-us", 0); + dev_pdata->off_on_delay_us = dev_read_u32_default(dev, + "off-on-delay-us", 0); return 0; } @@ -123,6 +126,9 @@ static int fixed_regulator_set_enable(struct udevice *dev, bool enable) udelay(dev_pdata->startup_delay_us); debug("%s: done\n", __func__); + if (!enable && dev_pdata->off_on_delay_us) + udelay(dev_pdata->off_on_delay_us); + return 0; } -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 36/41] drivers: regulator: fixed: add off-on-delay-us 2018-05-28 12:25 ` [U-Boot] [PATCH 36/41] drivers: regulator: fixed: add off-on-delay-us Peng Fan @ 2018-05-30 19:18 ` Simon Glass 0 siblings, 0 replies; 69+ messages in thread From: Simon Glass @ 2018-05-30 19:18 UTC (permalink / raw) To: u-boot On 28 May 2018 at 06:25, Peng Fan <peng.fan@nxp.com> wrote: > Add off-on-delay-us for fixed regulator. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Cc: Simon Glass <sjg@chromium.org> > --- > drivers/power/regulator/fixed.c | 6 ++++++ > 1 file changed, 6 insertions(+) Reviewed-by: Simon Glass <sjg@chromium.org> Can you also please add the DT binding file for this? ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 37/41] mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (35 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 36/41] drivers: regulator: fixed: add off-on-delay-us Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-05-28 22:32 ` Benoît Thébaudeau 2018-05-28 12:25 ` [U-Boot] [PATCH 38/41] log: include command header file Peng Fan ` (5 subsequent siblings) 42 siblings, 1 reply; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot From: Ye Li <ye.li@nxp.com> When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode, the actual clock rate is just half of the expected clock. This patch set the DDR_EN bit first for DDR mode, hardware divide the usdhc clock automatically, then follow the original sdr clock setting method. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> --- drivers/mmc/fsl_esdhc.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 1b062ff06d..bf4ae74847 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -583,18 +583,32 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) #else int pre_div = 2; #endif - int ddr_pre_div = mmc->ddr_mode ? 2 : 1; int sdhc_clk = priv->sdhc_clk; uint clk; + /* + * For ddr mode, usdhc need to enable DDR mode first, after select + * this DDR mode, usdhc will automatically divide the usdhc clock + */ + if (mmc->ddr_mode) { + writel(readl(®s->mixctrl) | MIX_CTRL_DDREN, ®s->mixctrl); + sdhc_clk >>= 1; + } + if (clock < mmc->cfg->f_min) clock = mmc->cfg->f_min; - while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) - pre_div *= 2; + if ((sdhc_clk / 16) > clock) { + for (; pre_div < 256; pre_div *= 2) + if ((sdhc_clk / pre_div) <= (clock * 16)) + break; + } else { + pre_div = 1; + } - while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) - div++; + for (div = 1; div <= 16; div++) + if ((sdhc_clk / (div * pre_div)) <= clock) + break; pre_div >>= 1; div -= 1; -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 37/41] mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue 2018-05-28 12:25 ` [U-Boot] [PATCH 37/41] mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue Peng Fan @ 2018-05-28 22:32 ` Benoît Thébaudeau 2018-05-29 1:45 ` Peng Fan 0 siblings, 1 reply; 69+ messages in thread From: Benoît Thébaudeau @ 2018-05-28 22:32 UTC (permalink / raw) To: u-boot Dear Peng Fan, On Mon, May 28, 2018 at 2:25 PM, Peng Fan <peng.fan@nxp.com> wrote: > From: Ye Li <ye.li@nxp.com> > > When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode, > the actual clock rate is just half of the expected clock. > > This patch set the DDR_EN bit first for DDR mode, hardware divide > the usdhc clock automatically, then follow the original sdr clock > setting method. > > Signed-off-by: Haibo Chen <haibo.chen@nxp.com> > Signed-off-by: Ye Li <ye.li@nxp.com> > --- > drivers/mmc/fsl_esdhc.c | 24 +++++++++++++++++++----- > 1 file changed, 19 insertions(+), 5 deletions(-) > > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c > index 1b062ff06d..bf4ae74847 100644 > --- a/drivers/mmc/fsl_esdhc.c > +++ b/drivers/mmc/fsl_esdhc.c > @@ -583,18 +583,32 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) > #else > int pre_div = 2; > #endif > - int ddr_pre_div = mmc->ddr_mode ? 2 : 1; > int sdhc_clk = priv->sdhc_clk; > uint clk; > > + /* > + * For ddr mode, usdhc need to enable DDR mode first, after select > + * this DDR mode, usdhc will automatically divide the usdhc clock > + */ > + if (mmc->ddr_mode) { > + writel(readl(®s->mixctrl) | MIX_CTRL_DDREN, ®s->mixctrl); > + sdhc_clk >>= 1; > + } > + > if (clock < mmc->cfg->f_min) > clock = mmc->cfg->f_min; > > - while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) > - pre_div *= 2; > + if ((sdhc_clk / 16) > clock) { > + for (; pre_div < 256; pre_div *= 2) > + if ((sdhc_clk / pre_div) <= (clock * 16)) > + break; > + } else { > + pre_div = 1; This value is not always available for this divider. See the conditions in the initialization of this variable giving its minimum value. > + } > > - while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) > - div++; > + for (div = 1; div <= 16; div++) > + if ((sdhc_clk / (div * pre_div)) <= clock) > + break; > > pre_div >>= 1; > div -= 1; Best regards, Benoît ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 37/41] mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue 2018-05-28 22:32 ` Benoît Thébaudeau @ 2018-05-29 1:45 ` Peng Fan 2018-05-29 20:47 ` Benoît Thébaudeau 0 siblings, 1 reply; 69+ messages in thread From: Peng Fan @ 2018-05-29 1:45 UTC (permalink / raw) To: u-boot > -----Original Message----- > From: Benoît Thébaudeau [mailto:benoit.thebaudeau.dev at gmail.com] > Sent: 2018年5月29日 6:32 > To: Peng Fan <peng.fan@nxp.com> > Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>; U-Boot > <u-boot@lists.denx.de>; Bough Chen <haibo.chen@nxp.com> > Subject: Re: [U-Boot] [PATCH 37/41] mmc: fsl_esdhc: fix sd/mmc ddr mode clock > setting issue > > Dear Peng Fan, > > On Mon, May 28, 2018 at 2:25 PM, Peng Fan <peng.fan@nxp.com> wrote: > > From: Ye Li <ye.li@nxp.com> > > > > When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode, > the > > actual clock rate is just half of the expected clock. > > > > This patch set the DDR_EN bit first for DDR mode, hardware divide the > > usdhc clock automatically, then follow the original sdr clock setting > > method. > > > > Signed-off-by: Haibo Chen <haibo.chen@nxp.com> > > Signed-off-by: Ye Li <ye.li@nxp.com> > > --- > > drivers/mmc/fsl_esdhc.c | 24 +++++++++++++++++++----- > > 1 file changed, 19 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index > > 1b062ff06d..bf4ae74847 100644 > > --- a/drivers/mmc/fsl_esdhc.c > > +++ b/drivers/mmc/fsl_esdhc.c > > @@ -583,18 +583,32 @@ static void set_sysctl(struct fsl_esdhc_priv > > *priv, struct mmc *mmc, uint clock) #else > > int pre_div = 2; > > #endif > > - int ddr_pre_div = mmc->ddr_mode ? 2 : 1; > > int sdhc_clk = priv->sdhc_clk; > > uint clk; > > > > + /* > > + * For ddr mode, usdhc need to enable DDR mode first, after select > > + * this DDR mode, usdhc will automatically divide the usdhc clock > > + */ > > + if (mmc->ddr_mode) { > > + writel(readl(®s->mixctrl) | MIX_CTRL_DDREN, > ®s->mixctrl); > > + sdhc_clk >>= 1; > > + } > > + > > if (clock < mmc->cfg->f_min) > > clock = mmc->cfg->f_min; > > > > - while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < > 256) > > - pre_div *= 2; > > + if ((sdhc_clk / 16) > clock) { > > + for (; pre_div < 256; pre_div *= 2) > > + if ((sdhc_clk / pre_div) <= (clock * 16)) > > + break; > > + } else { > > + pre_div = 1; > > This value is not always available for this divider. See the conditions in the > initialization of this variable giving its minimum value. The else {pre_div = 1;} could be removed then. Thanks, Peng. > > > + } > > > > - while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) > > - div++; > > + for (div = 1; div <= 16; div++) > > + if ((sdhc_clk / (div * pre_div)) <= clock) > > + break; > > > > pre_div >>= 1; > > div -= 1; > > Best regards, > Benoît ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 37/41] mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue 2018-05-29 1:45 ` Peng Fan @ 2018-05-29 20:47 ` Benoît Thébaudeau 0 siblings, 0 replies; 69+ messages in thread From: Benoît Thébaudeau @ 2018-05-29 20:47 UTC (permalink / raw) To: u-boot Dear Peng Fan, Some other remarks. On Tue, May 29, 2018 at 3:45 AM, Peng Fan <peng.fan@nxp.com> wrote: > > >> -----Original Message----- >> From: Benoît Thébaudeau [mailto:benoit.thebaudeau.dev at gmail.com] >> Sent: 2018年5月29日 6:32 >> To: Peng Fan <peng.fan@nxp.com> >> Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>; U-Boot >> <u-boot@lists.denx.de>; Bough Chen <haibo.chen@nxp.com> >> Subject: Re: [U-Boot] [PATCH 37/41] mmc: fsl_esdhc: fix sd/mmc ddr mode clock >> setting issue >> >> Dear Peng Fan, >> >> On Mon, May 28, 2018 at 2:25 PM, Peng Fan <peng.fan@nxp.com> wrote: >> > From: Ye Li <ye.li@nxp.com> >> > >> > When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode, >> the >> > actual clock rate is just half of the expected clock. >> > >> > This patch set the DDR_EN bit first for DDR mode, hardware divide the >> > usdhc clock automatically, then follow the original sdr clock setting >> > method. >> > >> > Signed-off-by: Haibo Chen <haibo.chen@nxp.com> >> > Signed-off-by: Ye Li <ye.li@nxp.com> >> > --- >> > drivers/mmc/fsl_esdhc.c | 24 +++++++++++++++++++----- >> > 1 file changed, 19 insertions(+), 5 deletions(-) >> > >> > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index >> > 1b062ff06d..bf4ae74847 100644 >> > --- a/drivers/mmc/fsl_esdhc.c >> > +++ b/drivers/mmc/fsl_esdhc.c >> > @@ -583,18 +583,32 @@ static void set_sysctl(struct fsl_esdhc_priv >> > *priv, struct mmc *mmc, uint clock) #else >> > int pre_div = 2; >> > #endif >> > - int ddr_pre_div = mmc->ddr_mode ? 2 : 1; >> > int sdhc_clk = priv->sdhc_clk; >> > uint clk; >> > >> > + /* >> > + * For ddr mode, usdhc need to enable DDR mode first, after select >> > + * this DDR mode, usdhc will automatically divide the usdhc clock >> > + */ >> > + if (mmc->ddr_mode) { >> > + writel(readl(®s->mixctrl) | MIX_CTRL_DDREN, >> ®s->mixctrl); Isn't this redundant with what is done in esdhc_set_timing()? According to the reference manual, the prescalers might have to be set after DDREN (as done here), so perhaps DDREN does not have to be set too in esdhc_set_timing(). >> > + sdhc_clk >>= 1; >> > + } >> > + >> > if (clock < mmc->cfg->f_min) >> > clock = mmc->cfg->f_min; >> > >> > - while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < >> 256) >> > - pre_div *= 2; >> > + if ((sdhc_clk / 16) > clock) { >> > + for (; pre_div < 256; pre_div *= 2) >> > + if ((sdhc_clk / pre_div) <= (clock * 16)) >> > + break; >> > + } else { >> > + pre_div = 1; >> >> This value is not always available for this divider. See the conditions in the >> initialization of this variable giving its minimum value. > > The else {pre_div = 1;} could be removed then. And the if conditioning the for loop becomes useless. In the end, the new loop would be equivalent to the previous while loop. >> >> > + } >> > >> > - while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) >> > - div++; >> > + for (div = 1; div <= 16; div++) div is already initialized in its definition, so only one of these initializations can be kept. >> > + if ((sdhc_clk / (div * pre_div)) <= clock) >> > + break; The only difference with the previous while loop is the "<= 16", which is correct, but maybe the change could have been limited to that. >> > >> > pre_div >>= 1; >> > div -= 1; Best regards, Benoît ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 38/41] log: include command header file 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (36 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 37/41] mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-05-30 19:18 ` Simon Glass 2018-05-28 12:25 ` [U-Boot] [PATCH 39/41] i2c-mux: pca954x: support pca9646 i2c switch Peng Fan ` (4 subsequent siblings) 42 siblings, 1 reply; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot cmd_tbl_t is defined in command.h, so include it in log.h Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> --- include/log.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/log.h b/include/log.h index a3edd25546..51cfd6fc0b 100644 --- a/include/log.h +++ b/include/log.h @@ -9,6 +9,7 @@ #ifndef __LOG_H #define __LOG_H +#include <command.h> #include <dm/uclass-id.h> #include <linux/list.h> -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 38/41] log: include command header file 2018-05-28 12:25 ` [U-Boot] [PATCH 38/41] log: include command header file Peng Fan @ 2018-05-30 19:18 ` Simon Glass 0 siblings, 0 replies; 69+ messages in thread From: Simon Glass @ 2018-05-30 19:18 UTC (permalink / raw) To: u-boot On 28 May 2018 at 06:25, Peng Fan <peng.fan@nxp.com> wrote: > cmd_tbl_t is defined in command.h, so include it in log.h > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Cc: Simon Glass <sjg@chromium.org> > --- > include/log.h | 1 + > 1 file changed, 1 insertion(+) > Reviewed-by: Simon Glass <sjg@chromium.org> Better I think to get rid of the cmd_tbl_t typedef and forward-declare the struct in log.h ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 39/41] i2c-mux: pca954x: support pca9646 i2c switch 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (37 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 38/41] log: include command header file Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 40/41] dts: imx8qxp: Add DTS and binding header files Peng Fan ` (3 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot Add the PCA9646 support, which is 2-wire bus switch and buffered 4-channel. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- drivers/i2c/muxes/pca954x.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c index 4debc03957..ab8b4000af 100644 --- a/drivers/i2c/muxes/pca954x.c +++ b/drivers/i2c/muxes/pca954x.c @@ -17,7 +17,8 @@ DECLARE_GLOBAL_DATA_PTR; enum pca_type { PCA9544, PCA9547, - PCA9548 + PCA9548, + PCA9646 }; struct chip_desc { @@ -51,6 +52,11 @@ static const struct chip_desc chips[] = { .muxtype = pca954x_isswi, .width = 8, }, + [PCA9646] = { + .enable = 0x0, + .muxtype = pca954x_isswi, + .width = 4, + }, }; static int pca954x_deselect(struct udevice *mux, struct udevice *bus, @@ -86,6 +92,7 @@ static const struct udevice_id pca954x_ids[] = { { .compatible = "nxp,pca9544", .data = PCA9544 }, { .compatible = "nxp,pca9547", .data = PCA9547 }, { .compatible = "nxp,pca9548", .data = PCA9548 }, + { .compatible = "nxp,pca9646", .data = PCA9646 }, { } }; -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 40/41] dts: imx8qxp: Add DTS and binding header files 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (38 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 39/41] i2c-mux: pca954x: support pca9646 i2c switch Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 41/41] imx: 8qxp_mek: Add i.MX8QXP MEK board support Peng Fan ` (2 subsequent siblings) 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot Introduce dtsi file for i.MX8QXP. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/dts/Makefile | 2 + arch/arm/dts/fsl-imx8qxp-mek.dts | 416 ++++++++ arch/arm/dts/fsl-imx8qxp.dtsi | 1593 +++++++++++++++++++++++++++++ include/dt-bindings/clock/imx8qxp-clock.h | 533 ++++++++++ include/dt-bindings/soc/imx8_pd.h | 197 ++++ 5 files changed, 2741 insertions(+) create mode 100644 arch/arm/dts/fsl-imx8qxp-mek.dts create mode 100644 arch/arm/dts/fsl-imx8qxp.dtsi create mode 100644 include/dt-bindings/clock/imx8qxp-clock.h create mode 100644 include/dt-bindings/soc/imx8_pd.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a0349a8975..da9cdeef1e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -432,6 +432,8 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb +dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb + dtb-$(CONFIG_RCAR_GEN3) += \ r8a7795-h3ulcb.dtb \ r8a7795-salvator-x.dtb \ diff --git a/arch/arm/dts/fsl-imx8qxp-mek.dts b/arch/arm/dts/fsl-imx8qxp-mek.dts new file mode 100644 index 0000000000..55960d0a67 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-mek.dts @@ -0,0 +1,416 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/* First 128KB is for PSCI ATF. */ +/* Last 127M is for M4/RPMSG */ +/memreserve/ 0x80000000 0x08000000; + +#include "fsl-imx8qxp.dtsi" + +/ { + model = "Freescale i.MX8QXP MEK"; + compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; + + aliases { + i2c4 = &bb_i2c1; + i2c5 = &mfi_i2c1; + i2c6 = &i2cexp1_i2c1; + i2c7 = &i2cexp2_i2c1; + }; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + reg_usb_otg1_vbus: regulator at 0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + }; +}; + +&iomuxc { + pinctrl-names = "default"; + imx8qxp-mek { + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000048 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x06000048 + SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x06000048 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x06000048 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x06000048 + SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x06000048 + SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x06000048 + SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x06000048 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x06000048 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x06000048 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x06000048 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x06000048 + SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x06000048 + >; + }; + + pinctrl_lpi2c1: lpi1cgrp { + fsl,pins = < + SC_P_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000020 + SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x06000021 + SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x06000021 + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x06000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x06000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x06000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x06000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x06000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x06000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x06000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x06000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x06000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x06000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x06000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x06000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x06000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x06000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x06000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x06000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000020 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c + >; + }; + + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + >; + }; + + pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + >; + }; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy at 0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy at 1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba at 0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + pca9646_switch: mux at 71 { + compatible = "nxp,pca9646"; + reg = <0x71>; + u-boot,i2c-offset-len = <0>; + #address-cells = <1>; + #size-cells = <0>; + + bb_i2c1: i2c at 0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + mfi_i2c1: i2c at 1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + + i2cexp1_i2c1: i2c at 2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + i2cexp2_i2c1: i2c at 3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + pca9557_a: gpio at 1a { + compatible = "nxp,pca9557"; + reg = <0x1a>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio at 1d { + compatible = "nxp,pca9557"; + reg = <0x1d>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; +}; + +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; + clock-frequency = <100000>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-imx8qxp.dtsi b/arch/arm/dts/fsl-imx8qxp.dtsi new file mode 100644 index 0000000000..b2c7168127 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp.dtsi @@ -0,0 +1,1593 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/soc/imx_rsrc.h> +#include <dt-bindings/soc/imx8_pd.h> +#include <dt-bindings/clock/imx8qxp-clock.h> +#include <dt-bindings/pinctrl/pads-imx8qxp.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "fsl,imx8qxp"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &fec1; + ethernet1 = &fec2; + serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &gpio5; + gpio6 = &gpio6; + gpio7 = &gpio7; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c13 = &i2c0_mipi_lvds0; + i2c15 = &i2c0_mipi_lvds1; + spi0 = &flexspi0; + }; + + memory at 80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + /* DRAM space - 1, size : 1 GB DRAM */ + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x80000000 0 0x80000000>; + linux,cma-default; + }; + }; + + gic: interrupt-controller at 51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + mu: mu at 5d1b0000 { + compatible = "fsl,imx8-mu"; + reg = <0x0 0x5d1b0000 0x0 0x10000>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + fsl,scu_ap_mu_id = <0>; + #mbox-cells = <4>; + status = "okay"; + }; + + mu13: mu13 at 5d280000 { + compatible = "fsl,imx8-mu-hifi"; + reg = <0x0 0x5d280000 0x0 0x10000>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + fsl,hifi_ap_mu_id = <13>; + status = "okay"; + }; + + clk: clk { + compatible = "fsl,imx8qxp-clk"; + #clock-cells = <1>; + }; + + iomuxc: iomuxc { + compatible = "fsl,imx8qxp-iomuxc"; + }; + + rtc: rtc { + compatible = "fsl,imx-sc-rtc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ + clock-frequency = <8000000>; + }; + + imx8qx-pm { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + pd_lsio: PD_LSIO { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_lsio_pwm0: PD_LSIO_PWM_0 { + reg = <SC_R_PWM_0>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm1: PD_LSIO_PWM_1 { + reg = <SC_R_PWM_1>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm2: PD_LSIO_PWM_2 { + reg = <SC_R_PWM_2>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm3: PD_LSIO_PWM_3 { + reg = <SC_R_PWM_3>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm4: PD_LSIO_PWM_4 { + reg = <SC_R_PWM_4>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm5: PD_LSIO_PWM_5 { + reg = <SC_R_PWM_5>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm6: PD_LSIO_PWM_6 { + reg = <SC_R_PWM_6>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm7: PD_LSIO_PWM_7 { + reg = <SC_R_PWM_7>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_kpp: PD_LSIO_KPP { + reg = <SC_R_KPP>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio0: PD_LSIO_GPIO_0 { + reg = <SC_R_GPIO_0>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio1: PD_LSIO_GPIO_1 { + reg = <SC_R_GPIO_1>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio2: PD_LSIO_GPIO_2 { + reg = <SC_R_GPIO_2>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio3: PD_LSIO_GPIO_3 { + reg = <SC_R_GPIO_3>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio4: PD_LSIO_GPIO_4 { + reg = <SC_R_GPIO_4>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio5: PD_LSIO_GPIO_5{ + reg = <SC_R_GPIO_5>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio6:PD_LSIO_GPIO_6 { + reg = <SC_R_GPIO_6>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio7: PD_LSIO_GPIO_7 { + reg = <SC_R_GPIO_7>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt0: PD_LSIO_GPT_0 { + reg = <SC_R_GPT_0>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt1: PD_LSIO_GPT_1 { + reg = <SC_R_GPT_1>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt2: PD_LSIO_GPT_2 { + reg = <SC_R_GPT_2>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt3: PD_LSIO_GPT_3 { + reg = <SC_R_GPT_3>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt4: PD_LSIO_GPT_4 { + reg = <SC_R_GPT_4>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_flexspi0: PD_LSIO_FSPI_0 { + reg = <SC_R_FSPI_0>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_flexspi1: PD_LSIO_FSPI_1{ + reg = <SC_R_FSPI_1>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + }; + + pd_conn: PD_CONN { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_conn_usbotg0: PD_CONN_USB_0 { + reg = <SC_R_USB_0>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY { + reg = <SC_R_USB_0_PHY>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_usbotg1: PD_CONN_USB_1 { + reg = <SC_R_USB_1>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_usb2: PD_CONN_USB_2 { + reg = <SC_R_USB_2>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_usb2_phy: PD_CONN_USB_2_PHY { + reg = <SC_R_USB_2_PHY>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_sdch0: PD_CONN_SDHC_0 { + reg = <SC_R_SDHC_0>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_sdch1: PD_CONN_SDHC_1 { + reg = <SC_R_SDHC_1>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_sdch2: PD_CONN_SDHC_2 { + reg = <SC_R_SDHC_2>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_enet0: PD_CONN_ENET_0 { + reg = <SC_R_ENET_0>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_enet1: PD_CONN_ENET_1 { + reg = <SC_R_ENET_1>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_nand: PD_CONN_NAND { + reg = <SC_R_NAND>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_mlb0: PD_CONN_MLB_0 { + reg = <SC_R_MLB_0>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_edma_ch0: PD_CONN_DMA_4_CH0 { + reg = <SC_R_DMA_4_CH0>; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch1: PD_CONN_DMA_4_CH1 { + reg = <SC_R_DMA_4_CH1>; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch2: PD_CONN_DMA_4_CH2 { + reg = <SC_R_DMA_4_CH2>; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch3: PD_CONN_DMA_4_CH3 { + reg = <SC_R_DMA_4_CH3>; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch4: PD_CONN_DMA_4_CH4 { + reg = <SC_R_DMA_4_CH4>; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + }; + + pd_audio: PD_AUDIO { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_asrc0:PD_AUD_ASRC_0 { + reg = <SC_R_ASRC_0>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_asrc1: PD_AUD_ASRC_1 { + reg = <SC_R_ASRC_1>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_esai0: PD_AUD_ESAI_0 { + reg = <SC_R_ESAI_0>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_spdif0: PD_AUD_SPDIF_0 { + reg = <SC_R_SPDIF_0>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_sai0:PD_AUD_SAI_0 { + reg = <SC_R_SAI_0>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_sai1: PD_AUD_SAI_1 { + reg = <SC_R_SAI_1>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_sai2: PD_AUD_SAI_2 { + reg = <SC_R_SAI_2>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_sai3: PD_AUD_SAI_3 { + reg = <SC_R_SAI_3>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_sai4: PD_AUD_SAI_4 { + reg = <SC_R_SAI_4>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_sai5: PD_AUD_SAI_5 { + reg = <SC_R_SAI_5>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_gpt5: PD_AUD_GPT_5 { + reg = <SC_R_GPT_5>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_gpt6: PD_AUD_GPT_6 { + reg = <SC_R_GPT_6>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_gpt7: PD_AUD_GPT_7 { + reg = <SC_R_GPT_7>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_gpt8: PD_AUD_GPT_8 { + reg = <SC_R_GPT_8>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_gpt9: PD_AUD_GPT_9 { + reg = <SC_R_GPT_9>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_gpt10: PD_AUD_GPT_10 { + reg = <SC_R_GPT_10>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_amix: PD_AUD_AMIX { + reg = <SC_R_AMIX>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_mqs0: PD_AUD_MQS_0 { + reg = <SC_R_MQS_0>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_hifi: PD_AUD_HIFI { + reg = <SC_R_DSP>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_hifi_ram: PD_AUD_OCRAM { + reg = <SC_R_DSP_RAM>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_mclk_out0: PD_AUD_MCLK_OUT_0 { + reg = <SC_R_MCLK_OUT_0>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_mclk_out1: PD_AUD_MCLK_OUT_1 { + reg = <SC_R_MCLK_OUT_1>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_audio_pll0: PD_AUD_AUDIO_PLL_0 { + reg = <SC_R_AUDIO_PLL_0>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_audio_pll1: PD_AUD_AUDIO_PLL_1 { + reg = <SC_R_AUDIO_PLL_1>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_audio_clk0: PD_AUD_AUDIO_CLK_0 { + reg = <SC_R_AUDIO_CLK_0>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + pd_audio_clk1: PD_AUD_AUDIO_CLK_1 { + reg = <SC_R_AUDIO_CLK_1>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + }; + }; + + pd_dma: PD_DMA { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma_flexcan0: PD_DMA_CAN_0 { + reg = <SC_R_CAN_0>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_flexcan1: PD_DMA_CAN_1 { + reg = <SC_R_CAN_1>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_flexcan2: PD_DMA_CAN_2 { + reg = <SC_R_CAN_2>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_ftm0: PD_DMA_FTM_0 { + reg = <SC_R_FTM_0>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_ftm1: PD_DMA_FTM_1 { + reg = <SC_R_FTM_1>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_adc0: PD_DMA_ADC_0 { + reg = <SC_R_ADC_0>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c0: PD_DMA_I2C_0 { + reg = <SC_R_I2C_0>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c1: PD_DMA_I2C_1 { + reg = <SC_R_I2C_1>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c2:PD_DMA_I2C_2 { + reg = <SC_R_I2C_2>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c3: PD_DMA_I2C_3 { + reg = <SC_R_I2C_3>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpuart0: PD_DMA_UART0 { + reg = <SC_R_UART_0>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpuart1: PD_DMA_UART1 { + reg = <SC_R_UART_1>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpuart2: PD_DMA_UART2 { + reg = <SC_R_UART_2>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpuart3: PD_DMA_UART3 { + reg = <SC_R_UART_3>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi0: PD_DMA_SPI_0 { + reg = <SC_R_SPI_0>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi1: PD_DMA_SPI_1 { + reg = <SC_R_SPI_1>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi2: PD_DMA_SPI_2 { + reg = <SC_R_SPI_2>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi3: PD_DMA_SPI_3 { + reg = <SC_R_SPI_3>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_pwm0: PD_DMA_PWM_0 { + reg = <SC_R_LCD_0_PWM_0>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lcd0: PD_DMA_LCD_0 { + reg = <SC_R_LCD_0>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + }; + + pd_gpu: gpu-power-domain { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_gpu0: gpu0 { + name = "gpu0"; + reg = <SC_R_GPU_0_PID0>; + #power-domain-cells = <0>; + power-domains =<&pd_gpu>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + pd_vpu: vpu-power-domain { + compatible = "nxp,imx8-pd"; + reg = <SC_R_VPU>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_vpu_core: vpu_core { + name = "vpu_core"; + reg = <SC_R_VPUCORE>; + #power-domain-cells = <0>; + power-domains =<&pd_vpu>; + }; + }; + + pd_hsio: hsio-power-domain { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_serdes1: PD_HSIO_SERDES_1 { + reg = <SC_R_SERDES_1>; + #power-domain-cells = <0>; + power-domains =<&pd_hsio>; + #address-cells = <1>; + #size-cells = <0>; + + pd_pcie: PD_HSIO_PCIE_B { + reg = <SC_R_PCIE_B>; + #power-domain-cells = <0>; + power-domains =<&pd_serdes1>; + }; + }; + }; + + pd_cm40: PD_CM40 { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_cm40_i2c: PD_CM40_I2C { + reg = <SC_R_M4_0_I2C>; + #power-domain-cells = <0>; + power-domains =<&pd_cm40>; + }; + + pd_cm40_intmux: PD_CM40_INTMUX { + reg = <SC_R_M4_0_INTMUX>; + #power-domain-cells = <0>; + power-domains =<&pd_cm40>; + }; + }; + + + pd_dc0: PD_DC_0 { + compatible = "nxp,imx8-pd"; + reg = <SC_R_DC_0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc0_pll0: PD_DC_0_PLL_0{ + reg = <SC_R_DC_0_PLL_0>; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc0_pll1: PD_DC_0_PLL_1{ + reg = <SC_R_DC_0_PLL_1>; + #power-domain-cells = <0>; + power-domains =<&pd_dc0_pll0>; + }; + }; + pd_mipi_dsi0: PD_MIPI_0_DSI { + reg = <SC_R_MIPI_0>; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_mipi_dsi_0_lvds: PD_LVDS0 { + reg = <SC_R_LVDS_0>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi0>; + }; + + pd_mipi_dsi_0_i2c0: PD_MIPI_0_DSI_I2C0 { + reg = <SC_R_MIPI_0_I2C_0>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi0>; + }; + pd_mipi_dsi_0_i2c1: PD_MIPI_0_DSI_I2C1 { + reg = <SC_R_MIPI_0_I2C_1>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi0>; + }; + pd_mipi_0_pwm0: PD_MIPI_0_DSI_PWM0 { + reg = <SC_R_MIPI_0_PWM_0>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi0>; + }; + }; + + pd_mipi_dsi1: PD_MIPI_1_DSI { + reg = <SC_R_MIPI_1>; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_mipi_dsi_1_lvds: PD_LVDS1 { + reg = <SC_R_LVDS_1>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi1>; + }; + + pd_mipi_dsi_1_i2c0: PD_MIPI_1_DSI_I2C0 { + reg = <SC_R_MIPI_1_I2C_0>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi1>; + }; + pd_mipi_dsi_1_i2c1: PD_MIPI_1_DSI_I2C1 { + reg = <SC_R_MIPI_1_I2C_1>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi1>; + }; + pd_mipi_1_pwm0: PD_MIPI_1_DSI_PWM0 { + reg = <SC_R_MIPI_1_PWM_0>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi1>; + }; + }; + }; + + pd_isi_ch0: PD_IMAGING { + compatible = "nxp,imx8-pd"; + reg = <SC_R_ISI_CH0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_mipi_csi: PD_MIPI_CSI0 { + reg = <SC_R_CSI_0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + power-domains =<&pd_isi_ch0>; + + pd_mipi_csi_i2c0: PD_MIPI_CSI0_I2C { + name = "mipi_csi0_i2c"; + reg = <SC_R_CSI_0_I2C_0>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_csi>; + }; + + pd_mipi_csi_pwm0: PD_MIPI_CSI0_PWM { + name = "mipi_csi0_pwm"; + reg = <SC_R_CSI_0_PWM_0>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_csi>; + }; + }; + + pd_isi_ch1: PD_IMAGING_PDMA1 { + reg = <SC_R_ISI_CH1>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch2: PD_IMAGING_PDMA2 { + reg = <SC_R_ISI_CH2>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch3: PD_IMAGING_PDMA3 { + reg = <SC_R_ISI_CH3>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch4: PD_IMAGING_PDMA4 { + reg = <SC_R_ISI_CH4>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch5: PD_IMAGING_PDMA5 { + reg = <SC_R_ISI_CH5>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch6: PD_IMAGING_PDMA6 { + reg = <SC_R_ISI_CH6>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch7: PD_IMAGING_PDMA7 { + reg = <SC_R_ISI_CH7>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + }; + }; + + tsens: thermal-sensor { + compatible = "nxp,imx8qxp-sc-tsens"; + u-boot,dm-pre-reloc; + /* number of the temp sensor on the chip */ + tsens-num = <1>; + #thermal-sensor-cells = <1>; + }; + + thermal-zones { + /* cpu thermal */ + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + /*the slope and offset of the temp sensor */ + thermal-sensors = <&tsens 0>; + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + gpio0: gpio at 5d080000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d080000 0x0 0x10000>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_lsio_gpio0>; + }; + + gpio1: gpio at 5d090000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d090000 0x0 0x10000>; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_lsio_gpio1>; + }; + + gpio2: gpio at 5d0a0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0a0000 0x0 0x10000>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_lsio_gpio2>; + }; + + gpio3: gpio at 5d0b0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0b0000 0x0 0x10000>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_lsio_gpio3>; + }; + + gpio4: gpio at 5d0c0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0c0000 0x0 0x10000>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_lsio_gpio4>; + }; + + gpio5: gpio at 5d0d0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0d0000 0x0 0x10000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_lsio_gpio5>; + }; + + gpio6: gpio at 5d0e0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0e0000 0x0 0x10000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_lsio_gpio6>; + }; + + gpio7: gpio at 5d0f0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0f0000 0x0 0x10000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_lsio_gpio7>; + }; + + irqsteer_csi: irqsteer at 58220000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x58220000 0x0 0x1000>; + interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QXP_CSI0_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_mipi_csi>; + }; + + i2c0_csi0: i2c at 58226000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x58226000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_csi>; + clocks = <&clk IMX8QXP_CSI0_I2C0_CLK>, + <&clk IMX8QXP_CSI0_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_CSI0_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_mipi_csi_i2c0>; + status = "disabled"; + }; + + irqsteer_mipi_lvds0: irqsteer at 56220000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x56220000 0x0 0x1000>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QXP_MIPI0_LIS_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_mipi_dsi0>; + }; + + i2c0_mipi_lvds0: i2c at 56226000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c"; + reg = <0x0 0x56226000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_mipi_lvds0>; + clocks = <&clk IMX8QXP_MIPI0_I2C0_CLK>, + <&clk IMX8QXP_MIPI0_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_MIPI0_I2C0_DIV>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_mipi_dsi_0_i2c0>; + status = "disabled"; + }; + + irqsteer_mipi_lvds1: irqsteer at 56240000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x56240000 0x0 0x1000>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QXP_MIPI1_LIS_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_mipi_dsi1>; + }; + + i2c0_mipi_lvds1: i2c at 56246000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c"; + reg = <0x0 0x56246000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_mipi_lvds1>; + clocks = <&clk IMX8QXP_MIPI1_I2C0_CLK>, + <&clk IMX8QXP_MIPI1_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_MIPI1_I2C0_DIV>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_mipi_dsi_1_i2c0>; + status = "disabled"; + }; + + i2c0: i2c at 5a800000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a800000 0x0 0x4000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_I2C0_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c0>; + status = "disabled"; + }; + + i2c1: i2c at 5a810000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a810000 0x0 0x4000>; + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_I2C1_CLK>, + <&clk IMX8QXP_I2C1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_I2C1_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c1>; + status = "disabled"; + }; + + i2c2: i2c at 5a820000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a820000 0x0 0x4000>; + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_I2C2_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_I2C2_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c2>; + status = "disabled"; + }; + + i2c3: i2c at 5a830000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a830000 0x0 0x4000>; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_I2C3_CLK>, + <&clk IMX8QXP_I2C3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_I2C3_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c3>; + status = "disabled"; + }; + + lpuart0: serial at 5a060000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a060000 0x0 0x1000>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_UART0_CLK>, + <&clk IMX8QXP_UART0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART0_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart0>; + status = "disabled"; + }; + + lpuart1: serial at 5a070000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a070000 0x0 0x1000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_UART1_CLK>, + <&clk IMX8QXP_UART1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART1_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart1>; + dma-names = "tx","rx"; + dmas = <&edma0 11 0 0>, + <&edma0 10 0 1>; + status = "disabled"; + }; + + lpuart2: serial at 5a080000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a080000 0x0 0x1000>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_UART2_CLK>, + <&clk IMX8QXP_UART2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART2_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart2>; + dma-names = "tx","rx"; + dmas = <&edma0 13 0 0>, + <&edma0 12 0 1>; + status = "disabled"; + }; + + lpuart3: serial at 5a090000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a090000 0x0 0x1000>; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_UART3_CLK>, + <&clk IMX8QXP_UART3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART3_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart3>; + dma-names = "tx","rx"; + dmas = <&edma0 15 0 0>, + <&edma0 14 0 1>; + status = "disabled"; + }; + + edma0: dma-controller at 5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a280000 0x0 0x10000>, /* channel8 UART0 rx */ + <0x0 0x5a290000 0x0 0x10000>, /* channel9 UART0 tx */ + <0x0 0x5a2a0000 0x0 0x10000>, /* channel10 UART1 rx */ + <0x0 0x5a2b0000 0x0 0x10000>, /* channel11 UART1 tx */ + <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART2 rx */ + <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART2 tx */ + <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART3 rx */ + <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART3 tx */ + #dma-cells = <3>; + dma-channels = <8>; + interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma-chan8-tx", "edma-chan9-tx", + "edma-chan10-tx", "edma-chan11-tx", + "edma-chan12-tx", "edma-chan13-tx", + "edma-chan14-tx", "edma-chan15-tx"; + status = "okay"; + }; + + edma2: dma-controller at 591F0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */ + <0x0 0x59210000 0x0 0x10000>, + <0x0 0x59220000 0x0 0x10000>, + <0x0 0x59230000 0x0 0x10000>, + <0x0 0x59240000 0x0 0x10000>, + <0x0 0x59250000 0x0 0x10000>, + <0x0 0x59260000 0x0 0x10000>, /* esai0 rx */ + <0x0 0x59270000 0x0 0x10000>, /* esai0 tx */ + <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */ + <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */ + <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */ + <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */ + <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */ + <0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */ + <0x0 0x59350000 0x0 0x10000>, + <0x0 0x59370000 0x0 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <16>; + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */ + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */ + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma-chan0-tx", "edma-chan1-tx", /* asrc0 */ + "edma-chan2-tx", "edma-chan3-tx", + "edma-chan4-tx", "edma-chan5-tx", + "edma-chan6-tx", "edma-chan7-tx", /* esai0 */ + "edma-chan8-tx", "edma-chan9-tx", /* spdif0 */ + "edma-chan12-tx", "edma-chan13-tx", /* sai0 */ + "edma-chan14-tx", "edma-chan15-tx", /* sai1 */ + "edma-chan21-tx", /* gpt5 */ + "edma-chan23-tx"; /* gpt7 */ + status = "okay"; + }; + + edma3: dma-controller at 599F0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x59A00000 0x0 0x10000>, /* asrc1 */ + <0x0 0x59A10000 0x0 0x10000>, + <0x0 0x59A20000 0x0 0x10000>, + <0x0 0x59A30000 0x0 0x10000>, + <0x0 0x59A40000 0x0 0x10000>, + <0x0 0x59A50000 0x0 0x10000>, + <0x0 0x59A80000 0x0 0x10000>, /* sai4 rx */ + <0x0 0x59A90000 0x0 0x10000>, /* sai4 tx */ + <0x0 0x59AA0000 0x0 0x10000>; /* sai5 tx */ + #dma-cells = <3>; + shared-interrupt; + dma-channels = <9>; + interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc 1 */ + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */ + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */ + interrupt-names = "edma-chan0-tx", "edma-chan1-tx", /* asrc1 */ + "edma-chan2-tx", "edma-chan3-tx", + "edma-chan4-tx", "edma-chan5-tx", + "edma-chan8-tx", "edma-chan9-tx", /* sai4 */ + "edma-chan10-tx"; /* sai5 */ + status = "okay"; + }; + + acm: acm at 59e00000 { + compatible = "nxp,imx8qm-acm"; + reg = <0x0 0x59e00000 0x0 0x1D0000>; + status = "disabled"; + }; + + sai0: sai at 59040000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59040000 0x0 0x10000>; + interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_AUD_SAI_0_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_0_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma2 12 0 1>, <&edma2 13 0 0>; + status = "disabled"; + power-domains = <&pd_sai0>; + }; + + sai1: sai at 59050000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59050000 0x0 0x10000>; + interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_AUD_SAI_1_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_1_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma2 14 0 1>, <&edma2 15 0 0>; + status = "disabled"; + power-domains = <&pd_sai1>; + }; + + sai4: sai at 59820000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59820000 0x0 0x10000>; + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_AUD_SAI_4_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_4_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + dmas = <&edma3 8 0 1>, <&edma3 9 0 0>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + status = "disabled"; + power-domains = <&pd_sai4>; + }; + + sai5: sai at 59830000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59830000 0x0 0x10000>; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_AUD_SAI_5_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_5_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "tx"; + dmas = <&edma3 10 0 0>; + status = "disabled"; + power-domains = <&pd_sai5>; + }; + + amix: amix at 59840000 { + compatible = "fsl,imx8qm-amix"; + reg = <0x0 0x59840000 0x0 0x10000>; + clocks = <&clk IMX8QXP_AUD_AMIX_IPG>; + clock-names = "ipg"; + power-domains = <&pd_amix>; + status = "disabled"; + }; + + asrc0: asrc at 59000000 { + compatible = "fsl,imx8qm-asrc0"; + reg = <0x0 0x59000000 0x0 0x10000>; + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_AUD_ASRC_0_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma2 0 0 0>, <&edma2 1 0 0>, <&edma2 2 0 0>, + <&edma2 3 0 1>, <&edma2 4 0 1>, <&edma2 5 0 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + power-domains = <&pd_asrc0>; + status = "disabled"; + }; + + asrc1: asrc at 59800000 { + compatible = "fsl,imx8qm-asrc1"; + reg = <0x0 0x59800000 0x0 0x10000>; + interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_AUD_ASRC_1_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma3 0 0 0>, <&edma3 1 0 0>, <&edma3 2 0 0>, + <&edma3 3 0 1>, <&edma3 4 0 1>, <&edma3 5 0 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + power-domains = <&pd_asrc1>; + status = "disabled"; + }; + + mqs: mqs at 59850000 { + compatible = "fsl,imx8qm-mqs"; + reg = <0x0 0x59850000 0x0 0x10000>; + clocks = <&clk IMX8QXP_AUD_MQS_IPG>, + <&clk IMX8QXP_AUD_MQS_HMCLK>; + clock-names = "core", "mclk"; + power-domains = <&pd_mqs0>; + status = "disabled"; + }; + + usdhc1: usdhc at 5b010000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0x5b010000 0x0 0x10000>; + clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>, + <&clk IMX8QXP_SDHC0_CLK>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QXP_SDHC0_DIV>; + assigned-clock-rates = <400000000>; + power-domains = <&pd_conn_sdch0>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc2: usdhc at 5b020000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0x5b020000 0x0 0x10000>; + clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>, + <&clk IMX8QXP_SDHC1_CLK>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QXP_SDHC1_DIV>; + assigned-clock-rates = <200000000>; + power-domains = <&pd_conn_sdch1>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc3: usdhc at 5b030000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0x5b030000 0x0 0x10000>; + clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>, + <&clk IMX8QXP_SDHC2_CLK>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QXP_SDHC2_DIV>; + assigned-clock-rates = <200000000>; + power-domains = <&pd_conn_sdch2>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step = <2>; + status = "disabled"; + }; + + fec1: ethernet at 5b040000 { + compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec"; + reg = <0x0 0x5b040000 0x0 0x10000>; + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>, <&clk IMX8QXP_ENET0_RGMII_TX_CLK>, + <&clk IMX8QXP_ENET0_PTP_CLK>, <&clk IMX8QXP_ENET0_TX_CLK>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; + assigned-clocks = <&clk IMX8QXP_ENET0_ROOT_DIV>, + <&clk IMX8QXP_ENET0_REF_DIV>, + <&clk IMX8QXP_ENET0_PTP_CLK>; + assigned-clock-rates = <250000000>, <125000000>, <125000000>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + power-domains = <&pd_conn_enet0>; + status = "disabled"; + }; + + fec2: ethernet at 5b050000 { + compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec"; + reg = <0x0 0x5b050000 0x0 0x10000>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>, <&clk IMX8QXP_ENET1_RGMII_TX_CLK>, + <&clk IMX8QXP_ENET1_PTP_CLK>, <&clk IMX8QXP_ENET1_TX_CLK>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; + assigned-clocks = <&clk IMX8QXP_ENET1_ROOT_DIV>, + <&clk IMX8QXP_ENET1_REF_DIV>, + <&clk IMX8QXP_ENET1_PTP_CLK>; + assigned-clock-rates = <250000000>, <125000000>, <125000000>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + power-domains = <&pd_conn_enet1>; + status = "disabled"; + }; + + mlb: mlb at 5B060000 { + compatible = "fsl,imx6q-mlb150"; + reg = <0x0 0x5B060000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>, + <0 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_MLB_CLK>, + <&clk IMX8QXP_MLB_HCLK>, + <&clk IMX8QXP_MLB_IPG_CLK>; + clock-names = "mlb", "hclk", "ipg"; + assigned-clocks = <&clk IMX8QXP_MLB_CLK>, + <&clk IMX8QXP_MLB_HCLK>, + <&clk IMX8QXP_MLB_IPG_CLK>; + assigned-clock-rates = <333333333>, <333333333>, <83333333>; + power-domains = <&pd_conn_mlb0>; + status = "disabled"; + }; + + hifi4: hifi4 at 586e8000 { + compatible = "fsl,imx8qxp-hifi4"; + reg = <0x0 0x596e8000 0x0 0x88000>; + clocks = <&clk IMX8QXP_AUD_HIFI_IPG>, + <&clk IMX8QXP_AUD_OCRAM_IPG>, + <&clk IMX8QXP_AUD_HIFI_CORE_CLK>; + clock-names = "ipg", "ocram", "core"; + fsl,hifi4-firmware = "imx/hifi/hifi4.bin"; + power-domains = <&pd_hifi>; + }; + + esai0: esai at 59010000 { + compatible = "fsl,imx6ull-esai"; + reg = <0x0 0x59010000 0x0 0x10000>; + interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_AUD_ESAI_0_IPG>, + <&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>, + <&clk IMX8QXP_AUD_ESAI_0_IPG>; + clock-names = "core", "extal", "fsys"; + dmas = <&edma2 6 0 1>, <&edma2 7 0 0>; + dma-names = "rx", "tx"; + power-domains = <&pd_esai0>; + status = "disabled"; + }; + + spdif0: spdif at 59020000 { + compatible = "fsl,imx8qm-spdif"; + reg = <0x0 0x59020000 0x0 0x10000>; + interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */ + <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */ + clocks = <&clk IMX8QXP_AUD_SPDIF_0_GCLKW>, /* core */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx0 */ + <&clk IMX8QXP_AUD_SPDIF_0_TX_CLK>, /* rxtx1 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8QXP_IPG_AUD_CLK_ROOT>, /* rxtx5 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8QXP_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&edma2 8 0 5>, <&edma2 9 0 4>; + dma-names = "rx", "tx"; + power-domains = <&pd_spdif0>; + status = "disabled"; + }; + + flexspi0: flexspi at 05d120000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-flexspi"; + reg = <0x0 0x5d120000 0x0 0x10000>, <0x0 0x08000000 0x0 0x19ffffff>; + reg-names = "FlexSPI", "FlexSPI-memory"; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_LSIO_FSPI0_CLK>, + <&clk IMX8QXP_LSIO_FSPI0_CLK>; + assigned-clock-rates = <29000000>,<29000000>; + clock-names = "qspi_en", "qspi"; + power-domains = <&pd_lsio_flexspi0>; + status = "disabled"; + }; +}; diff --git a/include/dt-bindings/clock/imx8qxp-clock.h b/include/dt-bindings/clock/imx8qxp-clock.h new file mode 100644 index 0000000000..a31c120dc0 --- /dev/null +++ b/include/dt-bindings/clock/imx8qxp-clock.h @@ -0,0 +1,533 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8QXP_H +#define __DT_BINDINGS_CLOCK_IMX8QXP_H + +#define IMX8QXP_CLK_DUMMY 0 + +#define IMX8QXP_UART0_IPG_CLK 1 +#define IMX8QXP_UART0_DIV 2 +#define IMX8QXP_UART0_CLK 3 + +#define IMX8QXP_IPG_DMA_CLK_ROOT 4 + +/* GPU Clocks. */ +#define IMX8QXP_GPU0_CORE_DIV 5 +#define IMX8QXP_GPU0_CORE_CLK 6 +#define IMX8QXP_GPU0_SHADER_DIV 7 +#define IMX8QXP_GPU0_SHADER_CLK 8 + +#define IMX8QXP_24MHZ 9 +#define IMX8QXP_GPT_3M 10 +#define IMX8QXP_32KHZ 11 + +/* LSIO SS */ +#define IMX8QXP_LSIO_MEM_CLK 12 +#define IMX8QXP_LSIO_BUS_CLK 13 +#define IMX8QXP_LSIO_PWM0_DIV 14 +#define IMX8QXP_LSIO_PWM0_IPG_S_CLK 15 +#define IMX8QXP_LSIO_PWM0_IPG_SLV_CLK 16 +#define IMX8QXP_LSIO_PWM0_IPG_MSTR_CLK 17 +#define IMX8QXP_LSIO_PWM0_HF_CLK 18 +#define IMX8QXP_LSIO_PWM0_CLK 19 +#define IMX8QXP_LSIO_PWM1_DIV 20 +#define IMX8QXP_LSIO_PWM1_IPG_S_CLK 21 +#define IMX8QXP_LSIO_PWM1_IPG_SLV_CLK 22 +#define IMX8QXP_LSIO_PWM1_IPG_MSTR_CLK 23 +#define IMX8QXP_LSIO_PWM1_HF_CLK 24 +#define IMX8QXP_LSIO_PWM1_CLK 25 +#define IMX8QXP_LSIO_PWM2_DIV 26 +#define IMX8QXP_LSIO_PWM2_IPG_S_CLK 27 +#define IMX8QXP_LSIO_PWM2_IPG_SLV_CLK 28 +#define IMX8QXP_LSIO_PWM2_IPG_MSTR_CLK 29 +#define IMX8QXP_LSIO_PWM2_HF_CLK 30 +#define IMX8QXP_LSIO_PWM2_CLK 31 +#define IMX8QXP_LSIO_PWM3_DIV 32 +#define IMX8QXP_LSIO_PWM3_IPG_S_CLK 33 +#define IMX8QXP_LSIO_PWM3_IPG_SLV_CLK 34 +#define IMX8QXP_LSIO_PWM3_IPG_MSTR_CLK 35 +#define IMX8QXP_LSIO_PWM3_HF_CLK 36 +#define IMX8QXP_LSIO_PWM3_CLK 37 +#define IMX8QXP_LSIO_PWM4_DIV 38 +#define IMX8QXP_LSIO_PWM4_IPG_S_CLK 39 +#define IMX8QXP_LSIO_PWM4_IPG_SLV_CLK 40 +#define IMX8QXP_LSIO_PWM4_IPG_MSTR_CLK 42 +#define IMX8QXP_LSIO_PWM4_HF_CLK 43 +#define IMX8QXP_LSIO_PWM4_CLK 44 +#define IMX8QXP_LSIO_PWM5_DIV 45 +#define IMX8QXP_LSIO_PWM5_IPG_S_CLK 46 +#define IMX8QXP_LSIO_PWM5_IPG_SLV_CLK 47 +#define IMX8QXP_LSIO_PWM5_IPG_MSTR_CLK 48 +#define IMX8QXP_LSIO_PWM5_HF_CLK 49 +#define IMX8QXP_LSIO_PWM5_CLK 50 +#define IMX8QXP_LSIO_PWM6_DIV 51 +#define IMX8QXP_LSIO_PWM6_IPG_S_CLK 52 +#define IMX8QXP_LSIO_PWM6_IPG_SLV_CLK 53 +#define IMX8QXP_LSIO_PWM6_IPG_MSTR_CLK 54 +#define IMX8QXP_LSIO_PWM6_HF_CLK 55 +#define IMX8QXP_LSIO_PWM6_CLK 56 +#define IMX8QXP_LSIO_PWM7_DIV 57 +#define IMX8QXP_LSIO_PWM7_IPG_S_CLK 58 +#define IMX8QXP_LSIO_PWM7_IPG_SLV_CLK 59 +#define IMX8QXP_LSIO_PWM7_IPG_MSTR_CLK 60 +#define IMX8QXP_LSIO_PWM7_HF_CLK 61 +#define IMX8QXP_LSIO_PWM7_CLK 62 +#define IMX8QXP_LSIO_GPT0_DIV 63 +#define IMX8QXP_LSIO_GPT0_IPG_S_CLK 64 +#define IMX8QXP_LSIO_GPT0_IPG_SLV_CLK 65 +#define IMX8QXP_LSIO_GPT0_IPG_MSTR_CLK 66 +#define IMX8QXP_LSIO_GPT0_HF_CLK 67 +#define IMX8QXP_LSIO_GPT0_CLK 68 +#define IMX8QXP_LSIO_GPT1_DIV 69 +#define IMX8QXP_LSIO_GPT1_IPG_S_CLK 70 +#define IMX8QXP_LSIO_GPT1_IPG_SLV_CLK 71 +#define IMX8QXP_LSIO_GPT1_IPG_MSTR_CLK 72 +#define IMX8QXP_LSIO_GPT1_HF_CLK 73 +#define IMX8QXP_LSIO_GPT1_CLK 74 +#define IMX8QXP_LSIO_GPT2_DIV 75 +#define IMX8QXP_LSIO_GPT2_IPG_S_CLK 76 +#define IMX8QXP_LSIO_GPT2_IPG_SLV_CLK 77 +#define IMX8QXP_LSIO_GPT2_IPG_MSTR_CLK 78 +#define IMX8QXP_LSIO_GPT2_HF_CLK 79 +#define IMX8QXP_LSIO_GPT2_CLK 80 +#define IMX8QXP_LSIO_GPT3_DIV 81 +#define IMX8QXP_LSIO_GPT3_IPG_S_CLK 82 +#define IMX8QXP_LSIO_GPT3_IPG_SLV_CLK 83 +#define IMX8QXP_LSIO_GPT3_IPG_MSTR_CLK 84 +#define IMX8QXP_LSIO_GPT3_HF_CLK 85 +#define IMX8QXP_LSIO_GPT3_CLK 86 +#define IMX8QXP_LSIO_GPT4_DIV 87 +#define IMX8QXP_LSIO_GPT4_IPG_S_CLK 88 +#define IMX8QXP_LSIO_GPT4_IPG_SLV_CLK 89 +#define IMX8QXP_LSIO_GPT4_IPG_MSTR_CLK 90 +#define IMX8QXP_LSIO_GPT4_HF_CLK 91 +#define IMX8QXP_LSIO_GPT4_CLK 92 +#define IMX8QXP_LSIO_FSPI0_DIV 93 +#define IMX8QXP_LSIO_FSPI0_HCLK 94 +#define IMX8QXP_LSIO_FSPI0_IPG_S_CLK 95 +#define IMX8QXP_LSIO_FSPI0_IPG_CLK 96 +#define IMX8QXP_LSIO_FSPI0_CLK 97 +#define IMX8QXP_LSIO_FSPI1_DIV 98 +#define IMX8QXP_LSIO_FSPI1_HCLK 99 +#define IMX8QXP_LSIO_FSPI1_IPG_S_CLK 100 +#define IMX8QXP_LSIO_FSPI1_IPG_CLK 101 +#define IMX8QXP_LSIO_FSPI1_CLK 102 +#define IMX8QXP_LSIO_GPIO0_IPG_S_CLK 103 +#define IMX8QXP_LSIO_GPIO1_IPG_S_CLK 104 +#define IMX8QXP_LSIO_GPIO2_IPG_S_CLK 105 +#define IMX8QXP_LSIO_GPIO3_IPG_S_CLK 106 +#define IMX8QXP_LSIO_GPIO4_IPG_S_CLK 107 +#define IMX8QXP_LSIO_GPIO5_IPG_S_CLK 108 +#define IMX8QXP_LSIO_GPIO6_IPG_S_CLK 109 +#define IMX8QXP_LSIO_GPIO7_IPG_S_CLK 110 +#define IMX8QXP_LSIO_ROMCP_REG_CLK 111 +#define IMX8QXP_LSIO_ROMCP_CLK 112 +#define IMX8QXP_LSIO_96KROM_CLK 113 +#define IMX8QXP_LSIO_OCRAM_MEM_CLK 114 +#define IMX8QXP_LSIO_OCRAM_CTRL_CLK 115 + +/* ADMA SS */ +#define IMX8QXP_UART1_IPG_CLK 116 +#define IMX8QXP_UART2_IPG_CLK 117 +#define IMX8QXP_UART3_IPG_CLK 118 +#define IMX8QXP_UART1_DIV 119 +#define IMX8QXP_UART2_DIV 120 +#define IMX8QXP_UART3_DIV 121 +#define IMX8QXP_UART1_CLK 122 +#define IMX8QXP_UART2_CLK 123 +#define IMX8QXP_UART3_CLK 124 +#define IMX8QXP_SPI0_IPG_CLK 125 +#define IMX8QXP_SPI1_IPG_CLK 126 +#define IMX8QXP_SPI2_IPG_CLK 127 +#define IMX8QXP_SPI3_IPG_CLK 128 +#define IMX8QXP_SPI0_DIV 129 +#define IMX8QXP_SPI1_DIV 130 +#define IMX8QXP_SPI2_DIV 131 +#define IMX8QXP_SPI3_DIV 132 +#define IMX8QXP_SPI0_CLK 133 +#define IMX8QXP_SPI1_CLK 134 +#define IMX8QXP_SPI2_CLK 135 +#define IMX8QXP_SPI3_CLK 136 +#define IMX8QXP_CAN0_IPG_CHI_CLK 137 +#define IMX8QXP_CAN1_IPG_CHI_CLK 138 +#define IMX8QXP_CAN2_IPG_CHI_CLK 139 +#define IMX8QXP_CAN0_IPG_CLK 140 +#define IMX8QXP_CAN1_IPG_CLK 141 +#define IMX8QXP_CAN2_IPG_CLK 142 +#define IMX8QXP_CAN0_DIV 143 +#define IMX8QXP_CAN1_DIV 144 +#define IMX8QXP_CAN2_DIV 145 +#define IMX8QXP_CAN0_CLK 146 +#define IMX8QXP_CAN1_CLK 147 +#define IMX8QXP_CAN2_CLK 148 +#define IMX8QXP_I2C0_IPG_CLK 149 +#define IMX8QXP_I2C1_IPG_CLK 150 +#define IMX8QXP_I2C2_IPG_CLK 151 +#define IMX8QXP_I2C3_IPG_CLK 152 +#define IMX8QXP_I2C0_DIV 153 +#define IMX8QXP_I2C1_DIV 154 +#define IMX8QXP_I2C2_DIV 155 +#define IMX8QXP_I2C3_DIV 156 +#define IMX8QXP_I2C0_CLK 157 +#define IMX8QXP_I2C1_CLK 158 +#define IMX8QXP_I2C2_CLK 159 +#define IMX8QXP_I2C3_CLK 160 +#define IMX8QXP_FTM0_IPG_CLK 161 +#define IMX8QXP_FTM1_IPG_CLK 162 +#define IMX8QXP_FTM0_DIV 163 +#define IMX8QXP_FTM1_DIV 164 +#define IMX8QXP_FTM0_CLK 165 +#define IMX8QXP_FTM1_CLK 166 +#define IMX8QXP_ADC0_IPG_CLK 167 +#define IMX8QXP_ADC0_DIV 168 +#define IMX8QXP_ADC0_CLK 169 +#define IMX8QXP_PWM_IPG_CLK 170 +#define IMX8QXP_PWM_DIV 171 +#define IMX8QXP_PWM_CLK 172 +#define IMX8QXP_LCD_IPG_CLK 173 +#define IMX8QXP_LCD_DIV 174 +#define IMX8QXP_LCD_CLK 175 + +/* Connectivity SS */ +#define IMX8QXP_AXI_CONN_CLK_ROOT 176 +#define IMX8QXP_AHB_CONN_CLK_ROOT 177 +#define IMX8QXP_IPG_CONN_CLK_ROOT 178 +#define IMX8QXP_SDHC0_IPG_CLK 179 +#define IMX8QXP_SDHC1_IPG_CLK 180 +#define IMX8QXP_SDHC2_IPG_CLK 181 +#define IMX8QXP_SDHC0_DIV 182 +#define IMX8QXP_SDHC1_DIV 183 +#define IMX8QXP_SDHC2_DIV 184 +#define IMX8QXP_SDHC0_CLK 185 +#define IMX8QXP_SDHC1_CLK 186 +#define IMX8QXP_SDHC2_CLK 187 +#define IMX8QXP_ENET0_ROOT_DIV 188 +#define IMX8QXP_ENET0_REF_DIV 189 +#define IMX8QXP_ENET1_REF_DIV 190 +#define IMX8QXP_ENET0_BYPASS_DIV 191 +#define IMX8QXP_ENET0_RGMII_DIV 192 +#define IMX8QXP_ENET1_ROOT_DIV 193 +#define IMX8QXP_ENET1_BYPASS_DIV 194 +#define IMX8QXP_ENET1_RGMII_DIV 195 +#define IMX8QXP_ENET0_AHB_CLK 196 +#define IMX8QXP_ENET0_IPG_S_CLK 197 +#define IMX8QXP_ENET0_IPG_CLK 198 +#define IMX8QXP_ENET1_AHB_CLK 199 +#define IMX8QXP_ENET1_IPG_S_CLK 200 +#define IMX8QXP_ENET1_IPG_CLK 201 +#define IMX8QXP_ENET0_ROOT_CLK 202 +#define IMX8QXP_ENET1_ROOT_CLK 203 +#define IMX8QXP_ENET0_TX_CLK 204 +#define IMX8QXP_ENET1_TX_CLK 205 +#define IMX8QXP_ENET0_PTP_CLK 206 +#define IMX8QXP_ENET1_PTP_CLK 207 +#define IMX8QXP_ENET0_REF_25MHZ_125MHZ_SEL 208 +#define IMX8QXP_ENET1_REF_25MHZ_125MHZ_SEL 209 +#define IMX8QXP_ENET0_RMII_TX_SEL 210 +#define IMX8QXP_ENET1_RMII_TX_SEL 211 +#define IMX8QXP_ENET0_RGMII_TX_CLK 212 +#define IMX8QXP_ENET1_RGMII_TX_CLK 213 +#define IMX8QXP_ENET0_RMII_RX_CLK 214 +#define IMX8QXP_ENET1_RMII_RX_CLK 215 +#define IMX8QXP_ENET0_REF_25MHZ_125MHZ_CLK 216 +#define IMX8QXP_ENET1_REF_25MHZ_125MHZ_CLK 217 +#define IMX8QXP_ENET0_REF_50MHZ_CLK 218 +#define IMX8QXP_ENET1_REF_50MHZ_CLK 219 +#define IMX8QXP_GPMI_BCH_IO_DIV 220 +#define IMX8QXP_GPMI_BCH_DIV 221 +#define IMX8QXP_GPMI_APB_CLK 222 +#define IMX8QXP_GPMI_APB_BCH_CLK 223 +#define IMX8QXP_GPMI_BCH_IO_CLK 224 +#define IMX8QXP_GPMI_BCH_CLK 225 +#define IMX8QXP_APBHDMA_CLK 226 +#define IMX8QXP_USB3_ACLK_DIV 227 +#define IMX8QXP_USB3_BUS_DIV 228 +#define IMX8QXP_USB3_LPM_DIV 229 +#define IMX8QXP_USB3_IPG_CLK 230 +#define IMX8QXP_USB3_CORE_PCLK 231 +#define IMX8QXP_USB3_PHY_CLK 232 +#define IMX8QXP_USB3_ACLK 233 +#define IMX8QXP_USB3_BUS_CLK 234 +#define IMX8QXP_USB3_LPM_CLK 235 +#define IMX8QXP_USB2_OH_AHB_CLK 236 +#define IMX8QXP_USB2_OH_IPG_S_CLK 237 +#define IMX8QXP_USB2_OH_IPG_S_PL301_CLK 238 +#define IMX8QXP_USB2_PHY_IPG_CLK 239 +#define IMX8QXP_EDMA_CLK 240 +#define IMX8QXP_EDMA_IPG_CLK 241 +#define IMX8QXP_MLB_HCLK 242 +#define IMX8QXP_MLB_CLK 243 +#define IMX8QXP_MLB_IPG_CLK 244 + +/* Display controller SS */ +/* DC part1 */ +#define IMX8QXP_DC_AXI_EXT_CLK 245 +#define IMX8QXP_DC_AXI_INT_CLK 246 +#define IMX8QXP_DC_CFG_CLK 247 +#define IMX8QXP_DC0_DISP0_CLK 248 +#define IMX8QXP_DC0_DISP1_CLK 249 +#define IMX8QXP_DC0_PRG0_RTRAM_CLK 250 +#define IMX8QXP_DC0_PRG0_APB_CLK 251 +#define IMX8QXP_DC0_PRG1_RTRAM_CLK 252 +#define IMX8QXP_DC0_PRG1_APB_CLK 253 +#define IMX8QXP_DC0_PRG2_RTRAM_CLK 254 +#define IMX8QXP_DC0_PRG2_APB_CLK 255 +#define IMX8QXP_DC0_PRG3_RTRAM_CLK 256 +#define IMX8QXP_DC0_PRG3_APB_CLK 257 +#define IMX8QXP_DC0_PRG4_RTRAM_CLK 258 +#define IMX8QXP_DC0_PRG4_APB_CLK 259 +#define IMX8QXP_DC0_PRG5_RTRAM_CLK 260 +#define IMX8QXP_DC0_PRG5_APB_CLK 261 +#define IMX8QXP_DC0_PRG6_RTRAM_CLK 262 +#define IMX8QXP_DC0_PRG6_APB_CLK 263 +#define IMX8QXP_DC0_PRG7_RTRAM_CLK 264 +#define IMX8QXP_DC0_PRG7_APB_CLK 265 +#define IMX8QXP_DC0_PRG8_RTRAM_CLK 266 +#define IMX8QXP_DC0_PRG8_APB_CLK 267 +#define IMX8QXP_DC0_DPR0_APB_CLK 268 +#define IMX8QXP_DC0_DPR0_B_CLK 269 +#define IMX8QXP_DC0_RTRAM0_CLK 270 +#define IMX8QXP_DC0_RTRAM1_CLK 271 + +/* MIPI-LVDS part1 */ +#define IMX8QXP_MIPI_IPG_CLK 272 +#define IMX8QXP_MIPI0_I2C0_DIV 273 +#define IMX8QXP_MIPI0_I2C1_DIV 274 +#define IMX8QXP_MIPI0_I2C0_CLK 275 +#define IMX8QXP_MIPI0_I2C1_CLK 276 +#define IMX8QXP_MIPI0_I2C0_IPG_S_CLK 277 +#define IMX8QXP_MIPI0_I2C0_IPG_CLK 278 +#define IMX8QXP_MIPI0_I2C1_IPG_S_CLK 279 +#define IMX8QXP_MIPI0_I2C1_IPG_CLK 280 +#define IMX8QXP_MIPI0_PWM_IPG_S_CLK 281 +#define IMX8QXP_MIPI0_PWM_IPG_CLK 282 +#define IMX8QXP_MIPI0_PWM_32K_CLK 283 +#define IMX8QXP_MIPI0_GPIO_IPG_CLK 284 + +#define IMX8QXP_IMG_JPEG_ENC_IPG_CLK 285 +#define IMX8QXP_IMG_JPEG_ENC_CLK 286 +#define IMX8QXP_IMG_JPEG_DEC_IPG_CLK 287 +#define IMX8QXP_IMG_JPEG_DEC_CLK 288 +#define IMX8QXP_IMG_PXL_LINK_DC0_CLK 289 +#define IMX8QXP_IMG_PXL_LINK_DC1_CLK 290 +#define IMX8QXP_IMG_PXL_LINK_CSI0_CLK 291 +#define IMX8QXP_IMG_PXL_LINK_CSI1_CLK 292 +#define IMX8QXP_IMG_PXL_LINK_HDMI_IN_CLK 293 +#define IMX8QXP_IMG_PDMA_0_CLK 294 +#define IMX8QXP_IMG_PDMA_1_CLK 295 +#define IMX8QXP_IMG_PDMA_2_CLK 296 +#define IMX8QXP_IMG_PDMA_3_CLK 297 +#define IMX8QXP_IMG_PDMA_4_CLK 298 +#define IMX8QXP_IMG_PDMA_5_CLK 299 +#define IMX8QXP_IMG_PDMA_6_CLK 300 +#define IMX8QXP_IMG_PDMA_7_CLK 301 +#define IMX8QXP_IMG_AXI_CLK 302 +#define IMX8QXP_IMG_IPG_CLK 303 +#define IMX8QXP_IMG_PXL_CLK 304 + +#define IMX8QXP_CSI0_I2C0_DIV 305 +#define IMX8QXP_CSI0_PWM0_DIV 306 +#define IMX8QXP_CSI0_CORE_DIV 307 +#define IMX8QXP_CSI0_ESC_DIV 308 +#define IMX8QXP_CSI0_IPG_CLK_S 309 +#define IMX8QXP_CSI0_IPG_CLK 310 +#define IMX8QXP_CSI0_APB_CLK 311 +#define IMX8QXP_CSI0_I2C0_IPG_CLK 312 +#define IMX8QXP_CSI0_I2C0_CLK 313 +#define IMX8QXP_CSI0_PWM0_IPG_CLK 314 +#define IMX8QXP_CSI0_PWM0_CLK 315 +#define IMX8QXP_CSI0_CORE_CLK 316 +#define IMX8QXP_CSI0_ESC_CLK 317 + +#define IMX8QXP_HSIO_AXI_CLK 318 +#define IMX8QXP_HSIO_PER_CLK 319 +#define IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK 320 +#define IMX8QXP_HSIO_PCIE_SLV_AXI_CLK 321 +#define IMX8QXP_HSIO_PCIE_DBI_AXI_CLK 322 +#define IMX8QXP_HSIO_PCIE_X1_PER_CLK 323 +#define IMX8QXP_HSIO_PHY_X1_PER_CLK 324 +#define IMX8QXP_HSIO_MISC_PER_CLK 325 +#define IMX8QXP_HSIO_PHY_X1_APB_CLK 326 +#define IMX8QXP_HSIO_GPIO_CLK 327 +#define IMX8QXP_HSIO_PHY_X1_PCLK 328 + +#define IMX8QXP_A35_DIV 329 + +/* ACM */ +#define IMX8QXP_EXT_AUD_MCLK0 330 +#define IMX8QXP_EXT_AUD_MCLK1 331 +#define IMX8QXP_ESAI0_RX_CLK 332 +#define IMX8QXP_ESAI0_RX_HF_CLK 333 +#define IMX8QXP_ESAI0_TX_CLK 334 +#define IMX8QXP_ESAI0_TX_HF_CLK 335 +#define IMX8QXP_SPDIF0_RX 336 +#define IMX8QXP_SAI0_RX_BCLK 337 +#define IMX8QXP_SAI0_TX_BCLK 338 +#define IMX8QXP_SAI1_RX_BCLK 339 +#define IMX8QXP_SAI1_TX_BCLK 340 +#define IMX8QXP_SAI2_RX_BCLK 341 +#define IMX8QXP_SAI3_RX_BCLK 342 +#define IMX8QXP_SAI4_RX_BCLK 343 + +#define IMX8QXP_ACM_AUD_CLK0_SEL 344 +#define IMX8QXP_ACM_AUD_CLK0_CLK 345 +#define IMX8QXP_ACM_AUD_CLK1_SEL 346 +#define IMX8QXP_ACM_AUD_CLK1_CLK 347 +#define IMX8QXP_ACM_MCLKOUT0_SEL 348 +#define IMX8QXP_ACM_MCLKOUT0_CLK 349 +#define IMX8QXP_ACM_MCLKOUT1_SEL 350 +#define IMX8QXP_ACM_MCLKOUT1_CLK 351 +#define IMX8QXP_ACM_ESAI0_MCLK_SEL 352 +#define IMX8QXP_ACM_ESAI0_MCLK_CLK 353 +#define IMX8QXP_ACM_GPT0_MUX_CLK_SEL 354 +#define IMX8QXP_ACM_GPT0_MUX_CLK_CLK 355 +#define IMX8QXP_ACM_GPT1_MUX_CLK_SEL 356 +#define IMX8QXP_ACM_GPT1_MUX_CLK_CLK 357 +#define IMX8QXP_ACM_GPT2_MUX_CLK_SEL 358 +#define IMX8QXP_ACM_GPT2_MUX_CLK_CLK 359 +#define IMX8QXP_ACM_GPT3_MUX_CLK_SEL 360 +#define IMX8QXP_ACM_GPT3_MUX_CLK_CLK 361 +#define IMX8QXP_ACM_GPT4_MUX_CLK_SEL 362 +#define IMX8QXP_ACM_GPT4_MUX_CLK_CLK 363 +#define IMX8QXP_ACM_GPT5_MUX_CLK_SEL 364 +#define IMX8QXP_ACM_GPT5_MUX_CLK_CLK 365 +#define IMX8QXP_ACM_SAI0_MCLK_SEL 366 +#define IMX8QXP_ACM_SAI0_MCLK_CLK 367 +#define IMX8QXP_ACM_SAI1_MCLK_SEL 368 +#define IMX8QXP_ACM_SAI1_MCLK_CLK 369 +#define IMX8QXP_ACM_SAI2_MCLK_SEL 370 +#define IMX8QXP_ACM_SAI2_MCLK_CLK 371 +#define IMX8QXP_ACM_SAI3_MCLK_SEL 372 +#define IMX8QXP_ACM_SAI3_MCLK_CLK 373 +#define IMX8QXP_ACM_SAI4_MCLK_SEL 374 +#define IMX8QXP_ACM_SAI4_MCLK_CLK 375 +#define IMX8QXP_ACM_SAI5_MCLK_SEL 376 +#define IMX8QXP_ACM_SAI5_MCLK_CLK 377 +#define IMX8QXP_ACM_SPDIF0_TX_CLK_SEL 378 +#define IMX8QXP_ACM_SPDIF0_TX_CLK_CLK 379 +#define IMX8QXP_ACM_MQS_TX_CLK_SEL 380 +#define IMX8QXP_ACM_MQS_TX_CLK_CLK 381 +#define IMX8QXP_ACM_ASRC0_MUX_CLK_SEL 382 +#define IMX8QXP_ACM_ASRC1_MUX_CLK_SEL 383 +#define IMX8QXP_ACM_ASRC0_MUX_CLK_CLK 384 +#define IMX8QXP_ACM_ASRC1_MUX_CLK_CLK 385 + +#define IMX8QXP_IPG_AUD_CLK_ROOT 386 + +/* Audio */ +#define IMX8QXP_AUD_PLL0_DIV 387 +#define IMX8QXP_AUD_PLL0 388 +#define IMX8QXP_AUD_PLL1_DIV 389 +#define IMX8QXP_AUD_PLL1 390 +#define IMX8QXP_AUD_AMIX_IPG 391 +#define IMX8QXP_AUD_ESAI_0_IPG 392 +#define IMX8QXP_AUD_ESAI_0_EXTAL_IPG 393 +#define IMX8QXP_AUD_SAI_0_IPG 394 +#define IMX8QXP_AUD_SAI_0_MCLK 395 +#define IMX8QXP_AUD_SAI_1_IPG 396 +#define IMX8QXP_AUD_SAI_1_MCLK 397 +#define IMX8QXP_AUD_SAI_2_IPG 398 +#define IMX8QXP_AUD_SAI_2_MCLK 399 +#define IMX8QXP_AUD_SAI_3_IPG 400 +#define IMX8QXP_AUD_SAI_3_MCLK 401 +#define IMX8QXP_AUD_SAI_4_IPG 402 +#define IMX8QXP_AUD_SAI_4_MCLK 403 +#define IMX8QXP_AUD_SAI_5_IPG 404 +#define IMX8QXP_AUD_SAI_5_MCLK 405 +#define IMX8QXP_AUD_MQS_IPG 406 +#define IMX8QXP_AUD_MQS_HMCLK 407 +#define IMX8QXP_AUD_GPT5_IPG 408 +#define IMX8QXP_AUD_GPT5_CLKIN 409 +#define IMX8QXP_AUD_GPT6_IPG 410 +#define IMX8QXP_AUD_GPT6_CLKIN 411 +#define IMX8QXP_AUD_GPT7_IPG 412 +#define IMX8QXP_AUD_GPT7_CLKIN 413 +#define IMX8QXP_AUD_GPT8_IPG 414 +#define IMX8QXP_AUD_GPT8_CLKIN 415 +#define IMX8QXP_AUD_GPT9_IPG 416 +#define IMX8QXP_AUD_GPT9_CLKIN 417 +#define IMX8QXP_AUD_GPT10_IPG 418 +#define IMX8QXP_AUD_GPT10_CLKIN 419 +#define IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV 420 +#define IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK 421 +#define IMX8QXP_AUD_ACM_AUD_PLL_CLK1_DIV 422 +#define IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK 423 +#define IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV 424 +#define IMX8QXP_AUD_ACM_AUD_REC_CLK0_CLK 425 +#define IMX8QXP_AUD_ACM_AUD_REC_CLK1_DIV 426 +#define IMX8QXP_AUD_ACM_AUD_REC_CLK1_CLK 427 +#define IMX8QXP_AUD_MCLKOUT0 428 +#define IMX8QXP_AUD_MCLKOUT1 429 +#define IMX8QXP_AUD_SPDIF_0_TX_CLK 430 +#define IMX8QXP_AUD_SPDIF_0_GCLKW 431 +#define IMX8QXP_AUD_SPDIF_0_IPG 432 +#define IMX8QXP_AUD_ASRC_0_IPG 433 +#define IMX8QXP_AUD_ASRC_1_IPG 434 +#define IMX8QXP_AUD_HIFI_ADB_ACLK 435 +#define IMX8QXP_AUD_HIFI_IPG 436 +#define IMX8QXP_AUD_HIFI_CORE_CLK 437 +#define IMX8QXP_AUD_OCRAM_IPG 438 + +/* DC part2 */ +#define IMX8QXP_DC0_DISP0_DIV 439 +#define IMX8QXP_DC0_DISP1_DIV 440 +#define IMX8QXP_DC0_BYPASS_0_DIV 441 +#define IMX8QXP_DC0_BYPASS_1_DIV 442 +#define IMX8QXP_DC0_PLL0_DIV 443 +#define IMX8QXP_DC0_PLL1_DIV 444 +#define IMX8QXP_DC0_PLL0_CLK 445 +#define IMX8QXP_DC0_PLL1_CLK 446 + +/* MIPI-LVDS part2 */ +#define IMX8QXP_MIPI0_BYPASS_CLK 447 +#define IMX8QXP_MIPI0_PIXEL_DIV 448 +#define IMX8QXP_MIPI0_PIXEL_CLK 449 +#define IMX8QXP_MIPI0_LVDS_PIXEL_DIV 450 +#define IMX8QXP_MIPI0_LVDS_PIXEL_CLK 451 +#define IMX8QXP_MIPI0_LVDS_BYPASS_CLK 452 +#define IMX8QXP_MIPI0_LVDS_PHY_DIV 453 +#define IMX8QXP_MIPI0_LVDS_PHY_CLK 454 +#define IMX8QXP_MIPI0_LIS_IPG_CLK 455 +#define IMX8QXP_MIPI1_I2C0_DIV 456 +#define IMX8QXP_MIPI1_I2C1_DIV 457 +#define IMX8QXP_MIPI1_I2C0_CLK 458 +#define IMX8QXP_MIPI1_I2C1_CLK 459 +#define IMX8QXP_MIPI1_I2C0_IPG_S_CLK 460 +#define IMX8QXP_MIPI1_I2C0_IPG_CLK 461 +#define IMX8QXP_MIPI1_I2C1_IPG_S_CLK 462 +#define IMX8QXP_MIPI1_I2C1_IPG_CLK 463 +#define IMX8QXP_MIPI1_PWM_IPG_S_CLK 464 +#define IMX8QXP_MIPI1_PWM_IPG_CLK 465 +#define IMX8QXP_MIPI1_PWM_32K_CLK 466 +#define IMX8QXP_MIPI1_GPIO_IPG_CLK 467 +#define IMX8QXP_MIPI1_BYPASS_CLK 468 +#define IMX8QXP_MIPI1_PIXEL_DIV 469 +#define IMX8QXP_MIPI1_PIXEL_CLK 470 +#define IMX8QXP_MIPI1_LVDS_PIXEL_DIV 471 +#define IMX8QXP_MIPI1_LVDS_PIXEL_CLK 472 +#define IMX8QXP_MIPI1_LVDS_BYPASS_CLK 473 +#define IMX8QXP_MIPI1_LVDS_PHY_DIV 474 +#define IMX8QXP_MIPI1_LVDS_PHY_CLK 475 +#define IMX8QXP_MIPI1_LIS_IPG_CLK 476 + +/* CM40 */ +#define IMX8QXP_CM40_IPG_CLK 477 +#define IMX8QXP_CM40_I2C_DIV 478 +#define IMX8QXP_CM40_I2C_CLK 479 +#define IMX8QXP_CM40_I2C_IPG_CLK 480 + +#define IMX8QXP_CLK_END 481 +#endif /* __DT_BINDINGS_CLOCK_IMX8QXP_H */ diff --git a/include/dt-bindings/soc/imx8_pd.h b/include/dt-bindings/soc/imx8_pd.h new file mode 100644 index 0000000000..ef685fe73b --- /dev/null +++ b/include/dt-bindings/soc/imx8_pd.h @@ -0,0 +1,197 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_IMX8_PD_H +#define __DT_BINDINGS_IMX8_PD_H + +/*! + * These defines are used to indicate a resource. Resources include peripherals + * and bus masters (but not memory regions). Note items from list should + * never be changed or removed (only added to at the end of the list). + */ +#define PD_DC_0 dc0_power_domain +#define PD_DC_0_PLL_0 dc0_pll0 +#define PD_DC_0_PLL_1 dc0_pll1 +#define PD_LVDS0 lvds0_power_domain +#define PD_LVDS0_I2C0 lvds0_i2c0 +#define PD_LVDS0_I2C1 lvds0_i2c1 +#define PD_LVDS0_PWM lvds0_pwm +#define PD_LVDS0_PWM lvds0_pwm +#define PD_LVDS0_GPIO lvds0_gpio +#define PD_DC_1 dc1_power_domain +#define PD_DC_1_PLL_0 dc1_pll0 +#define PD_DC_1_PLL_1 dc1_pll1 +#define PD_LVDS1 lvds1_power_domain +#define PD_LVDS1_I2C0 lvds1_i2c0 +#define PD_LVDS1_I2C1 lvds1_i2c1 +#define PD_LVDS1_PWM lvds1_pwm +#define PD_LVDS1_GPIO lvds1_gpio + +#define PD_DMA dma_power_domain +#define PD_DMA_SPI_0 dma_spi0 +#define PD_DMA_SPI_1 dma_spi1 +#define PD_DMA_SPI_2 dma_spi2 +#define PD_DMA_SPI_3 dma_spi3 +#define PD_DMA_UART0 dma_lpuart0 +#define PD_DMA_UART1 dma_lpuart1 +#define PD_DMA_UART2 dma_lpuart2 +#define PD_DMA_UART3 dma_lpuart3 +#define PD_DMA_UART4 dma_lpuart4 +#define PD_DMA_EMVSIM_0 dma_emvsim0 +#define PD_DMA_EMVSIM_1 dma_emvsim1 +#define PD_DMA_I2C_0 dma_lpi2c0 +#define PD_DMA_I2C_1 dma_lpi2c1 +#define PD_DMA_I2C_2 dma_lpi2c2 +#define PD_DMA_I2C_3 dma_lpi2c3 +#define PD_DMA_I2C_4 dma_lpi2c4 +#define PD_DMA_ADC_0 dma_adc0 +#define PD_DMA_ADC_1 dma_adc1 +#define PD_DMA_FTM_0 dma_ftm0 +#define PD_DMA_FTM_1 dma_ftm1 +#define PD_DMA_CAN_0 dma_flexcan0 +#define PD_DMA_CAN_1 dma_flexcan1 +#define PD_DMA_CAN_2 dma_flexcan2 +#define PD_DMA_PWM_0 dma_pwm0 +#define PD_DMA_LCD_0 dma_lcd0 + +#define PD_HSIO hsio_power_domain +#define PD_HSIO_PCIE_A hsio_pcie0 +#define PD_HSIO_PCIE_B hsio_pcie1 +#define PD_HSIO_SATA_0 hsio_sata0 +#define PD_HSIO_GPIO hsio_gpio + +#define PD_LCD_0 lcd0_power_domain +#define PD_LCD_0_I2C_0 lcd0_i2c0 +#define PD_LCD_0_I2C_1 lcd0_i2c1 +#define PD_LCD_PWM_0 lcd0_pwm0 + +#define PD_LSIO lsio_power_domain +#define PD_LSIO_GPIO_0 lsio_gpio0 +#define PD_LSIO_GPIO_1 lsio_gpio1 +#define PD_LSIO_GPIO_2 lsio_gpio2 +#define PD_LSIO_GPIO_3 lsio_gpio3 +#define PD_LSIO_GPIO_4 lsio_gpio4 +#define PD_LSIO_GPIO_5 lsio_gpio5 +#define PD_LSIO_GPIO_6 lsio_gpio6 +#define PD_LSIO_GPIO_7 lsio_gpio7 +#define PD_LSIO_GPT_0 lsio_gpt0 +#define PD_LSIO_GPT_1 lsio_gpt1 +#define PD_LSIO_GPT_2 lsio_gpt2 +#define PD_LSIO_GPT_3 lsio_gpt3 +#define PD_LSIO_GPT_4 lsio_gpt4 +#define PD_LSIO_KPP lsio_kpp +#define PD_LSIO_FSPI_0 lsio_fspi0 +#define PD_LSIO_FSPI_1 lsio_fspi1 +#define PD_LSIO_PWM_0 lsio_pwm0 +#define PD_LSIO_PWM_1 lsio_pwm1 +#define PD_LSIO_PWM_2 lsio_pwm2 +#define PD_LSIO_PWM_3 lsio_pwm3 +#define PD_LSIO_PWM_4 lsio_pwm4 +#define PD_LSIO_PWM_5 lsio_pwm5 +#define PD_LSIO_PWM_6 lsio_pwm6 +#define PD_LSIO_PWM_7 lsio_pwm7 + +#define PD_CONN connectivity_power_domain +#define PD_CONN_SDHC_0 conn_sdhc0 +#define PD_CONN_SDHC_1 conn_sdhc1 +#define PD_CONN_SDHC_2 conn_sdhc2 +#define PD_CONN_ENET_0 conn_enet0 +#define PD_CONN_ENET_1 conn_enet1 +#define PD_CONN_MLB_0 conn_mlb0 +#define PD_CONN_DMA_4_CH0 conn_dma4_ch0 +#define PD_CONN_DMA_4_CH1 conn_dma4_ch1 +#define PD_CONN_DMA_4_CH2 conn_dma4_ch2 +#define PD_CONN_DMA_4_CH3 conn_dma4_ch3 +#define PD_CONN_DMA_4_CH4 conn_dma4_ch4 +#define PD_CONN_USB_0 conn_usb0 +#define PD_CONN_USB_1 conn_usb1 +#define PD_CONN_USB_0_PHY conn_usb0_phy +#define PD_CONN_USB_2 conn_usb2 +#define PD_CONN_USB_2_PHY conn_usb2_phy +#define PD_CONN_NAND conn_nand + +#define PD_AUDIO audio_power_domain +#define PD_AUD_SAI_0 audio_sai0 +#define PD_AUD_SAI_1 audio_sai1 +#define PD_AUD_SAI_2 audio_sai2 +#define PD_AUD_ASRC_0 audio_asrc0 +#define PD_AUD_ASRC_1 audio_asrc1 +#define PD_AUD_ESAI_0 audio_esai0 +#define PD_AUD_ESAI_1 audio_esai1 +#define PD_AUD_SPDIF_0 audio_spdif0 +#define PD_AUD_SPDIF_1 audio_spdif1 +#define PD_AUD_SAI_3 audio_sai3 +#define PD_AUD_SAI_4 audio_sai4 +#define PD_AUD_SAI_5 audio_sai5 +#define PD_AUD_SAI_6 audio_sai6 +#define PD_AUD_SAI_7 audio_sai7 +#define PD_AUD_GPT_5 audio_gpt5 +#define PD_AUD_GPT_6 audio_gpt6 +#define PD_AUD_GPT_7 audio_gpt7 +#define PD_AUD_GPT_8 audio_gpt8 +#define PD_AUD_GPT_9 audio_gpt9 +#define PD_AUD_GPT_10 audio_gpt10 +#define PD_AUD_AMIX audio_amix +#define PD_AUD_MQS_0 audio_mqs0 +#define PD_AUD_HIFI audio_hifi +#define PD_AUD_OCRAM audio_ocram +#define PD_AUD_MCLK_OUT_0 audio_mclkout0 +#define PD_AUD_MCLK_OUT_1 audio_mclkout1 +#define PD_AUD_AUDIO_PLL_0 audio_audiopll0 +#define PD_AUD_AUDIO_PLL_1 audio_audiopll1 +#define PD_AUD_AUDIO_CLK_0 audio_audioclk0 +#define PD_AUD_AUDIO_CLK_1 audio_audioclk1 + +#define PD_IMAGING imaging_power_domain +#define PD_IMAGING_JPEG_DEC imaging_jpeg_dec +#define PD_IMAGING_JPEG_ENC imaging_jpeg_enc +#define PD_IMAGING_PDMA0 PD_IMAGING +#define PD_IMAGING_PDMA1 imaging_pdma1 +#define PD_IMAGING_PDMA2 imaging_pdma2 +#define PD_IMAGING_PDMA3 imaging_pdma3 +#define PD_IMAGING_PDMA4 imaging_pdma4 +#define PD_IMAGING_PDMA5 imaging_pdma5 +#define PD_IMAGING_PDMA6 imaging_pdma6 +#define PD_IMAGING_PDMA7 imaging_pdma7 + +#define PD_MIPI_0_DSI mipi0_dsi_power_domain +#define PD_MIPI_0_DSI_I2C0 mipi0_dsi_i2c0 +#define PD_MIPI_0_DSI_I2C1 mipi0_dsi_i2c1 +#define PD_MIPI_0_DSI_PWM0 mipi0_dsi_pwm0 +#define PD_MIPI_1_DSI mipi1_dsi_power_domain +#define PD_MIPI_1_DSI_I2C0 mipi1_dsi_i2c0 +#define PD_MIPI_1_DSI_I2C1 mipi1_dsi_i2c1 +#define PD_MIPI_1_DSI_PWM0 mipi1_dsi_pwm0 + +#define PD_MIPI_CSI0 mipi_csi0_power_domain +#define PD_MIPI_CSI0_PWM mipi_csi0_pwm +#define PD_MIPI_CSI0_I2C mipi_csi0_i2c +#define PD_MIPI_CSI1 mipi_csi1_power_domain +#define PD_MIPI_CSI1_PWM_0 mipi_csi1_pwm +#define PD_MIPI_CSI1_I2C_0 mipi_csi1_i2c + +#define PD_HDMI hdmi_power_domain +#define PD_HDMI_I2C_0 hdmi_i2c +#define PD_HDMI_PWM_0 hdmi_pwm +#define PD_HDMI_GPIO_0 hdmi_gpio + +#define PD_HDMI_RX hdmi_rx_power_domain +#define PD_HDMI_RX_I2C hdmi_rx_i2c +#define PD_HDMI_RX_PWM hdmi_rx_pwm + +#define PD_CM40 cm40_power_domain +#define PD_CM40_I2C cm40_i2c +#define PD_CM40_INTMUX cm40_intmux + +#endif /* __DT_BINDINGS_IMX8_PD_H */ -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 41/41] imx: 8qxp_mek: Add i.MX8QXP MEK board support 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (39 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 40/41] dts: imx8qxp: Add DTS and binding header files Peng Fan @ 2018-05-28 12:25 ` Peng Fan 2018-06-12 9:43 ` [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan 2018-06-27 8:13 ` Stefano Babic 42 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-05-28 12:25 UTC (permalink / raw) To: u-boot Add board level codes and configs for i.MX8QXP MEK board. - Enabled DM driver: FEC, LPUART, LPI2C, GPIO, SD/MMC, PCA953X, pinctrl, Power-domain - Board defconfigs: imx8qxp_mek_defconfig Boot log: " U-Boot 2018.05-00384-g8907416f0e (May 28 2018 - 14:06:27 +0800) CPU: Freescale i.MX8QXP revB A35 at 1200 MHz Model: Freescale i.MX8QXP MEK Board: iMX8QXP MEK Boot: SD1 DRAM: 3 GiB MMC: Actual rate for SDHC_0 is 333333333 Actual rate for SDHC_1 is 200000000 FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... OK In: serial at 5a060000 Out: serial at 5a060000 Err: serial at 5a060000 Net: No ethernet found. Hit any key to stop autoboot: 0 " Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/mach-imx/imx8/Kconfig | 13 +++ board/freescale/imx8qxp_mek/Kconfig | 14 +++ board/freescale/imx8qxp_mek/MAINTAINERS | 6 ++ board/freescale/imx8qxp_mek/Makefile | 7 ++ board/freescale/imx8qxp_mek/imx8qxp_mek.c | 159 ++++++++++++++++++++++++++++++ configs/imx8qxp_mek_defconfig | 47 +++++++++ include/configs/imx8qxp_mek.h | 157 +++++++++++++++++++++++++++++ 7 files changed, 403 insertions(+) create mode 100644 board/freescale/imx8qxp_mek/Kconfig create mode 100644 board/freescale/imx8qxp_mek/MAINTAINERS create mode 100644 board/freescale/imx8qxp_mek/Makefile create mode 100644 board/freescale/imx8qxp_mek/imx8qxp_mek.c create mode 100644 configs/imx8qxp_mek_defconfig create mode 100644 include/configs/imx8qxp_mek.h diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 58cb19946f..d15dfe3a6e 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -10,4 +10,17 @@ config IMX8QXP config SYS_SOC default "imx8" +choice + prompt "i.MX8 board select" + optional + +config TARGET_IMX8QXP_MEK + bool "Support i.MX8QXP MEK board" + select BOARD_LATE_INIT + select IMX8QXP + +endchoice + +source "board/freescale/imx8qxp_mek/Kconfig" + endif diff --git a/board/freescale/imx8qxp_mek/Kconfig b/board/freescale/imx8qxp_mek/Kconfig new file mode 100644 index 0000000000..b67300d816 --- /dev/null +++ b/board/freescale/imx8qxp_mek/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX8QXP_MEK + +config SYS_BOARD + default "imx8qxp_mek" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8qxp_mek" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx8qxp_mek/MAINTAINERS b/board/freescale/imx8qxp_mek/MAINTAINERS new file mode 100644 index 0000000000..e9bf0b35a3 --- /dev/null +++ b/board/freescale/imx8qxp_mek/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX8QXP MEK BOARD +M: Peng Fan <peng.fan@nxp.com> +S: Maintained +F: board/freescale/imx8qxp_mek/ +F: include/configs/imx8qxp_mek.h +F: configs/imx8qxp_mek_defconfig diff --git a/board/freescale/imx8qxp_mek/Makefile b/board/freescale/imx8qxp_mek/Makefile new file mode 100644 index 0000000000..f9ee8aeff3 --- /dev/null +++ b/board/freescale/imx8qxp_mek/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8qxp_mek.o diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c new file mode 100644 index 0000000000..e74c3a2547 --- /dev/null +++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <errno.h> +#include <linux/libfdt.h> +#include <environment.h> +#include <fsl_esdhc.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clock.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/imx8-pins.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +int board_early_init_f(void) +{ + sc_ipc_t ipchndl; + sc_err_t scierr; + /* Set UART0 clock root to 80 MHz */ + sc_pm_clock_rate_t rate = 80000000; + + ipchndl = gd->arch.ipc_channel_handle; + + /* Power up UART0 */ + scierr = sc_pm_set_resource_power_mode(ipchndl, SC_R_UART_0, + SC_PM_PW_MODE_ON); + if (scierr != SC_ERR_NONE) + return 0; + + scierr = sc_pm_set_clock_rate(ipchndl, SC_R_UART_0, 2, &rate); + if (scierr != SC_ERR_NONE) + return 0; + + /* Enable UART0 clock root */ + scierr = sc_pm_clock_enable(ipchndl, SC_R_UART_0, 2, true, false); + if (scierr != SC_ERR_NONE) + return 0; + + setup_iomux_uart(); + + return 0; +} + +#ifdef CONFIG_MXC_GPIO +#define IOEXP_RESET IMX_GPIO_NR(1, 1) + +static iomux_cfg_t board_gpios[] = { + SC_P_SPI2_SDO | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL), + SC_P_ENET0_REFCLK_125M_25M | MUX_MODE_ALT(4) | + MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +static void board_gpio_init(void) +{ + int ret; + struct gpio_desc desc; + + ret = dm_gpio_lookup_name("gpio at 1a_3", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "bb_per_rst_b"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 0); + udelay(50); + dm_gpio_set_value(&desc, 1); + + imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios)); + + /* enable i2c port expander assert reset line */ + gpio_request(IOEXP_RESET, "ioexp_rst"); + gpio_direction_output(IOEXP_RESET, 1); +} +#endif + +int checkboard(void) +{ + puts("Board: iMX8QXP MEK\n"); + + print_bootinfo(); + + return 0; +} + +int board_init(void) +{ +#ifdef CONFIG_MXC_GPIO + board_gpio_init(); +#endif + + return 0; +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + puts("SCI reboot request"); + sc_pm_reboot(SC_IPC_CH, SC_PM_RESET_TYPE_COLD); + while (1) + putc('.'); +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "MEK"); + env_set("board_rev", "iMX8QXP"); +#endif + + return 0; +} diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig new file mode 100644 index 0000000000..15b63da839 --- /dev/null +++ b/configs/imx8qxp_mek_defconfig @@ -0,0 +1,47 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" +CONFIG_TARGET_IMX8QXP_MEK=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_ENV_IS_IN_MMC=y diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h new file mode 100644 index 0000000000..f0aa1c7541 --- /dev/null +++ b/include/configs/imx8qxp_mek.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __IMX8QXP_MEK_H +#define __IMX8QXP_MEK_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD + +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +/* GPIO configs */ +#define CONFIG_MXC_GPIO + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fdt=try\0" \ + "fdt_file=fsl-imx8qxp-mek.dtb\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +/* Default environment is in SD */ +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_OFFSET (64 * SZ_64K) +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_NR_DRAM_BANKS 3 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +/* LPDDR4 board total DDR is 3GB */ +#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */ + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Monitor Command Prompt */ +#define CONFIG_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#ifndef CONFIG_DM_PCA953X +#define CONFIG_PCA953X +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO +#endif + +#endif /* __IMX8QXP_MEK_H */ -- 2.14.1 ^ permalink raw reply related [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (40 preceding siblings ...) 2018-05-28 12:25 ` [U-Boot] [PATCH 41/41] imx: 8qxp_mek: Add i.MX8QXP MEK board support Peng Fan @ 2018-06-12 9:43 ` Peng Fan 2018-06-12 14:07 ` Fabio Estevam 2018-06-27 8:13 ` Stefano Babic 42 siblings, 1 reply; 69+ messages in thread From: Peng Fan @ 2018-06-12 9:43 UTC (permalink / raw) To: u-boot Hi Stefano, Fabio, Sorry for the bother in patch 1, that patch is big. So ask here. Do you have any comments on the patchset? Thanks, Peng > -----Original Message----- > From: Peng Fan > Sent: 2018年5月28日 20:25 > To: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com> > Cc: u-boot at lists.denx.de; Peng Fan <peng.fan@nxp.com> > Subject: [PATCH 00/41] imx: add i.MX8QXP support > > This patchset is to upstream i.MX8QXP and mek board support, with some > drivers update to support i.MX8QXP. The information about the processor could > be found > https://www.nxp.com/products/processors-and-microcontrollers/applications-p > rocessors/i.mx-applications-processors/i.mx-8-processors/i.mx-8x-family-arm-co > rtex-a35-3d-graphics-4k-video-dsp-error-correcting-code-on-ddr:i.MX8X > > The architecture of i.MX8QXP is different from i.MX6/7/8M, inside i.MX8QXP, > there is a dedicated processor(SCU) used for power/clock/pin/ pad/resource > management/thermal and etc. The ACore need to communicate with SCU using > SCFW API. The SCFW API is exported by SCFW, so we directly import it into > U-Boot source code. > > Gao Pan (1): > imx: lpi2c: fix clock issue when NACK detected > > Peng Fan (32): > imx: import SCFW API > imx: add Kconfig entry for i.MX8 > arm: build mach-imx for i.MX8 > imx8: add IPC communication support between ACore and SCU > arm: global_data: introduce ipc_channel_handle > imx: boot_mode: Add FLEXSPI boot entry > imx8: add imx-regs header file > imx8: pins: include i.MX8QXP pin header when CONFIG_IMX8QXP defined > imx: add i.MX8 cpu type > imx8: add basic cpu support > imx8: add boot device detection > imx8: implement mmc_get_env_dev > imx8: implement imx_get_mac_from_fuse > imx8: implement get_board_serial > imx8: add mmu and dram related functiions > imx8: add bootaux support > imx8: add arch_cpu_init > imx8: add clock driver > imx8: add iomux configuration code > serial_lpuart: Update lpuart driver to support i.MX8 > net: fec: do not access reserved register for i.MX8 > gpio: mxc_gpio: add support for i.MX8 > pinctrl: Add pinctrl driver for i.MX8 > power: Add power domain driver for i.MX8 > power: Add PD device lookup interface to power domain uclass > power-domain: add dummy functions when CONFIG_POWER_DOMAIN not > defined > dm: core: device: enable power domain in probe > drivers: regulator: fixed: add off-on-delay-us > log: include command header file > i2c-mux: pca954x: support pca9646 i2c switch > dts: imx8qxp: Add DTS and binding header files > imx: 8qxp_mek: Add i.MX8QXP MEK board support > > Ye Li (8): > fsl_esdhc: Update usdhc driver to support i.MX8 > serial: lpuart: Enable RX and TX FIFO > imx_lpi2c: Update lpi2c driver to support imx8 > lpi2c: Fix bus stop problem in xfer > lpi2c: Add bus busy error handling > net: fec_mxc: Add the init_clk_fec function > sata: Add i.MX8 SATA support > mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue > > arch/arm/Kconfig | 8 + > arch/arm/Makefile | 2 +- > arch/arm/dts/Makefile | 2 + > arch/arm/dts/fsl-imx8qxp-mek.dts | 416 +++++ > arch/arm/dts/fsl-imx8qxp.dtsi | 1593 > ++++++++++++++++++++ > arch/arm/include/asm/arch-imx/cpu.h | 5 + > arch/arm/include/asm/arch-imx8/clock.h | 36 + > arch/arm/include/asm/arch-imx8/cpu.h | 26 + > arch/arm/include/asm/arch-imx8/fsl_mu_hal.h | 54 + > arch/arm/include/asm/arch-imx8/gpio.h | 22 + > arch/arm/include/asm/arch-imx8/i2c.h | 34 + > arch/arm/include/asm/arch-imx8/imx-regs.h | 119 ++ > arch/arm/include/asm/arch-imx8/imx8-pins.h | 15 + > arch/arm/include/asm/arch-imx8/imx8qm_pads.h | 295 ++++ > arch/arm/include/asm/arch-imx8/imx8qxp_pads.h | 200 +++ > arch/arm/include/asm/arch-imx8/iomux.h | 40 + > arch/arm/include/asm/arch-imx8/power-domain.h | 15 + > arch/arm/include/asm/arch-imx8/sci/ipc.h | 67 + > arch/arm/include/asm/arch-imx8/sci/rpc.h | 131 ++ > arch/arm/include/asm/arch-imx8/sci/sci.h | 39 + > arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h | 160 ++ > arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h | 523 +++++++ > arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h | 568 +++++++ > arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h | 686 +++++++++ > arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h | 759 ++++++++++ > arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h | 306 ++++ > arch/arm/include/asm/arch-imx8/sci/types.h | 862 +++++++++++ > arch/arm/include/asm/arch-imx8/sys_proto.h | 19 + > arch/arm/include/asm/global_data.h | 4 + > arch/arm/include/asm/mach-imx/boot_mode.h | 1 + > arch/arm/include/asm/mach-imx/sys_proto.h | 3 + > arch/arm/mach-imx/Makefile | 1 + > arch/arm/mach-imx/imx8/Kconfig | 26 + > arch/arm/mach-imx/imx8/Makefile | 13 + > arch/arm/mach-imx/imx8/clock.c | 361 +++++ > arch/arm/mach-imx/imx8/cpu.c | 783 > ++++++++++ > arch/arm/mach-imx/imx8/fsl_mu_hal.c | 28 + > arch/arm/mach-imx/imx8/iomux.c | 47 + > arch/arm/mach-imx/imx8/sci/ipc.c | 100 ++ > arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h | 54 + > arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c | 76 + > arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h | 76 + > arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c | 515 +++++++ > arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h | 68 + > arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c | 475 ++++++ > arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h | 73 + > arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c | 460 ++++++ > arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h | 83 + > arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c | 645 ++++++++ > arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h | 67 + > arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c | 365 +++++ > board/freescale/imx8qxp_mek/Kconfig | 14 + > board/freescale/imx8qxp_mek/MAINTAINERS | 6 + > board/freescale/imx8qxp_mek/Makefile | 7 + > board/freescale/imx8qxp_mek/imx8qxp_mek.c | 159 ++ > configs/imx8qxp_mek_defconfig | 47 + > drivers/ata/Kconfig | 6 + > drivers/ata/Makefile | 1 + > drivers/ata/ahci.c | 25 + > drivers/ata/sata_imx.c | 64 + > drivers/core/device.c | 7 + > drivers/gpio/mxc_gpio.c | 30 +- > drivers/i2c/imx_lpi2c.c | 82 +- > drivers/i2c/muxes/pca954x.c | 9 +- > drivers/mmc/fsl_esdhc.c | 32 +- > drivers/net/fec_mxc.c | 9 +- > drivers/pinctrl/nxp/Kconfig | 18 + > drivers/pinctrl/nxp/Makefile | 2 + > drivers/pinctrl/nxp/pinctrl-imx.c | 209 +-- > drivers/pinctrl/nxp/pinctrl-imx.h | 16 + > drivers/pinctrl/nxp/pinctrl-imx8.c | 42 + > drivers/pinctrl/nxp/pinctrl-scu.c | 72 + > drivers/power/domain/Kconfig | 6 + > drivers/power/domain/Makefile | 1 + > drivers/power/domain/imx8-power-domain.c | 315 ++++ > drivers/power/domain/power-domain-uclass.c | 42 + > drivers/power/regulator/fixed.c | 6 + > drivers/serial/serial_lpuart.c | 48 +- > include/configs/imx8qxp_mek.h | 157 ++ > include/dt-bindings/clock/imx8qxp-clock.h | 533 +++++++ > include/dt-bindings/pinctrl/pads-imx8qm.h | 975 ++++++++++++ > include/dt-bindings/pinctrl/pads-imx8qxp.h | 770 ++++++++++ > include/dt-bindings/soc/imx8_pd.h | 197 +++ > include/dt-bindings/soc/imx_rsrc.h | 560 +++++++ > include/fsl_lpuart.h | 2 +- > .../asm/arch-mx7ulp => include}/imx_lpi2c.h | 0 > include/log.h | 1 + > include/power-domain.h | 52 + > 88 files changed, 15691 insertions(+), 157 deletions(-) create mode 100644 > arch/arm/dts/fsl-imx8qxp-mek.dts create mode 100644 > arch/arm/dts/fsl-imx8qxp.dtsi create mode 100644 > arch/arm/include/asm/arch-imx8/clock.h > create mode 100644 arch/arm/include/asm/arch-imx8/cpu.h > create mode 100644 arch/arm/include/asm/arch-imx8/fsl_mu_hal.h > create mode 100644 arch/arm/include/asm/arch-imx8/gpio.h > create mode 100644 arch/arm/include/asm/arch-imx8/i2c.h > create mode 100644 arch/arm/include/asm/arch-imx8/imx-regs.h > create mode 100644 arch/arm/include/asm/arch-imx8/imx8-pins.h > create mode 100644 arch/arm/include/asm/arch-imx8/imx8qm_pads.h > create mode 100644 arch/arm/include/asm/arch-imx8/imx8qxp_pads.h > create mode 100644 arch/arm/include/asm/arch-imx8/iomux.h > create mode 100644 arch/arm/include/asm/arch-imx8/power-domain.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/ipc.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/rpc.h > create mode 100644 arch/arm/include/asm/arch-imx8/sci/sci.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/types.h > create mode 100644 arch/arm/include/asm/arch-imx8/sys_proto.h > create mode 100644 arch/arm/mach-imx/imx8/Kconfig create mode 100644 > arch/arm/mach-imx/imx8/Makefile create mode 100644 > arch/arm/mach-imx/imx8/clock.c create mode 100644 > arch/arm/mach-imx/imx8/cpu.c create mode 100644 > arch/arm/mach-imx/imx8/fsl_mu_hal.c > create mode 100644 arch/arm/mach-imx/imx8/iomux.c create mode > 100644 arch/arm/mach-imx/imx8/sci/ipc.c create mode 100644 > arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c > create mode 100644 board/freescale/imx8qxp_mek/Kconfig > create mode 100644 board/freescale/imx8qxp_mek/MAINTAINERS > create mode 100644 board/freescale/imx8qxp_mek/Makefile > create mode 100644 board/freescale/imx8qxp_mek/imx8qxp_mek.c > create mode 100644 configs/imx8qxp_mek_defconfig create mode 100644 > drivers/ata/sata_imx.c create mode 100644 drivers/pinctrl/nxp/pinctrl-imx8.c > create mode 100644 drivers/pinctrl/nxp/pinctrl-scu.c create mode 100644 > drivers/power/domain/imx8-power-domain.c > create mode 100644 include/configs/imx8qxp_mek.h create mode 100644 > include/dt-bindings/clock/imx8qxp-clock.h > create mode 100644 include/dt-bindings/pinctrl/pads-imx8qm.h > create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h > create mode 100644 include/dt-bindings/soc/imx8_pd.h create mode > 100644 include/dt-bindings/soc/imx_rsrc.h > rename {arch/arm/include/asm/arch-mx7ulp => include}/imx_lpi2c.h (100%) > > -- > 2.14.1 ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support 2018-06-12 9:43 ` [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan @ 2018-06-12 14:07 ` Fabio Estevam 2018-06-15 6:45 ` Peng Fan 0 siblings, 1 reply; 69+ messages in thread From: Fabio Estevam @ 2018-06-12 14:07 UTC (permalink / raw) To: u-boot Hi Peng, On Tue, Jun 12, 2018 at 6:43 AM, Peng Fan <peng.fan@nxp.com> wrote: > Hi Stefano, Fabio, > > Sorry for the bother in patch 1, that patch is big. So ask here. > Do you have any comments on the patchset? It would be better if you could split this 41 patch series into smaller pieces. For example: you could send driver related patches to each subsystem maintainer separately instead of being part of this the huge series. I will try to provide some feedback during this week. Thanks for working on this. ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support 2018-06-12 14:07 ` Fabio Estevam @ 2018-06-15 6:45 ` Peng Fan 0 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-06-15 6:45 UTC (permalink / raw) To: u-boot Hi Fabio > -----Original Message----- > From: Fabio Estevam [mailto:festevam at gmail.com] > Sent: 2018年6月12日 22:08 > To: Peng Fan <peng.fan@nxp.com> > Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>; > u-boot at lists.denx.de > Subject: Re: [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support > > Hi Peng, > > On Tue, Jun 12, 2018 at 6:43 AM, Peng Fan <peng.fan@nxp.com> wrote: > > Hi Stefano, Fabio, > > > > Sorry for the bother in patch 1, that patch is big. So ask here. > > Do you have any comments on the patchset? > > It would be better if you could split this 41 patch series into smaller pieces. > > For example: you could send driver related patches to each subsystem > maintainer separately instead of being part of this the huge series. Ok. I'll split them into small patchset in next version. > > I will try to provide some feedback during this week. Thanks. Thanks, Peng. > > Thanks for working on this. ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan ` (41 preceding siblings ...) 2018-06-12 9:43 ` [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan @ 2018-06-27 8:13 ` Stefano Babic 2018-07-07 12:55 ` Peng Fan 42 siblings, 1 reply; 69+ messages in thread From: Stefano Babic @ 2018-06-27 8:13 UTC (permalink / raw) To: u-boot Hi Peng, On 28/05/2018 14:24, Peng Fan wrote: > This patchset is to upstream i.MX8QXP and mek board support, with some > drivers update to support i.MX8QXP. The information about the processor > could be found > https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-8-processors/i.mx-8x-family-arm-cortex-a35-3d-graphics-4k-video-dsp-error-correcting-code-on-ddr:i.MX8X > > The architecture of i.MX8QXP is different from i.MX6/7/8M, inside i.MX8QXP, > there is a dedicated processor(SCU) used for power/clock/pin/ > pad/resource management/thermal and etc. The ACore need to communicate > with SCU using SCFW API. The SCFW API is exported by SCFW, so we directly > import it into U-Boot source code. > first at all, thanks for this. It is a huge work, and all of us want to get the MX8 into U-Boot. I would like to plan how we can introduce the architecture in U-Boot. First at all, I beg you to split the huge series into small pieces. It is quite difficult to review. I suggest you extract parts that are not related to MX8. Some of patches in the series can be already be merged because unrelated. For example, I2C patches: lpi2c: Fix bus stop problem in xfer lpi2c: Add bus busy error handling They can be simply merged because they fix issues. Some other Ye's patch fall into this category and can be merged independently foro mi.MX8. I will also ask to split Patch 1 in small and easier to review pieces. Best regards, Stefano > Gao Pan (1): > imx: lpi2c: fix clock issue when NACK detected > > Peng Fan (32): > imx: import SCFW API > imx: add Kconfig entry for i.MX8 > arm: build mach-imx for i.MX8 > imx8: add IPC communication support between ACore and SCU > arm: global_data: introduce ipc_channel_handle > imx: boot_mode: Add FLEXSPI boot entry > imx8: add imx-regs header file > imx8: pins: include i.MX8QXP pin header when CONFIG_IMX8QXP defined > imx: add i.MX8 cpu type > imx8: add basic cpu support > imx8: add boot device detection > imx8: implement mmc_get_env_dev > imx8: implement imx_get_mac_from_fuse > imx8: implement get_board_serial > imx8: add mmu and dram related functiions > imx8: add bootaux support > imx8: add arch_cpu_init > imx8: add clock driver > imx8: add iomux configuration code > serial_lpuart: Update lpuart driver to support i.MX8 > net: fec: do not access reserved register for i.MX8 > gpio: mxc_gpio: add support for i.MX8 > pinctrl: Add pinctrl driver for i.MX8 > power: Add power domain driver for i.MX8 > power: Add PD device lookup interface to power domain uclass > power-domain: add dummy functions when CONFIG_POWER_DOMAIN not defined > dm: core: device: enable power domain in probe > drivers: regulator: fixed: add off-on-delay-us > log: include command header file > i2c-mux: pca954x: support pca9646 i2c switch > dts: imx8qxp: Add DTS and binding header files > imx: 8qxp_mek: Add i.MX8QXP MEK board support > > Ye Li (8): > fsl_esdhc: Update usdhc driver to support i.MX8 > serial: lpuart: Enable RX and TX FIFO > imx_lpi2c: Update lpi2c driver to support imx8 > lpi2c: Fix bus stop problem in xfer > lpi2c: Add bus busy error handling > net: fec_mxc: Add the init_clk_fec function > sata: Add i.MX8 SATA support > mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue > > arch/arm/Kconfig | 8 + > arch/arm/Makefile | 2 +- > arch/arm/dts/Makefile | 2 + > arch/arm/dts/fsl-imx8qxp-mek.dts | 416 +++++ > arch/arm/dts/fsl-imx8qxp.dtsi | 1593 ++++++++++++++++++++ > arch/arm/include/asm/arch-imx/cpu.h | 5 + > arch/arm/include/asm/arch-imx8/clock.h | 36 + > arch/arm/include/asm/arch-imx8/cpu.h | 26 + > arch/arm/include/asm/arch-imx8/fsl_mu_hal.h | 54 + > arch/arm/include/asm/arch-imx8/gpio.h | 22 + > arch/arm/include/asm/arch-imx8/i2c.h | 34 + > arch/arm/include/asm/arch-imx8/imx-regs.h | 119 ++ > arch/arm/include/asm/arch-imx8/imx8-pins.h | 15 + > arch/arm/include/asm/arch-imx8/imx8qm_pads.h | 295 ++++ > arch/arm/include/asm/arch-imx8/imx8qxp_pads.h | 200 +++ > arch/arm/include/asm/arch-imx8/iomux.h | 40 + > arch/arm/include/asm/arch-imx8/power-domain.h | 15 + > arch/arm/include/asm/arch-imx8/sci/ipc.h | 67 + > arch/arm/include/asm/arch-imx8/sci/rpc.h | 131 ++ > arch/arm/include/asm/arch-imx8/sci/sci.h | 39 + > arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h | 160 ++ > arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h | 523 +++++++ > arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h | 568 +++++++ > arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h | 686 +++++++++ > arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h | 759 ++++++++++ > arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h | 306 ++++ > arch/arm/include/asm/arch-imx8/sci/types.h | 862 +++++++++++ > arch/arm/include/asm/arch-imx8/sys_proto.h | 19 + > arch/arm/include/asm/global_data.h | 4 + > arch/arm/include/asm/mach-imx/boot_mode.h | 1 + > arch/arm/include/asm/mach-imx/sys_proto.h | 3 + > arch/arm/mach-imx/Makefile | 1 + > arch/arm/mach-imx/imx8/Kconfig | 26 + > arch/arm/mach-imx/imx8/Makefile | 13 + > arch/arm/mach-imx/imx8/clock.c | 361 +++++ > arch/arm/mach-imx/imx8/cpu.c | 783 ++++++++++ > arch/arm/mach-imx/imx8/fsl_mu_hal.c | 28 + > arch/arm/mach-imx/imx8/iomux.c | 47 + > arch/arm/mach-imx/imx8/sci/ipc.c | 100 ++ > arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h | 54 + > arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c | 76 + > arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h | 76 + > arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c | 515 +++++++ > arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h | 68 + > arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c | 475 ++++++ > arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h | 73 + > arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c | 460 ++++++ > arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h | 83 + > arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c | 645 ++++++++ > arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h | 67 + > arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c | 365 +++++ > board/freescale/imx8qxp_mek/Kconfig | 14 + > board/freescale/imx8qxp_mek/MAINTAINERS | 6 + > board/freescale/imx8qxp_mek/Makefile | 7 + > board/freescale/imx8qxp_mek/imx8qxp_mek.c | 159 ++ > configs/imx8qxp_mek_defconfig | 47 + > drivers/ata/Kconfig | 6 + > drivers/ata/Makefile | 1 + > drivers/ata/ahci.c | 25 + > drivers/ata/sata_imx.c | 64 + > drivers/core/device.c | 7 + > drivers/gpio/mxc_gpio.c | 30 +- > drivers/i2c/imx_lpi2c.c | 82 +- > drivers/i2c/muxes/pca954x.c | 9 +- > drivers/mmc/fsl_esdhc.c | 32 +- > drivers/net/fec_mxc.c | 9 +- > drivers/pinctrl/nxp/Kconfig | 18 + > drivers/pinctrl/nxp/Makefile | 2 + > drivers/pinctrl/nxp/pinctrl-imx.c | 209 +-- > drivers/pinctrl/nxp/pinctrl-imx.h | 16 + > drivers/pinctrl/nxp/pinctrl-imx8.c | 42 + > drivers/pinctrl/nxp/pinctrl-scu.c | 72 + > drivers/power/domain/Kconfig | 6 + > drivers/power/domain/Makefile | 1 + > drivers/power/domain/imx8-power-domain.c | 315 ++++ > drivers/power/domain/power-domain-uclass.c | 42 + > drivers/power/regulator/fixed.c | 6 + > drivers/serial/serial_lpuart.c | 48 +- > include/configs/imx8qxp_mek.h | 157 ++ > include/dt-bindings/clock/imx8qxp-clock.h | 533 +++++++ > include/dt-bindings/pinctrl/pads-imx8qm.h | 975 ++++++++++++ > include/dt-bindings/pinctrl/pads-imx8qxp.h | 770 ++++++++++ > include/dt-bindings/soc/imx8_pd.h | 197 +++ > include/dt-bindings/soc/imx_rsrc.h | 560 +++++++ > include/fsl_lpuart.h | 2 +- > .../asm/arch-mx7ulp => include}/imx_lpi2c.h | 0 > include/log.h | 1 + > include/power-domain.h | 52 + > 88 files changed, 15691 insertions(+), 157 deletions(-) > create mode 100644 arch/arm/dts/fsl-imx8qxp-mek.dts > create mode 100644 arch/arm/dts/fsl-imx8qxp.dtsi > create mode 100644 arch/arm/include/asm/arch-imx8/clock.h > create mode 100644 arch/arm/include/asm/arch-imx8/cpu.h > create mode 100644 arch/arm/include/asm/arch-imx8/fsl_mu_hal.h > create mode 100644 arch/arm/include/asm/arch-imx8/gpio.h > create mode 100644 arch/arm/include/asm/arch-imx8/i2c.h > create mode 100644 arch/arm/include/asm/arch-imx8/imx-regs.h > create mode 100644 arch/arm/include/asm/arch-imx8/imx8-pins.h > create mode 100644 arch/arm/include/asm/arch-imx8/imx8qm_pads.h > create mode 100644 arch/arm/include/asm/arch-imx8/imx8qxp_pads.h > create mode 100644 arch/arm/include/asm/arch-imx8/iomux.h > create mode 100644 arch/arm/include/asm/arch-imx8/power-domain.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/ipc.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/rpc.h > create mode 100644 arch/arm/include/asm/arch-imx8/sci/sci.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h > create mode 100755 arch/arm/include/asm/arch-imx8/sci/types.h > create mode 100644 arch/arm/include/asm/arch-imx8/sys_proto.h > create mode 100644 arch/arm/mach-imx/imx8/Kconfig > create mode 100644 arch/arm/mach-imx/imx8/Makefile > create mode 100644 arch/arm/mach-imx/imx8/clock.c > create mode 100644 arch/arm/mach-imx/imx8/cpu.c > create mode 100644 arch/arm/mach-imx/imx8/fsl_mu_hal.c > create mode 100644 arch/arm/mach-imx/imx8/iomux.c > create mode 100644 arch/arm/mach-imx/imx8/sci/ipc.c > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c > create mode 100644 board/freescale/imx8qxp_mek/Kconfig > create mode 100644 board/freescale/imx8qxp_mek/MAINTAINERS > create mode 100644 board/freescale/imx8qxp_mek/Makefile > create mode 100644 board/freescale/imx8qxp_mek/imx8qxp_mek.c > create mode 100644 configs/imx8qxp_mek_defconfig > create mode 100644 drivers/ata/sata_imx.c > create mode 100644 drivers/pinctrl/nxp/pinctrl-imx8.c > create mode 100644 drivers/pinctrl/nxp/pinctrl-scu.c > create mode 100644 drivers/power/domain/imx8-power-domain.c > create mode 100644 include/configs/imx8qxp_mek.h > create mode 100644 include/dt-bindings/clock/imx8qxp-clock.h > create mode 100644 include/dt-bindings/pinctrl/pads-imx8qm.h > create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h > create mode 100644 include/dt-bindings/soc/imx8_pd.h > create mode 100644 include/dt-bindings/soc/imx_rsrc.h > rename {arch/arm/include/asm/arch-mx7ulp => include}/imx_lpi2c.h (100%) > -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 69+ messages in thread
* [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support 2018-06-27 8:13 ` Stefano Babic @ 2018-07-07 12:55 ` Peng Fan 0 siblings, 0 replies; 69+ messages in thread From: Peng Fan @ 2018-07-07 12:55 UTC (permalink / raw) To: u-boot Hi Stefano, > -----Original Message----- > From: Stefano Babic [mailto:sbabic at denx.de] > Sent: 2018年6月27日 16:14 > To: Peng Fan <peng.fan@nxp.com>; sbabic at denx.de; Fabio Estevam > <fabio.estevam@nxp.com> > Cc: u-boot at lists.denx.de; Anatolij Gustschin <agust@denx.de> > Subject: Re: [PATCH 00/41] imx: add i.MX8QXP support > > Hi Peng, > > > On 28/05/2018 14:24, Peng Fan wrote: > > This patchset is to upstream i.MX8QXP and mek board support, with some > > drivers update to support i.MX8QXP. The information about the > > processor could be found > > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww > > .nxp.com%2Fproducts%2Fprocessors-and-microcontrollers%2Fapplications-p > > rocessors%2Fi.mx-applications-processors%2Fi.mx-8-processors%2Fi.mx-8x > > -family-arm-cortex-a35-3d-graphics-4k-video-dsp-error-correcting-code- > > > on-ddr%3Ai.MX8X&data=02%7C01%7Cpeng.fan%40nxp.com%7C1aeecdf44004 > 48a1ee > > > aa08d5dc05ea14%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636 > 6568403 > > > 29616566&sdata=Fgi%2FTq16goRxKyLtVkFQwW7VfZEhFwKnIXAEuqRNPZo%3D > &reserv > > ed=0 > > > > The architecture of i.MX8QXP is different from i.MX6/7/8M, inside > > i.MX8QXP, there is a dedicated processor(SCU) used for > > power/clock/pin/ pad/resource management/thermal and etc. The ACore > > need to communicate with SCU using SCFW API. The SCFW API is exported > > by SCFW, so we directly import it into U-Boot source code. > > > > first at all, thanks for this. It is a huge work, and all of us want to get the MX8 > into U-Boot. I would like to plan how we can introduce the architecture in > U-Boot. > > First at all, I beg you to split the huge series into small pieces. It is quite difficult > to review. I suggest you extract parts that are not related to MX8. Some of > patches in the series can be already be merged because unrelated. > > For example, I2C patches: > > lpi2c: Fix bus stop problem in xfer > lpi2c: Add bus busy error handling > > They can be simply merged because they fix issues. Some other Ye's patch fall > into this category and can be merged independently foro mi.MX8. I'll spit them into small patches. > > I will also ask to split Patch 1 in small and easier to review pieces. The first patch which is the SCFW API is generated from SCFW. I need to find a way to cleanup. Thanks, Peng. > > Best regards, > Stefano > > > Gao Pan (1): > > imx: lpi2c: fix clock issue when NACK detected > > > > Peng Fan (32): > > imx: import SCFW API > > imx: add Kconfig entry for i.MX8 > > arm: build mach-imx for i.MX8 > > imx8: add IPC communication support between ACore and SCU > > arm: global_data: introduce ipc_channel_handle > > imx: boot_mode: Add FLEXSPI boot entry > > imx8: add imx-regs header file > > imx8: pins: include i.MX8QXP pin header when CONFIG_IMX8QXP defined > > imx: add i.MX8 cpu type > > imx8: add basic cpu support > > imx8: add boot device detection > > imx8: implement mmc_get_env_dev > > imx8: implement imx_get_mac_from_fuse > > imx8: implement get_board_serial > > imx8: add mmu and dram related functiions > > imx8: add bootaux support > > imx8: add arch_cpu_init > > imx8: add clock driver > > imx8: add iomux configuration code > > serial_lpuart: Update lpuart driver to support i.MX8 > > net: fec: do not access reserved register for i.MX8 > > gpio: mxc_gpio: add support for i.MX8 > > pinctrl: Add pinctrl driver for i.MX8 > > power: Add power domain driver for i.MX8 > > power: Add PD device lookup interface to power domain uclass > > power-domain: add dummy functions when CONFIG_POWER_DOMAIN not > defined > > dm: core: device: enable power domain in probe > > drivers: regulator: fixed: add off-on-delay-us > > log: include command header file > > i2c-mux: pca954x: support pca9646 i2c switch > > dts: imx8qxp: Add DTS and binding header files > > imx: 8qxp_mek: Add i.MX8QXP MEK board support > > > > Ye Li (8): > > fsl_esdhc: Update usdhc driver to support i.MX8 > > serial: lpuart: Enable RX and TX FIFO > > imx_lpi2c: Update lpi2c driver to support imx8 > > lpi2c: Fix bus stop problem in xfer > > lpi2c: Add bus busy error handling > > net: fec_mxc: Add the init_clk_fec function > > sata: Add i.MX8 SATA support > > mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue > > > > arch/arm/Kconfig | 8 + > > arch/arm/Makefile | 2 +- > > arch/arm/dts/Makefile | 2 + > > arch/arm/dts/fsl-imx8qxp-mek.dts | 416 +++++ > > arch/arm/dts/fsl-imx8qxp.dtsi | 1593 > ++++++++++++++++++++ > > arch/arm/include/asm/arch-imx/cpu.h | 5 + > > arch/arm/include/asm/arch-imx8/clock.h | 36 + > > arch/arm/include/asm/arch-imx8/cpu.h | 26 + > > arch/arm/include/asm/arch-imx8/fsl_mu_hal.h | 54 + > > arch/arm/include/asm/arch-imx8/gpio.h | 22 + > > arch/arm/include/asm/arch-imx8/i2c.h | 34 + > > arch/arm/include/asm/arch-imx8/imx-regs.h | 119 ++ > > arch/arm/include/asm/arch-imx8/imx8-pins.h | 15 + > > arch/arm/include/asm/arch-imx8/imx8qm_pads.h | 295 ++++ > > arch/arm/include/asm/arch-imx8/imx8qxp_pads.h | 200 +++ > > arch/arm/include/asm/arch-imx8/iomux.h | 40 + > > arch/arm/include/asm/arch-imx8/power-domain.h | 15 + > > arch/arm/include/asm/arch-imx8/sci/ipc.h | 67 + > > arch/arm/include/asm/arch-imx8/sci/rpc.h | 131 ++ > > arch/arm/include/asm/arch-imx8/sci/sci.h | 39 + > > arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h | 160 ++ > > arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h | 523 +++++++ > > arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h | 568 +++++++ > > arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h | 686 +++++++++ > > arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h | 759 ++++++++++ > > arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h | 306 ++++ > > arch/arm/include/asm/arch-imx8/sci/types.h | 862 > +++++++++++ > > arch/arm/include/asm/arch-imx8/sys_proto.h | 19 + > > arch/arm/include/asm/global_data.h | 4 + > > arch/arm/include/asm/mach-imx/boot_mode.h | 1 + > > arch/arm/include/asm/mach-imx/sys_proto.h | 3 + > > arch/arm/mach-imx/Makefile | 1 + > > arch/arm/mach-imx/imx8/Kconfig | 26 + > > arch/arm/mach-imx/imx8/Makefile | 13 + > > arch/arm/mach-imx/imx8/clock.c | 361 +++++ > > arch/arm/mach-imx/imx8/cpu.c | 783 > ++++++++++ > > arch/arm/mach-imx/imx8/fsl_mu_hal.c | 28 + > > arch/arm/mach-imx/imx8/iomux.c | 47 + > > arch/arm/mach-imx/imx8/sci/ipc.c | 100 ++ > > arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h | 54 + > > arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c | 76 + > > arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h | 76 + > > arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c | 515 +++++++ > > arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h | 68 + > > arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c | 475 ++++++ > > arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h | 73 + > > arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c | 460 ++++++ > > arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h | 83 + > > arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c | 645 ++++++++ > > arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h | 67 + > > arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c | 365 +++++ > > board/freescale/imx8qxp_mek/Kconfig | 14 + > > board/freescale/imx8qxp_mek/MAINTAINERS | 6 + > > board/freescale/imx8qxp_mek/Makefile | 7 + > > board/freescale/imx8qxp_mek/imx8qxp_mek.c | 159 ++ > > configs/imx8qxp_mek_defconfig | 47 + > > drivers/ata/Kconfig | 6 + > > drivers/ata/Makefile | 1 + > > drivers/ata/ahci.c | 25 + > > drivers/ata/sata_imx.c | 64 + > > drivers/core/device.c | 7 + > > drivers/gpio/mxc_gpio.c | 30 +- > > drivers/i2c/imx_lpi2c.c | 82 +- > > drivers/i2c/muxes/pca954x.c | 9 +- > > drivers/mmc/fsl_esdhc.c | 32 +- > > drivers/net/fec_mxc.c | 9 +- > > drivers/pinctrl/nxp/Kconfig | 18 + > > drivers/pinctrl/nxp/Makefile | 2 + > > drivers/pinctrl/nxp/pinctrl-imx.c | 209 +-- > > drivers/pinctrl/nxp/pinctrl-imx.h | 16 + > > drivers/pinctrl/nxp/pinctrl-imx8.c | 42 + > > drivers/pinctrl/nxp/pinctrl-scu.c | 72 + > > drivers/power/domain/Kconfig | 6 + > > drivers/power/domain/Makefile | 1 + > > drivers/power/domain/imx8-power-domain.c | 315 ++++ > > drivers/power/domain/power-domain-uclass.c | 42 + > > drivers/power/regulator/fixed.c | 6 + > > drivers/serial/serial_lpuart.c | 48 +- > > include/configs/imx8qxp_mek.h | 157 ++ > > include/dt-bindings/clock/imx8qxp-clock.h | 533 +++++++ > > include/dt-bindings/pinctrl/pads-imx8qm.h | 975 > ++++++++++++ > > include/dt-bindings/pinctrl/pads-imx8qxp.h | 770 ++++++++++ > > include/dt-bindings/soc/imx8_pd.h | 197 +++ > > include/dt-bindings/soc/imx_rsrc.h | 560 +++++++ > > include/fsl_lpuart.h | 2 +- > > .../asm/arch-mx7ulp => include}/imx_lpi2c.h | 0 > > include/log.h | 1 + > > include/power-domain.h | 52 + > > 88 files changed, 15691 insertions(+), 157 deletions(-) create mode > > 100644 arch/arm/dts/fsl-imx8qxp-mek.dts create mode 100644 > > arch/arm/dts/fsl-imx8qxp.dtsi create mode 100644 > > arch/arm/include/asm/arch-imx8/clock.h > > create mode 100644 arch/arm/include/asm/arch-imx8/cpu.h > > create mode 100644 arch/arm/include/asm/arch-imx8/fsl_mu_hal.h > > create mode 100644 arch/arm/include/asm/arch-imx8/gpio.h > > create mode 100644 arch/arm/include/asm/arch-imx8/i2c.h > > create mode 100644 arch/arm/include/asm/arch-imx8/imx-regs.h > > create mode 100644 arch/arm/include/asm/arch-imx8/imx8-pins.h > > create mode 100644 arch/arm/include/asm/arch-imx8/imx8qm_pads.h > > create mode 100644 arch/arm/include/asm/arch-imx8/imx8qxp_pads.h > > create mode 100644 arch/arm/include/asm/arch-imx8/iomux.h > > create mode 100644 arch/arm/include/asm/arch-imx8/power-domain.h > > create mode 100755 arch/arm/include/asm/arch-imx8/sci/ipc.h > > create mode 100755 arch/arm/include/asm/arch-imx8/sci/rpc.h > > create mode 100644 arch/arm/include/asm/arch-imx8/sci/sci.h > > create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h > > create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h > > create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h > > create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h > > create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h > > create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h > > create mode 100755 arch/arm/include/asm/arch-imx8/sci/types.h > > create mode 100644 arch/arm/include/asm/arch-imx8/sys_proto.h > > create mode 100644 arch/arm/mach-imx/imx8/Kconfig create mode > 100644 > > arch/arm/mach-imx/imx8/Makefile create mode 100644 > > arch/arm/mach-imx/imx8/clock.c create mode 100644 > > arch/arm/mach-imx/imx8/cpu.c create mode 100644 > > arch/arm/mach-imx/imx8/fsl_mu_hal.c > > create mode 100644 arch/arm/mach-imx/imx8/iomux.c create mode > 100644 > > arch/arm/mach-imx/imx8/sci/ipc.c create mode 100644 > > arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h > > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c > > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h > > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c > > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h > > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c > > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h > > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c > > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h > > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c > > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h > > create mode 100644 arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c > > create mode 100644 board/freescale/imx8qxp_mek/Kconfig > > create mode 100644 board/freescale/imx8qxp_mek/MAINTAINERS > > create mode 100644 board/freescale/imx8qxp_mek/Makefile > > create mode 100644 board/freescale/imx8qxp_mek/imx8qxp_mek.c > > create mode 100644 configs/imx8qxp_mek_defconfig create mode > 100644 > > drivers/ata/sata_imx.c create mode 100644 > > drivers/pinctrl/nxp/pinctrl-imx8.c > > create mode 100644 drivers/pinctrl/nxp/pinctrl-scu.c create mode > > 100644 drivers/power/domain/imx8-power-domain.c > > create mode 100644 include/configs/imx8qxp_mek.h create mode > 100644 > > include/dt-bindings/clock/imx8qxp-clock.h > > create mode 100644 include/dt-bindings/pinctrl/pads-imx8qm.h > > create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h > > create mode 100644 include/dt-bindings/soc/imx8_pd.h create mode > > 100644 include/dt-bindings/soc/imx_rsrc.h > > rename {arch/arm/include/asm/arch-mx7ulp => include}/imx_lpi2c.h > > (100%) > > > > > -- > ================================================================ > ===== > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de > ================================================================ > ===== ^ permalink raw reply [flat|nested] 69+ messages in thread
end of thread, other threads:[~2018-10-18 13:38 UTC | newest] Thread overview: 69+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2018-05-28 12:24 [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 01/41] imx: import SCFW API Peng Fan 2018-06-12 9:41 ` Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 02/41] imx: add Kconfig entry for i.MX8 Peng Fan 2018-06-27 8:19 ` Stefano Babic 2018-07-07 12:46 ` Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 03/41] arm: build mach-imx " Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 04/41] imx8: add IPC communication support between ACore and SCU Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 05/41] arm: global_data: introduce ipc_channel_handle Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 06/41] imx: boot_mode: Add FLEXSPI boot entry Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 07/41] imx8: add imx-regs header file Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 08/41] imx8: pins: include i.MX8QXP pin header when CONFIG_IMX8QXP defined Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 09/41] imx: add i.MX8 cpu type Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 10/41] imx8: add basic cpu support Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 11/41] imx8: add boot device detection Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 12/41] imx8: implement mmc_get_env_dev Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 13/41] imx8: implement imx_get_mac_from_fuse Peng Fan 2018-05-28 12:24 ` [U-Boot] [PATCH 14/41] imx8: implement get_board_serial Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 15/41] imx8: add mmu and dram related functiions Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 16/41] imx8: add bootaux support Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 17/41] imx8: add arch_cpu_init Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 18/41] imx8: add clock driver Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 19/41] imx8: add iomux configuration code Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 20/41] fsl_esdhc: Update usdhc driver to support i.MX8 Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 21/41] serial_lpuart: Update lpuart " Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 22/41] serial: lpuart: Enable RX and TX FIFO Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 23/41] imx_lpi2c: Update lpi2c driver to support imx8 Peng Fan 2018-05-29 3:40 ` Heiko Schocher 2018-05-28 12:25 ` [U-Boot] [PATCH 24/41] imx: lpi2c: fix clock issue when NACK detected Peng Fan 2018-05-29 3:52 ` Heiko Schocher 2018-05-28 12:25 ` [U-Boot] [PATCH 25/41] lpi2c: Fix bus stop problem in xfer Peng Fan 2018-05-29 3:55 ` Heiko Schocher 2018-05-28 12:25 ` [U-Boot] [PATCH 26/41] lpi2c: Add bus busy error handling Peng Fan 2018-05-29 3:59 ` Heiko Schocher 2018-05-28 12:25 ` [U-Boot] [PATCH 27/41] net: fec: do not access reserved register for i.MX8 Peng Fan 2018-06-12 18:26 ` Joe Hershberger 2018-10-18 13:38 ` Anatolij Gustschin 2018-05-28 12:25 ` [U-Boot] [PATCH 28/41] net: fec_mxc: Add the init_clk_fec function Peng Fan 2018-06-12 18:27 ` Joe Hershberger 2018-06-13 1:26 ` Simon Glass 2018-06-15 6:46 ` Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 29/41] sata: Add i.MX8 SATA support Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 30/41] gpio: mxc_gpio: add support for i.MX8 Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 31/41] pinctrl: Add pinctrl driver " Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 32/41] power: Add power domain " Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 33/41] power: Add PD device lookup interface to power domain uclass Peng Fan 2018-05-30 19:18 ` Simon Glass 2018-05-28 12:25 ` [U-Boot] [PATCH 34/41] power-domain: add dummy functions when CONFIG_POWER_DOMAIN not defined Peng Fan 2018-05-30 19:18 ` Simon Glass 2018-05-28 12:25 ` [U-Boot] [PATCH 35/41] dm: core: device: enable power domain in probe Peng Fan 2018-05-30 19:18 ` Simon Glass 2018-07-18 12:56 ` Peng Fan 2018-07-19 1:32 ` Simon Glass 2018-05-28 12:25 ` [U-Boot] [PATCH 36/41] drivers: regulator: fixed: add off-on-delay-us Peng Fan 2018-05-30 19:18 ` Simon Glass 2018-05-28 12:25 ` [U-Boot] [PATCH 37/41] mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue Peng Fan 2018-05-28 22:32 ` Benoît Thébaudeau 2018-05-29 1:45 ` Peng Fan 2018-05-29 20:47 ` Benoît Thébaudeau 2018-05-28 12:25 ` [U-Boot] [PATCH 38/41] log: include command header file Peng Fan 2018-05-30 19:18 ` Simon Glass 2018-05-28 12:25 ` [U-Boot] [PATCH 39/41] i2c-mux: pca954x: support pca9646 i2c switch Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 40/41] dts: imx8qxp: Add DTS and binding header files Peng Fan 2018-05-28 12:25 ` [U-Boot] [PATCH 41/41] imx: 8qxp_mek: Add i.MX8QXP MEK board support Peng Fan 2018-06-12 9:43 ` [U-Boot] [PATCH 00/41] imx: add i.MX8QXP support Peng Fan 2018-06-12 14:07 ` Fabio Estevam 2018-06-15 6:45 ` Peng Fan 2018-06-27 8:13 ` Stefano Babic 2018-07-07 12:55 ` Peng Fan
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