From: Keerthy <j-keerthy@ti.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 3/6] arm: mach-omap2: am33xx: Enable HW Leveling in the rtc+ddr path
Date: Fri, 12 Apr 2019 12:08:17 +0530 [thread overview]
Message-ID: <20190412063820.25924-4-j-keerthy@ti.com> (raw)
In-Reply-To: <20190412063820.25924-1-j-keerthy@ti.com>
From: Brad Griffis <bgriffis@ti.com>
Enable HW leveling in RTC+DDR path. The mandate is to enable
HW leveling bit and then wait for 1 ms before accessing any
register.
Signed-off-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
---
arch/arm/mach-omap2/am33xx/board.c | 30 +++++++++++++++++++++++++++++-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c
index 62158a9592..fe7b8e1e55 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -38,6 +38,14 @@
#include <asm/omap_musb.h>
#include <asm/davinci_rtc.h>
+#define AM43XX_EMIF_BASE 0x4C000000
+#define AM43XX_SDRAM_CONFIG_OFFSET 0x8
+#define AM43XX_SDRAM_TYPE_MASK 0xE0000000
+#define AM43XX_SDRAM_TYPE_SHIFT 29
+#define AM43XX_SDRAM_TYPE_DDR3 3
+#define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC
+#define AM43XX_RDWRLVLFULL_START 0x80000000
+
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
@@ -435,7 +443,7 @@ static void rtc_only(void)
struct prm_device_inst *prm_device =
(struct prm_device_inst *)PRM_DEVICE_INST;
- u32 scratch1;
+ u32 scratch1, sdrc;
void (*resume_func)(void);
scratch1 = readl(&rtc->scratch1);
@@ -476,6 +484,26 @@ static void rtc_only(void)
/* Disable EMIF_DEVOFF for normal operation and to exit self-refresh */
writel(0, &prm_device->emif_ctrl);
+ /* Check EMIF4D_SDRAM_CONFIG[31:29] SDRAM_TYPE */
+ /* Only perform leveling if SDRAM_TYPE = 3 (DDR3) */
+ sdrc = readl(AM43XX_EMIF_BASE + AM43XX_SDRAM_CONFIG_OFFSET);
+
+ sdrc &= AM43XX_SDRAM_TYPE_MASK;
+ sdrc >>= AM43XX_SDRAM_TYPE_SHIFT;
+
+ if (sdrc == AM43XX_SDRAM_TYPE_DDR3) {
+ writel(AM43XX_RDWRLVLFULL_START,
+ AM43XX_EMIF_BASE +
+ AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
+ mdelay(1);
+
+am43xx_wait:
+ sdrc = readl(AM43XX_EMIF_BASE +
+ AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
+ if (sdrc == AM43XX_RDWRLVLFULL_START)
+ goto am43xx_wait;
+ }
+
resume_func = (void *)readl(&rtc->scratch0);
if (resume_func)
resume_func();
--
2.17.1
next prev parent reply other threads:[~2019-04-12 6:38 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-12 6:38 [U-Boot] [PATCH 0/6] board: ti: am43xx: Enable hardware leveling Keerthy
2019-04-12 6:38 ` [U-Boot] [PATCH 1/6] arm: mach-omap2: am33xx: ddr: programming of EXT_PHY_CTRL1 and EXT_PHY_CTRL1_SHADOW Keerthy
2019-04-12 6:38 ` [U-Boot] [PATCH 2/6] arm: mach-omap2: am33xx: ddr: Add 1ms delay to avoid L3 error Keerthy
2019-04-12 6:38 ` Keerthy [this message]
2019-04-12 6:38 ` [U-Boot] [PATCH 4/6] arm: mach-omap2: am33xx: Disable EMIF_DEVOFF immediately before hw leveling Keerthy
2019-04-26 11:16 ` [U-Boot] [U-Boot, " Tom Rini
2019-04-26 11:53 ` Lokesh Vutla
2019-04-26 12:55 ` Tom Rini
2019-04-26 16:44 ` Keerthy
2019-04-26 16:46 ` Tom Rini
2019-04-26 16:50 ` Keerthy
2019-04-26 16:39 ` Keerthy
2019-04-26 14:11 ` Keerthy
2019-04-12 6:38 ` [U-Boot] [PATCH 5/6] arm: mach-omap2: am33xx: ddr: update value for ext_phy_ctrl_36 Keerthy
2019-04-12 6:38 ` [U-Boot] [PATCH 6/6] board: ti: am43xx: Enable hardware leveling Keerthy
2019-04-13 13:02 ` [U-Boot] [PATCH 0/6] " Tom Rini
2019-04-15 0:49 ` keerthy
2019-04-15 1:05 ` Tom Rini
2019-04-15 2:13 ` keerthy
2019-04-15 8:56 ` Keerthy
2019-04-15 9:22 ` Tero Kristo
2019-04-15 11:28 ` Tom Rini
2019-04-15 12:10 ` Keerthy
2019-04-15 12:14 ` Tom Rini
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