* [U-Boot] [PATCH 1/2] ARM: imx6: DHCOM i.MX6 PDK: use Kconfig for inclusion of DDR calibration
@ 2019-04-12 11:29 Ludwig Zenz
2019-04-12 11:29 ` [U-Boot] [PATCH 2/2] ARM: imx6: update 1GB DDR3 calibration for DHCOM i.MX6qd PDK Ludwig Zenz
2019-04-12 13:26 ` [U-Boot] [PATCH 1/2] ARM: imx6: DHCOM i.MX6 PDK: use Kconfig for inclusion of DDR calibration Marek Vasut
0 siblings, 2 replies; 4+ messages in thread
From: Ludwig Zenz @ 2019-04-12 11:29 UTC (permalink / raw)
To: u-boot
The four x16 DDR3 are wired in T-topology. From NXP AN4467:
'Although not required, T-Topologies may also benefit from performing
Write Leveling as there are package delays on both the processor and DDR
devices that can be de-skewed by performing Write Leveling. Therefore,
Freescale recommends determining Write Leveling calibration parameters
for all boards, regardless of topology used.'
That is why write level calibration is also done.
Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.com>
---
board/dhelectronics/dh_imx6/dh_imx6_spl.c | 32 +++++++++++++++++++++++++------
1 file changed, 26 insertions(+), 6 deletions(-)
diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
index 04e9eab272a..bbd2dc26828 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
@@ -482,6 +482,29 @@ static void setup_iomux_usb(void)
SETUP_IOMUX_PADS(usb_pads);
}
+/* Perform DDR DRAM calibration */
+static int spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
+{
+ int ret = 0;
+
+#ifdef CONFIG_MX6_DDRCAL
+ udelay(100);
+ ret = mmdc_do_write_level_calibration(sysinfo);
+ if (ret) {
+ printf("DDR3: Write level calibration error [%d]\n", ret);
+ return ret;
+ }
+
+ ret = mmdc_do_dqs_calibration(sysinfo);
+ if (ret) {
+ printf("DDR3: DQS calibration error [%d]\n", ret);
+ return ret;
+ }
+#endif /* CONFIG_MX6_DDRCAL */
+
+ return ret;
+}
+
/* DRAM */
static void dhcom_spl_dram_init(void)
@@ -509,8 +532,7 @@ static void dhcom_spl_dram_init(void)
}
/* Perform DDR DRAM calibration */
- udelay(100);
- mmdc_do_dqs_calibration(&dhcom_ddr_64bit);
+ spl_dram_perform_cal(&dhcom_ddr_64bit);
} else if (is_cpu_type(MXC_CPU_MX6DL)) {
mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs,
@@ -528,8 +550,7 @@ static void dhcom_spl_dram_init(void)
}
/* Perform DDR DRAM calibration */
- udelay(100);
- mmdc_do_dqs_calibration(&dhcom_ddr_64bit);
+ spl_dram_perform_cal(&dhcom_ddr_64bit);
} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs,
@@ -552,8 +573,7 @@ static void dhcom_spl_dram_init(void)
}
/* Perform DDR DRAM calibration */
- udelay(100);
- mmdc_do_dqs_calibration(&dhcom_ddr_32bit);
+ spl_dram_perform_cal(&dhcom_ddr_32bit);
}
}
--
2.11.0
^ permalink raw reply related [flat|nested] 4+ messages in thread* [U-Boot] [PATCH 2/2] ARM: imx6: update 1GB DDR3 calibration for DHCOM i.MX6qd PDK
2019-04-12 11:29 [U-Boot] [PATCH 1/2] ARM: imx6: DHCOM i.MX6 PDK: use Kconfig for inclusion of DDR calibration Ludwig Zenz
@ 2019-04-12 11:29 ` Ludwig Zenz
2019-04-12 13:26 ` Marek Vasut
2019-04-12 13:26 ` [U-Boot] [PATCH 1/2] ARM: imx6: DHCOM i.MX6 PDK: use Kconfig for inclusion of DDR calibration Marek Vasut
1 sibling, 1 reply; 4+ messages in thread
From: Ludwig Zenz @ 2019-04-12 11:29 UTC (permalink / raw)
To: u-boot
Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.com>
---
board/dhelectronics/dh_imx6/dh_imx6_spl.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
index bbd2dc26828..2939389de39 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
@@ -161,18 +161,18 @@ static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x4g_800 = {
};
static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_1066 = {
- .p0_mpwldectrl0 = 0x0011000E,
- .p0_mpwldectrl1 = 0x000E001B,
- .p1_mpwldectrl0 = 0x00190015,
- .p1_mpwldectrl1 = 0x00070018,
- .p0_mpdgctrl0 = 0x42720306,
- .p0_mpdgctrl1 = 0x026F0266,
- .p1_mpdgctrl0 = 0x4273030A,
- .p1_mpdgctrl1 = 0x02740240,
- .p0_mprddlctl = 0x45393B3E,
- .p1_mprddlctl = 0x403A3747,
- .p0_mpwrdlctl = 0x40434541,
- .p1_mpwrdlctl = 0x473E4A3B,
+ .p0_mpwldectrl0 = 0x001a001a,
+ .p0_mpwldectrl1 = 0x00260015,
+ .p0_mpdgctrl0 = 0x030c0320,
+ .p0_mpdgctrl1 = 0x03100304,
+ .p0_mprddlctl = 0x432e3538,
+ .p0_mpwrdlctl = 0x363f423d,
+ .p1_mpwldectrl0 = 0x0006001e,
+ .p1_mpwldectrl1 = 0x00050015,
+ .p1_mpdgctrl0 = 0x031c0324,
+ .p1_mpdgctrl1 = 0x030c0258,
+ .p1_mprddlctl = 0x3834313f,
+ .p1_mpwrdlctl = 0x47374a42,
};
static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_800 = {
--
2.11.0
^ permalink raw reply related [flat|nested] 4+ messages in thread* [U-Boot] [PATCH 2/2] ARM: imx6: update 1GB DDR3 calibration for DHCOM i.MX6qd PDK
2019-04-12 11:29 ` [U-Boot] [PATCH 2/2] ARM: imx6: update 1GB DDR3 calibration for DHCOM i.MX6qd PDK Ludwig Zenz
@ 2019-04-12 13:26 ` Marek Vasut
0 siblings, 0 replies; 4+ messages in thread
From: Marek Vasut @ 2019-04-12 13:26 UTC (permalink / raw)
To: u-boot
On 4/12/19 1:29 PM, Ludwig Zenz wrote:
Commit message is missing , please fix.
> Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.com>
> ---
> board/dhelectronics/dh_imx6/dh_imx6_spl.c | 24 ++++++++++++------------
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
> index bbd2dc26828..2939389de39 100644
> --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
> +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
> @@ -161,18 +161,18 @@ static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x4g_800 = {
> };
>
> static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_1066 = {
> - .p0_mpwldectrl0 = 0x0011000E,
> - .p0_mpwldectrl1 = 0x000E001B,
> - .p1_mpwldectrl0 = 0x00190015,
> - .p1_mpwldectrl1 = 0x00070018,
> - .p0_mpdgctrl0 = 0x42720306,
> - .p0_mpdgctrl1 = 0x026F0266,
> - .p1_mpdgctrl0 = 0x4273030A,
> - .p1_mpdgctrl1 = 0x02740240,
> - .p0_mprddlctl = 0x45393B3E,
> - .p1_mprddlctl = 0x403A3747,
> - .p0_mpwrdlctl = 0x40434541,
> - .p1_mpwrdlctl = 0x473E4A3B,
> + .p0_mpwldectrl0 = 0x001a001a,
> + .p0_mpwldectrl1 = 0x00260015,
> + .p0_mpdgctrl0 = 0x030c0320,
> + .p0_mpdgctrl1 = 0x03100304,
> + .p0_mprddlctl = 0x432e3538,
> + .p0_mpwrdlctl = 0x363f423d,
> + .p1_mpwldectrl0 = 0x0006001e,
> + .p1_mpwldectrl1 = 0x00050015,
> + .p1_mpdgctrl0 = 0x031c0324,
> + .p1_mpdgctrl1 = 0x030c0258,
> + .p1_mprddlctl = 0x3834313f,
> + .p1_mpwrdlctl = 0x47374a42,
> };
>
> static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_800 = {
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH 1/2] ARM: imx6: DHCOM i.MX6 PDK: use Kconfig for inclusion of DDR calibration
2019-04-12 11:29 [U-Boot] [PATCH 1/2] ARM: imx6: DHCOM i.MX6 PDK: use Kconfig for inclusion of DDR calibration Ludwig Zenz
2019-04-12 11:29 ` [U-Boot] [PATCH 2/2] ARM: imx6: update 1GB DDR3 calibration for DHCOM i.MX6qd PDK Ludwig Zenz
@ 2019-04-12 13:26 ` Marek Vasut
1 sibling, 0 replies; 4+ messages in thread
From: Marek Vasut @ 2019-04-12 13:26 UTC (permalink / raw)
To: u-boot
On 4/12/19 1:29 PM, Ludwig Zenz wrote:
> The four x16 DDR3 are wired in T-topology. From NXP AN4467:
> 'Although not required, T-Topologies may also benefit from performing
> Write Leveling as there are package delays on both the processor and DDR
> devices that can be de-skewed by performing Write Leveling. Therefore,
> Freescale recommends determining Write Leveling calibration parameters
> for all boards, regardless of topology used.'
> That is why write level calibration is also done.
>
> Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
> ---
> board/dhelectronics/dh_imx6/dh_imx6_spl.c | 32 +++++++++++++++++++++++++------
> 1 file changed, 26 insertions(+), 6 deletions(-)
>
> diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
> index 04e9eab272a..bbd2dc26828 100644
> --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
> +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
> @@ -482,6 +482,29 @@ static void setup_iomux_usb(void)
> SETUP_IOMUX_PADS(usb_pads);
> }
>
> +/* Perform DDR DRAM calibration */
> +static int spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
> +{
> + int ret = 0;
> +
> +#ifdef CONFIG_MX6_DDRCAL
> + udelay(100);
> + ret = mmdc_do_write_level_calibration(sysinfo);
> + if (ret) {
> + printf("DDR3: Write level calibration error [%d]\n", ret);
> + return ret;
> + }
> +
> + ret = mmdc_do_dqs_calibration(sysinfo);
> + if (ret) {
> + printf("DDR3: DQS calibration error [%d]\n", ret);
> + return ret;
> + }
> +#endif /* CONFIG_MX6_DDRCAL */
> +
> + return ret;
> +}
> +
>
> /* DRAM */
> static void dhcom_spl_dram_init(void)
> @@ -509,8 +532,7 @@ static void dhcom_spl_dram_init(void)
> }
>
> /* Perform DDR DRAM calibration */
> - udelay(100);
> - mmdc_do_dqs_calibration(&dhcom_ddr_64bit);
> + spl_dram_perform_cal(&dhcom_ddr_64bit);
>
> } else if (is_cpu_type(MXC_CPU_MX6DL)) {
> mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs,
> @@ -528,8 +550,7 @@ static void dhcom_spl_dram_init(void)
> }
>
> /* Perform DDR DRAM calibration */
> - udelay(100);
> - mmdc_do_dqs_calibration(&dhcom_ddr_64bit);
> + spl_dram_perform_cal(&dhcom_ddr_64bit);
>
> } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
> mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs,
> @@ -552,8 +573,7 @@ static void dhcom_spl_dram_init(void)
> }
>
> /* Perform DDR DRAM calibration */
> - udelay(100);
> - mmdc_do_dqs_calibration(&dhcom_ddr_32bit);
> + spl_dram_perform_cal(&dhcom_ddr_32bit);
> }
> }
>
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 4+ messages in thread
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2019-04-12 11:29 [U-Boot] [PATCH 1/2] ARM: imx6: DHCOM i.MX6 PDK: use Kconfig for inclusion of DDR calibration Ludwig Zenz
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2019-04-12 13:26 ` Marek Vasut
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