From: Andre Przywara <andre.przywara@arm.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 2/7] sunxi: H6: DRAM: follow recommended PHY init algorithm
Date: Tue, 2 Jul 2019 10:51:43 +0100 [thread overview]
Message-ID: <20190702095148.191065-3-andre.przywara@arm.com> (raw)
In-Reply-To: <20190702095148.191065-1-andre.przywara@arm.com>
The DRAM controller manual suggests to first program the PHY
initialisation parameters to the PHY_PIR register, and then set bit 0 to
trigger the initialisation. This is also used in boot0.
Follow this recommendation by setting bit 0 in a separate step.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/mach-sunxi/dram_sun50i_h6.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c
index e2f141eb9b..7a8b724f08 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c
@@ -75,12 +75,14 @@ static void mctl_core_init(struct dram_para *para)
mctl_channel_init(para);
}
+/* PHY initialisation */
static void mctl_phy_pir_init(u32 val)
{
struct sunxi_mctl_phy_reg * const mctl_phy =
(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
- writel(val | BIT(0), &mctl_phy->pir);
+ writel(val, &mctl_phy->pir);
+ writel(val | BIT(0), &mctl_phy->pir); /* Start initialisation. */
mctl_await_completion(&mctl_phy->pgsr[0], BIT(0), BIT(0));
}
--
2.17.1
next prev parent reply other threads:[~2019-07-02 9:51 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-02 9:51 [U-Boot] [PATCH v2 0/7] sunxi: Add H6 DDR3 DRAM support Andre Przywara
2019-07-02 9:51 ` [U-Boot] [PATCH v2 1/7] sunxi: H6: DRAM: avoid memcpy() on MMIO registers Andre Przywara
2019-07-02 9:51 ` Andre Przywara [this message]
2019-07-02 9:51 ` [U-Boot] [PATCH v2 3/7] sunxi: H6: move LPDDR3 timing definition into separate file Andre Przywara
2019-07-02 10:25 ` [U-Boot] [linux-sunxi] " Icenowy Zheng
2019-07-02 9:51 ` [U-Boot] [PATCH v2 4/7] sunxi: H6: Add DDR3 support to DRAM controller driver Andre Przywara
2019-07-02 9:51 ` [U-Boot] [PATCH v2 5/7] sunxi: H6: Add DDR3-1333 timings Andre Przywara
2019-07-02 9:51 ` [U-Boot] [PATCH v2 6/7] sunxi: H6: Add DDR3 DRAM delay values Andre Przywara
2019-07-02 9:51 ` [U-Boot] [PATCH v2 7/7] sunxi: H6: Add basic Eachlink H6 Mini support Andre Przywara
2019-07-13 9:55 ` [U-Boot] [PATCH v2 0/7] sunxi: Add H6 DDR3 DRAM support Jernej Škrabec
2019-07-15 1:29 ` André Przywara
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