From: Andre Przywara <andre.przywara@arm.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 6/7] sunxi: H6: Add DDR3 DRAM delay values
Date: Tue, 2 Jul 2019 10:51:47 +0100 [thread overview]
Message-ID: <20190702095148.191065-7-andre.przywara@arm.com> (raw)
In-Reply-To: <20190702095148.191065-1-andre.przywara@arm.com>
From: Jernej Skrabec <jernej.skrabec@siol.net>
Add some basic line delay values to be used with DDR3 DRAM chips on
some H6 TV boxes.
Taken from a register dump after boot0 initialised the DRAM.
Put them as the default delay values for DDR3 DRAM until we know better.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/mach-sunxi/dram_sun50i_h6.c | 23 +++++++++++++++++------
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c
index 17649ffbf9..2a8275da3a 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c
@@ -594,17 +594,28 @@ unsigned long mctl_calc_size(struct dram_para *para)
return (1ULL << (para->cols + para->rows + 3)) * 4 * para->ranks;
}
-#define SUN50I_H6_DX_WRITE_DELAYS \
+#define SUN50I_H6_LPDDR3_DX_WRITE_DELAYS \
{{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, 0 }, \
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
-#define SUN50I_H6_DX_READ_DELAYS \
+#define SUN50I_H6_LPDDR3_DX_READ_DELAYS \
{{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }}
+#define SUN50I_H6_DDR3_DX_WRITE_DELAYS \
+ {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
+#define SUN50I_H6_DDR3_DX_READ_DELAYS \
+ {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
+ { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
+
unsigned long sunxi_dram_init(void)
{
struct sunxi_mctl_com_reg * const mctl_com =
@@ -616,12 +627,12 @@ unsigned long sunxi_dram_init(void)
.rows = 14,
#ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
.type = SUNXI_DRAM_TYPE_LPDDR3,
- .dx_read_delays = SUN50I_H6_DX_READ_DELAYS,
- .dx_write_delays = SUN50I_H6_DX_WRITE_DELAYS,
+ .dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS,
+ .dx_write_delays = SUN50I_H6_LPDDR3_DX_WRITE_DELAYS,
#elif defined(CONFIG_SUNXI_DRAM_H6_DDR3_1333)
.type = SUNXI_DRAM_TYPE_DDR3,
- .dx_read_delays = SUN50I_H6_DX_READ_DELAYS,
- .dx_write_delays = SUN50I_H6_DX_WRITE_DELAYS,
+ .dx_read_delays = SUN50I_H6_DDR3_DX_READ_DELAYS,
+ .dx_write_delays = SUN50I_H6_DDR3_DX_WRITE_DELAYS,
#endif
};
--
2.17.1
next prev parent reply other threads:[~2019-07-02 9:51 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-02 9:51 [U-Boot] [PATCH v2 0/7] sunxi: Add H6 DDR3 DRAM support Andre Przywara
2019-07-02 9:51 ` [U-Boot] [PATCH v2 1/7] sunxi: H6: DRAM: avoid memcpy() on MMIO registers Andre Przywara
2019-07-02 9:51 ` [U-Boot] [PATCH v2 2/7] sunxi: H6: DRAM: follow recommended PHY init algorithm Andre Przywara
2019-07-02 9:51 ` [U-Boot] [PATCH v2 3/7] sunxi: H6: move LPDDR3 timing definition into separate file Andre Przywara
2019-07-02 10:25 ` [U-Boot] [linux-sunxi] " Icenowy Zheng
2019-07-02 9:51 ` [U-Boot] [PATCH v2 4/7] sunxi: H6: Add DDR3 support to DRAM controller driver Andre Przywara
2019-07-02 9:51 ` [U-Boot] [PATCH v2 5/7] sunxi: H6: Add DDR3-1333 timings Andre Przywara
2019-07-02 9:51 ` Andre Przywara [this message]
2019-07-02 9:51 ` [U-Boot] [PATCH v2 7/7] sunxi: H6: Add basic Eachlink H6 Mini support Andre Przywara
2019-07-13 9:55 ` [U-Boot] [PATCH v2 0/7] sunxi: Add H6 DDR3 DRAM support Jernej Škrabec
2019-07-15 1:29 ` André Przywara
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