* [U-Boot] [PATCH v2 4/8] pico-imx6: Add initial support
2019-09-20 19:47 [U-Boot] [PATCH v2 1/8] configs: Sync all baseboard specific pico-imx7d Otavio Salvador
2019-09-20 19:47 ` [U-Boot] [PATCH v2 2/8] mx53loco: Fix U-Boot corruption after saving the environment Otavio Salvador
2019-09-20 19:47 ` [U-Boot] [PATCH v2 3/8] mx6: clock: Allow enable_ipu_clock() to be built for SPL code Otavio Salvador
@ 2019-09-20 19:47 ` Otavio Salvador
2019-09-20 19:47 ` [U-Boot] [PATCH v2 5/8] pico-imx6: Fix bootmenu handling Otavio Salvador
` (3 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Otavio Salvador @ 2019-09-20 19:47 UTC (permalink / raw)
To: u-boot
From: Fabio Estevam <festevam@gmail.com>
Add the initial support for the pico-imx6 variants.
DDR initialization is based on the TechNexion's U-Boot code.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/imx6dl-pico.dts | 17 +
arch/arm/dts/imx6q-pico.dts | 17 +
arch/arm/dts/imx6qdl-pico.dtsi | 424 +++++++++++++++++++++++++
arch/arm/mach-imx/mx6/Kconfig | 11 +
board/technexion/pico-imx6/Kconfig | 15 +
board/technexion/pico-imx6/MAINTAINERS | 9 +
board/technexion/pico-imx6/Makefile | 5 +
board/technexion/pico-imx6/README | 73 +++++
board/technexion/pico-imx6/pico-imx6.c | 78 +++++
board/technexion/pico-imx6/spl.c | 303 ++++++++++++++++++
configs/pico-imx6_defconfig | 71 +++++
include/configs/pico-imx6.h | 130 ++++++++
13 files changed, 1155 insertions(+)
create mode 100644 arch/arm/dts/imx6dl-pico.dts
create mode 100644 arch/arm/dts/imx6q-pico.dts
create mode 100644 arch/arm/dts/imx6qdl-pico.dtsi
create mode 100644 board/technexion/pico-imx6/Kconfig
create mode 100644 board/technexion/pico-imx6/MAINTAINERS
create mode 100644 board/technexion/pico-imx6/Makefile
create mode 100644 board/technexion/pico-imx6/README
create mode 100644 board/technexion/pico-imx6/pico-imx6.c
create mode 100644 board/technexion/pico-imx6/spl.c
create mode 100644 configs/pico-imx6_defconfig
create mode 100644 include/configs/pico-imx6.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d098966380..ae644037ee 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -559,6 +559,7 @@ dtb-y += \
imx6dl-icore-rqs.dtb \
imx6dl-mamoj.dtb \
imx6dl-nitrogen6x.dtb \
+ imx6dl-pico.dtb \
imx6dl-sabreauto.dtb \
imx6dl-sabresd.dtb \
imx6dl-wandboard-revb1.dtb \
@@ -577,6 +578,7 @@ dtb-y += \
imx6q-logicpd.dtb \
imx6q-nitrogen6x.dtb \
imx6q-novena.dtb \
+ imx6q-pico.dtb \
imx6q-sabreauto.dtb \
imx6q-sabrelite.dtb \
imx6q-sabresd.dtb \
diff --git a/arch/arm/dts/imx6dl-pico.dts b/arch/arm/dts/imx6dl-pico.dts
new file mode 100644
index 0000000000..43763c1faa
--- /dev/null
+++ b/arch/arm/dts/imx6dl-pico.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright 2018 Technexion Ltd.
+//
+// Author: Wig Cheng <wig.cheng@technexion.com>
+// Richard Hu <richard.hu@technexion.com>
+// Tapani Utriainen <tapani@technexion.com>
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-pico.dtsi"
+
+/ {
+ model = "TechNexion PICO-IMX6 DualLite/Solo";
+ compatible = "technexion,imx6dl-pico", "fsl,imx6dl";
+};
diff --git a/arch/arm/dts/imx6q-pico.dts b/arch/arm/dts/imx6q-pico.dts
new file mode 100644
index 0000000000..bfc6f9c744
--- /dev/null
+++ b/arch/arm/dts/imx6q-pico.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright 2018 Technexion Ltd.
+//
+// Author: Wig Cheng <wig.cheng@technexion.com>
+// Richard Hu <richard.hu@technexion.com>
+// Tapani Utriainen <tapani@technexion.com>
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-pico.dtsi"
+
+/ {
+ model = "TechNexion PICO-IMX6 Quad";
+ compatible = "technexion,imx6q-pico", "fsl,imx6q";
+};
diff --git a/arch/arm/dts/imx6qdl-pico.dtsi b/arch/arm/dts/imx6qdl-pico.dtsi
new file mode 100644
index 0000000000..50379d04b7
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-pico.dtsi
@@ -0,0 +1,424 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright 2018 Technexion Ltd.
+//
+// Author: Wig Cheng <wig.cheng@technexion.com>
+// Richard Hu <richard.hu@technexion.com>
+// Tapani Utriainen <tapani@technexion.com>
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ aliases {
+ mmc0 = &usdhc3;
+ usb0 = &usbotg;
+ };
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ reg_2p5v: regulator-2p5v {
+ compatible = "regulator-fixed";
+ regulator-name = "2P5V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg_vbus>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "okay";
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ cs-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii-id";
+ phy-reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c2>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie_reset>;
+ reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+ status = "okay";
+};
+
+&ssi1 {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 { /* Bluetooth module */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <®_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <8>;
+ cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&usdhc2 { /* Wifi/BT */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <4>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ bus-width = <8>;
+ no-1-8-v;
+ non-removable;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x4001b0b5 /* PICO_P24 */
+ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x4001b0b5 /* PICO_P25 */
+ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x4001b0b5 /* PICO_P26 */
+ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b5 /* PICO_P28 */
+ MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b0b5 /* PICO_P30 */
+ MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b0b5 /* PICO_P32 */
+ MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x4001b0b5 /* PICO_P34 */
+ MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x4001b0b5 /* PICO_P42 */
+ MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x4001b0b5 /* PICO_P44 */
+ MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x4001b0b5 /* PICO_P48 */
+ >;
+ };
+
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
+ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
+ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
+ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x000f0b0
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1b0b1
+ MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x1b0b1
+ MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x1b0b1
+ MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000f0b0
+ MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x000f0b0
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1f0b1
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
+ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_pcie_reset: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x130b0
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
+ MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+ >;
+ };
+
+ pinctrl_usbotg_vbus: usbotgvbusgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x17071
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ >;
+ };
+};
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 36e1c98fb5..01f0121beb 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -422,6 +422,16 @@ config TARGET_OT1200
select SUPPORT_SPL
imply CMD_SATA
+config TARGET_PICO_IMX6
+ bool "PICO-IMX6"
+ select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
+ select DM
+ select DM_THERMAL
+ select MX6QDL
+ select SUPPORT_SPL
+ imply CMD_DM
+
config TARGET_PICO_IMX6UL
bool "PICO-IMX6UL-EMMC"
select MX6UL
@@ -609,6 +619,7 @@ source "board/logicpd/imx6/Kconfig"
source "board/seco/Kconfig"
source "board/sks-kinkel/sksimx6/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig"
+source "board/technexion/pico-imx6/Kconfig"
source "board/technexion/pico-imx6ul/Kconfig"
source "board/tbs/tbs2910/Kconfig"
source "board/tqc/tqma6/Kconfig"
diff --git a/board/technexion/pico-imx6/Kconfig b/board/technexion/pico-imx6/Kconfig
new file mode 100644
index 0000000000..4af18e53bc
--- /dev/null
+++ b/board/technexion/pico-imx6/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PICO_IMX6
+
+config SYS_BOARD
+ default "pico-imx6"
+
+config SYS_VENDOR
+ default "technexion"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "pico-imx6"
+
+endif
diff --git a/board/technexion/pico-imx6/MAINTAINERS b/board/technexion/pico-imx6/MAINTAINERS
new file mode 100644
index 0000000000..dd6fb96e44
--- /dev/null
+++ b/board/technexion/pico-imx6/MAINTAINERS
@@ -0,0 +1,9 @@
+TECHNEXION PICO-IMX6 BOARD
+M: Fabio Estevam <festevam@gmail.com>
+S: Maintained
+F: arch/arm/dts/imx6qdl-pico.dtsi
+F: arch/arm/dts/imx6q-pico.dts
+F: arch/arm/dts/imx6dl-pico.dts
+F: board/technexion/pico-imx6/
+F: include/configs/pico-imx6.h
+F: configs/pico-imx6_defconfig
diff --git a/board/technexion/pico-imx6/Makefile b/board/technexion/pico-imx6/Makefile
new file mode 100644
index 0000000000..ddb1604f1d
--- /dev/null
+++ b/board/technexion/pico-imx6/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2013 Freescale Semiconductor, Inc.
+
+obj-y := pico-imx6.o spl.o
diff --git a/board/technexion/pico-imx6/README b/board/technexion/pico-imx6/README
new file mode 100644
index 0000000000..f1e84bfe82
--- /dev/null
+++ b/board/technexion/pico-imx6/README
@@ -0,0 +1,73 @@
+How to Update U-Boot on pico-imx6q/dl boards
+--------------------------------------------
+
+Required software on the host PC:
+
+- UUU: https://github.com/NXPmicro/mfgtools
+
+Build U-Boot for pico:
+
+$ make mrproper
+$ make pico-imx6_defconfig
+$ make
+
+This generates the SPL and u-boot-dtb.img binaries.
+
+1. Loading U-Boot via USB Serial Download Protocol
+
+Note: This method is convenient for development purposes.
+If the eMMC has already a U-Boot flashed then the user can
+go to step 2 below in order to update U-Boot.
+
+Put pico board in USB download mode (Refer to the following link for details:
+https://www.technexion.com/support/knowledgebase/boot-configuration-settings-for-pico-baseboards/).
+
+Connect a USB to serial adapter between the host PC and pico.
+
+Connect a USB cable between the OTG pico port and the host PC.
+
+Open a terminal program such as minicom.
+
+Copy SPL and u-boot-dtb.img to the uuu folder.
+
+Load the U-Boot via USB:
+
+$ sudo ./uuu -v uuu_script
+
+where uuu_script contains the following:
+
+SDP: boot -f SPL
+SDPU: write -f u-boot-dtb.img -addr 0x10000000
+SDPU: jump -addr 0x10000000
+
+Then U-Boot starts and its messages appear in the console program.
+
+Use the default environment variables:
+
+=> env default -f -a
+=> saveenv
+
+2. Flashing U-Boot into the eMMC
+
+The default U-Boot environment expects the use of eMMC user
+partition. To ensure we are using the proper eMMC partition for boot,
+please run:
+
+=> mmc partconf 0 0 0 0
+
+Next, run the DFU agent so we can flash the new images using dfu-util
+tool:
+
+=> dfu 0 mmc 0
+
+Flash SPL and u-boot-dtb.img into the eMMC running the following commands on a PC:
+
+$ sudo dfu-util -D SPL -a spl
+
+$ sudo dfu-util -D u-boot-dtb.img -a u-boot
+
+Remove power from the pico board.
+
+Put pico board into normal boot mode.
+
+Power up the board and the new updated U-Boot should boot from eMMC.
diff --git a/board/technexion/pico-imx6/pico-imx6.c b/board/technexion/pico-imx6/pico-imx6.c
new file mode 100644
index 0000000000..717f20d9d7
--- /dev/null
+++ b/board/technexion/pico-imx6/pico-imx6.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2014 O.S. Systems Software LTDA.
+ *
+ * Author: Fabio Estevam <festevam@gmail.com>
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static void setup_iomux_uart(void)
+{
+ SETUP_IOMUX_PADS(uart1_pads);
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int overwrite_console(void)
+{
+ return 1;
+}
+
+int board_late_init(void)
+{
+ if (is_mx6dq())
+ env_set("board_rev", "MX6Q");
+ else
+ env_set("board_rev", "MX6DL");
+
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: PICO-IMX6\n");
+
+ return 0;
+}
diff --git a/board/technexion/pico-imx6/spl.c b/board/technexion/pico-imx6/spl.c
new file mode 100644
index 0000000000..5bf87023ac
--- /dev/null
+++ b/board/technexion/pico-imx6/spl.c
@@ -0,0 +1,303 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Technexion Ltd.
+ *
+ * Author: Richard Hu <richard.hu@technexion.com>
+ * Fabio Estevam <festevam@gmail.com>
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/video.h>
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <spl.h>
+
+#if defined(CONFIG_SPL_BUILD)
+#include <asm/arch/mx6-ddr.h>
+
+#define IMX6DQ_DRIVE_STRENGTH 0x30
+#define IMX6SDL_DRIVE_STRENGTH 0x28
+
+/* configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
+ .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_cas = IMX6DQ_DRIVE_STRENGTH,
+ .dram_ras = IMX6DQ_DRIVE_STRENGTH,
+ .dram_reset = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
+ .grp_ddr_type = 0x000c0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_addds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+ .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_cas = IMX6SDL_DRIVE_STRENGTH,
+ .dram_ras = IMX6SDL_DRIVE_STRENGTH,
+ .dram_reset = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+ .grp_ddr_type = 0x000c0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_addds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* H5T04G63AFR-PB for i.mx6Solo/DL operating DDR at 400MHz */
+static struct mx6_ddr3_cfg h5t04g63afr = {
+ .mem_speed = 800,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 15,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1500,
+ .trcmin = 5250,
+ .trasmin = 3750,
+};
+
+/* H5TQ2G63FFR-H9 for i.mx6Solo/DL operating DDR at 400MHz */
+static struct mx6_ddr3_cfg h5tq2g63ffr = {
+ .mem_speed = 800,
+ .density = 2,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1500,
+ .trcmin = 5250,
+ .trasmin = 3750,
+};
+
+static struct mx6_mmdc_calibration mx6q_1g_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x00000000,
+ .p0_mpwldectrl1 = 0x00000000,
+ .p1_mpwldectrl0 = 0x00000000,
+ .p1_mpwldectrl1 = 0x00000000,
+ .p0_mpdgctrl0 = 0x032C0340,
+ .p0_mpdgctrl1 = 0x03300324,
+ .p1_mpdgctrl0 = 0x032C0338,
+ .p1_mpdgctrl1 = 0x03300274,
+ .p0_mprddlctl = 0x423A383E,
+ .p1_mprddlctl = 0x3638323E,
+ .p0_mpwrdlctl = 0x363C4640,
+ .p1_mpwrdlctl = 0x4034423C,
+};
+
+/* DDR 32bit */
+static struct mx6_ddr_sysinfo mem_s = {
+ .dsize = 1,
+ .cs1_mirror = 0,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32,
+ .ncs = 1,
+ .bi_on = 1,
+ .rtt_nom = 1,
+ .rtt_wr = 0,
+ .ralat = 5,
+ .walat = 0,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+};
+
+static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x001f001f,
+ .p0_mpwldectrl1 = 0x001f001f,
+ .p1_mpwldectrl0 = 0x001f001f,
+ .p1_mpwldectrl1 = 0x001f001f,
+ .p0_mpdgctrl0 = 0x420e020e,
+ .p0_mpdgctrl1 = 0x02000200,
+ .p1_mpdgctrl0 = 0x42020202,
+ .p1_mpdgctrl1 = 0x01720172,
+ .p0_mprddlctl = 0x494c4f4c,
+ .p1_mprddlctl = 0x4a4c4c49,
+ .p0_mpwrdlctl = 0x3f3f3133,
+ .p1_mpwrdlctl = 0x39373f2e,
+};
+
+static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x0040003c,
+ .p0_mpwldectrl1 = 0x0032003e,
+ .p0_mpdgctrl0 = 0x42350231,
+ .p0_mpdgctrl1 = 0x021a0218,
+ .p0_mprddlctl = 0x4b4b4e49,
+ .p0_mpwrdlctl = 0x3f3f3035,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFC000, &ccm->CCGR2);
+ writel(0x3FF03000, &ccm->CCGR3);
+ writel(0x00FFF300, &ccm->CCGR4);
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void spl_dram_init(void)
+{
+ if (is_mx6solo()) {
+ mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+ mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63ffr);
+ } else if (is_mx6dl()) {
+ mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+ mx6_dram_cfg(&mem_s, &mx6dl_1g_mmdc_calib, &h5t04g63afr);
+ } else if (is_mx6dq()) {
+ mx6dq_dram_iocfg(32, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
+ mx6_dram_cfg(&mem_s, &mx6q_1g_mmdc_calib, &h5t04g63afr);
+ }
+
+ udelay(100);
+}
+
+void board_init_f(ulong dummy)
+{
+ ccgr_init();
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ gpr_init();
+
+ /* iomux */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+}
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC3_BASE_ADDR},
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ /* SOM MicroSD Card Detect */
+ IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ SETUP_IOMUX_PADS(usdhc3_pads);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ if (is_mx6dq() && !strcmp(name, "imx6q-pico"))
+ return 0;
+ else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-pico"))
+ return 0;
+
+ return -EINVAL;
+}
+#endif
diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig
new file mode 100644
index 0000000000..a0448b2236
--- /dev/null
+++ b/configs/pico-imx6_defconfig
@@ -0,0 +1,71 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_PICO_IMX6=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT_PRINT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_BOOTCOMMAND="run findbaseboard; run findfdt; run finduuid; run distro_bootcmd"
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_DEFAULT_FDT_FILE="ask"
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_FIT_IMAGE_TINY=y
+CONFIG_SPL_FS_EXT4=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_SPL=y
+CONFIG_CMD_SPL_WRITE_SIZE=0x20000
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-pico"
+CONFIG_OF_LIST="imx6dl-pico imx6q-pico"
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DFU_MMC=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h
new file mode 100644
index 0000000000..2ea50f5488
--- /dev/null
+++ b/include/configs/pico-imx6.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the pico-imx6 board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#include "imx6_spl.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
+
+/* MMC Configuration */
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
+#define CONFIG_SUPPORT_EMMC_BOOT
+#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
+
+/* USB Configs */
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
+#define DFU_DEFAULT_POLL_TIMEOUT 300
+
+#define CONFIG_DFU_ENV_SETTINGS \
+ "dfu_alt_info=" \
+ "spl raw 0x2 0x400;" \
+ "u-boot raw 0x8a 0x1000;" \
+ "/boot/zImage ext4 0 1;" \
+ "rootfs part 0 1\0" \
+
+#define BOOTMENU_ENV \
+ "bootmenu_0=Boot using PICO-Hobbit baseboard=" \
+ "setenv baseboard hobbit\0" \
+ "bootmenu_1=Boot using PICO-Pi baseboard=" \
+ "setenv baseboard pi\0" \
+ "bootmenu_2=Boot using PICO-Dwarf baseboard=" \
+ "setenv baseboard dwarf\0" \
+ "bootmenu_3=Boot using PICO-Nymph baseboard=" \
+ "setenv baseboard nymph\0" \
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=ttymxc0\0" \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ BOOTMENU_ENV \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_addr_r=0x18000000\0" \
+ "fdt_addr=0x18000000\0" \
+ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+ CONFIG_DFU_ENV_SETTINGS \
+ "finduuid=part uuid mmc 0:1 uuid\0" \
+ "findbaseboard=" \
+ "if test $baseboard = ask ; then " \
+ "bootmenu -1; fi;" \
+ "if test $baseboard != ask ; then " \
+ "saveenv; fi;\0" \
+ "findfdt="\
+ "if test $baseboard = hobbit && test $board_rev = MX6Q ; then " \
+ "setenv fdtfile imx6q-pico-hobbit.dtb; fi; " \
+ "if test $baseboard = pi && test $board_rev = MX6Q ; then " \
+ "setenv fdtfile imx6q-pico-pi.dtb; fi; " \
+ "if test $baseboard = dwarf && test $board_rev = MX6Q ; then " \
+ "setenv fdtfile imx6q-pico-dwarf.dtb; fi; " \
+ "if test $baseboard = nymph && test $board_rev = MX6Q ; then " \
+ "setenv fdtfile imx6q-pico-nymph.dtb; fi; " \
+ "if test $baseboard = hobbit && test $board_rev = MX6DL ; then " \
+ "setenv fdtfile imx6dl-pico-hobbit.dtb; fi; " \
+ "if test $baseboard = pi && test $board_rev = MX6DL ; then " \
+ "setenv fdtfile imx6dl-pico-pi.dtb; fi; " \
+ "if test $baseboard = dwarf && test $board_rev = MX6DL ; then " \
+ "setenv fdtfile imx6dl-pico-dwarf.dtb; fi; " \
+ "if test $baseboard = nymph && test $board_rev = MX6DL ; then " \
+ "setenv fdtfile imx6dl-pico-nymph.dtb; fi; " \
+ "if test $fdtfile = ask; then " \
+ "echo WARNING: Could not determine dtb to use; fi; \0" \
+ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "ramdisk_addr_r=0x13000000\0" \
+ "ramdiskaddr=0x13000000\0" \
+ "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+ BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(USB, usb, 0)
+
+#include <config_distro_bootcmd.h>
+
+/* Physical Memory Map */
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+/* Environment starts at 768k = 768 * 1024 = 786432 */
+#define CONFIG_ENV_OFFSET 786432
+/*
+ * Detect overlap between U-Boot image and environment area in build-time
+ *
+ * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.img offset
+ * CONFIG_BOARD_SIZE_LIMIT = 768k - 69k = 699k = 715776
+ *
+ * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so
+ * write the direct value here
+ */
+#define CONFIG_BOARD_SIZE_LIMIT 715776
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif /* __CONFIG_H * */
--
2.23.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [U-Boot] [PATCH v2 6/8] pico-imx6: Add Ethernet support
2019-09-20 19:47 [U-Boot] [PATCH v2 1/8] configs: Sync all baseboard specific pico-imx7d Otavio Salvador
` (3 preceding siblings ...)
2019-09-20 19:47 ` [U-Boot] [PATCH v2 5/8] pico-imx6: Fix bootmenu handling Otavio Salvador
@ 2019-09-20 19:47 ` Otavio Salvador
2019-09-20 20:58 ` Anatolij Gustschin
2019-09-20 19:47 ` [U-Boot] [PATCH v2 7/8] pico-imx6: Add splashscreen support Otavio Salvador
2019-09-20 19:47 ` [U-Boot] [PATCH v2 8/8] pico-imx6: Add Falcon mode Otavio Salvador
6 siblings, 1 reply; 10+ messages in thread
From: Otavio Salvador @ 2019-09-20 19:47 UTC (permalink / raw)
To: u-boot
From: Fabio Estevam <festevam@gmail.com>
Add Ethernet support.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
---
board/technexion/pico-imx6/pico-imx6.c | 74 ++++++++++++++++++++++++++
include/configs/pico-imx6.h | 10 ++++
2 files changed, 84 insertions(+)
diff --git a/board/technexion/pico-imx6/pico-imx6.c b/board/technexion/pico-imx6/pico-imx6.c
index 717f20d9d7..2ae5af83d2 100644
--- a/board/technexion/pico-imx6/pico-imx6.c
+++ b/board/technexion/pico-imx6/pico-imx6.c
@@ -17,6 +17,9 @@
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <phy.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -24,6 +27,11 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ETH_PHY_RESET IMX_GPIO_NR(1, 26)
+
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
@@ -41,6 +49,39 @@ static void setup_iomux_uart(void)
SETUP_IOMUX_PADS(uart1_pads);
}
+static iomux_v3_cfg_t const enet_pads[] = {
+ IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ /* AR8035 PHY Reset */
+ IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void setup_iomux_enet(void)
+{
+ SETUP_IOMUX_PADS(enet_pads);
+
+ /* Reset AR8031 PHY */
+ gpio_request(ETH_PHY_RESET, "enet_phy_reset");
+ gpio_direction_output(ETH_PHY_RESET, 0);
+ udelay(500);
+ gpio_set_value(ETH_PHY_RESET, 1);
+}
+
int board_early_init_f(void)
{
setup_iomux_uart();
@@ -48,6 +89,39 @@ int board_early_init_f(void)
return 0;
}
+int board_eth_init(bd_t *bis)
+{
+ setup_iomux_enet();
+
+ return cpu_eth_init(bis);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ unsigned short val;
+
+ /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+ val &= 0xffe7;
+ val |= 0x18;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+ /* introduce tx clock delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+ val |= 0x0100;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
int overwrite_console(void)
{
return 1;
diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h
index d151da07f2..d539b88bf7 100644
--- a/include/configs/pico-imx6.h
+++ b/include/configs/pico-imx6.h
@@ -129,4 +129,14 @@
#define CONFIG_BOARD_SIZE_LIMIT 715776
#define CONFIG_SYS_MMC_ENV_DEV 0
+/* Ethernet Configuration */
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 1
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+
#endif /* __CONFIG_H * */
--
2.23.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [U-Boot] [PATCH v2 7/8] pico-imx6: Add splashscreen support
2019-09-20 19:47 [U-Boot] [PATCH v2 1/8] configs: Sync all baseboard specific pico-imx7d Otavio Salvador
` (4 preceding siblings ...)
2019-09-20 19:47 ` [U-Boot] [PATCH v2 6/8] pico-imx6: Add Ethernet support Otavio Salvador
@ 2019-09-20 19:47 ` Otavio Salvador
2019-09-20 19:47 ` [U-Boot] [PATCH v2 8/8] pico-imx6: Add Falcon mode Otavio Salvador
6 siblings, 0 replies; 10+ messages in thread
From: Otavio Salvador @ 2019-09-20 19:47 UTC (permalink / raw)
To: u-boot
From: Fabio Estevam <festevam@gmail.com>
Add splashscreen support. Tested with the parallel
FT5x06-WVGA panel.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
---
board/technexion/pico-imx6/pico-imx6.c | 210 +++++++++++++++++++++++++
configs/pico-imx6_defconfig | 2 +
include/configs/pico-imx6.h | 10 ++
3 files changed, 222 insertions(+)
diff --git a/board/technexion/pico-imx6/pico-imx6.c b/board/technexion/pico-imx6/pico-imx6.c
index 2ae5af83d2..f8eeb40555 100644
--- a/board/technexion/pico-imx6/pico-imx6.c
+++ b/board/technexion/pico-imx6/pico-imx6.c
@@ -13,6 +13,8 @@
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/mach-imx/video.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <linux/sizes.h>
@@ -31,6 +33,8 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define ETH_PHY_RESET IMX_GPIO_NR(1, 26)
+#define LVDS0_EN IMX_GPIO_NR(2, 8)
+#define LVDS0_BL_EN IMX_GPIO_NR(2, 9)
int dram_init(void)
{
@@ -49,6 +53,15 @@ static void setup_iomux_uart(void)
SETUP_IOMUX_PADS(uart1_pads);
}
+static iomux_v3_cfg_t const lvds_pads[] = {
+ /* lvds */
+ IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
static iomux_v3_cfg_t const enet_pads[] = {
IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
@@ -82,10 +95,207 @@ static void setup_iomux_enet(void)
gpio_set_value(ETH_PHY_RESET, 1);
}
+#if defined(CONFIG_VIDEO_IPUV3)
+static iomux_v3_cfg_t const ft5x06_wvga_pads[] = {
+ IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
+ IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
+ IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
+ IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
+ IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
+ IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
+ IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
+ IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
+ IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
+ IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
+ IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
+ IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
+ IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
+ IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
+ IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
+ IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
+ IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
+ IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
+ IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
+ IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
+ IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
+ IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
+ IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
+ IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18),
+ IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19),
+ IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20),
+ IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21),
+ IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22),
+ IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23),
+ IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
+ IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
+};
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+ imx_enable_hdmi_phy();
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+ struct iomuxc *iomux = (struct iomuxc *)
+ IOMUXC_BASE_ADDR;
+
+ /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
+ u32 reg = readl(&iomux->gpr[2]);
+ reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
+ writel(reg, &iomux->gpr[2]);
+
+ /* Enable Backlight - use GPIO for Brightness adjustment */
+ SETUP_IOMUX_PAD(PAD_SD4_DAT1__GPIO2_IO09);
+ gpio_request(IMX_GPIO_NR(2, 9), "backlight_enable");
+ gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
+
+ gpio_request(IMX_GPIO_NR(2, 8), "brightness");
+ SETUP_IOMUX_PAD(PAD_SD4_DAT0__GPIO2_IO08);
+ gpio_direction_output(IMX_GPIO_NR(2, 8), 1);
+}
+
+static void enable_ft5x06_wvga(struct display_info_t const *dev)
+{
+ SETUP_IOMUX_PADS(ft5x06_wvga_pads);
+
+ gpio_request(IMX_GPIO_NR(2, 10), "parallel_enable");
+ gpio_request(IMX_GPIO_NR(2, 11), "parallel_brightness");
+ gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
+ gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
+}
+
+struct display_info_t const displays[] = {{
+ .bus = 1,
+ .addr = 0x38,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = NULL,
+ .enable = enable_ft5x06_wvga,
+ .mode = {
+ .name = "FT5x06-WVGA",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 30303,
+ .left_margin = 45,
+ .right_margin = 210,
+ .upper_margin = 22,
+ .lower_margin = 22,
+ .hsync_len = 1,
+ .vsync_len = 1,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = NULL,
+ .enable = enable_lvds,
+ .mode = {
+ .name = "hj070na",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 600,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = do_enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int reg;
+
+ /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
+ SETUP_IOMUX_PADS(lvds_pads);
+ gpio_request(LVDS0_EN, "lvds0_enable");
+ gpio_request(LVDS0_BL_EN, "lvds0_bl_enable");
+ gpio_direction_output(LVDS0_EN, 1);
+ gpio_direction_output(LVDS0_BL_EN, 1);
+
+ enable_ipu_clock();
+ imx_setup_hdmi();
+
+ reg = __raw_readl(&mxc_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
+ writel(reg, &mxc_ccm->CCGR3);
+
+ /* set LDB0, LDB1 clk select to 011/011 */
+ reg = readl(&mxc_ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+ | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+ reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+ | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->cs2cdr);
+
+ reg = readl(&mxc_ccm->cscmr2);
+ reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
+ writel(reg, &mxc_ccm->cscmr2);
+
+ reg = readl(&mxc_ccm->chsccdr);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->chsccdr);
+
+ reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+ | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
+ | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+ | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+ | IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT
+ | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+ | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
+ | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
+ | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+ writel(reg, &iomux->gpr[2]);
+ reg = readl(&iomux->gpr[3]);
+
+ reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
+ | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
+ | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+ << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+
+ writel(reg, &iomux->gpr[3]);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
int board_early_init_f(void)
{
setup_iomux_uart();
+#if defined(CONFIG_VIDEO_IPUV3)
+ setup_display();
+#endif
+
return 0;
}
diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig
index 4291f6fab0..02787f8250 100644
--- a/configs/pico-imx6_defconfig
+++ b/configs/pico-imx6_defconfig
@@ -69,3 +69,5 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h
index d539b88bf7..467d5ff4f5 100644
--- a/include/configs/pico-imx6.h
+++ b/include/configs/pico-imx6.h
@@ -139,4 +139,14 @@
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
+/* Framebuffer */
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+
#endif /* __CONFIG_H * */
--
2.23.0
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