[PATCH v2 2/7] riscv: Match memory barriers between send_ipi_many and handle_ipi

[Leo Liang <ycliang@andestech.com>]

On Mon, Sep 14, 2020 at 10:22:58AM -0400, Sean Anderson wrote:
> Without a matching barrier on the write side, the barrier in handle_ipi
> does nothing. It was entirely possible for the boot hart to write to addr,
> arg0, and arg1 *after* sending the IPI, because there was no barrier on the
> sending side.
> 
> Fixes: 90ae281437 ("riscv: add option to wait for ack from secondary harts in smp functions")
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> Reviewed-by: Bin Meng <bin.meng@windriver.com>
> Reviewed-by: Rick Chen <rick@andestech.com>
> ---
> 
> (no changes since v1)
> 
>  arch/riscv/lib/smp.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
> index ac22136314..ab6d8bd7fa 100644
> --- a/arch/riscv/lib/smp.c
> +++ b/arch/riscv/lib/smp.c
> @@ -54,6 +54,8 @@ static int send_ipi_many(struct ipi_data *ipi, int wait)
>  		gd->arch.ipi[reg].arg0 = ipi->arg0;
>  		gd->arch.ipi[reg].arg1 = ipi->arg1;
>  
> +		__smp_mb();
> +
>  		ret = riscv_send_ipi(reg);
>  		if (ret) {
>  			pr_err("Cannot send IPI to hart %d\n", reg);

Reviewed-by: Leo Liang <ycliang@andestech.com>