From: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
To: <lukma@denx.de>, <maxims@google.com>, <sjg@chromium.org>,
<u-boot@lists.denx.de>
Cc: <ryan_chen@aspeedtech.com>
Subject: [PATCH 10/14] ARM: dts: ast2600: Add ARCY to device tree
Date: Tue, 13 Jul 2021 17:00:12 +0800 [thread overview]
Message-ID: <20210713090016.2729-11-chiawei_wang@aspeedtech.com> (raw)
In-Reply-To: <20210713090016.2729-1-chiawei_wang@aspeedtech.com>
Add ARCY DTS node and enable it for AST2600 EVB.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
---
arch/arm/dts/ast2600-evb.dts | 5 +++++
arch/arm/dts/ast2600.dtsi | 9 +++++++++
2 files changed, 14 insertions(+)
diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts
index adb80a30ef..fd4e35e954 100644
--- a/arch/arm/dts/ast2600-evb.dts
+++ b/arch/arm/dts/ast2600-evb.dts
@@ -182,3 +182,8 @@
u-boot,dm-pre-reloc;
status = "okay";
};
+
+&arcy {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi
index 642206fb77..216156bfbb 100644
--- a/arch/arm/dts/ast2600.dtsi
+++ b/arch/arm/dts/ast2600.dtsi
@@ -195,6 +195,15 @@
status = "disabled";
};
+ arcy: arcy@1e6fa000 {
+ compatible = "aspeed,ast2600-arcy";
+ reg = <0x1e6fa000 0x1000>,
+ <0x1e710000 0x10000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scu ASPEED_CLK_GATE_RSACLK>;
+ status = "disabled";
+ };
+
edac: sdram@1e6e0000 {
compatible = "aspeed,ast2600-sdram-edac";
reg = <0x1e6e0000 0x174>;
--
2.17.1
next prev parent reply other threads:[~2021-07-13 9:02 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-13 9:00 [PATCH 00/14] aspeed: Support secure boot chain with FIT image verification Chia-Wei Wang
2021-07-13 9:00 ` [PATCH 01/14] aspeed: ast2600: Enlarge SRAM size Chia-Wei Wang
2021-07-13 9:00 ` [PATCH 02/14] clk: ast2600: Add YCLK control for HACE Chia-Wei Wang
2021-07-13 9:00 ` [PATCH 03/14] crypto: aspeed: Add AST2600 HACE support Chia-Wei Wang
2021-07-13 9:00 ` [PATCH 04/14] ast2600: spl: Add HACE probing Chia-Wei Wang
2021-07-13 9:00 ` [PATCH 05/14] ARM: dts: ast2600: Add HACE to device tree Chia-Wei Wang
2021-07-13 9:00 ` [PATCH 06/14] common: fit: Use hash.c to call CRC/SHA function Chia-Wei Wang
2021-07-13 9:00 ` [PATCH 07/14] clk: ast2600: Add RSACLK control for ARCY Chia-Wei Wang
2021-07-13 9:00 ` [PATCH 08/14] crypto: aspeed: Add AST2600 ARCY support Chia-Wei Wang
2021-07-13 9:00 ` [PATCH 09/14] ast2600: spl: Add ARCY probing Chia-Wei Wang
2021-07-13 9:00 ` Chia-Wei Wang [this message]
2021-07-13 9:00 ` [PATCH 11/14] ast2600: spl: Locate load buffer in DRAM space Chia-Wei Wang
2021-07-13 9:00 ` [PATCH 12/14] configs: ast2600-evb: Enable SPL FIT support Chia-Wei Wang
2021-07-13 9:00 ` [PATCH 13/14] configs: aspeed: Make EXTRA_ENV_SETTINGS board specific Chia-Wei Wang
2021-07-13 9:00 ` [PATCH 14/14] configs: ast2600: Boot kernel FIT in DRAM Chia-Wei Wang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210713090016.2729-11-chiawei_wang@aspeedtech.com \
--to=chiawei_wang@aspeedtech.com \
--cc=lukma@denx.de \
--cc=maxims@google.com \
--cc=ryan_chen@aspeedtech.com \
--cc=sjg@chromium.org \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox