From: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
To: <lukma@denx.de>, <maxims@google.com>, <sjg@chromium.org>,
<u-boot@lists.denx.de>
Cc: <ryan_chen@aspeedtech.com>
Subject: [PATCH 07/14] clk: ast2600: Add RSACLK control for ARCY
Date: Tue, 13 Jul 2021 17:00:09 +0800 [thread overview]
Message-ID: <20210713090016.2729-8-chiawei_wang@aspeedtech.com> (raw)
In-Reply-To: <20210713090016.2729-1-chiawei_wang@aspeedtech.com>
Add RSACLK enable for ARCY, the HW RSA/ECC crypto engine
of ASPEED AST26xx SoCs.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
---
arch/arm/include/asm/arch-aspeed/scu_ast2600.h | 1 +
drivers/clk/aspeed/clk_ast2600.c | 15 +++++++++++++++
2 files changed, 16 insertions(+)
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h b/arch/arm/include/asm/arch-aspeed/scu_ast2600.h
index d7b500f656..27f4e9f994 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2600.h
@@ -8,6 +8,7 @@
#define SCU_UNLOCK_KEY 0x1688a8a8
#define SCU_CLKGATE1_EMMC BIT(27)
+#define SCU_CLKGATE1_ARCY BIT(24)
#define SCU_CLKGATE1_MAC2 BIT(21)
#define SCU_CLKGATE1_MAC1 BIT(20)
#define SCU_CLKGATE1_USB_HUB BIT(14)
diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c
index 69128fd3c4..bf3379fce2 100644
--- a/drivers/clk/aspeed/clk_ast2600.c
+++ b/drivers/clk/aspeed/clk_ast2600.c
@@ -1030,6 +1030,18 @@ static ulong ast2600_enable_haceclk(struct ast2600_scu *scu)
return 0;
}
+static ulong ast2600_enable_rsaclk(struct ast2600_scu *scu)
+{
+ uint32_t clkgate_bit;
+
+ clkgate_bit = SCU_CLKGATE1_ARCY;
+
+ writel(clkgate_bit, &scu->clkgate_clr1);
+ mdelay(20);
+
+ return 0;
+}
+
static int ast2600_clk_enable(struct clk *clk)
{
struct ast2600_clk_priv *priv = dev_get_priv(clk->dev);
@@ -1071,6 +1083,9 @@ static int ast2600_clk_enable(struct clk *clk)
case ASPEED_CLK_GATE_YCLK:
ast2600_enable_haceclk(priv->scu);
break;
+ case ASPEED_CLK_GATE_RSACLK:
+ ast2600_enable_rsaclk(priv->scu);
+ break;
default:
pr_err("can't enable clk\n");
return -ENOENT;
--
2.17.1
next prev parent reply other threads:[~2021-07-13 9:01 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-13 9:00 [PATCH 00/14] aspeed: Support secure boot chain with FIT image verification Chia-Wei Wang
2021-07-13 9:00 ` [PATCH 01/14] aspeed: ast2600: Enlarge SRAM size Chia-Wei Wang
2021-07-13 9:00 ` [PATCH 02/14] clk: ast2600: Add YCLK control for HACE Chia-Wei Wang
2021-07-13 9:00 ` [PATCH 03/14] crypto: aspeed: Add AST2600 HACE support Chia-Wei Wang
2021-07-13 9:00 ` [PATCH 04/14] ast2600: spl: Add HACE probing Chia-Wei Wang
2021-07-13 9:00 ` [PATCH 05/14] ARM: dts: ast2600: Add HACE to device tree Chia-Wei Wang
2021-07-13 9:00 ` [PATCH 06/14] common: fit: Use hash.c to call CRC/SHA function Chia-Wei Wang
2021-07-13 9:00 ` Chia-Wei Wang [this message]
2021-07-13 9:00 ` [PATCH 08/14] crypto: aspeed: Add AST2600 ARCY support Chia-Wei Wang
2021-07-13 9:00 ` [PATCH 09/14] ast2600: spl: Add ARCY probing Chia-Wei Wang
2021-07-13 9:00 ` [PATCH 10/14] ARM: dts: ast2600: Add ARCY to device tree Chia-Wei Wang
2021-07-13 9:00 ` [PATCH 11/14] ast2600: spl: Locate load buffer in DRAM space Chia-Wei Wang
2021-07-13 9:00 ` [PATCH 12/14] configs: ast2600-evb: Enable SPL FIT support Chia-Wei Wang
2021-07-13 9:00 ` [PATCH 13/14] configs: aspeed: Make EXTRA_ENV_SETTINGS board specific Chia-Wei Wang
2021-07-13 9:00 ` [PATCH 14/14] configs: ast2600: Boot kernel FIT in DRAM Chia-Wei Wang
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