From: sin.hui.kho@intel.com
To: u-boot@lists.denx.de
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>,
Marek Vasut <marex@denx.de>,
Tien Fong Chee <tien.fong.chee@intel.com>,
Kok Kiang Hea <kok.kiang.hea@intel.com>,
Westergteen Dalon <dalon.westergreen@intel.com>,
Cozart Sue <sue.cozart@intel.com>,
Sin Hui Kho <sin.hui.kho@intel.com>
Subject: [PATCH 3/3] arm: socfpga: arria10: Enable double peripheral RBF configuration
Date: Sun, 7 Nov 2021 23:08:56 +0800 [thread overview]
Message-ID: <20211107150856.19256-3-sin.hui.kho@intel.com> (raw)
In-Reply-To: <20211107150856.19256-1-sin.hui.kho@intel.com>
From: Tien Fong Chee <tien.fong.chee@intel.com>
Double peripheral RBF configuration are needed on some devices or boards
to stabilize the IO configuration system.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com>
---
arch/arm/mach-socfpga/include/mach/misc.h | 2 ++
arch/arm/mach-socfpga/misc_arria10.c | 36 +++++++++++++++++++++++
arch/arm/mach-socfpga/spl_a10.c | 14 +++++++++
drivers/fpga/socfpga_arria10.c | 3 +-
4 files changed, 54 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
index 74e8e2590f..8460acb00d 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -45,7 +45,9 @@ int is_fpga_config_ready(void);
#endif
void do_bridge_reset(int enable, unsigned int mask);
+void force_periph_program(unsigned int status);
bool is_regular_boot_valid(void);
+bool is_periph_program_force(void);
void set_regular_boot(unsigned int status);
void socfpga_pl310_clear(void);
void socfpga_get_managers_addr(void);
diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
index 634e63ed42..0ed2adfd84 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -32,6 +32,7 @@
#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98
#define REGULAR_BOOT_MAGIC 0xd15ea5e
+#define PERIPH_RBF_PROG_FORCE 0x50455249
#define QSPI_S25FL_SOFT_RESET_COMMAND 0x00f0ff82
#define QSPI_N25_SOFT_RESET_COMMAND 0x00000001
@@ -131,6 +132,41 @@ void do_bridge_reset(int enable, unsigned int mask)
socfpga_bridges_reset();
}
+/*
+ * This function set/unset flag with number "0x50455249" to
+ * handoff register isw_handoff[7] - 0xffd0624c
+ * This flag is used to force periph RBF program regardless FPGA status
+ * and double periph RBF config are needed on some devices or boards to
+ * stabilize the IO config system.
+ */
+void force_periph_program(unsigned int status)
+{
+ if (status)
+ writel(PERIPH_RBF_PROG_FORCE, socfpga_get_sysmgr_addr() +
+ SYSMGR_A10_ISW_HANDOFF_BASE + SYSMGR_A10_ISW_HANDOFF_7);
+ else
+ writel(0, socfpga_get_sysmgr_addr() +
+ SYSMGR_A10_ISW_HANDOFF_BASE + SYSMGR_A10_ISW_HANDOFF_7);
+}
+
+/*
+ * This function is used to check whether
+ * handoff register isw_handoff[7] contains
+ * flag for forcing the periph RBF program "0x50455249".
+ */
+bool is_periph_program_force(void)
+{
+ unsigned int status;
+
+ status = readl(socfpga_get_sysmgr_addr() +
+ SYSMGR_A10_ISW_HANDOFF_BASE + SYSMGR_A10_ISW_HANDOFF_7);
+
+ if (status == PERIPH_RBF_PROG_FORCE)
+ return true;
+ else
+ return false;
+}
+
/*
* This function set/unset magic number "0xd15ea5e" to
* handoff register isw_handoff[7] - 0xffd0624c
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index 6450f75058..d2f454cd24 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -133,6 +133,20 @@ void spl_board_init(void)
} else if (!is_fpgamgr_early_user_mode()) {
/* Program IOSSM(early IO release) or full FPGA */
fpgamgr_program(buf, FPGA_BUFSIZ, 0);
+
+ /* Skipping double program for combined RBF */
+ if (!is_fpgamgr_user_mode()) {
+ /*
+ * Expect FPGA entered early user mode, so
+ * the flag is set to re-program IOSSM
+ */
+ force_periph_program(true);
+
+ /* Re-program IOSSM to stabilize IO system */
+ fpgamgr_program(buf, FPGA_BUFSIZ, 0);
+
+ force_periph_program(false);
+ }
}
/* If the IOSSM/full FPGA is already loaded, start DDR */
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index b992e6f080..798e3a3f90 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -604,7 +604,8 @@ static int first_loading_rbf_to_buffer(struct udevice *dev,
if (strstr(uname, "fpga-periph") &&
(!is_fpgamgr_early_user_mode() ||
- is_fpgamgr_user_mode())) {
+ is_fpgamgr_user_mode() ||
+ is_periph_program_force())) {
fpga_node_name = uname;
printf("FPGA: Start to program ");
printf("peripheral/full bitstream ...\n");
--
2.25.1
next prev parent reply other threads:[~2021-11-07 15:11 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-07 15:08 [PATCH 1/3] arm: socfpga: arria10: Setting image magic value to romcode initswstate reg sin.hui.kho
2021-11-07 15:08 ` [PATCH 2/3] arm: socfpga: arria10: Reset MPFE NoC after program periph / combined RBF sin.hui.kho
2021-11-25 2:12 ` Chee, Tien Fong
2021-11-07 15:08 ` sin.hui.kho [this message]
2021-11-25 2:13 ` [PATCH 3/3] arm: socfpga: arria10: Enable double peripheral RBF configuration Chee, Tien Fong
2021-11-25 2:09 ` [PATCH 1/3] arm: socfpga: arria10: Setting image magic value to romcode initswstate reg Chee, Tien Fong
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