From: Tom Rini <trini@konsulko.com>
To: "Stefan Mätje" <stefan.maetje@esd.eu>
Cc: Jagan Teki <jagan@amarulasolutions.com>, u-boot@lists.denx.de
Subject: Re: [PATCH 1/1] Fix wrong QSPI clock calculation for AM4372
Date: Mon, 17 Jan 2022 13:36:23 -0500 [thread overview]
Message-ID: <20220117183623.GU2631111@bill-the-cat> (raw)
In-Reply-To: <20211130000656.1837826-2-stefan.maetje@esd.eu>
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On Tue, Nov 30, 2021 at 01:06:56AM +0100, Stefan Mätje wrote:
> On AM4372 the SPI_GCLK input gets its clock from the PRCM module which
> divides the PER_CLKOUTM2 frequency (192MHz) by a fixed factor of 4.
> See AM437x Reference Manual in section 27 QSPI >> 27.2 Integration.
>
> The QSPI_FCLK therefore needs to take this factor into account and
> becomes (192000000 / 4).
>
> Signed-off-by: Stefan Mätje <stefan.maetje@esd.eu>
Applied to u-boot/master, thanks!
--
Tom
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prev parent reply other threads:[~2022-01-17 18:36 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-30 0:06 [PATCH 0/1] Provide a fix for wrong QSPI clock calculation on AM4372 Stefan Mätje
2021-11-30 0:06 ` [PATCH 1/1] Fix wrong QSPI clock calculation for AM4372 Stefan Mätje
2021-11-30 3:58 ` Tom Rini
2021-11-30 12:14 ` Stefan Mätje
2021-11-30 12:51 ` Tom Rini
2022-01-17 18:36 ` Tom Rini [this message]
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