From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Cc: Marek Vasut <marex@denx.de>, Ramon Fried <rfried.dev@gmail.com>,
"Ariel D'Alessandro" <ariel.dalessandro@collabora.com>,
"NXP i.MX U-Boot Team" <uboot-imx@nxp.com>,
Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>,
Fabio Estevam <festevam@gmail.com>,
Joe Hershberger <joe.hershberger@ni.com>,
Lukasz Majewski <lukma@denx.de>,
Marcel Ziswiler <marcel.ziswiler@toradex.com>,
Michael Trimarchi <michael@amarulasolutions.com>,
Peng Fan <peng.fan@nxp.com>, Sean Anderson <seanga2@gmail.com>,
Stefano Babic <sbabic@denx.de>,
Tim Harvey <tharvey@gateworks.com>,
Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Subject: [PATCH v2 05/10] net: dwc_eth_qos: Set DMA_MODE SWR bit to reset the MAC
Date: Thu, 9 Feb 2023 22:50:43 +0100 [thread overview]
Message-ID: <20230209215048.259223-5-marex@denx.de> (raw)
In-Reply-To: <20230209215048.259223-1-marex@denx.de>
The driver currently only waits for DMA_MODE SWR bit to clear itself.
This is insufficient e.g. on i.MX8M Plus, where the MAC must be reset
before IOMUX GPR[1] content is latched into the MAC and used. Without
the proper reset, the i.MX8M Plus MAC variant does not take the value
in IOMUX GPR[1] into account, which makes it impossible e.g. to switch
interface mode from RGMII to any other.
Since proper reset is desired in general to put the block into defined
state, always assert the DMA_MODE SWR bit before waiting for the bit
to clear itself.
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Cc: u-boot@lists.denx.de
---
V2: Add RB from Ramon
---
drivers/net/dwc_eth_qos.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index bdf0f2e6812..66e3f354b65 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -761,6 +761,12 @@ static int eqos_start(struct udevice *dev)
eqos->reg_access_ok = true;
+ /*
+ * Assert the SWR first, the actually reset the MAC and to latch in
+ * e.g. i.MX8M Plus GPR[1] content, which selects interface mode.
+ */
+ setbits_le32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR);
+
ret = wait_for_bit_le32(&eqos->dma_regs->mode,
EQOS_DMA_MODE_SWR, false,
eqos->config->swr_wait, false);
--
2.39.1
next prev parent reply other threads:[~2023-02-09 21:51 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-09 21:50 [PATCH v2 01/10] clk: imx8mp: Add EQoS MAC clock Marek Vasut
2023-02-09 21:50 ` [PATCH v2 02/10] net: dwc_eth_qos: Drop bogus return after goto Marek Vasut
2023-02-09 21:50 ` [PATCH v2 03/10] net: dwc_eth_qos: Drop unused dm_gpio_free() on STM32 Marek Vasut
2023-02-09 21:50 ` [PATCH v2 04/10] net: dwc_eth_qos: Staticize eqos_inval_buffer_tegra186() Marek Vasut
2023-02-09 21:50 ` Marek Vasut [this message]
2023-02-09 21:50 ` [PATCH v2 06/10] net: dwc_eth_qos: Add DM CLK support for i.MX8M Plus Marek Vasut
2023-02-12 17:57 ` Sean Anderson
2023-02-09 21:50 ` [PATCH v2 07/10] net: dwc_eth_qos: Add i.MX8M Plus RMII support Marek Vasut
2023-02-09 21:50 ` [PATCH v2 08/10] net: dwc_eth_qos: Add board_interface_eth_init() for i.MX8M Plus Marek Vasut
2023-02-09 21:50 ` [PATCH v2 09/10] arm64: dts: imx8mp: Drop EQoS clock workaround Marek Vasut
2023-02-09 21:50 ` [PATCH v2 10/10] arm64: imx8mp: Drop EQoS GPR[1] board workaround Marek Vasut
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