From: Lukasz Majewski <lukma@denx.de>
To: Marek Vasut <marek.vasut@mailbox.org>
Cc: u-boot@lists.denx.de, Tom Rini <trini@konsulko.com>,
Anatolij Gustschin <agust@denx.de>,
Ramon Fried <rfried.dev@gmail.com>,
Joe Hershberger <joe.hershberger@ni.com>,
Marek Vasut <marek.vasut+renesas@mailbox.org>,
Michal Simek <michal.simek@amd.com>
Subject: Re: [PATCH v1 2/6] net: mv88e61xx: Configure PHY ports to also pass packets between them
Date: Thu, 1 Jun 2023 13:02:51 +0200 [thread overview]
Message-ID: <20230601130251.12f18dca@wsk> (raw)
In-Reply-To: <0ab25898-2fe6-7d86-7d63-ff3d43e82b63@mailbox.org>
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Hi Marek,
> On 6/1/23 12:00, Lukasz Majewski wrote:
> > After this change PHY ports are able to pass packets between them
> > (and also to CPU port).
> >
> > The Kconfig variable - CONFIG_MV88E61XX_PHY_PORTS - is used to get
> > the PHY ports of the switch and generate proper mask.
> >
> > Signed-off-by: Lukasz Majewski <lukma@denx.de>
> > Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
>
> Was there a V0 before ? Or where did these RB tags come from ?
>
There was v1 in 2021 - The patman is not allowing "v1 RESEND" tag
adding.
> > ---
> >
> > drivers/net/phy/mv88e61xx.c | 9 +++++++--
> > 1 file changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/net/phy/mv88e61xx.c
> > b/drivers/net/phy/mv88e61xx.c index 31f9b57456d6..4aee83551beb
> > 100644 --- a/drivers/net/phy/mv88e61xx.c
> > +++ b/drivers/net/phy/mv88e61xx.c
> > @@ -865,14 +865,19 @@ static int mv88e61xx_phy_setup(struct
> > phy_device *phydev, u8 phy)
> > static int mv88e61xx_phy_config_port(struct phy_device *phydev,
> > u8 phy) {
> > + struct mv88e61xx_phy_priv *priv = phydev->priv;
> > + u16 port_mask;
> > int val;
> >
> > val = mv88e61xx_port_enable(phydev, phy);
> > if (val < 0)
> > return val;
> >
> > - val = mv88e61xx_port_set_vlan(phydev, phy,
> > - 1 << CONFIG_MV88E61XX_CPU_PORT);
> > + port_mask = PORT_MASK(priv->port_count) &
> > CONFIG_MV88E61XX_PHY_PORTS;
> > + port_mask &= ~(1 << phy);
> > + port_mask |= (1 << CONFIG_MV88E61XX_CPU_PORT);
>
> BIT() ?
I've kept the "style" from the rest of the file.
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
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next prev parent reply other threads:[~2023-06-01 11:03 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-01 9:59 [PATCH v1 0/6] Provide support for mv88e6020 Marvell switch Lukasz Majewski
2023-06-01 10:00 ` [PATCH v1 1/6] net: mv88e61xx: Add support for checking addressing mode Lukasz Majewski
2023-06-01 10:00 ` [PATCH v1 2/6] net: mv88e61xx: Configure PHY ports to also pass packets between them Lukasz Majewski
2023-06-01 10:35 ` Marek Vasut
2023-06-01 11:02 ` Lukasz Majewski [this message]
2023-06-01 11:44 ` Marek Vasut
2023-06-01 16:46 ` Vladimir Oltean
2023-06-02 13:56 ` Lukasz Majewski
2023-06-01 10:00 ` [PATCH v1 3/6] net: mv88e61xx: Clear temporary structs before using them in get_phy_id() Lukasz Majewski
2023-06-01 10:36 ` Marek Vasut
2023-06-01 10:00 ` [PATCH v1 4/6] net: mv88e61xx: Directly access the switch chip Lukasz Majewski
2023-06-01 10:00 ` [PATCH v1 5/6] net: mv88e61xx: Set proper offset when R0_LED/ADDR4 is set on bootstrap Lukasz Majewski
2023-06-01 10:00 ` [PATCH v1 6/6] net: mv88e61xx: Reset switch PHYs when bootstrapped to !NO_CPU Lukasz Majewski
2023-06-01 10:38 ` Marek Vasut
2023-06-01 12:13 ` Lukasz Majewski
2023-06-01 15:16 ` Marek Vasut
-- strict thread matches above, loose matches on Subject: below --
2021-03-17 14:14 [PATCH v1 0/6] Provide support for mv88e6020 Marvell switch Lukasz Majewski
2021-03-17 14:14 ` [PATCH v1 2/6] net: mv88e61xx: Configure PHY ports to also pass packets between them Lukasz Majewski
2021-05-08 6:25 ` Ramon Fried
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