From: Jit Loon Lim <jit.loon.lim@intel.com>
To: u-boot@lists.denx.de
Cc: Jagan Teki <jagan@amarulasolutions.com>, Marek <marex@denx.de>,
Simon <simon.k.r.goldschmidt@gmail.com>,
Tien Fong <tien.fong.chee@intel.com>,
Kok Kiang <kok.kiang.hea@intel.com>,
Raaj <raaj.lokanathan@intel.com>,
Dinesh <dinesh.maniyam@intel.com>,
Boon Khai <boon.khai.ng@intel.com>,
Alif <alif.zakuan.yuslaimi@intel.com>,
Teik Heng <teik.heng.chong@intel.com>,
Hazim <muhammad.hazim.izzat.zamri@intel.com>,
Jit Loon Lim <jit.loon.lim@intel.com>,
Sieu Mun Tang <sieu.mun.tang@intel.com>,
Sin Hui Kho <sin.hui.kho@intel.com>
Subject: [PATCH v1] arm: socfpga: agilex5: Define MMU mapping region for FPGA
Date: Wed, 21 Jun 2023 22:00:57 +0800 [thread overview]
Message-ID: <20230621140057.8787-1-jit.loon.lim@intel.com> (raw)
From: Sin Hui Kho <sin.hui.kho@intel.com>
Add MMU mapping region for FPGA including 512 MB LW HPS2FPGA and
1GB HPS2FPGA.
Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com>
---
arch/arm/mach-socfpga/mmu-arm64_s10.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c
index 0951233cad..c88f0e8632 100644
--- a/arch/arm/mach-socfpga/mmu-arm64_s10.c
+++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c
@@ -36,6 +36,14 @@ static struct mm_region socfpga_agilex5_mem_map[] = {
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN,
}, {
+ /* FPGA 1.5GB */
+ .virt = 0x20000000UL,
+ .phys = 0x20000000UL,
+ .size = 0x60000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+ },{
/* MEM 2GB */
.virt = 0x80000000UL,
.phys = 0x80000000UL,
--
2.26.2
reply other threads:[~2023-06-21 14:01 UTC|newest]
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