From: sbabic@denx.de
To: Adam Ford <aford173@gmail.com>,u-boot@lists.denx.de
Subject: [PATCH 2/2] arm: dts: imx8mp: Sync the DT with kernel 6.4-rc4
Date: Wed, 12 Jul 2023 15:41:14 +0200 (CEST) [thread overview]
Message-ID: <20230712134117.7BF5886A9D@phobos.denx.de> (raw)
In-Reply-To: <20230530224558.9340-2-aford173@gmail.com>
> Several changes have been made to the device tree
> in the kernel, so update that as well as the
> corresponding imx8mp-u-boot.dtsi files to prevent
> breaking the booting.
> Signed-off-by: Adam Ford <aford173@gmail.com>
> Reviewed-by: Fabio Estevam <festevam@denx.de>
> diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi
> index 18d1728e1d..dfb747bb02 100644
> --- a/arch/arm/dts/imx8mp-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mp-u-boot.dtsi
> @@ -44,6 +44,9 @@
>
> &aips3 {
> bootph-pre-ram;
> + spba-bus@30800000 {
> + bootph-pre-ram;
> + };
> };
>
> &iomuxc {
> diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
> index bb916a0948..428c60462e 100644
> --- a/arch/arm/dts/imx8mp.dtsi
> +++ b/arch/arm/dts/imx8mp.dtsi
> @@ -123,6 +123,7 @@
>
> A53_L2: l2-cache0 {
> compatible = "cache";
> + cache-unified;
> cache-level = <2>;
> cache-size = <0x80000>;
> cache-line-size = <64>;
> @@ -379,6 +380,8 @@
> compatible = "fsl,imx8mp-tmu";
> reg = <0x30260000 0x10000>;
> clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
> + nvmem-cells = <&tmu_calib>;
> + nvmem-cell-names = "calib";
> #thermal-sensor-cells = <1>;
> };
>
> @@ -406,12 +409,36 @@
> status = "disabled";
> };
>
> + gpt1: timer@302d0000 {
> + compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
> + reg = <0x302d0000 0x10000>;
> + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>;
> + clock-names = "ipg", "per";
> + };
> +
> + gpt2: timer@302e0000 {
> + compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
> + reg = <0x302e0000 0x10000>;
> + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>;
> + clock-names = "ipg", "per";
> + };
> +
> + gpt3: timer@302f0000 {
> + compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
> + reg = <0x302f0000 0x10000>;
> + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>;
> + clock-names = "ipg", "per";
> + };
> +
> iomuxc: pinctrl@30330000 {
> compatible = "fsl,imx8mp-iomuxc";
> reg = <0x30330000 0x10000>;
> };
>
> - gpr: iomuxc-gpr@30340000 {
> + gpr: syscon@30340000 {
> compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
> reg = <0x30340000 0x10000>;
> };
> @@ -424,27 +451,44 @@
> #address-cells = <1>;
> #size-cells = <1>;
>
> - imx8mp_uid: unique-id@420 {
> + /*
> + * The register address below maps to the MX8M
> + * Fusemap Description Table entries this way.
> + * Assuming
> + * reg = <ADDR SIZE>;
> + * then
> + * Fuse Address = (ADDR * 4) + 0x400
> + * Note that if SIZE is greater than 4, then
> + * each subsequent fuse is located at offset
> + * +0x10 in Fusemap Description Table (e.g.
> + * reg = <0x8 0x8> describes fuses 0x420 and
> + * 0x430).
> + */
> + imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
> reg = <0x8 0x8>;
> };
>
> - cpu_speed_grade: speed-grade@10 {
> + cpu_speed_grade: speed-grade@10 { /* 0x440 */
> reg = <0x10 4>;
> };
>
> - eth_mac1: mac-address@90 {
> + eth_mac1: mac-address@90 { /* 0x640 */
> reg = <0x90 6>;
> };
>
> - eth_mac2: mac-address@96 {
> + eth_mac2: mac-address@96 { /* 0x658 */
> reg = <0x96 6>;
> };
> +
> + tmu_calib: calib@264 { /* 0xd90-0xdc0 */
> + reg = <0x264 0x10>;
> + };
> };
>
> - anatop: anatop@30360000 {
> - compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
> - "syscon";
> + anatop: clock-controller@30360000 {
> + compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop";
> reg = <0x30360000 0x10000>;
> + #clock-cells = <1>;
> };
>
> snvs: snvs@30370000 {
> @@ -523,6 +567,7 @@
> compatible = "fsl,imx8mp-gpc";
> reg = <0x303a0000 0x1000>;
> interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-controller;
> #interrupt-cells = <3>;
>
> @@ -589,7 +634,7 @@
> reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
> };
>
> - pgc_hsiomix: power-domains@17 {
> + pgc_hsiomix: power-domain@17 {
> #power-domain-cells = <0>;
> reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
> clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
> @@ -631,6 +676,14 @@
> reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
> clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
> };
> +
> + pgc_mlmix: power-domain@24 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MP_POWER_DOMAIN_MLMIX>;
> + clocks = <&clk IMX8MP_CLK_ML_AXI>,
> + <&clk IMX8MP_CLK_ML_AHB>,
> + <&clk IMX8MP_CLK_NPU_ROOT>;
> + };
> };
> };
> };
> @@ -693,6 +746,30 @@
> clocks = <&osc_24m>;
> clock-names = "per";
> };
> +
> + gpt6: timer@306e0000 {
> + compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
> + reg = <0x306e0000 0x10000>;
> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>;
> + clock-names = "ipg", "per";
> + };
> +
> + gpt5: timer@306f0000 {
> + compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
> + reg = <0x306f0000 0x10000>;
> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>;
> + clock-names = "ipg", "per";
> + };
> +
> + gpt4: timer@30700000 {
> + compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
> + reg = <0x30700000 0x10000>;
> + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>;
> + clock-names = "ipg", "per";
> + };
> };
>
> aips3: bus@30800000 {
> @@ -702,112 +779,129 @@
> #size-cells = <1>;
> ranges;
>
> - ecspi1: spi@30820000 {
> + spba-bus@30800000 {
> + compatible = "fsl,spba-bus", "simple-bus";
> + reg = <0x30800000 0x100000>;
> #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
> - reg = <0x30820000 0x10000>;
> - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
> - <&clk IMX8MP_CLK_ECSPI1_ROOT>;
> - clock-names = "ipg", "per";
> - dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> - };
> + #size-cells = <1>;
> + ranges;
>
> - ecspi2: spi@30830000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
> - reg = <0x30830000 0x10000>;
> - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
> - <&clk IMX8MP_CLK_ECSPI2_ROOT>;
> - clock-names = "ipg", "per";
> - dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> - };
> + ecspi1: spi@30820000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
> + reg = <0x30820000 0x10000>;
> + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
> + <&clk IMX8MP_CLK_ECSPI1_ROOT>;
> + clock-names = "ipg", "per";
> + assigned-clock-rates = <80000000>;
> + assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
> + dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
>
> - ecspi3: spi@30840000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
> - reg = <0x30840000 0x10000>;
> - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
> - <&clk IMX8MP_CLK_ECSPI3_ROOT>;
> - clock-names = "ipg", "per";
> - dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> - };
> + ecspi2: spi@30830000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
> + reg = <0x30830000 0x10000>;
> + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
> + <&clk IMX8MP_CLK_ECSPI2_ROOT>;
> + clock-names = "ipg", "per";
> + assigned-clock-rates = <80000000>;
> + assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
> + dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
>
> - uart1: serial@30860000 {
> - compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
> - reg = <0x30860000 0x10000>;
> - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
> - <&clk IMX8MP_CLK_UART1_ROOT>;
> - clock-names = "ipg", "per";
> - dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> - };
> + ecspi3: spi@30840000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
> + reg = <0x30840000 0x10000>;
> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
> + <&clk IMX8MP_CLK_ECSPI3_ROOT>;
> + clock-names = "ipg", "per";
> + assigned-clock-rates = <80000000>;
> + assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
> + dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
>
> - uart3: serial@30880000 {
> - compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
> - reg = <0x30880000 0x10000>;
> - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
> - <&clk IMX8MP_CLK_UART3_ROOT>;
> - clock-names = "ipg", "per";
> - dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> - };
> + uart1: serial@30860000 {
> + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
> + reg = <0x30860000 0x10000>;
> + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
> + <&clk IMX8MP_CLK_UART1_ROOT>;
> + clock-names = "ipg", "per";
> + dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
>
> - uart2: serial@30890000 {
> - compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
> - reg = <0x30890000 0x10000>;
> - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
> - <&clk IMX8MP_CLK_UART2_ROOT>;
> - clock-names = "ipg", "per";
> - dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> - };
> + uart3: serial@30880000 {
> + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
> + reg = <0x30880000 0x10000>;
> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
> + <&clk IMX8MP_CLK_UART3_ROOT>;
> + clock-names = "ipg", "per";
> + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
>
> - flexcan1: can@308c0000 {
> - compatible = "fsl,imx8mp-flexcan";
> - reg = <0x308c0000 0x10000>;
> - interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
> - <&clk IMX8MP_CLK_CAN1_ROOT>;
> - clock-names = "ipg", "per";
> - assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
> - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
> - assigned-clock-rates = <40000000>;
> - fsl,clk-source = /bits/ 8 <0>;
> - fsl,stop-mode = <&gpr 0x10 4>;
> - status = "disabled";
> - };
> + uart2: serial@30890000 {
> + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
> + reg = <0x30890000 0x10000>;
> + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
> + <&clk IMX8MP_CLK_UART2_ROOT>;
> + clock-names = "ipg", "per";
> + dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
>
> - flexcan2: can@308d0000 {
> - compatible = "fsl,imx8mp-flexcan";
> - reg = <0x308d0000 0x10000>;
> - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
> - <&clk IMX8MP_CLK_CAN2_ROOT>;
> - clock-names = "ipg", "per";
> - assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
> - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
> - assigned-clock-rates = <40000000>;
> - fsl,clk-source = /bits/ 8 <0>;
> - fsl,stop-mode = <&gpr 0x10 5>;
> - status = "disabled";
> + flexcan1: can@308c0000 {
> + compatible = "fsl,imx8mp-flexcan";
> + reg = <0x308c0000 0x10000>;
> + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
> + <&clk IMX8MP_CLK_CAN1_ROOT>;
> + clock-names = "ipg", "per";
> + assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
> + assigned-clock-rates = <40000000>;
> + fsl,clk-source = /bits/ 8 <0>;
> + fsl,stop-mode = <&gpr 0x10 4>;
> + status = "disabled";
> + };
> +
> + flexcan2: can@308d0000 {
> + compatible = "fsl,imx8mp-flexcan";
> + reg = <0x308d0000 0x10000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
> + <&clk IMX8MP_CLK_CAN2_ROOT>;
> + clock-names = "ipg", "per";
> + assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
> + assigned-clock-rates = <40000000>;
> + fsl,clk-source = /bits/ 8 <0>;
> + fsl,stop-mode = <&gpr 0x10 5>;
> + status = "disabled";
> + };
> };
>
> crypto: crypto@30900000 {
> @@ -1063,11 +1157,11 @@
> noc_opp_table: opp-table {
> compatible = "operating-points-v2";
>
> - opp-200M {
> + opp-200000000 {
> opp-hz = /bits/ 64 <200000000>;
> };
>
> - opp-1000M {
> + opp-1000000000 {
> opp-hz = /bits/ 64 <1000000000>;
> };
> };
> @@ -1080,10 +1174,78 @@
> #size-cells = <1>;
> ranges;
>
> + mipi_dsi: dsi@32e60000 {
> + compatible = "fsl,imx8mp-mipi-dsim";
> + reg = <0x32e60000 0x400>;
> + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
> + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
> + clock-names = "bus_clk", "sclk_mipi";
> + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>,
> + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
> + <&clk IMX8MP_CLK_24M>;
> + assigned-clock-rates = <200000000>, <24000000>;
> + samsung,pll-clock-frequency = <24000000>;
> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + dsim_from_lcdif1: endpoint {
> + remote-endpoint = <&lcdif1_to_dsim>;
> + };
> + };
> + };
> + };
> +
> + lcdif1: display-controller@32e80000 {
> + compatible = "fsl,imx8mp-lcdif";
> + reg = <0x32e80000 0x10000>;
> + clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
> + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
> + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
> + clock-names = "pix", "axi", "disp_axi";
> + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>;
> + status = "disabled";
> +
> + port {
> + lcdif1_to_dsim: endpoint {
> + remote-endpoint = <&dsim_from_lcdif1>;
> + };
> + };
> + };
> +
> + lcdif2: display-controller@32e90000 {
> + compatible = "fsl,imx8mp-lcdif";
> + reg = <0x32e90000 0x10000>;
> + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
> + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
> + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
> + clock-names = "pix", "axi", "disp_axi";
> + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;
> + status = "disabled";
> +
> + port {
> + lcdif2_to_ldb: endpoint {
> + remote-endpoint = <&ldb_from_lcdif2>;
> + };
> + };
> + };
> +
> media_blk_ctrl: blk-ctrl@32ec0000 {
> compatible = "fsl,imx8mp-media-blk-ctrl",
> "syscon";
> reg = <0x32ec0000 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> power-domains = <&pgc_mediamix>,
> <&pgc_mipi_phy1>,
> <&pgc_mipi_phy1>,
> @@ -1122,12 +1284,55 @@
> "disp1", "disp2", "isp", "phy";
>
> assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
> - <&clk IMX8MP_CLK_MEDIA_APB>;
> + <&clk IMX8MP_CLK_MEDIA_APB>,
> + <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
> + <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
> + <&clk IMX8MP_VIDEO_PLL1>;
> assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
> - <&clk IMX8MP_SYS_PLL1_800M>;
> - assigned-clock-rates = <500000000>, <200000000>;
> -
> + <&clk IMX8MP_SYS_PLL1_800M>,
> + <&clk IMX8MP_VIDEO_PLL1_OUT>,
> + <&clk IMX8MP_VIDEO_PLL1_OUT>;
> + assigned-clock-rates = <500000000>, <200000000>,
> + <0>, <0>, <1039500000>;
> #power-domain-cells = <1>;
> +
> + lvds_bridge: bridge@5c {
> + compatible = "fsl,imx8mp-ldb";
> + reg = <0x5c 0x4>, <0x128 0x4>;
> + reg-names = "ldb", "lvds";
> + clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
> + clock-names = "ldb";
> + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
> + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + ldb_from_lcdif2: endpoint {
> + remote-endpoint = <&lcdif2_to_ldb>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + ldb_lvds_ch0: endpoint {
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> +
> + ldb_lvds_ch1: endpoint {
> + };
> + };
> + };
> + };
> };
>
> pcie_phy: pcie-phy@32f00000 {
> @@ -1158,6 +1363,7 @@
> <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>;
> interconnect-names = "noc-pcie", "usb1", "usb2", "pcie";
> #power-domain-cells = <1>;
> + #clock-cells = <0>;
> };
> };
>
> @@ -1165,6 +1371,13 @@
> compatible = "fsl,imx8mp-pcie";
> reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
> reg-names = "dbi", "config";
> + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> + <&clk IMX8MP_CLK_HSIO_AXI>,
> + <&clk IMX8MP_CLK_PCIE_ROOT>;
> + clock-names = "pcie", "pcie_bus", "pcie_aux";
> + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
> + assigned-clock-rates = <10000000>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
> #address-cells = <3>;
> #size-cells = <2>;
> device_type = "pci";
> @@ -1192,6 +1405,32 @@
> status = "disabled";
> };
>
> + pcie_ep: pcie-ep@33800000 {
> + compatible = "fsl,imx8mp-pcie-ep";
> + reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;
> + reg-names = "dbi", "addr_space";
> + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> + <&clk IMX8MP_CLK_HSIO_AXI>,
> + <&clk IMX8MP_CLK_PCIE_ROOT>;
> + clock-names = "pcie", "pcie_bus", "pcie_aux";
> + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
> + assigned-clock-rates = <10000000>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
> + num-lanes = <1>;
> + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
> + interrupt-names = "dma";
> + fsl,max-link-speed = <3>;
> + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
> + resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
> + <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
> + reset-names = "apps", "turnoff";
> + phys = <&pcie_phy>;
> + phy-names = "pcie-phy";
> + num-ib-windows = <4>;
> + num-ob-windows = <4>;
> + status = "disabled";
> + };
> +
> gpu3d: gpu@38000000 {
> compatible = "vivante,gc";
> reg = <0x38000000 0x8000>;
> @@ -1223,6 +1462,28 @@
> power-domains = <&pgc_gpu2d>;
> };
>
> + vpu_g1: video-codec@38300000 {
> + compatible = "nxp,imx8mm-vpu-g1";
> + reg = <0x38300000 0x10000>;
> + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
> + assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;
> + assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
> + assigned-clock-rates = <600000000>;
> + power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;
> + };
> +
> + vpu_g2: video-codec@38310000 {
> + compatible = "nxp,imx8mq-vpu-g2";
> + reg = <0x38310000 0x10000>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
> + assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
> + assigned-clock-rates = <500000000>;
> + power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;
> + };
> +
> vpumix_blk_ctrl: blk-ctrl@38330000 {
> compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon";
> reg = <0x38330000 0x100>;
> @@ -1234,6 +1495,9 @@
> <&clk IMX8MP_CLK_VPU_G2_ROOT>,
> <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
> clock-names = "g1", "g2", "vc8000e";
> + assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>;
> + assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
> + assigned-clock-rates = <600000000>, <600000000>;
> interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>,
> <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>,
> <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;
> @@ -1279,7 +1543,7 @@
> reg = <0x32f10100 0x8>,
> <0x381f0000 0x20>;
> clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> - <&clk IMX8MP_CLK_USB_ROOT>;
> + <&clk IMX8MP_CLK_USB_SUSP>;
> clock-names = "hsio", "suspend";
> interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
> @@ -1292,9 +1556,9 @@
> usb_dwc3_0: usb@38100000 {
> compatible = "snps,dwc3";
> reg = <0x38100000 0x10000>;
> - clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
> + clocks = <&clk IMX8MP_CLK_USB_ROOT>,
> <&clk IMX8MP_CLK_USB_CORE_REF>,
> - <&clk IMX8MP_CLK_USB_ROOT>;
> + <&clk IMX8MP_CLK_USB_SUSP>;
> clock-names = "bus_early", "ref", "suspend";
> interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> phys = <&usb3_phy0>, <&usb3_phy0>;
> @@ -1321,7 +1585,7 @@
> reg = <0x32f10108 0x8>,
> <0x382f0000 0x20>;
> clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> - <&clk IMX8MP_CLK_USB_ROOT>;
> + <&clk IMX8MP_CLK_USB_SUSP>;
> clock-names = "hsio", "suspend";
> interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
> @@ -1334,9 +1598,9 @@
> usb_dwc3_1: usb@38200000 {
> compatible = "snps,dwc3";
> reg = <0x38200000 0x10000>;
> - clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
> + clocks = <&clk IMX8MP_CLK_USB_ROOT>,
> <&clk IMX8MP_CLK_USB_CORE_REF>,
> - <&clk IMX8MP_CLK_USB_ROOT>;
> + <&clk IMX8MP_CLK_USB_SUSP>;
> clock-names = "bus_early", "ref", "suspend";
> interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> phys = <&usb3_phy1>, <&usb3_phy1>;
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
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HRB 165235 Munich, Office: Kirchenstr.5, 82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
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next prev parent reply other threads:[~2023-07-12 13:43 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-30 22:45 [PATCH 1/2] clk: imx8mp: Update clocks based on kernel 6.4-RC4 Adam Ford
2023-05-30 22:45 ` [PATCH 2/2] arm: dts: imx8mp: Sync the DT with kernel 6.4-rc4 Adam Ford
2023-05-30 23:10 ` Fabio Estevam
2023-07-12 13:41 ` sbabic [this message]
2023-05-30 23:10 ` [PATCH 1/2] clk: imx8mp: Update clocks based on kernel 6.4-RC4 Fabio Estevam
2023-05-31 15:44 ` Tim Harvey
2023-05-31 15:49 ` Adam Ford
2023-05-31 15:58 ` Tim Harvey
2023-07-12 13:40 ` sbabic
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