* [PATCH] arm: mvebu: AC5: Use finer grained memory map
@ 2023-10-27 0:44 Chris Packham
2023-10-27 0:54 ` Tom Rini
2024-01-10 14:08 ` Stefan Roese
0 siblings, 2 replies; 4+ messages in thread
From: Chris Packham @ 2023-10-27 0:44 UTC (permalink / raw)
To: u-boot; +Cc: Chris Packham, Simon Glass, Stefan Roese, Tom Rini
The ATF implementation for AC5/AC5X ends up with bl31 living in some
internal SRAM. This is in the middle of the large MMIO region that we
were using. Adjust this to be finer grained blocks based on the address
map from the AC5X Family Control and Management Subsystem Functional
Datasheet.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
---
arch/arm/mach-mvebu/alleycat5/cpu.c | 66 ++++++++++++++++++++++-------
1 file changed, 51 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c
index 8204d9627515..0f72ae1709be 100644
--- a/arch/arm/mach-mvebu/alleycat5/cpu.c
+++ b/arch/arm/mach-mvebu/alleycat5/cpu.c
@@ -16,7 +16,10 @@
DECLARE_GLOBAL_DATA_PTR;
-#define RAM_SIZE SZ_1G
+#define AC5_PTE_BLOCK_DEVICE \
+ (PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | \
+ PTE_BLOCK_NON_SHARE | \
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN)
static struct mm_region ac5_mem_map[] = {
{
@@ -31,30 +34,63 @@ static struct mm_region ac5_mem_map[] = {
.phys = 0x00000000,
.virt = 0xa0000000,
.size = 0x100000,
-
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ .attrs = AC5_PTE_BLOCK_DEVICE,
},
{
/* MMIO regions */
.phys = 0x100000,
.virt = 0x100000,
.size = 0x3ff00000,
-
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ .attrs = AC5_PTE_BLOCK_DEVICE,
},
{
- /* MMIO regions */
.phys = 0x7F000000,
.virt = 0x7F000000,
- .size = 0x21000000,
-
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ .size = SZ_8M,
+ .attrs = AC5_PTE_BLOCK_DEVICE,
+ },
+ {
+ .phys = 0x7F800000,
+ .virt = 0x7F800000,
+ .size = SZ_4M,
+ .attrs = AC5_PTE_BLOCK_DEVICE,
+ },
+ {
+ .phys = 0x7FC00000,
+ .virt = 0x7FC00000,
+ .size = SZ_512K,
+ .attrs = AC5_PTE_BLOCK_DEVICE,
+ },
+ {
+ .phys = 0x7FC80000,
+ .virt = 0x7FC80000,
+ .size = SZ_512K,
+ .attrs = AC5_PTE_BLOCK_DEVICE,
+ },
+ {
+ .phys = 0x7FD00000,
+ .virt = 0x7FD00000,
+ .size = SZ_512K,
+ .attrs = AC5_PTE_BLOCK_DEVICE,
+ },
+ /* ATF region 0x7FE00000-0x7FE20000 not mapped */
+ {
+ .phys = 0x7FE80000,
+ .virt = 0x7FE80000,
+ .size = SZ_512K,
+ .attrs = AC5_PTE_BLOCK_DEVICE,
+ },
+ {
+ .phys = 0x7FFF0000,
+ .virt = 0x7FFF0000,
+ .size = SZ_1M,
+ .attrs = AC5_PTE_BLOCK_DEVICE,
+ },
+ {
+ .phys = 0x80000000,
+ .virt = 0x80000000,
+ .size = SZ_2G,
+ .attrs = AC5_PTE_BLOCK_DEVICE,
},
{
0,
--
2.42.0
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] arm: mvebu: AC5: Use finer grained memory map
2023-10-27 0:44 [PATCH] arm: mvebu: AC5: Use finer grained memory map Chris Packham
@ 2023-10-27 0:54 ` Tom Rini
2023-10-27 5:04 ` Chris Packham
2024-01-10 14:08 ` Stefan Roese
1 sibling, 1 reply; 4+ messages in thread
From: Tom Rini @ 2023-10-27 0:54 UTC (permalink / raw)
To: Chris Packham; +Cc: u-boot, Simon Glass, Stefan Roese
[-- Attachment #1: Type: text/plain, Size: 537 bytes --]
On Fri, Oct 27, 2023 at 01:44:11PM +1300, Chris Packham wrote:
> The ATF implementation for AC5/AC5X ends up with bl31 living in some
> internal SRAM. This is in the middle of the large MMIO region that we
> were using. Adjust this to be finer grained blocks based on the address
> map from the AC5X Family Control and Management Subsystem Functional
> Datasheet.
>
> Signed-off-by: Chris Packham <judge.packham@gmail.com>
Does this mean we don't need to revert that other patch, or is this
unrelated? Thanks.
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] arm: mvebu: AC5: Use finer grained memory map
2023-10-27 0:54 ` Tom Rini
@ 2023-10-27 5:04 ` Chris Packham
0 siblings, 0 replies; 4+ messages in thread
From: Chris Packham @ 2023-10-27 5:04 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot, Simon Glass, Stefan Roese
Hi Tom,
On Fri, 27 Oct 2023, 1:54 pm Tom Rini, <trini@konsulko.com> wrote:
> On Fri, Oct 27, 2023 at 01:44:11PM +1300, Chris Packham wrote:
>
> > The ATF implementation for AC5/AC5X ends up with bl31 living in some
> > internal SRAM. This is in the middle of the large MMIO region that we
> > were using. Adjust this to be finer grained blocks based on the address
> > map from the AC5X Family Control and Management Subsystem Functional
> > Datasheet.
> >
> > Signed-off-by: Chris Packham <judge.packham@gmail.com>
>
> Does this mean we don't need to revert that other patch, or is this
> unrelated? Thanks.
>
Unrelated. Just something I found along the way.
I had hope it would fix the hang but with or without this change the HAFDBS
support causes issues for me.
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] arm: mvebu: AC5: Use finer grained memory map
2023-10-27 0:44 [PATCH] arm: mvebu: AC5: Use finer grained memory map Chris Packham
2023-10-27 0:54 ` Tom Rini
@ 2024-01-10 14:08 ` Stefan Roese
1 sibling, 0 replies; 4+ messages in thread
From: Stefan Roese @ 2024-01-10 14:08 UTC (permalink / raw)
To: Chris Packham, u-boot; +Cc: Simon Glass, Tom Rini
On 10/27/23 02:44, Chris Packham wrote:
> The ATF implementation for AC5/AC5X ends up with bl31 living in some
> internal SRAM. This is in the middle of the large MMIO region that we
> were using. Adjust this to be finer grained blocks based on the address
> map from the AC5X Family Control and Management Subsystem Functional
> Datasheet.
>
> Signed-off-by: Chris Packham <judge.packham@gmail.com>
Applied to u-boot-marvell/master
Thanks,
Stefan
> ---
>
> arch/arm/mach-mvebu/alleycat5/cpu.c | 66 ++++++++++++++++++++++-------
> 1 file changed, 51 insertions(+), 15 deletions(-)
>
> diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c
> index 8204d9627515..0f72ae1709be 100644
> --- a/arch/arm/mach-mvebu/alleycat5/cpu.c
> +++ b/arch/arm/mach-mvebu/alleycat5/cpu.c
> @@ -16,7 +16,10 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -#define RAM_SIZE SZ_1G
> +#define AC5_PTE_BLOCK_DEVICE \
> + (PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | \
> + PTE_BLOCK_NON_SHARE | \
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN)
>
> static struct mm_region ac5_mem_map[] = {
> {
> @@ -31,30 +34,63 @@ static struct mm_region ac5_mem_map[] = {
> .phys = 0x00000000,
> .virt = 0xa0000000,
> .size = 0x100000,
> -
> - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> - PTE_BLOCK_NON_SHARE |
> - PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + .attrs = AC5_PTE_BLOCK_DEVICE,
> },
> {
> /* MMIO regions */
> .phys = 0x100000,
> .virt = 0x100000,
> .size = 0x3ff00000,
> -
> - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> - PTE_BLOCK_NON_SHARE |
> - PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + .attrs = AC5_PTE_BLOCK_DEVICE,
> },
> {
> - /* MMIO regions */
> .phys = 0x7F000000,
> .virt = 0x7F000000,
> - .size = 0x21000000,
> -
> - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> - PTE_BLOCK_NON_SHARE |
> - PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + .size = SZ_8M,
> + .attrs = AC5_PTE_BLOCK_DEVICE,
> + },
> + {
> + .phys = 0x7F800000,
> + .virt = 0x7F800000,
> + .size = SZ_4M,
> + .attrs = AC5_PTE_BLOCK_DEVICE,
> + },
> + {
> + .phys = 0x7FC00000,
> + .virt = 0x7FC00000,
> + .size = SZ_512K,
> + .attrs = AC5_PTE_BLOCK_DEVICE,
> + },
> + {
> + .phys = 0x7FC80000,
> + .virt = 0x7FC80000,
> + .size = SZ_512K,
> + .attrs = AC5_PTE_BLOCK_DEVICE,
> + },
> + {
> + .phys = 0x7FD00000,
> + .virt = 0x7FD00000,
> + .size = SZ_512K,
> + .attrs = AC5_PTE_BLOCK_DEVICE,
> + },
> + /* ATF region 0x7FE00000-0x7FE20000 not mapped */
> + {
> + .phys = 0x7FE80000,
> + .virt = 0x7FE80000,
> + .size = SZ_512K,
> + .attrs = AC5_PTE_BLOCK_DEVICE,
> + },
> + {
> + .phys = 0x7FFF0000,
> + .virt = 0x7FFF0000,
> + .size = SZ_1M,
> + .attrs = AC5_PTE_BLOCK_DEVICE,
> + },
> + {
> + .phys = 0x80000000,
> + .virt = 0x80000000,
> + .size = SZ_2G,
> + .attrs = AC5_PTE_BLOCK_DEVICE,
> },
> {
> 0,
Viele Grüße,
Stefan Roese
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de
^ permalink raw reply [flat|nested] 4+ messages in thread
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2023-10-27 0:44 [PATCH] arm: mvebu: AC5: Use finer grained memory map Chris Packham
2023-10-27 0:54 ` Tom Rini
2023-10-27 5:04 ` Chris Packham
2024-01-10 14:08 ` Stefan Roese
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