[PATCH RFC 0/2] Unify K3 initial memory map

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* [PATCH RFC 0/2] Unify K3 initial memory map
@ 2023-11-22 15:14 Andrew Davis
  2023-11-22 15:14 ` [PATCH RFC 1/2] arm: mach-k3: Remove non-cached memory map areas Andrew Davis
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Andrew Davis @ 2023-11-22 15:14 UTC (permalink / raw)
  To: Neha Malcom Francis, Vignesh Raghavendra, Nishanth Menon,
	Simon Glass, Tom Rini, Apurva Nandan
  Cc: u-boot, Andrew Davis

Hello all,

This is just an RFC as it probably breaks remoteproc loading.
I wanted to post anyway as the complexity of having a dedicated
memory map for each SoC came up in a different series.

Or maybe we can take this now and that will expose the issue in
remoteproc loading better and force someone to go fix it. :)

This series depends on this[0].

Thanks,
Andrew

[0] https://patchwork.ozlabs.org/project/uboot/patch/20231106165205.22066-1-afd@ti.com/

Andrew Davis (2):
  arm: mach-k3: Remove non-cached memory map areas
  arm: mach-k3: Merge initial memory maps

 arch/arm/mach-k3/arm64-mmu.c | 253 +----------------------------------
 1 file changed, 2 insertions(+), 251 deletions(-)

-- 
2.39.2


^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PATCH RFC 1/2] arm: mach-k3: Remove non-cached memory map areas
  2023-11-22 15:14 [PATCH RFC 0/2] Unify K3 initial memory map Andrew Davis
@ 2023-11-22 15:14 ` Andrew Davis
  2023-11-22 15:14 ` [PATCH RFC 2/2] arm: mach-k3: Merge initial memory maps Andrew Davis
  2023-11-23 16:29 ` [PATCH RFC 0/2] Unify K3 initial memory map Nishanth Menon
  2 siblings, 0 replies; 4+ messages in thread
From: Andrew Davis @ 2023-11-22 15:14 UTC (permalink / raw)
  To: Neha Malcom Francis, Vignesh Raghavendra, Nishanth Menon,
	Simon Glass, Tom Rini, Apurva Nandan
  Cc: u-boot, Andrew Davis

All normal memory areas should be mapped as such.

We added these un-cached holes in our memory map to hack around the
remoteproc driver missing the proper cache maintenance operations.

The problem is having these non-cached memory map areas causes stability
issues later in system operation due to the nature of the K3 coherency
architecture. Plus these are board specific carveouts and instead
should have been added at the board level, not here in the SoC common
code area.

Remove these non-cached memory map areas.

Signed-off-by: Andrew Davis <afd@ti.com>
---
 arch/arm/mach-k3/arm64-mmu.c | 48 +++---------------------------------
 1 file changed, 3 insertions(+), 45 deletions(-)

diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
index 471295fa7eb..a5afdf9f4a7 100644
--- a/arch/arm/mach-k3/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64-mmu.c
@@ -25,19 +25,7 @@ struct mm_region am654_mem_map[] = {
 	}, {
 		.virt = 0x80000000UL,
 		.phys = 0x80000000UL,
-		.size = 0x20000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-		.virt = 0xa0000000UL,
-		.phys = 0xa0000000UL,
-		.size = 0x02100000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-		.virt = 0xa2100000UL,
-		.phys = 0xa2100000UL,
-		.size = 0x5df00000UL,
+		.size = 0x80000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
 	}, {
@@ -76,19 +64,7 @@ struct mm_region j721e_mem_map[] = {
 	}, {
 		.virt = 0x80000000UL,
 		.phys = 0x80000000UL,
-		.size = 0x20000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-		.virt = 0xa0000000UL,
-		.phys = 0xa0000000UL,
-		.size = 0x1bc00000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
-			 PTE_BLOCK_NON_SHARE
-	}, {
-		.virt = 0xbbc00000UL,
-		.phys = 0xbbc00000UL,
-		.size = 0x44400000UL,
+		.size = 0x80000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
 	}, {
@@ -104,12 +80,6 @@ struct mm_region j721e_mem_map[] = {
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		.virt = 0x4d80000000UL,
-		.phys = 0x4d80000000UL,
-		.size = 0x0002000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
-			 PTE_BLOCK_INNER_SHARE
 	}, {
 		/* List terminator */
 		0,
@@ -131,19 +101,7 @@ struct mm_region j7200_mem_map[] = {
 	}, {
 		.virt = 0x80000000UL,
 		.phys = 0x80000000UL,
-		.size = 0x20000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-		.virt = 0xa0000000UL,
-		.phys = 0xa0000000UL,
-		.size = 0x04800000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
-			 PTE_BLOCK_NON_SHARE
-	}, {
-		.virt = 0xa4800000UL,
-		.phys = 0xa4800000UL,
-		.size = 0x5b800000UL,
+		.size = 0x80000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
 	}, {
-- 
2.39.2


^ permalink raw reply related	[flat|nested] 4+ messages in thread

* [PATCH RFC 2/2] arm: mach-k3: Merge initial memory maps
  2023-11-22 15:14 [PATCH RFC 0/2] Unify K3 initial memory map Andrew Davis
  2023-11-22 15:14 ` [PATCH RFC 1/2] arm: mach-k3: Remove non-cached memory map areas Andrew Davis
@ 2023-11-22 15:14 ` Andrew Davis
  2023-11-23 16:29 ` [PATCH RFC 0/2] Unify K3 initial memory map Nishanth Menon
  2 siblings, 0 replies; 4+ messages in thread
From: Andrew Davis @ 2023-11-22 15:14 UTC (permalink / raw)
  To: Neha Malcom Francis, Vignesh Raghavendra, Nishanth Menon,
	Simon Glass, Tom Rini, Apurva Nandan
  Cc: u-boot, Andrew Davis

The Device vs Normal memory map is the same for all K3 SoCs. Merge
the SoC specific maps into one.

Signed-off-by: Andrew Davis <afd@ti.com>
---
 arch/arm/mach-k3/arm64-mmu.c | 211 +----------------------------------
 1 file changed, 2 insertions(+), 209 deletions(-)

diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
index a5afdf9f4a7..cfd3b40d54c 100644
--- a/arch/arm/mach-k3/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64-mmu.c
@@ -13,8 +13,7 @@
 #include <asm/system.h>
 #include <asm/armv8/mmu.h>
 
-#ifdef CONFIG_SOC_K3_AM654
-struct mm_region am654_mem_map[] = {
+struct mm_region k3_mem_map[] = {
 	{
 		.virt = 0x0UL,
 		.phys = 0x0UL,
@@ -47,210 +46,4 @@ struct mm_region am654_mem_map[] = {
 	}
 };
 
-struct mm_region *mem_map = am654_mem_map;
-#endif /* CONFIG_SOC_K3_AM654 */
-
-#ifdef CONFIG_SOC_K3_J721E
-
-#ifdef CONFIG_TARGET_J721E_A72_EVM
-struct mm_region j721e_mem_map[] = {
-	{
-		.virt = 0x0UL,
-		.phys = 0x0UL,
-		.size = 0x80000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-			 PTE_BLOCK_NON_SHARE |
-			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		.virt = 0x80000000UL,
-		.phys = 0x80000000UL,
-		.size = 0x80000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-		.virt = 0x880000000UL,
-		.phys = 0x880000000UL,
-		.size = 0x80000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-		.virt = 0x500000000UL,
-		.phys = 0x500000000UL,
-		.size = 0x400000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-			 PTE_BLOCK_NON_SHARE |
-			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		/* List terminator */
-		0,
-	}
-};
-
-struct mm_region *mem_map = j721e_mem_map;
-#endif /* CONFIG_TARGET_J721E_A72_EVM */
-
-#ifdef CONFIG_TARGET_J7200_A72_EVM
-struct mm_region j7200_mem_map[] = {
-	{
-		.virt = 0x0UL,
-		.phys = 0x0UL,
-		.size = 0x80000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-			 PTE_BLOCK_NON_SHARE |
-			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		.virt = 0x80000000UL,
-		.phys = 0x80000000UL,
-		.size = 0x80000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-		.virt = 0x880000000UL,
-		.phys = 0x880000000UL,
-		.size = 0x80000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-		.virt = 0x500000000UL,
-		.phys = 0x500000000UL,
-		.size = 0x400000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-			 PTE_BLOCK_NON_SHARE |
-			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		/* List terminator */
-		0,
-	}
-};
-
-struct mm_region *mem_map = j7200_mem_map;
-#endif /* CONFIG_TARGET_J7200_A72_EVM */
-
-#endif /* CONFIG_SOC_K3_J721E */
-
-#ifdef CONFIG_SOC_K3_J721S2
-struct mm_region j721s2_mem_map[] = {
-	{
-		.virt = 0x0UL,
-		.phys = 0x0UL,
-		.size = 0x80000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-			 PTE_BLOCK_NON_SHARE |
-			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		.virt = 0x80000000UL,
-		.phys = 0x80000000UL,
-		.size = 0x80000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-		.virt = 0x880000000UL,
-		.phys = 0x880000000UL,
-		.size = 0x80000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-		.virt = 0x500000000UL,
-		.phys = 0x500000000UL,
-		.size = 0x400000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-			 PTE_BLOCK_NON_SHARE |
-			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		/* List terminator */
-		0,
-	}
-};
-
-struct mm_region *mem_map = j721s2_mem_map;
-
-#endif /* CONFIG_SOC_K3_J721S2 */
-
-#if defined(CONFIG_SOC_K3_AM625) || defined(CONFIG_SOC_K3_AM62A7)
-
-struct mm_region am62_mem_map[] = {
-	{
-		.virt = 0x0UL,
-		.phys = 0x0UL,
-		.size = 0x80000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-			 PTE_BLOCK_NON_SHARE |
-			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		.virt = 0x80000000UL,
-		.phys = 0x80000000UL,
-		.size = 0x1E780000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			PTE_BLOCK_INNER_SHARE
-	}, {
-		.virt = 0xA0000000UL,
-		.phys = 0xA0000000UL,
-		.size = 0x60000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-
-	}, {
-		.virt = 0x880000000UL,
-		.phys = 0x880000000UL,
-		.size = 0x80000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-		.virt = 0x500000000UL,
-		.phys = 0x500000000UL,
-		.size = 0x400000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-			 PTE_BLOCK_NON_SHARE |
-			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		/* List terminator */
-		0,
-	}
-};
-
-struct mm_region *mem_map = am62_mem_map;
-#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */
-
-#ifdef CONFIG_SOC_K3_AM642
-
-struct mm_region am64_mem_map[] = {
-	{
-		.virt = 0x0UL,
-		.phys = 0x0UL,
-		.size = 0x80000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-			 PTE_BLOCK_NON_SHARE |
-			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		.virt = 0x80000000UL,
-		.phys = 0x80000000UL,
-		.size = 0x1E800000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			PTE_BLOCK_INNER_SHARE
-	}, {
-		.virt = 0xA0000000UL,
-		.phys = 0xA0000000UL,
-		.size = 0x60000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-		.virt = 0x880000000UL,
-		.phys = 0x880000000UL,
-		.size = 0x80000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-		.virt = 0x500000000UL,
-		.phys = 0x500000000UL,
-		.size = 0x400000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-			 PTE_BLOCK_NON_SHARE |
-			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		/* List terminator */
-		0,
-	}
-};
-
-struct mm_region *mem_map = am64_mem_map;
-#endif /* CONFIG_SOC_K3_AM642 */
+struct mm_region *mem_map = k3_mem_map;
-- 
2.39.2


^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [PATCH RFC 0/2] Unify K3 initial memory map
  2023-11-22 15:14 [PATCH RFC 0/2] Unify K3 initial memory map Andrew Davis
  2023-11-22 15:14 ` [PATCH RFC 1/2] arm: mach-k3: Remove non-cached memory map areas Andrew Davis
  2023-11-22 15:14 ` [PATCH RFC 2/2] arm: mach-k3: Merge initial memory maps Andrew Davis
@ 2023-11-23 16:29 ` Nishanth Menon
  2 siblings, 0 replies; 4+ messages in thread
From: Nishanth Menon @ 2023-11-23 16:29 UTC (permalink / raw)
  To: Andrew Davis
  Cc: Neha Malcom Francis, Vignesh Raghavendra, Simon Glass, Tom Rini,
	Apurva Nandan, u-boot

On 09:14-20231122, Andrew Davis wrote:
> Hello all,
> 
> This is just an RFC as it probably breaks remoteproc loading.
> I wanted to post anyway as the complexity of having a dedicated
> memory map for each SoC came up in a different series.
> 
> Or maybe we can take this now and that will expose the issue in
> remoteproc loading better and force someone to go fix it. :)
> 
> This series depends on this[0].
> 
> Thanks,
> Andrew
> 
> [0] https://patchwork.ozlabs.org/project/uboot/patch/20231106165205.22066-1-afd@ti.com/
> 
> Andrew Davis (2):
>   arm: mach-k3: Remove non-cached memory map areas
>   arm: mach-k3: Merge initial memory maps
> 
>  arch/arm/mach-k3/arm64-mmu.c | 253 +----------------------------------
>  1 file changed, 2 insertions(+), 251 deletions(-)
> 
> -- 
> 2.39.2
> 
Could you rebase and submit as non-RFC? Please free to add:

Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>

tested along with the v2 of dependency patch https://lore.kernel.org/all/20231122211218.607757-1-afd@ti.com/
on top of:
next 054222eb68f6 Merge branch '2023-11-22-TI-K3-cleanups' into next

platforms tested:
beagleplay-gp-uart
j721s2-evm
am68_sk-fs
j721e-sk
j721e-idk-gw
j7200-hsevm
j7200-evm
am64xx-hsevm
am64xx_sk-fs
am62xx_sk-fs
am62xx-sk
am62axx_sk-fs

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2023-11-23 16:29 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-11-22 15:14 [PATCH RFC 0/2] Unify K3 initial memory map Andrew Davis
2023-11-22 15:14 ` [PATCH RFC 1/2] arm: mach-k3: Remove non-cached memory map areas Andrew Davis
2023-11-22 15:14 ` [PATCH RFC 2/2] arm: mach-k3: Merge initial memory maps Andrew Davis
2023-11-23 16:29 ` [PATCH RFC 0/2] Unify K3 initial memory map Nishanth Menon

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