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From: Simon Glass <sjg@chromium.org>
To: U-Boot Mailing List <u-boot@lists.denx.de>
Cc: Tom Rini <trini@konsulko.com>, Simon Glass <sjg@chromium.org>,
	Jeffy Chen <jeffy.chen@rock-chips.com>,
	Jonas Karlman <jonas@kwiboo.se>,
	Kever Yang <kever.yang@rock-chips.com>,
	Philipp Tomsich <philipp.tomsich@vrull.eu>,
	Quentin Schulz <quentin.schulz@cherry.de>,
	huang lin <hl@rock-chips.com>
Subject: [PATCH v2 7/9] rockchip: Ensure memory size is available in RK3399 SPL
Date: Mon, 10 Jun 2024 08:59:18 -0600	[thread overview]
Message-ID: <20240610145920.3302001-8-sjg@chromium.org> (raw)
In-Reply-To: <20240610145920.3302001-1-sjg@chromium.org>

At present gd->ram_size is 0 in SPL, meaning that it is not possible to
enable the cache. Correct this by always populating the RAM size
correctly.

Part of the confusion here comes from the large blocks of code which
are #ifdefed out. Add a function phase_sdram_init() which returns
whether SDRAM init should happen in the current phase, using that as
needed to control the code flow.

This increases code size by about 500 bytes in SPL when the cache is on,
since it must call the rather large rockchip_sdram_size() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Add new patch to correct memory size in SPL

 drivers/ram/rockchip/sdram_rk3399.c | 49 ++++++++++++++++-------------
 1 file changed, 27 insertions(+), 22 deletions(-)

diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 02cc4a38cf0..2f37dd712e7 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -13,6 +13,7 @@
 #include <log.h>
 #include <ram.h>
 #include <regmap.h>
+#include <spl.h>
 #include <syscon.h>
 #include <asm/arch-rockchip/clock.h>
 #include <asm/arch-rockchip/cru.h>
@@ -63,8 +64,6 @@ struct chan_info {
 };
 
 struct dram_info {
-#if defined(CONFIG_TPL_BUILD) || \
-	(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
 	u32 pwrup_srefresh_exit[2];
 	struct chan_info chan[2];
 	struct clk ddr_clk;
@@ -75,7 +74,6 @@ struct dram_info {
 	struct rk3399_pmusgrf_regs *pmusgrf;
 	struct rk3399_ddr_cic_regs *cic;
 	const struct sdram_rk3399_ops *ops;
-#endif
 	struct ram_info info;
 	struct rk3399_pmugrf_regs *pmugrf;
 };
@@ -92,9 +90,6 @@ struct sdram_rk3399_ops {
 					struct rk3399_sdram_params *params);
 };
 
-#if defined(CONFIG_TPL_BUILD) || \
-	(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
-
 struct rockchip_dmc_plat {
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 	struct dtd_rockchip_rk3399_dmc dtplat;
@@ -191,6 +186,17 @@ struct io_setting {
 	},
 };
 
+/**
+ * phase_sdram_init() - Check if this is the phase where SDRAM init happens
+ *
+ * Returns: true to do SDRAM init in this phase, false to not
+ */
+static bool phase_sdram_init(void)
+{
+	return spl_phase() == PHASE_TPL ||
+	    (!IS_ENABLED(CONFIG_TPL) && !spl_in_proper());
+}
+
 static struct io_setting *
 lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5)
 {
@@ -3024,7 +3030,7 @@ static int rk3399_dmc_of_to_plat(struct udevice *dev)
 	struct rockchip_dmc_plat *plat = dev_get_plat(dev);
 	int ret;
 
-	if (!CONFIG_IS_ENABLED(OF_REAL))
+	if (!CONFIG_IS_ENABLED(OF_REAL) || !phase_sdram_init())
 		return 0;
 
 	ret = dev_read_u32_array(dev, "rockchip,sdram-params",
@@ -3138,23 +3144,25 @@ static int rk3399_dmc_init(struct udevice *dev)
 
 	return 0;
 }
-#endif
 
 static int rk3399_dmc_probe(struct udevice *dev)
 {
-#if defined(CONFIG_TPL_BUILD) || \
-	(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
-	if (rk3399_dmc_init(dev))
-		return 0;
-#else
 	struct dram_info *priv = dev_get_priv(dev);
 
-	priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
-	debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
-	priv->info.base = CFG_SYS_SDRAM_BASE;
-	priv->info.size =
-		rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
-#endif
+	if (phase_sdram_init()) {
+		if (rk3399_dmc_init(dev))
+			return 0;
+	} else {
+		priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+		debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
+	}
+
+	if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) {
+		priv->info.base = CFG_SYS_SDRAM_BASE;
+		priv->info.size =
+			rockchip_sdram_size((ulong)&priv->pmugrf->os_reg2);
+	}
+
 	return 0;
 }
 
@@ -3181,10 +3189,7 @@ U_BOOT_DRIVER(dmc_rk3399) = {
 	.id = UCLASS_RAM,
 	.of_match = rk3399_dmc_ids,
 	.ops = &rk3399_dmc_ops,
-#if defined(CONFIG_TPL_BUILD) || \
-	(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
 	.of_to_plat = rk3399_dmc_of_to_plat,
-#endif
 	.probe = rk3399_dmc_probe,
 	.priv_auto	= sizeof(struct dram_info),
 #if defined(CONFIG_TPL_BUILD) || \
-- 
2.34.1


  parent reply	other threads:[~2024-06-10 15:00 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-10 14:59 [PATCH v2 0/9] Bug-fixes for a few boards Simon Glass
2024-06-10 14:59 ` [PATCH v2 1/9] nvidia: nyan-big: Disable debug UART Simon Glass
2024-06-10 14:59 ` [PATCH v2 2/9] tpm: Avoid code bloat when not using EFI_TCG2_PROTOCOL Simon Glass
2024-06-14  6:03   ` Ilias Apalodimas
2024-06-14  6:59     ` Heinrich Schuchardt
2024-06-14  7:01       ` Ilias Apalodimas
2024-06-14  9:04         ` Heinrich Schuchardt
2024-06-15  7:01           ` Ilias Apalodimas
2024-06-15  7:03           ` Ilias Apalodimas
2024-06-17 13:53             ` Simon Glass
2024-06-17 17:16               ` Tom Rini
2024-06-18 12:43                 ` Simon Glass
2024-06-18 14:15                   ` Tom Rini
2024-06-19  3:03                     ` Simon Glass
2024-06-19 15:32                       ` Tom Rini
2024-06-20 23:05                         ` Simon Glass
2024-06-20 23:19                           ` Tom Rini
2024-06-21 14:57                             ` Simon Glass
2024-06-21 16:05                               ` Tom Rini
2024-06-21 17:55                                 ` Simon Glass
2024-06-21 19:19                                   ` Tom Rini
2024-06-21 19:38                                     ` Simon Glass
2024-06-21 22:12                                       ` Tom Rini
2024-06-23 21:52                                         ` Simon Glass
2024-06-24 17:28                                           ` Tom Rini
2024-06-10 14:59 ` [PATCH v2 3/9] rockchip: veyron: Add logging for power init Simon Glass
2024-06-10 17:02   ` Quentin Schulz
2024-06-10 14:59 ` [PATCH v2 4/9] power: regulator: Handle autoset in regulators_enable_boot_on() Simon Glass
2024-06-10 14:59 ` [PATCH v2 5/9] fdt: Correct condition for bloblist existing Simon Glass
2024-06-10 14:59 ` [PATCH v2 6/9] spl: Allow ATF to work when dcache is disabled Simon Glass
2024-06-10 14:59 ` Simon Glass [this message]
2024-06-11 11:27   ` [PATCH v2 7/9] rockchip: Ensure memory size is available in RK3399 SPL Quentin Schulz
2024-06-11 13:43     ` Jonas Karlman
2024-06-11 13:50       ` Quentin Schulz
2024-06-11 19:13     ` Simon Glass
2024-06-10 14:59 ` [PATCH v2 8/9] rockchip: bob: kevin: Disable dcache in SPL Simon Glass
2024-06-10 14:59 ` [PATCH v2 9/9] Drop the special am335x_boneblack_vboot target Simon Glass
2024-06-10 16:29   ` Tom Rini

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