[PATCH 0/5] clk: mediatek: mt7623: clk migration for OF_UPSTREAM

[PATCH 0/5] clk: mediatek: mt7623: clk migration for OF_UPSTREAM

[Christian Marangi]

These are all the required patches to migrate clk and correctly support
OF_UPSTREAM. This will align the clk index to upstream to support the same
clk implementation with downstream and upstream DTS.

Christian Marangi (5):
  clk: mediatek: mt7623: fix broken peri_cgs clk with XTAL parents
  clk: mediatek: mt7623: split clk tree to dedicated topckgen and
    apmixed
  clk: mediatek: mt7623: define id_offs_map and import clk ID from
    upstream
  clk: mediatek: mt7623: remap apmixedsys clock ID
  clk: mediatek: mt7623: remap peri clock ID and add MUX

 drivers/clk/mediatek/clk-mt7623.c      | 326 +++++++++-
 include/dt-bindings/clock/mt7623-clk.h | 832 ++++++++++++++-----------
 2 files changed, 757 insertions(+), 401 deletions(-)

-- 
2.45.2

[PATCH 1/5] clk: mediatek: mt7623: fix broken peri_cgs clk with XTAL parents

[Christian Marangi]

Fix broken peri_cgs and infra_cgs clock with XTAL parents as they have
wrong definition of the parent type.

Correctly fix them and use CLK_PARENT_XTAL for them.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/clk/mediatek/clk-mt7623.c | 27 ++++++++++++++++++---------
 1 file changed, 18 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
index 5072c9983c1..4be914c8297 100644
--- a/drivers/clk/mediatek/clk-mt7623.c
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -586,21 +586,26 @@ static const struct mtk_gate_regs infra_cg_regs = {
 	.sta_ofs = 0x48,
 };
 
-#define GATE_INFRA(_id, _parent, _shift) {			\
+#define GATE_INFRA_FLAGS(_id, _parent, _shift, _flags) {	\
 		.id = _id,					\
 		.parent = _parent,				\
 		.regs = &infra_cg_regs,				\
 		.shift = _shift,				\
-		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+		.flags = _flags,				\
 	}
+#define GATE_INFRA(_id, _parent, _shift) \
+	GATE_INFRA_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
+#define GATE_INFRA_XTAL(_id, _parent, _shift) \
+	GATE_INFRA_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL)
+
 
 static const struct mtk_gate infra_cgs[] = {
 	GATE_INFRA(CLK_INFRA_DBG, CLK_TOP_AXI_SEL, 0),
 	GATE_INFRA(CLK_INFRA_SMI, CLK_TOP_MM_SEL, 1),
 	GATE_INFRA(CLK_INFRA_QAXI_CM4, CLK_TOP_AXI_SEL, 2),
 	GATE_INFRA(CLK_INFRA_AUD_SPLIN_B, CLK_TOP_HADDS2PLL_294M, 4),
-	GATE_INFRA(CLK_INFRA_AUDIO, CLK_XTAL, 5),
-	GATE_INFRA(CLK_INFRA_EFUSE, CLK_XTAL, 6),
+	GATE_INFRA_XTAL(CLK_INFRA_AUDIO, CLK_XTAL, 5),
+	GATE_INFRA_XTAL(CLK_INFRA_EFUSE, CLK_XTAL, 6),
 	GATE_INFRA(CLK_INFRA_L2C_SRAM, CLK_TOP_MM_SEL, 7),
 	GATE_INFRA(CLK_INFRA_M4U, CLK_TOP_MEM_SEL, 8),
 	GATE_INFRA(CLK_INFRA_CONNMCU, CLK_TOP_WBG_DIG_416M, 12),
@@ -628,13 +633,17 @@ static const struct mtk_gate_regs peri1_cg_regs = {
 	.sta_ofs = 0x1C,
 };
 
-#define GATE_PERI0(_id, _parent, _shift) {			\
+#define GATE_PERI0_FLAGS(_id, _parent, _shift, _flags) {	\
 		.id = _id,					\
 		.parent = _parent,				\
 		.regs = &peri0_cg_regs,				\
 		.shift = _shift,				\
-		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+		.flags = _flags,				\
 	}
+#define GATE_PERI0(_id, _parent, _shift) \
+	GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
+#define GATE_PERI0_XTAL(_id, _parent, _shift) \
+	GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL)
 
 #define GATE_PERI1(_id, _parent, _shift) {			\
 		.id = _id,					\
@@ -672,10 +681,10 @@ static const struct mtk_gate peri_cgs[] = {
 	GATE_PERI0(CLK_PERI_I2C0, CLK_TOP_AXI_SEL, 24),
 	GATE_PERI0(CLK_PERI_I2C1, CLK_TOP_AXI_SEL, 25),
 	GATE_PERI0(CLK_PERI_I2C2, CLK_TOP_AXI_SEL, 26),
-	GATE_PERI0(CLK_PERI_I2C3, CLK_XTAL, 27),
-	GATE_PERI0(CLK_PERI_AUXADC, CLK_XTAL, 28),
+	GATE_PERI0_XTAL(CLK_PERI_I2C3, CLK_XTAL, 27),
+	GATE_PERI0_XTAL(CLK_PERI_AUXADC, CLK_XTAL, 28),
 	GATE_PERI0(CLK_PERI_SPI0, CLK_TOP_SPI0_SEL, 29),
-	GATE_PERI0(CLK_PERI_ETH, CLK_XTAL, 30),
+	GATE_PERI0_XTAL(CLK_PERI_ETH, CLK_XTAL, 30),
 	GATE_PERI0(CLK_PERI_USB0_MCU, CLK_TOP_AXI_SEL, 31),
 
 	GATE_PERI1(CLK_PERI_USB1_MCU, CLK_TOP_AXI_SEL, 0),
-- 
2.45.2

[PATCH 2/5] clk: mediatek: mt7623: split clk tree to dedicated topckgen and apmixed

[Christian Marangi]

Split clk tree to dedicated topckgen and apmixed in preparation for
remap table.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/clk/mediatek/clk-mt7623.c | 25 ++++++++++++++++---------
 1 file changed, 16 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
index 4be914c8297..79936f1803d 100644
--- a/drivers/clk/mediatek/clk-mt7623.c
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -739,12 +739,15 @@ static const struct mtk_gate hif_cgs[] = {
 	GATE_ETH_HIF1(CLK_HIFSYS_PCIE2, CLK_TOP_ETHPLL_500M, 26),
 };
 
-static const struct mtk_clk_tree mt7623_clk_tree = {
-	.xtal_rate = 26 * MHZ,
+static const struct mtk_clk_tree mt7623_apmixedsys_clk_tree = {
 	.xtal2_rate = 26 * MHZ,
+	.plls = apmixed_plls,
+};
+
+static const struct mtk_clk_tree mt7623_topckgen_clk_tree = {
+	.xtal_rate = 26 * MHZ,
 	.fdivs_offs = CLK_TOP_SYSPLL,
 	.muxes_offs = CLK_TOP_AXI_SEL,
-	.plls = apmixed_plls,
 	.fclks = top_fixed_clks,
 	.fdivs = top_fixed_divs,
 	.muxes = top_muxes,
@@ -769,7 +772,7 @@ static int mt7623_apmixedsys_probe(struct udevice *dev)
 	struct mtk_clk_priv *priv = dev_get_priv(dev);
 	int ret;
 
-	ret = mtk_common_clk_init(dev, &mt7623_clk_tree);
+	ret = mtk_common_clk_init(dev, &mt7623_apmixedsys_clk_tree);
 	if (ret)
 		return ret;
 
@@ -783,27 +786,31 @@ static int mt7623_apmixedsys_probe(struct udevice *dev)
 
 static int mt7623_topckgen_probe(struct udevice *dev)
 {
-	return mtk_common_clk_init(dev, &mt7623_clk_tree);
+	return mtk_common_clk_init(dev, &mt7623_topckgen_clk_tree);
 }
 
 static int mt7623_infracfg_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, infra_cgs);
+	return mtk_common_clk_gate_init(dev, &mt7623_topckgen_clk_tree,
+					infra_cgs);
 }
 
 static int mt7623_pericfg_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, peri_cgs);
+	return mtk_common_clk_gate_init(dev, &mt7623_topckgen_clk_tree,
+					peri_cgs);
 }
 
 static int mt7623_hifsys_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, hif_cgs);
+	return mtk_common_clk_gate_init(dev, &mt7623_topckgen_clk_tree,
+					hif_cgs);
 }
 
 static int mt7623_ethsys_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, eth_cgs);
+	return mtk_common_clk_gate_init(dev, &mt7623_topckgen_clk_tree,
+					eth_cgs);
 }
 
 static int mt7623_ethsys_hifsys_bind(struct udevice *dev)
-- 
2.45.2

[PATCH 3/5] clk: mediatek: mt7623: define id_offs_map and import clk ID from upstream

[Christian Marangi]

Define id_offs_map and use clk ID form upstream linux kernel to have a
1:1 match for the TOPCKGEN clock and permit usage of OF_UPSTREAM with
upstream dtsi.

For all the gate clock, the clk ID starts from 1 instead of zero. Define
an additional clock tree for them and set the .gates_offs to 1 to
account for this.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/clk/mediatek/clk-mt7623.c      | 188 +++++-
 include/dt-bindings/clock/mt7623-clk.h | 832 ++++++++++++++-----------
 2 files changed, 633 insertions(+), 387 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
index 79936f1803d..6af6f9f11bd 100644
--- a/drivers/clk/mediatek/clk-mt7623.c
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -71,6 +71,176 @@ static const struct mtk_pll_data apmixed_plls[] = {
 };
 
 /* topckgen */
+
+/* Fixed CLK exposed upstream by the hdmi PHY driver */
+#define CLK_TOP_HDMITX_CLKDIG_CTS		CLK_TOP_NR
+
+static const int top_id_offs_map[CLK_TOP_NR + 1] = {
+	/* Fixed CLK */
+	[CLK_TOP_DPI]				= 0,
+	[CLK_TOP_DMPLL]				= 1,
+	[CLK_TOP_VENCPLL]			= 2,
+	[CLK_TOP_HDMI_0_PIX340M]		= 3,
+	[CLK_TOP_HDMI_0_DEEP340M]		= 4,
+	[CLK_TOP_HDMI_0_PLL340M]		= 5,
+	[CLK_TOP_HADDS2_FB]			= 6,
+	[CLK_TOP_WBG_DIG_416M]			= 7,
+	[CLK_TOP_DSI0_LNTC_DSI]			= 8,
+	[CLK_TOP_HDMI_SCL_RX]			= 9,
+	[CLK_TOP_32K_EXTERNAL]			= 10,
+	[CLK_TOP_HDMITX_CLKDIG_CTS]		= 11,
+	[CLK_TOP_AUD_EXT1]			= 12,
+	[CLK_TOP_AUD_EXT2]			= 13,
+	[CLK_TOP_NFI1X_PAD]			= 14,
+	/* Factor CLK */
+	[CLK_TOP_SYSPLL]			= 15,
+	[CLK_TOP_SYSPLL_D2]			= 16,
+	[CLK_TOP_SYSPLL_D3]			= 17,
+	[CLK_TOP_SYSPLL_D5]			= 18,
+	[CLK_TOP_SYSPLL_D7]			= 19,
+	[CLK_TOP_SYSPLL1_D2]			= 20,
+	[CLK_TOP_SYSPLL1_D4]			= 21,
+	[CLK_TOP_SYSPLL1_D8]			= 22,
+	[CLK_TOP_SYSPLL1_D16]			= 23,
+	[CLK_TOP_SYSPLL2_D2]			= 24,
+	[CLK_TOP_SYSPLL2_D4]			= 25,
+	[CLK_TOP_SYSPLL2_D8]			= 26,
+	[CLK_TOP_SYSPLL3_D2]			= 27,
+	[CLK_TOP_SYSPLL3_D4]			= 28,
+	[CLK_TOP_SYSPLL4_D2]			= 29,
+	[CLK_TOP_SYSPLL4_D4]			= 30,
+	[CLK_TOP_UNIVPLL]			= 31,
+	[CLK_TOP_UNIVPLL_D2]			= 32,
+	[CLK_TOP_UNIVPLL_D3]			= 33,
+	[CLK_TOP_UNIVPLL_D5]			= 34,
+	[CLK_TOP_UNIVPLL_D7]			= 35,
+	[CLK_TOP_UNIVPLL_D26]			= 36,
+	[CLK_TOP_UNIVPLL_D52]			= 37,
+	[CLK_TOP_UNIVPLL_D108]			= 38,
+	[CLK_TOP_USB_PHY48M]			= 39,
+	[CLK_TOP_UNIVPLL1_D2]			= 40,
+	[CLK_TOP_UNIVPLL1_D4]			= 41,
+	[CLK_TOP_UNIVPLL1_D8]			= 42,
+	[CLK_TOP_UNIVPLL2_D2]			= 43,
+	[CLK_TOP_UNIVPLL2_D4]			= 44,
+	[CLK_TOP_UNIVPLL2_D8]			= 45,
+	[CLK_TOP_UNIVPLL2_D16]			= 46,
+	[CLK_TOP_UNIVPLL2_D32]			= 47,
+	[CLK_TOP_UNIVPLL3_D2]			= 48,
+	[CLK_TOP_UNIVPLL3_D4]			= 49,
+	[CLK_TOP_UNIVPLL3_D8]			= 50,
+	[CLK_TOP_MSDCPLL]			= 51,
+	[CLK_TOP_MSDCPLL_D2]			= 52,
+	[CLK_TOP_MSDCPLL_D4]			= 53,
+	[CLK_TOP_MSDCPLL_D8]			= 54,
+	[CLK_TOP_MMPLL]				= 55,
+	[CLK_TOP_MMPLL_D2]			= 56,
+	[CLK_TOP_DMPLL_D2]			= 57,
+	[CLK_TOP_DMPLL_D4]			= 58,
+	[CLK_TOP_DMPLL_X2]			= 59,
+	[CLK_TOP_TVDPLL]			= 60,
+	[CLK_TOP_TVDPLL_D2]			= 61,
+	[CLK_TOP_TVDPLL_D4]			= 62,
+	[CLK_TOP_VDECPLL]			= 63,
+	[CLK_TOP_TVD2PLL]			= 64,
+	[CLK_TOP_TVD2PLL_D2]			= 65,
+	[CLK_TOP_MIPIPLL]			= 66,
+	[CLK_TOP_MIPIPLL_D2]			= 67,
+	[CLK_TOP_MIPIPLL_D4]			= 68,
+	[CLK_TOP_HDMIPLL]			= 69,
+	[CLK_TOP_HDMIPLL_D2]			= 70,
+	[CLK_TOP_HDMIPLL_D3]			= 71,
+	[CLK_TOP_ARMPLL_1P3G]			= 72,
+	[CLK_TOP_AUDPLL]			= 73,
+	[CLK_TOP_AUDPLL_D4]			= 74,
+	[CLK_TOP_AUDPLL_D8]			= 75,
+	[CLK_TOP_AUDPLL_D16]			= 76,
+	[CLK_TOP_AUDPLL_D24]			= 77,
+	[CLK_TOP_AUD1PLL_98M]			= 78,
+	[CLK_TOP_AUD2PLL_90M]			= 79,
+	[CLK_TOP_HADDS2PLL_98M]			= 80,
+	[CLK_TOP_HADDS2PLL_294M]		= 81,
+	[CLK_TOP_ETHPLL_500M]			= 82,
+	[CLK_TOP_CLK26M_D8]			= 83,
+	[CLK_TOP_32K_INTERNAL]			= 84,
+	[CLK_TOP_AXISEL_D4]			= 85,
+	[CLK_TOP_8BDAC]				= 86,
+	/* MUX CLK */
+	[CLK_TOP_AXI_SEL]			= 87,
+	[CLK_TOP_MEM_SEL]			= 88,
+	[CLK_TOP_DDRPHYCFG_SEL]			= 89,
+	[CLK_TOP_MM_SEL]			= 90,
+	[CLK_TOP_PWM_SEL]			= 91,
+	[CLK_TOP_VDEC_SEL]			= 92,
+	[CLK_TOP_MFG_SEL]			= 93,
+	[CLK_TOP_CAMTG_SEL]			= 94,
+	[CLK_TOP_UART_SEL]			= 95,
+	[CLK_TOP_SPI0_SEL]			= 96,
+	[CLK_TOP_USB20_SEL]			= 97,
+	[CLK_TOP_MSDC30_0_SEL]			= 98,
+	[CLK_TOP_MSDC30_1_SEL]			= 99,
+	[CLK_TOP_MSDC30_2_SEL]			= 100,
+	[CLK_TOP_AUDIO_SEL]			= 101,
+	[CLK_TOP_AUDINTBUS_SEL]			= 102,
+	[CLK_TOP_PMICSPI_SEL]			= 103,
+	[CLK_TOP_SCP_SEL]			= 104,
+	[CLK_TOP_DPI0_SEL]			= 105,
+	[CLK_TOP_DPI1_SEL]			= 106,
+	[CLK_TOP_TVE_SEL]			= 107,
+	[CLK_TOP_HDMI_SEL]			= 108,
+	[CLK_TOP_APLL_SEL]			= 109,
+	[CLK_TOP_RTC_SEL]			= 110,
+	[CLK_TOP_NFI2X_SEL]			= 111,
+	[CLK_TOP_EMMC_HCLK_SEL]			= 112,
+	[CLK_TOP_FLASH_SEL]			= 113,
+	[CLK_TOP_DI_SEL]			= 114,
+	[CLK_TOP_NR_SEL]			= 115,
+	[CLK_TOP_OSD_SEL]			= 116,
+	[CLK_TOP_HDMIRX_BIST_SEL]		= 117,
+	[CLK_TOP_INTDIR_SEL]			= 118,
+	[CLK_TOP_ASM_I_SEL]			= 119,
+	[CLK_TOP_ASM_M_SEL]			= 120,
+	[CLK_TOP_ASM_H_SEL]			= 121,
+	[CLK_TOP_MS_CARD_SEL]			= 122,
+	[CLK_TOP_ETHIF_SEL]			= 123,
+	[CLK_TOP_HDMIRX26_24_SEL]		= 124,
+	[CLK_TOP_MSDC30_3_SEL]			= 125,
+	[CLK_TOP_CMSYS_SEL]			= 126,
+	[CLK_TOP_SPI1_SEL]			= 127,
+	[CLK_TOP_SPI2_SEL]			= 128,
+	[CLK_TOP_8BDAC_SEL]			= 129,
+	[CLK_TOP_AUD2DVD_SEL]			= 130,
+	[CLK_TOP_PADMCLK_SEL]			= 131,
+	[CLK_TOP_AUD_MUX1_SEL]			= 132,
+	[CLK_TOP_AUD_MUX2_SEL]			= 133,
+	[CLK_TOP_AUDPLL_MUX_SEL]		= 134,
+	[CLK_TOP_AUD_K1_SRC_SEL]		= 135,
+	[CLK_TOP_AUD_K2_SRC_SEL]		= 136,
+	[CLK_TOP_AUD_K3_SRC_SEL]		= 137,
+	[CLK_TOP_AUD_K4_SRC_SEL]		= 138,
+	[CLK_TOP_AUD_K5_SRC_SEL]		= 139,
+	[CLK_TOP_AUD_K6_SRC_SEL]		= 140,
+	/* Misc CLK only used as parents */
+	[CLK_TOP_AUD_EXTCK1_DIV]		= 141,
+	[CLK_TOP_AUD_EXTCK2_DIV]		= 142,
+	[CLK_TOP_AUD_MUX1_DIV]			= 143,
+	[CLK_TOP_AUD_MUX2_DIV]			= 144,
+	[CLK_TOP_AUD_K1_SRC_DIV]		= 145,
+	[CLK_TOP_AUD_K2_SRC_DIV]		= 146,
+	[CLK_TOP_AUD_K3_SRC_DIV]		= 147,
+	[CLK_TOP_AUD_K4_SRC_DIV]		= 148,
+	[CLK_TOP_AUD_K5_SRC_DIV]		= 149,
+	[CLK_TOP_AUD_K6_SRC_DIV]		= 150,
+	[CLK_TOP_AUD_48K_TIMING]		= 151,
+	[CLK_TOP_AUD_44K_TIMING]		= 152,
+	[CLK_TOP_AUD_I2S1_MCLK]			= 153,
+	[CLK_TOP_AUD_I2S2_MCLK]			= 154,
+	[CLK_TOP_AUD_I2S3_MCLK]			= 155,
+	[CLK_TOP_AUD_I2S4_MCLK]			= 156,
+	[CLK_TOP_AUD_I2S5_MCLK]			= 157,
+	[CLK_TOP_AUD_I2S6_MCLK]			= 158,
+};
+
 #define FACTOR0(_id, _parent, _mult, _div)			\
 	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
 
@@ -746,8 +916,9 @@ static const struct mtk_clk_tree mt7623_apmixedsys_clk_tree = {
 
 static const struct mtk_clk_tree mt7623_topckgen_clk_tree = {
 	.xtal_rate = 26 * MHZ,
-	.fdivs_offs = CLK_TOP_SYSPLL,
-	.muxes_offs = CLK_TOP_AXI_SEL,
+	.id_offs_map = top_id_offs_map,
+	.fdivs_offs = top_id_offs_map[CLK_TOP_SYSPLL],
+	.muxes_offs = top_id_offs_map[CLK_TOP_AXI_SEL],
 	.fclks = top_fixed_clks,
 	.fdivs = top_fixed_divs,
 	.muxes = top_muxes,
@@ -789,27 +960,32 @@ static int mt7623_topckgen_probe(struct udevice *dev)
 	return mtk_common_clk_init(dev, &mt7623_topckgen_clk_tree);
 }
 
+static const struct mtk_clk_tree mt7623_clk_gate_tree = {
+	/* Each CLK ID for gates clock starts at index 1 */
+	.gates_offs = 1,
+};
+
 static int mt7623_infracfg_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt7623_topckgen_clk_tree,
+	return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree,
 					infra_cgs);
 }
 
 static int mt7623_pericfg_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt7623_topckgen_clk_tree,
+	return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree,
 					peri_cgs);
 }
 
 static int mt7623_hifsys_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt7623_topckgen_clk_tree,
+	return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree,
 					hif_cgs);
 }
 
 static int mt7623_ethsys_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt7623_topckgen_clk_tree,
+	return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree,
 					eth_cgs);
 }
 
diff --git a/include/dt-bindings/clock/mt7623-clk.h b/include/dt-bindings/clock/mt7623-clk.h
index 71ced1593af..0caeb65c3d2 100644
--- a/include/dt-bindings/clock/mt7623-clk.h
+++ b/include/dt-bindings/clock/mt7623-clk.h
@@ -7,407 +7,477 @@
 #define _DT_BINDINGS_CLK_MT2701_H
 
 /* TOPCKGEN */
-#define CLK_TOP_FCLKS_OFF			0
-
-#define CLK_TOP_DPI				0
-#define CLK_TOP_DMPLL				1
-#define CLK_TOP_VENCPLL				2
-#define CLK_TOP_HDMI_0_PIX340M			3
-#define CLK_TOP_HDMI_0_DEEP340M			4
-#define CLK_TOP_HDMI_0_PLL340M			5
-#define CLK_TOP_HADDS2_FB			6
-#define CLK_TOP_WBG_DIG_416M			7
-#define CLK_TOP_DSI0_LNTC_DSI			8
-#define CLK_TOP_HDMI_SCL_RX			9
-#define CLK_TOP_32K_EXTERNAL			10
-#define CLK_TOP_HDMITX_CLKDIG_CTS		11
-#define CLK_TOP_AUD_EXT1			12
-#define CLK_TOP_AUD_EXT2			13
-#define CLK_TOP_NFI1X_PAD			14
-
-#define CLK_TOP_SYSPLL				15
-#define CLK_TOP_SYSPLL_D2			16
-#define CLK_TOP_SYSPLL_D3			17
-#define CLK_TOP_SYSPLL_D5			18
-#define CLK_TOP_SYSPLL_D7			19
-#define CLK_TOP_SYSPLL1_D2			20
-#define CLK_TOP_SYSPLL1_D4			21
-#define CLK_TOP_SYSPLL1_D8			22
-#define CLK_TOP_SYSPLL1_D16			23
-#define CLK_TOP_SYSPLL2_D2			24
-#define CLK_TOP_SYSPLL2_D4			25
-#define CLK_TOP_SYSPLL2_D8			26
-#define CLK_TOP_SYSPLL3_D2			27
-#define CLK_TOP_SYSPLL3_D4			28
-#define CLK_TOP_SYSPLL4_D2			29
-#define CLK_TOP_SYSPLL4_D4			30
-#define CLK_TOP_UNIVPLL				31
-#define CLK_TOP_UNIVPLL_D2			32
-#define CLK_TOP_UNIVPLL_D3			33
-#define CLK_TOP_UNIVPLL_D5			34
-#define CLK_TOP_UNIVPLL_D7			35
-#define CLK_TOP_UNIVPLL_D26			36
-#define CLK_TOP_UNIVPLL_D52			37
-#define CLK_TOP_UNIVPLL_D108			38
-#define CLK_TOP_USB_PHY48M			39
-#define CLK_TOP_UNIVPLL1_D2			40
-#define CLK_TOP_UNIVPLL1_D4			41
-#define CLK_TOP_UNIVPLL1_D8			42
-#define CLK_TOP_UNIVPLL2_D2			43
-#define CLK_TOP_UNIVPLL2_D4			44
-#define CLK_TOP_UNIVPLL2_D8			45
-#define CLK_TOP_UNIVPLL2_D16			46
-#define CLK_TOP_UNIVPLL2_D32			47
-#define CLK_TOP_UNIVPLL3_D2			48
-#define CLK_TOP_UNIVPLL3_D4			49
-#define CLK_TOP_UNIVPLL3_D8			50
-#define CLK_TOP_MSDCPLL				51
-#define CLK_TOP_MSDCPLL_D2			52
-#define CLK_TOP_MSDCPLL_D4			53
-#define CLK_TOP_MSDCPLL_D8			54
-#define CLK_TOP_MMPLL				55
-#define CLK_TOP_MMPLL_D2			56
-#define CLK_TOP_DMPLL_D2			57
-#define CLK_TOP_DMPLL_D4			58
-#define CLK_TOP_DMPLL_X2			59
-#define CLK_TOP_TVDPLL				60
-#define CLK_TOP_TVDPLL_D2			61
-#define CLK_TOP_TVDPLL_D4			62
-#define CLK_TOP_VDECPLL				63
-#define CLK_TOP_TVD2PLL				64
-#define CLK_TOP_TVD2PLL_D2			65
-#define CLK_TOP_MIPIPLL				66
-#define CLK_TOP_MIPIPLL_D2			67
-#define CLK_TOP_MIPIPLL_D4			68
-#define CLK_TOP_HDMIPLL				69
-#define CLK_TOP_HDMIPLL_D2			70
-#define CLK_TOP_HDMIPLL_D3			71
-#define CLK_TOP_ARMPLL_1P3G			72
-#define CLK_TOP_AUDPLL				73
-#define CLK_TOP_AUDPLL_D4			74
-#define CLK_TOP_AUDPLL_D8			75
-#define CLK_TOP_AUDPLL_D16			76
-#define CLK_TOP_AUDPLL_D24			77
-#define CLK_TOP_AUD1PLL_98M			78
-#define CLK_TOP_AUD2PLL_90M			79
-#define CLK_TOP_HADDS2PLL_98M			80
-#define CLK_TOP_HADDS2PLL_294M			81
-#define CLK_TOP_ETHPLL_500M			82
-#define CLK_TOP_CLK26M_D8			83
-#define CLK_TOP_32K_INTERNAL			84
-#define CLK_TOP_AXISEL_D4			85
-#define CLK_TOP_8BDAC				86
-
-#define CLK_TOP_AXI_SEL				87
-#define CLK_TOP_MEM_SEL				88
-#define CLK_TOP_DDRPHYCFG_SEL			89
-#define CLK_TOP_MM_SEL				90
-#define CLK_TOP_PWM_SEL				91
-#define CLK_TOP_VDEC_SEL			92
-#define CLK_TOP_MFG_SEL				93
-#define CLK_TOP_CAMTG_SEL			94
-#define CLK_TOP_UART_SEL			95
-#define CLK_TOP_SPI0_SEL			96
-#define CLK_TOP_USB20_SEL			97
-#define CLK_TOP_MSDC30_0_SEL			98
-#define CLK_TOP_MSDC30_1_SEL			99
-#define CLK_TOP_MSDC30_2_SEL			100
-#define CLK_TOP_AUDIO_SEL			101
-#define CLK_TOP_AUDINTBUS_SEL			102
-#define CLK_TOP_PMICSPI_SEL			103
-#define CLK_TOP_SCP_SEL				104
-#define CLK_TOP_DPI0_SEL			105
-#define CLK_TOP_DPI1_SEL			106
-#define CLK_TOP_TVE_SEL				107
-#define CLK_TOP_HDMI_SEL			108
-#define CLK_TOP_APLL_SEL			109
-#define CLK_TOP_RTC_SEL				110
-#define CLK_TOP_NFI2X_SEL			111
-#define CLK_TOP_EMMC_HCLK_SEL			112
-#define CLK_TOP_FLASH_SEL			113
-#define CLK_TOP_DI_SEL				114
-#define CLK_TOP_NR_SEL				115
-#define CLK_TOP_OSD_SEL				116
-#define CLK_TOP_HDMIRX_BIST_SEL			117
-#define CLK_TOP_INTDIR_SEL			118
-#define CLK_TOP_ASM_I_SEL			119
-#define CLK_TOP_ASM_M_SEL			120
-#define CLK_TOP_ASM_H_SEL			121
-#define CLK_TOP_MS_CARD_SEL			122
-#define CLK_TOP_ETHIF_SEL			123
-#define CLK_TOP_HDMIRX26_24_SEL			124
-#define CLK_TOP_MSDC30_3_SEL			125
-#define CLK_TOP_CMSYS_SEL			126
-#define CLK_TOP_SPI1_SEL			127
-#define CLK_TOP_SPI2_SEL			128
-#define CLK_TOP_8BDAC_SEL			129
-#define CLK_TOP_AUD2DVD_SEL			130
-#define CLK_TOP_PADMCLK_SEL			131
-#define CLK_TOP_AUD_MUX1_SEL			132
-#define CLK_TOP_AUD_MUX2_SEL			133
-#define CLK_TOP_AUDPLL_MUX_SEL			134
-#define CLK_TOP_AUD_K1_SRC_SEL			135
-#define CLK_TOP_AUD_K2_SRC_SEL			136
-#define CLK_TOP_AUD_K3_SRC_SEL			137
-#define CLK_TOP_AUD_K4_SRC_SEL			138
-#define CLK_TOP_AUD_K5_SRC_SEL			139
-#define CLK_TOP_AUD_K6_SRC_SEL			140
-
-#define CLK_TOP_AUD_EXTCK1_DIV			141
-#define CLK_TOP_AUD_EXTCK2_DIV			142
-#define CLK_TOP_AUD_MUX1_DIV			143
-#define CLK_TOP_AUD_MUX2_DIV			144
-#define CLK_TOP_AUD_K1_SRC_DIV			145
-#define CLK_TOP_AUD_K2_SRC_DIV			146
-#define CLK_TOP_AUD_K3_SRC_DIV			147
-#define CLK_TOP_AUD_K4_SRC_DIV			148
-#define CLK_TOP_AUD_K5_SRC_DIV			149
-#define CLK_TOP_AUD_K6_SRC_DIV			150
-#define CLK_TOP_AUD_48K_TIMING			151
-#define CLK_TOP_AUD_44K_TIMING			152
-#define CLK_TOP_AUD_I2S1_MCLK			153
-#define CLK_TOP_AUD_I2S2_MCLK			154
-#define CLK_TOP_AUD_I2S3_MCLK			155
-#define CLK_TOP_AUD_I2S4_MCLK			156
-#define CLK_TOP_AUD_I2S5_MCLK			157
-#define CLK_TOP_AUD_I2S6_MCLK			158
+#define CLK_TOP_SYSPLL				1
+#define CLK_TOP_SYSPLL_D2			2
+#define CLK_TOP_SYSPLL_D3			3
+#define CLK_TOP_SYSPLL_D5			4
+#define CLK_TOP_SYSPLL_D7			5
+#define CLK_TOP_SYSPLL1_D2			6
+#define CLK_TOP_SYSPLL1_D4			7
+#define CLK_TOP_SYSPLL1_D8			8
+#define CLK_TOP_SYSPLL1_D16			9
+#define CLK_TOP_SYSPLL2_D2			10
+#define CLK_TOP_SYSPLL2_D4			11
+#define CLK_TOP_SYSPLL2_D8			12
+#define CLK_TOP_SYSPLL3_D2			13
+#define CLK_TOP_SYSPLL3_D4			14
+#define CLK_TOP_SYSPLL4_D2			15
+#define CLK_TOP_SYSPLL4_D4			16
+#define CLK_TOP_UNIVPLL				17
+#define CLK_TOP_UNIVPLL_D2			18
+#define CLK_TOP_UNIVPLL_D3			19
+#define CLK_TOP_UNIVPLL_D5			20
+#define CLK_TOP_UNIVPLL_D7			21
+#define CLK_TOP_UNIVPLL_D26			22
+#define CLK_TOP_UNIVPLL_D52			23
+#define CLK_TOP_UNIVPLL_D108			24
+#define CLK_TOP_USB_PHY48M			25
+#define CLK_TOP_UNIVPLL1_D2			26
+#define CLK_TOP_UNIVPLL1_D4			27
+#define CLK_TOP_UNIVPLL1_D8			28
+#define CLK_TOP_UNIVPLL2_D2			29
+#define CLK_TOP_UNIVPLL2_D4			30
+#define CLK_TOP_UNIVPLL2_D8			31
+#define CLK_TOP_UNIVPLL2_D16			32
+#define CLK_TOP_UNIVPLL2_D32			33
+#define CLK_TOP_UNIVPLL3_D2			34
+#define CLK_TOP_UNIVPLL3_D4			35
+#define CLK_TOP_UNIVPLL3_D8			36
+#define CLK_TOP_MSDCPLL				37
+#define CLK_TOP_MSDCPLL_D2			38
+#define CLK_TOP_MSDCPLL_D4			39
+#define CLK_TOP_MSDCPLL_D8			40
+#define CLK_TOP_MMPLL				41
+#define CLK_TOP_MMPLL_D2			42
+#define CLK_TOP_DMPLL				43
+#define CLK_TOP_DMPLL_D2			44
+#define CLK_TOP_DMPLL_D4			45
+#define CLK_TOP_DMPLL_X2			46
+#define CLK_TOP_TVDPLL				47
+#define CLK_TOP_TVDPLL_D2			48
+#define CLK_TOP_TVDPLL_D4			49
+#define CLK_TOP_TVD2PLL				50
+#define CLK_TOP_TVD2PLL_D2			51
+#define CLK_TOP_HADDS2PLL_98M			52
+#define CLK_TOP_HADDS2PLL_294M			53
+#define CLK_TOP_HADDS2_FB			54
+#define CLK_TOP_MIPIPLL_D2			55
+#define CLK_TOP_MIPIPLL_D4			56
+#define CLK_TOP_HDMIPLL				57
+#define CLK_TOP_HDMIPLL_D2			58
+#define CLK_TOP_HDMIPLL_D3			59
+#define CLK_TOP_HDMI_SCL_RX			60
+#define CLK_TOP_HDMI_0_PIX340M			61
+#define CLK_TOP_HDMI_0_DEEP340M			62
+#define CLK_TOP_HDMI_0_PLL340M			63
+#define CLK_TOP_AUD1PLL_98M			64
+#define CLK_TOP_AUD2PLL_90M			65
+#define CLK_TOP_AUDPLL				66
+#define CLK_TOP_AUDPLL_D4			67
+#define CLK_TOP_AUDPLL_D8			68
+#define CLK_TOP_AUDPLL_D16			69
+#define CLK_TOP_AUDPLL_D24			70
+#define CLK_TOP_ETHPLL_500M			71
+#define CLK_TOP_VDECPLL				72
+#define CLK_TOP_VENCPLL				73
+#define CLK_TOP_MIPIPLL				74
+#define CLK_TOP_ARMPLL_1P3G			75
+
+#define CLK_TOP_MM_SEL				76
+#define CLK_TOP_DDRPHYCFG_SEL			77
+#define CLK_TOP_MEM_SEL				78
+#define CLK_TOP_AXI_SEL				79
+#define CLK_TOP_CAMTG_SEL			80
+#define CLK_TOP_MFG_SEL				81
+#define CLK_TOP_VDEC_SEL			82
+#define CLK_TOP_PWM_SEL				83
+#define CLK_TOP_MSDC30_0_SEL			84
+#define CLK_TOP_USB20_SEL			85
+#define CLK_TOP_SPI0_SEL			86
+#define CLK_TOP_UART_SEL			87
+#define CLK_TOP_AUDINTBUS_SEL			88
+#define CLK_TOP_AUDIO_SEL			89
+#define CLK_TOP_MSDC30_2_SEL			90
+#define CLK_TOP_MSDC30_1_SEL			91
+#define CLK_TOP_DPI1_SEL			92
+#define CLK_TOP_DPI0_SEL			93
+#define CLK_TOP_SCP_SEL				94
+#define CLK_TOP_PMICSPI_SEL			95
+#define CLK_TOP_APLL_SEL			96
+#define CLK_TOP_HDMI_SEL			97
+#define CLK_TOP_TVE_SEL				98
+#define CLK_TOP_EMMC_HCLK_SEL			99
+#define CLK_TOP_NFI2X_SEL			100
+#define CLK_TOP_RTC_SEL				101
+#define CLK_TOP_OSD_SEL				102
+#define CLK_TOP_NR_SEL				103
+#define CLK_TOP_DI_SEL				104
+#define CLK_TOP_FLASH_SEL			105
+#define CLK_TOP_ASM_M_SEL			106
+#define CLK_TOP_ASM_I_SEL			107
+#define CLK_TOP_INTDIR_SEL			108
+#define CLK_TOP_HDMIRX_BIST_SEL			109
+#define CLK_TOP_ETHIF_SEL			110
+#define CLK_TOP_MS_CARD_SEL			111
+#define CLK_TOP_ASM_H_SEL			112
+#define CLK_TOP_SPI1_SEL			113
+#define CLK_TOP_CMSYS_SEL			114
+#define CLK_TOP_MSDC30_3_SEL			115
+#define CLK_TOP_HDMIRX26_24_SEL			116
+#define CLK_TOP_AUD2DVD_SEL			117
+#define CLK_TOP_8BDAC_SEL			118
+#define CLK_TOP_SPI2_SEL			119
+#define CLK_TOP_AUD_MUX1_SEL			120
+#define CLK_TOP_AUD_MUX2_SEL			121
+#define CLK_TOP_AUDPLL_MUX_SEL			122
+#define CLK_TOP_AUD_K1_SRC_SEL			123
+#define CLK_TOP_AUD_K2_SRC_SEL			124
+#define CLK_TOP_AUD_K3_SRC_SEL			125
+#define CLK_TOP_AUD_K4_SRC_SEL			126
+#define CLK_TOP_AUD_K5_SRC_SEL			127
+#define CLK_TOP_AUD_K6_SRC_SEL			128
+#define CLK_TOP_PADMCLK_SEL			129
+#define CLK_TOP_AUD_EXTCK1_DIV			130
+#define CLK_TOP_AUD_EXTCK2_DIV			131
+#define CLK_TOP_AUD_MUX1_DIV			132
+#define CLK_TOP_AUD_MUX2_DIV			133
+#define CLK_TOP_AUD_K1_SRC_DIV			134
+#define CLK_TOP_AUD_K2_SRC_DIV			135
+#define CLK_TOP_AUD_K3_SRC_DIV			136
+#define CLK_TOP_AUD_K4_SRC_DIV			137
+#define CLK_TOP_AUD_K5_SRC_DIV			138
+#define CLK_TOP_AUD_K6_SRC_DIV			139
+#define CLK_TOP_AUD_I2S1_MCLK			140
+#define CLK_TOP_AUD_I2S2_MCLK			141
+#define CLK_TOP_AUD_I2S3_MCLK			142
+#define CLK_TOP_AUD_I2S4_MCLK			143
+#define CLK_TOP_AUD_I2S5_MCLK			144
+#define CLK_TOP_AUD_I2S6_MCLK			145
+#define CLK_TOP_AUD_48K_TIMING			146
+#define CLK_TOP_AUD_44K_TIMING			147
+
+#define CLK_TOP_32K_INTERNAL			148
+#define CLK_TOP_32K_EXTERNAL			149
+#define CLK_TOP_CLK26M_D8			150
+#define CLK_TOP_8BDAC				151
+#define CLK_TOP_WBG_DIG_416M			152
+#define CLK_TOP_DPI				153
+#define CLK_TOP_DSI0_LNTC_DSI			154
+#define CLK_TOP_AUD_EXT1			155
+#define CLK_TOP_AUD_EXT2			156
+#define CLK_TOP_NFI1X_PAD			157
+#define CLK_TOP_AXISEL_D4			158
 #define CLK_TOP_NR				159
 
 /* APMIXEDSYS */
-#define CLK_APMIXED_ARMPLL			0
-#define CLK_APMIXED_MAINPLL			1
-#define CLK_APMIXED_UNIVPLL			2
-#define CLK_APMIXED_MMPLL			3
-#define CLK_APMIXED_MSDCPLL			4
-#define CLK_APMIXED_TVDPLL			5
-#define CLK_APMIXED_AUD1PLL			6
-#define CLK_APMIXED_TRGPLL			7
-#define CLK_APMIXED_ETHPLL			8
-#define CLK_APMIXED_VDECPLL			9
-#define CLK_APMIXED_HADDS2PLL			10
-#define CLK_APMIXED_AUD2PLL			11
-#define CLK_APMIXED_TVD2PLL			12
-#define CLK_APMIXED_NR				13
+
+#define CLK_APMIXED_ARMPLL			1
+#define CLK_APMIXED_MAINPLL			2
+#define CLK_APMIXED_UNIVPLL			3
+#define CLK_APMIXED_MMPLL			4
+#define CLK_APMIXED_MSDCPLL			5
+#define CLK_APMIXED_TVDPLL			6
+#define CLK_APMIXED_AUD1PLL			7
+#define CLK_APMIXED_TRGPLL			8
+#define CLK_APMIXED_ETHPLL			9
+#define CLK_APMIXED_VDECPLL			10
+#define CLK_APMIXED_HADDS2PLL			11
+#define CLK_APMIXED_AUD2PLL			12
+#define CLK_APMIXED_TVD2PLL			13
+#define CLK_APMIXED_HDMI_REF			14
+#define CLK_APMIXED_NR				15
+
+/* DDRPHY */
+
+#define CLK_DDRPHY_VENCPLL			1
+#define CLK_DDRPHY_NR				2
 
 /* INFRACFG */
-#define CLK_INFRA_DBG				0
-#define CLK_INFRA_SMI				1
-#define CLK_INFRA_QAXI_CM4			2
-#define CLK_INFRA_AUD_SPLIN_B			3
-#define CLK_INFRA_AUDIO				4
-#define CLK_INFRA_EFUSE				5
-#define CLK_INFRA_L2C_SRAM			6
-#define CLK_INFRA_M4U				7
-#define CLK_INFRA_CONNMCU			8
-#define CLK_INFRA_TRNG				9
-#define CLK_INFRA_RAMBUFIF			10
-#define CLK_INFRA_CPUM				11
-#define CLK_INFRA_KP				12
-#define CLK_INFRA_CEC				13
-#define CLK_INFRA_IRRX				14
-#define CLK_INFRA_PMICSPI			15
-#define CLK_INFRA_PMICWRAP			16
-#define CLK_INFRA_DDCCI				17
-#define CLK_INFRA_CPUSEL			18
-#define CLK_INFRA_NR				19
+
+#define CLK_INFRA_DBG				1
+#define CLK_INFRA_SMI				2
+#define CLK_INFRA_QAXI_CM4			3
+#define CLK_INFRA_AUD_SPLIN_B			4
+#define CLK_INFRA_AUDIO				5
+#define CLK_INFRA_EFUSE				6
+#define CLK_INFRA_L2C_SRAM			7
+#define CLK_INFRA_M4U				8
+#define CLK_INFRA_CONNMCU			9
+#define CLK_INFRA_TRNG				10
+#define CLK_INFRA_RAMBUFIF			11
+#define CLK_INFRA_CPUM				12
+#define CLK_INFRA_KP				13
+#define CLK_INFRA_CEC				14
+#define CLK_INFRA_IRRX				15
+#define CLK_INFRA_PMICSPI			16
+#define CLK_INFRA_PMICWRAP			17
+#define CLK_INFRA_DDCCI				18
+#define CLK_INFRA_CLK_13M			19
+#define CLK_INFRA_CPUSEL                        20
+#define CLK_INFRA_NR				21
 
 /* PERICFG */
-#define CLK_PERI_NFI				0
-#define CLK_PERI_THERM				1
-#define CLK_PERI_PWM1				2
-#define CLK_PERI_PWM2				3
-#define CLK_PERI_PWM3				4
-#define CLK_PERI_PWM4				5
-#define CLK_PERI_PWM5				6
-#define CLK_PERI_PWM6				7
-#define CLK_PERI_PWM7				8
-#define CLK_PERI_PWM				9
-#define CLK_PERI_USB0				10
-#define CLK_PERI_USB1				11
-#define CLK_PERI_AP_DMA				12
-#define CLK_PERI_MSDC30_0			13
-#define CLK_PERI_MSDC30_1			14
-#define CLK_PERI_MSDC30_2			15
-#define CLK_PERI_MSDC30_3			16
-#define CLK_PERI_MSDC50_3			17
-#define CLK_PERI_NLI				18
-#define CLK_PERI_UART0				19
-#define CLK_PERI_UART1				20
-#define CLK_PERI_UART2				21
-#define CLK_PERI_UART3				22
-#define CLK_PERI_BTIF				23
-#define CLK_PERI_I2C0				24
-#define CLK_PERI_I2C1				25
-#define CLK_PERI_I2C2				26
-#define CLK_PERI_I2C3				27
-#define CLK_PERI_AUXADC				28
-#define CLK_PERI_SPI0				39
-#define CLK_PERI_ETH				30
-#define CLK_PERI_USB0_MCU			31
-
-#define CLK_PERI_USB1_MCU			32
-#define CLK_PERI_USB_SLV			33
-#define CLK_PERI_GCPU				34
-#define CLK_PERI_NFI_ECC			35
-#define CLK_PERI_NFI_PAD			36
-#define CLK_PERI_FLASH				37
-#define CLK_PERI_HOST89_INT			38
-#define CLK_PERI_HOST89_SPI			39
-#define CLK_PERI_HOST89_DVD			40
-#define CLK_PERI_SPI1				41
-#define CLK_PERI_SPI2				42
-#define CLK_PERI_FCI				43
-#define CLK_PERI_NR				44
+
+#define CLK_PERI_NFI				1
+#define CLK_PERI_THERM				2
+#define CLK_PERI_PWM1				3
+#define CLK_PERI_PWM2				4
+#define CLK_PERI_PWM3				5
+#define CLK_PERI_PWM4				6
+#define CLK_PERI_PWM5				7
+#define CLK_PERI_PWM6				8
+#define CLK_PERI_PWM7				9
+#define CLK_PERI_PWM				10
+#define CLK_PERI_USB0				11
+#define CLK_PERI_USB1				12
+#define CLK_PERI_AP_DMA				13
+#define CLK_PERI_MSDC30_0			14
+#define CLK_PERI_MSDC30_1			15
+#define CLK_PERI_MSDC30_2			16
+#define CLK_PERI_MSDC30_3			17
+#define CLK_PERI_MSDC50_3			18
+#define CLK_PERI_NLI				19
+#define CLK_PERI_UART0				20
+#define CLK_PERI_UART1				21
+#define CLK_PERI_UART2				22
+#define CLK_PERI_UART3				23
+#define CLK_PERI_BTIF				24
+#define CLK_PERI_I2C0				25
+#define CLK_PERI_I2C1				26
+#define CLK_PERI_I2C2				27
+#define CLK_PERI_I2C3				28
+#define CLK_PERI_AUXADC				29
+#define CLK_PERI_SPI0				30
+#define CLK_PERI_ETH				31
+#define CLK_PERI_USB0_MCU			32
+
+#define CLK_PERI_USB1_MCU			33
+#define CLK_PERI_USB_SLV			34
+#define CLK_PERI_GCPU				35
+#define CLK_PERI_NFI_ECC			36
+#define CLK_PERI_NFI_PAD			37
+#define CLK_PERI_FLASH				38
+#define CLK_PERI_HOST89_INT			39
+#define CLK_PERI_HOST89_SPI			40
+#define CLK_PERI_HOST89_DVD			41
+#define CLK_PERI_SPI1				42
+#define CLK_PERI_SPI2				43
+#define CLK_PERI_FCI				44
+
+#define CLK_PERI_UART0_SEL			45
+#define CLK_PERI_UART1_SEL			46
+#define CLK_PERI_UART2_SEL			47
+#define CLK_PERI_UART3_SEL			48
+#define CLK_PERI_NR				49
 
 /* AUDIO */
-#define CLK_AUD_AFE				0
-#define CLK_AUD_LRCK_DETECT			1
-#define CLK_AUD_I2S				2
-#define CLK_AUD_APLL_TUNER			3
-#define CLK_AUD_HDMI				4
-#define CLK_AUD_SPDF				5
-#define CLK_AUD_SPDF2				6
-#define CLK_AUD_APLL				7
-#define CLK_AUD_TML				8
-#define CLK_AUD_AHB_IDLE_EXT			9
-#define CLK_AUD_AHB_IDLE_INT			10
-
-#define CLK_AUD_I2SIN1				11
-#define CLK_AUD_I2SIN2				12
-#define CLK_AUD_I2SIN3				13
-#define CLK_AUD_I2SIN4				14
-#define CLK_AUD_I2SIN5				15
-#define CLK_AUD_I2SIN6				16
-#define CLK_AUD_I2SO1				17
-#define CLK_AUD_I2SO2				18
-#define CLK_AUD_I2SO3				19
-#define CLK_AUD_I2SO4				20
-#define CLK_AUD_I2SO5				21
-#define CLK_AUD_I2SO6				22
-#define CLK_AUD_ASRCI1				23
-#define CLK_AUD_ASRCI2				24
-#define CLK_AUD_ASRCO1				25
-#define CLK_AUD_ASRCO2				26
-#define CLK_AUD_ASRC11				27
-#define CLK_AUD_ASRC12				28
-#define CLK_AUD_HDMIRX				29
-#define CLK_AUD_INTDIR				30
-#define CLK_AUD_A1SYS				31
-#define CLK_AUD_A2SYS				32
-#define CLK_AUD_AFE_CONN			33
-#define CLK_AUD_AFE_PCMIF			34
-#define CLK_AUD_AFE_MRGIF			35
-
-#define CLK_AUD_MMIF_UL1			36
-#define CLK_AUD_MMIF_UL2			37
-#define CLK_AUD_MMIF_UL3			38
-#define CLK_AUD_MMIF_UL4			39
-#define CLK_AUD_MMIF_UL5			40
-#define CLK_AUD_MMIF_UL6			41
-#define CLK_AUD_MMIF_DL1			42
-#define CLK_AUD_MMIF_DL2			43
-#define CLK_AUD_MMIF_DL3			44
-#define CLK_AUD_MMIF_DL4			45
-#define CLK_AUD_MMIF_DL5			46
-#define CLK_AUD_MMIF_DL6			47
-#define CLK_AUD_MMIF_DLMCH			48
-#define CLK_AUD_MMIF_ARB1			49
-#define CLK_AUD_MMIF_AWB1			50
-#define CLK_AUD_MMIF_AWB2			51
-#define CLK_AUD_MMIF_DAI			52
-
-#define CLK_AUD_DMIC1				53
-#define CLK_AUD_DMIC2				54
-#define CLK_AUD_ASRCI3				55
-#define CLK_AUD_ASRCI4				56
-#define CLK_AUD_ASRCI5				57
-#define CLK_AUD_ASRCI6				58
-#define CLK_AUD_ASRCO3				59
-#define CLK_AUD_ASRCO4				60
-#define CLK_AUD_ASRCO5				61
-#define CLK_AUD_ASRCO6				62
-#define CLK_AUD_MEM_ASRC1			63
-#define CLK_AUD_MEM_ASRC2			64
-#define CLK_AUD_MEM_ASRC3			65
-#define CLK_AUD_MEM_ASRC4			66
-#define CLK_AUD_MEM_ASRC5			67
-#define CLK_AUD_DSD_ENC				68
-#define CLK_AUD_ASRC_BRG			60
-#define CLK_AUD_NR				70
+
+#define CLK_AUD_AFE				1
+#define CLK_AUD_LRCK_DETECT			2
+#define CLK_AUD_I2S				3
+#define CLK_AUD_APLL_TUNER			4
+#define CLK_AUD_HDMI				5
+#define CLK_AUD_SPDF				6
+#define CLK_AUD_SPDF2				7
+#define CLK_AUD_APLL				8
+#define CLK_AUD_TML				9
+#define CLK_AUD_AHB_IDLE_EXT			10
+#define CLK_AUD_AHB_IDLE_INT			11
+
+#define CLK_AUD_I2SIN1				12
+#define CLK_AUD_I2SIN2				13
+#define CLK_AUD_I2SIN3				14
+#define CLK_AUD_I2SIN4				15
+#define CLK_AUD_I2SIN5				16
+#define CLK_AUD_I2SIN6				17
+#define CLK_AUD_I2SO1				18
+#define CLK_AUD_I2SO2				19
+#define CLK_AUD_I2SO3				20
+#define CLK_AUD_I2SO4				21
+#define CLK_AUD_I2SO5				22
+#define CLK_AUD_I2SO6				23
+#define CLK_AUD_ASRCI1				24
+#define CLK_AUD_ASRCI2				25
+#define CLK_AUD_ASRCO1				26
+#define CLK_AUD_ASRCO2				27
+#define CLK_AUD_ASRC11				28
+#define CLK_AUD_ASRC12				29
+#define CLK_AUD_HDMIRX				30
+#define CLK_AUD_INTDIR				31
+#define CLK_AUD_A1SYS				32
+#define CLK_AUD_A2SYS				33
+#define CLK_AUD_AFE_CONN			34
+#define CLK_AUD_AFE_PCMIF			35
+#define CLK_AUD_AFE_MRGIF			36
+
+#define CLK_AUD_MMIF_UL1			37
+#define CLK_AUD_MMIF_UL2			38
+#define CLK_AUD_MMIF_UL3			39
+#define CLK_AUD_MMIF_UL4			40
+#define CLK_AUD_MMIF_UL5			41
+#define CLK_AUD_MMIF_UL6			42
+#define CLK_AUD_MMIF_DL1			43
+#define CLK_AUD_MMIF_DL2			44
+#define CLK_AUD_MMIF_DL3			45
+#define CLK_AUD_MMIF_DL4			46
+#define CLK_AUD_MMIF_DL5			47
+#define CLK_AUD_MMIF_DL6			48
+#define CLK_AUD_MMIF_DLMCH			49
+#define CLK_AUD_MMIF_ARB1			50
+#define CLK_AUD_MMIF_AWB1			51
+#define CLK_AUD_MMIF_AWB2			52
+#define CLK_AUD_MMIF_DAI			53
+
+#define CLK_AUD_DMIC1				54
+#define CLK_AUD_DMIC2				55
+#define CLK_AUD_ASRCI3				56
+#define CLK_AUD_ASRCI4				57
+#define CLK_AUD_ASRCI5				58
+#define CLK_AUD_ASRCI6				59
+#define CLK_AUD_ASRCO3				60
+#define CLK_AUD_ASRCO4				61
+#define CLK_AUD_ASRCO5				62
+#define CLK_AUD_ASRCO6				63
+#define CLK_AUD_MEM_ASRC1			64
+#define CLK_AUD_MEM_ASRC2			65
+#define CLK_AUD_MEM_ASRC3			66
+#define CLK_AUD_MEM_ASRC4			67
+#define CLK_AUD_MEM_ASRC5			68
+#define CLK_AUD_DSD_ENC				69
+#define CLK_AUD_ASRC_BRG			70
+#define CLK_AUD_NR				71
 
 /* MMSYS */
-#define CLK_MM_SMI_COMMON			0
-#define CLK_MM_SMI_LARB0			1
-#define CLK_MM_CMDQ				2
-#define CLK_MM_MUTEX				3
-#define CLK_MM_DISP_COLOR			4
-#define CLK_MM_DISP_BLS				5
-#define CLK_MM_DISP_WDMA			6
-#define CLK_MM_DISP_RDMA			7
-#define CLK_MM_DISP_OVL				8
-#define CLK_MM_MDP_TDSHP			9
-#define CLK_MM_MDP_WROT				10
-#define CLK_MM_MDP_WDMA				11
-#define CLK_MM_MDP_RSZ1				12
-#define CLK_MM_MDP_RSZ0				13
-#define CLK_MM_MDP_RDMA				14
-#define CLK_MM_MDP_BLS_26M			15
-#define CLK_MM_CAM_MDP				16
-#define CLK_MM_FAKE_ENG				17
-#define CLK_MM_MUTEX_32K			18
-#define CLK_MM_DISP_RDMA1			19
-#define CLK_MM_DISP_UFOE			20
-
-#define CLK_MM_DSI_ENGINE			21
-#define CLK_MM_DSI_DIG				22
-#define CLK_MM_DPI_DIGL				23
-#define CLK_MM_DPI_ENGINE			24
-#define CLK_MM_DPI1_DIGL			25
-#define CLK_MM_DPI1_ENGINE			26
-#define CLK_MM_TVE_OUTPUT			27
-#define CLK_MM_TVE_INPUT			28
-#define CLK_MM_HDMI_PIXEL			29
-#define CLK_MM_HDMI_PLL				30
-#define CLK_MM_HDMI_AUDIO			31
-#define CLK_MM_HDMI_SPDIF			32
-#define CLK_MM_TVE_FMM				33
-#define CLK_MM_NR				34
+
+#define CLK_MM_SMI_COMMON			1
+#define CLK_MM_SMI_LARB0			2
+#define CLK_MM_CMDQ				3
+#define CLK_MM_MUTEX				4
+#define CLK_MM_DISP_COLOR			5
+#define CLK_MM_DISP_BLS				6
+#define CLK_MM_DISP_WDMA			7
+#define CLK_MM_DISP_RDMA			8
+#define CLK_MM_DISP_OVL				9
+#define CLK_MM_MDP_TDSHP			10
+#define CLK_MM_MDP_WROT				11
+#define CLK_MM_MDP_WDMA				12
+#define CLK_MM_MDP_RSZ1				13
+#define CLK_MM_MDP_RSZ0				14
+#define CLK_MM_MDP_RDMA				15
+#define CLK_MM_MDP_BLS_26M			16
+#define CLK_MM_CAM_MDP				17
+#define CLK_MM_FAKE_ENG				18
+#define CLK_MM_MUTEX_32K			19
+#define CLK_MM_DISP_RDMA1			20
+#define CLK_MM_DISP_UFOE			21
+
+#define CLK_MM_DSI_ENGINE			22
+#define CLK_MM_DSI_DIG				23
+#define CLK_MM_DPI_DIGL				24
+#define CLK_MM_DPI_ENGINE			25
+#define CLK_MM_DPI1_DIGL			26
+#define CLK_MM_DPI1_ENGINE			27
+#define CLK_MM_TVE_OUTPUT			28
+#define CLK_MM_TVE_INPUT			29
+#define CLK_MM_HDMI_PIXEL			30
+#define CLK_MM_HDMI_PLL				31
+#define CLK_MM_HDMI_AUDIO			32
+#define CLK_MM_HDMI_SPDIF			33
+#define CLK_MM_TVE_FMM				34
+#define CLK_MM_NR				35
 
 /* IMGSYS */
-#define CLK_IMG_SMI_COMM			0
-#define CLK_IMG_RESZ				1
-#define CLK_IMG_JPGDEC_SMI			2
-#define CLK_IMG_JPGDEC				3
-#define CLK_IMG_VENC_LT				4
-#define CLK_IMG_VENC				5
-#define CLK_IMG_NR				6
+
+#define CLK_IMG_SMI_COMM			1
+#define CLK_IMG_RESZ				2
+#define CLK_IMG_JPGDEC_SMI			3
+#define CLK_IMG_JPGDEC				4
+#define CLK_IMG_VENC_LT				5
+#define CLK_IMG_VENC				6
+#define CLK_IMG_NR				7
 
 /* VDEC */
-#define CLK_VDEC_CKGEN				0
-#define CLK_VDEC_LARB				1
-#define CLK_VDEC_NR				2
+
+#define CLK_VDEC_CKGEN				1
+#define CLK_VDEC_LARB				2
+#define CLK_VDEC_NR				3
 
 /* HIFSYS */
-#define CLK_HIFSYS_USB0PHY			0
-#define CLK_HIFSYS_USB1PHY			1
-#define CLK_HIFSYS_PCIE0			2
-#define CLK_HIFSYS_PCIE1			3
-#define CLK_HIFSYS_PCIE2			4
-#define CLK_HIFSYS_NR				5
+
+#define CLK_HIFSYS_USB0PHY			1
+#define CLK_HIFSYS_USB1PHY			2
+#define CLK_HIFSYS_PCIE0			3
+#define CLK_HIFSYS_PCIE1			4
+#define CLK_HIFSYS_PCIE2			5
+#define CLK_HIFSYS_NR				6
 
 /* ETHSYS */
-#define CLK_ETHSYS_HSDMA			0
-#define CLK_ETHSYS_ESW				1
-#define CLK_ETHSYS_GP2				2
-#define CLK_ETHSYS_GP1				3
-#define CLK_ETHSYS_PCM				4
-#define CLK_ETHSYS_GDMA				5
-#define CLK_ETHSYS_I2S				6
-#define CLK_ETHSYS_CRYPTO			7
-#define CLK_ETHSYS_NR				8
+#define CLK_ETHSYS_HSDMA			1
+#define CLK_ETHSYS_ESW				2
+#define CLK_ETHSYS_GP2				3
+#define CLK_ETHSYS_GP1				4
+#define CLK_ETHSYS_PCM				5
+#define CLK_ETHSYS_GDMA				6
+#define CLK_ETHSYS_I2S				7
+#define CLK_ETHSYS_CRYPTO			8
+#define CLK_ETHSYS_NR				9
 
 /* G3DSYS */
-#define CLK_G3DSYS_CORE				0
-#define CLK_G3DSYS_NR				1
+#define CLK_G3DSYS_CORE				1
+#define CLK_G3DSYS_NR				2
+
+/* BDP */
+
+#define CLK_BDP_BRG_BA				1
+#define CLK_BDP_BRG_DRAM			2
+#define CLK_BDP_LARB_DRAM			3
+#define CLK_BDP_WR_VDI_PXL			4
+#define CLK_BDP_WR_VDI_DRAM			5
+#define CLK_BDP_WR_B				6
+#define CLK_BDP_DGI_IN				7
+#define CLK_BDP_DGI_OUT				8
+#define CLK_BDP_FMT_MAST_27			9
+#define CLK_BDP_FMT_B				10
+#define CLK_BDP_OSD_B				11
+#define CLK_BDP_OSD_DRAM			12
+#define CLK_BDP_OSD_AGENT			13
+#define CLK_BDP_OSD_PXL				14
+#define CLK_BDP_RLE_B				15
+#define CLK_BDP_RLE_AGENT			16
+#define CLK_BDP_RLE_DRAM			17
+#define CLK_BDP_F27M				18
+#define CLK_BDP_F27M_VDOUT			19
+#define CLK_BDP_F27_74_74			20
+#define CLK_BDP_F2FS				21
+#define CLK_BDP_F2FS74_148			22
+#define CLK_BDP_FB				23
+#define CLK_BDP_VDO_DRAM			24
+#define CLK_BDP_VDO_2FS				25
+#define CLK_BDP_VDO_B				26
+#define CLK_BDP_WR_DI_PXL			27
+#define CLK_BDP_WR_DI_DRAM			28
+#define CLK_BDP_WR_DI_B				29
+#define CLK_BDP_NR_PXL				30
+#define CLK_BDP_NR_DRAM				31
+#define CLK_BDP_NR_B				32
+
+#define CLK_BDP_RX_F				33
+#define CLK_BDP_RX_X				34
+#define CLK_BDP_RXPDT				35
+#define CLK_BDP_RX_CSCL_N			36
+#define CLK_BDP_RX_CSCL				37
+#define CLK_BDP_RX_DDCSCL_N			38
+#define CLK_BDP_RX_DDCSCL			39
+#define CLK_BDP_RX_VCO				40
+#define CLK_BDP_RX_DP				41
+#define CLK_BDP_RX_P				42
+#define CLK_BDP_RX_M				43
+#define CLK_BDP_RX_PLL				44
+#define CLK_BDP_BRG_RT_B			45
+#define CLK_BDP_BRG_RT_DRAM			46
+#define CLK_BDP_LARBRT_DRAM			47
+#define CLK_BDP_TMDS_SYN			48
+#define CLK_BDP_HDMI_MON			49
+#define CLK_BDP_NR				50
 
 #endif /* _DT_BINDINGS_CLK_MT2701_H */
-- 
2.45.2

[PATCH 4/5] clk: mediatek: mt7623: remap apmixedsys clock ID

[Christian Marangi]

Define remap table also for apmixedsys clock ID. The clock ID starts
from 1 instead of 0 in upstream kernel linux.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/clk/mediatek/clk-mt7623.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
index 6af6f9f11bd..78e390d49f8 100644
--- a/drivers/clk/mediatek/clk-mt7623.c
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -25,6 +25,22 @@
 #define AXI_DIV_SEL(x)			(x)
 
 /* apmixedsys */
+static const int pll_id_offs_map[] = {
+	[CLK_APMIXED_ARMPLL]			= 0,
+	[CLK_APMIXED_MAINPLL]			= 1,
+	[CLK_APMIXED_UNIVPLL]			= 2,
+	[CLK_APMIXED_MMPLL]			= 3,
+	[CLK_APMIXED_MSDCPLL]			= 4,
+	[CLK_APMIXED_TVDPLL]			= 5,
+	[CLK_APMIXED_AUD1PLL]			= 6,
+	[CLK_APMIXED_TRGPLL]			= 7,
+	[CLK_APMIXED_ETHPLL]			= 8,
+	[CLK_APMIXED_VDECPLL]			= 9,
+	[CLK_APMIXED_HADDS2PLL]			= 10,
+	[CLK_APMIXED_AUD2PLL]			= 11,
+	[CLK_APMIXED_TVD2PLL]			= 12,
+};
+
 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,	\
 	    _pd_shift, _pcw_reg, _pcw_shift) {				\
 		.id = _id,						\
@@ -911,6 +927,7 @@ static const struct mtk_gate hif_cgs[] = {
 
 static const struct mtk_clk_tree mt7623_apmixedsys_clk_tree = {
 	.xtal2_rate = 26 * MHZ,
+	.id_offs_map = pll_id_offs_map,
 	.plls = apmixed_plls,
 };
 
-- 
2.45.2

[PATCH 5/5] clk: mediatek: mt7623: remap peri clock ID and add MUX

[Christian Marangi]

Upstream kernel linux makes use of peri clock MUX to setup UART.

Add definition for these and add remap table as in the upstream clock ID
order gates are before MUX but we require MUX first and then clocks in
our downstream driver.

Convert the peri clk tree to MUX + GATE implementation.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/clk/mediatek/clk-mt7623.c | 83 +++++++++++++++++++++++++++++--
 1 file changed, 80 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
index 78e390d49f8..d0b80f48b0a 100644
--- a/drivers/clk/mediatek/clk-mt7623.c
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -807,6 +807,74 @@ static const struct mtk_gate infra_cgs[] = {
 };
 
 /* pericfg */
+static const int peri_id_offs_map[] = {
+	/* MUX CLK */
+	[CLK_PERI_UART0_SEL]			= 1,
+	[CLK_PERI_UART1_SEL]			= 2,
+	[CLK_PERI_UART2_SEL]			= 3,
+	[CLK_PERI_UART3_SEL]			= 4,
+	/* GATE CLK */
+	[CLK_PERI_NFI]				= 5,
+	[CLK_PERI_THERM]			= 6,
+	[CLK_PERI_PWM1]				= 7,
+	[CLK_PERI_PWM2]				= 8,
+	[CLK_PERI_PWM3]				= 9,
+	[CLK_PERI_PWM4]				= 10,
+	[CLK_PERI_PWM5]				= 11,
+	[CLK_PERI_PWM6]				= 12,
+	[CLK_PERI_PWM7]				= 13,
+	[CLK_PERI_PWM]				= 14,
+	[CLK_PERI_USB0]				= 15,
+	[CLK_PERI_USB1]				= 16,
+	[CLK_PERI_AP_DMA]			= 17,
+	[CLK_PERI_MSDC30_0]			= 18,
+	[CLK_PERI_MSDC30_1]			= 19,
+	[CLK_PERI_MSDC30_2]			= 20,
+	[CLK_PERI_MSDC30_3]			= 21,
+	[CLK_PERI_MSDC50_3]			= 22,
+	[CLK_PERI_NLI]				= 23,
+	[CLK_PERI_UART0]			= 24,
+	[CLK_PERI_UART1]			= 25,
+	[CLK_PERI_UART2]			= 26,
+	[CLK_PERI_UART3]			= 27,
+	[CLK_PERI_BTIF]				= 28,
+	[CLK_PERI_I2C0]				= 29,
+	[CLK_PERI_I2C1]				= 30,
+	[CLK_PERI_I2C2]				= 31,
+	[CLK_PERI_I2C3]				= 32,
+	[CLK_PERI_AUXADC]			= 33,
+	[CLK_PERI_SPI0]				= 34,
+	[CLK_PERI_ETH]				= 35,
+	[CLK_PERI_USB0_MCU]			= 36,
+	[CLK_PERI_USB1_MCU]			= 37,
+	[CLK_PERI_USB_SLV]			= 38,
+	[CLK_PERI_GCPU]				= 39,
+	[CLK_PERI_NFI_ECC]			= 40,
+	[CLK_PERI_NFI_PAD]			= 41,
+	[CLK_PERI_FLASH]			= 42,
+	[CLK_PERI_HOST89_INT]			= 43,
+	[CLK_PERI_HOST89_SPI]			= 44,
+	[CLK_PERI_HOST89_DVD]			= 45,
+	[CLK_PERI_SPI1]				= 46,
+	[CLK_PERI_SPI2]				= 47,
+	[CLK_PERI_FCI]				= 48,
+};
+
+#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)
+#define XTAL_PARENT(_id) PARENT(_id, CLK_PARENT_XTAL)
+
+static const struct mtk_parent uart_ck_sel_parents[] = {
+	XTAL_PARENT(CLK_XTAL),
+	TOP_PARENT(CLK_TOP_UART_SEL),
+};
+
+static const struct mtk_composite peri_muxes[] = {
+	MUX_MIXED(CLK_PERI_UART0_SEL, uart_ck_sel_parents, 0x40C, 0, 1),
+	MUX_MIXED(CLK_PERI_UART1_SEL, uart_ck_sel_parents, 0x40C, 1, 1),
+	MUX_MIXED(CLK_PERI_UART2_SEL, uart_ck_sel_parents, 0x40C, 2, 1),
+	MUX_MIXED(CLK_PERI_UART3_SEL, uart_ck_sel_parents, 0x40C, 3, 1),
+};
+
 static const struct mtk_gate_regs peri0_cg_regs = {
 	.set_ofs = 0x8,
 	.clr_ofs = 0x10,
@@ -980,6 +1048,7 @@ static int mt7623_topckgen_probe(struct udevice *dev)
 static const struct mtk_clk_tree mt7623_clk_gate_tree = {
 	/* Each CLK ID for gates clock starts at index 1 */
 	.gates_offs = 1,
+	.xtal_rate = 26 * MHZ,
 };
 
 static int mt7623_infracfg_probe(struct udevice *dev)
@@ -988,10 +1057,18 @@ static int mt7623_infracfg_probe(struct udevice *dev)
 					infra_cgs);
 }
 
+static const struct mtk_clk_tree mt7623_clk_peri_tree = {
+	.id_offs_map = peri_id_offs_map,
+	.muxes_offs = peri_id_offs_map[CLK_PERI_UART0_SEL],
+	.gates_offs = peri_id_offs_map[CLK_PERI_NFI],
+	.muxes = peri_muxes,
+	.gates = peri_cgs,
+	.xtal_rate = 26 * MHZ,
+};
+
 static int mt7623_pericfg_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree,
-					peri_cgs);
+	return mtk_common_clk_infrasys_init(dev, &mt7623_clk_peri_tree);
 }
 
 static int mt7623_hifsys_probe(struct udevice *dev)
@@ -1098,7 +1175,7 @@ U_BOOT_DRIVER(mtk_clk_pericfg) = {
 	.of_match = mt7623_pericfg_compat,
 	.probe = mt7623_pericfg_probe,
 	.priv_auto	= sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.ops = &mtk_clk_infrasys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-- 
2.45.2

Aw: [PATCH 5/5] clk: mediatek: mt7623: remap peri clock ID and add MUX

[Frank Wunderlich]

Hi,

does not break downstream dts (still have some issues with ethernet without the series, which i cannot nail down) so only tested: usb,mmc,pci,sata

also works with upstream dts and a bunch of modifications (i still need to clean)

Tested-by: Frank Wunderlich <frank-w@public-files.de>

regards Frank


> Gesendet: Freitag, 02. August 2024 um 15:45 Uhr
> Von: "Christian Marangi" <ansuelsmth@gmail.com>
> An: "Lukasz Majewski" <lukma@denx.de>, "Sean Anderson" <seanga2@gmail.com>, "Ryder Lee" <ryder.lee@mediatek.com>, "Weijie Gao" <weijie.gao@mediatek.com>, "Chunfeng Yun" <chunfeng.yun@mediatek.com>, "GSS_MTK_Uboot_upstream" <GSS_MTK_Uboot_upstream@mediatek.com>, "Tom Rini" <trini@konsulko.com>, "Christian Marangi" <ansuelsmth@gmail.com>, u-boot@lists.denx.de
> Betreff: [PATCH 5/5] clk: mediatek: mt7623: remap peri clock ID and add MUX
>
> Upstream kernel linux makes use of peri clock MUX to setup UART.
>
> Add definition for these and add remap table as in the upstream clock ID
> order gates are before MUX but we require MUX first and then clocks in
> our downstream driver.
>
> Convert the peri clk tree to MUX + GATE implementation.
>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
>  drivers/clk/mediatek/clk-mt7623.c | 83 +++++++++++++++++++++++++++++--
>  1 file changed, 80 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
> index 78e390d49f8..d0b80f48b0a 100644
> --- a/drivers/clk/mediatek/clk-mt7623.c
> +++ b/drivers/clk/mediatek/clk-mt7623.c
> @@ -807,6 +807,74 @@ static const struct mtk_gate infra_cgs[] = {
>  };
>
>  /* pericfg */
> +static const int peri_id_offs_map[] = {
> +	/* MUX CLK */
> +	[CLK_PERI_UART0_SEL]			= 1,
> +	[CLK_PERI_UART1_SEL]			= 2,
> +	[CLK_PERI_UART2_SEL]			= 3,
> +	[CLK_PERI_UART3_SEL]			= 4,
> +	/* GATE CLK */
> +	[CLK_PERI_NFI]				= 5,
> +	[CLK_PERI_THERM]			= 6,
> +	[CLK_PERI_PWM1]				= 7,
> +	[CLK_PERI_PWM2]				= 8,
> +	[CLK_PERI_PWM3]				= 9,
> +	[CLK_PERI_PWM4]				= 10,
> +	[CLK_PERI_PWM5]				= 11,
> +	[CLK_PERI_PWM6]				= 12,
> +	[CLK_PERI_PWM7]				= 13,
> +	[CLK_PERI_PWM]				= 14,
> +	[CLK_PERI_USB0]				= 15,
> +	[CLK_PERI_USB1]				= 16,
> +	[CLK_PERI_AP_DMA]			= 17,
> +	[CLK_PERI_MSDC30_0]			= 18,
> +	[CLK_PERI_MSDC30_1]			= 19,
> +	[CLK_PERI_MSDC30_2]			= 20,
> +	[CLK_PERI_MSDC30_3]			= 21,
> +	[CLK_PERI_MSDC50_3]			= 22,
> +	[CLK_PERI_NLI]				= 23,
> +	[CLK_PERI_UART0]			= 24,
> +	[CLK_PERI_UART1]			= 25,
> +	[CLK_PERI_UART2]			= 26,
> +	[CLK_PERI_UART3]			= 27,
> +	[CLK_PERI_BTIF]				= 28,
> +	[CLK_PERI_I2C0]				= 29,
> +	[CLK_PERI_I2C1]				= 30,
> +	[CLK_PERI_I2C2]				= 31,
> +	[CLK_PERI_I2C3]				= 32,
> +	[CLK_PERI_AUXADC]			= 33,
> +	[CLK_PERI_SPI0]				= 34,
> +	[CLK_PERI_ETH]				= 35,
> +	[CLK_PERI_USB0_MCU]			= 36,
> +	[CLK_PERI_USB1_MCU]			= 37,
> +	[CLK_PERI_USB_SLV]			= 38,
> +	[CLK_PERI_GCPU]				= 39,
> +	[CLK_PERI_NFI_ECC]			= 40,
> +	[CLK_PERI_NFI_PAD]			= 41,
> +	[CLK_PERI_FLASH]			= 42,
> +	[CLK_PERI_HOST89_INT]			= 43,
> +	[CLK_PERI_HOST89_SPI]			= 44,
> +	[CLK_PERI_HOST89_DVD]			= 45,
> +	[CLK_PERI_SPI1]				= 46,
> +	[CLK_PERI_SPI2]				= 47,
> +	[CLK_PERI_FCI]				= 48,
> +};
> +
> +#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)
> +#define XTAL_PARENT(_id) PARENT(_id, CLK_PARENT_XTAL)
> +
> +static const struct mtk_parent uart_ck_sel_parents[] = {
> +	XTAL_PARENT(CLK_XTAL),
> +	TOP_PARENT(CLK_TOP_UART_SEL),
> +};
> +
> +static const struct mtk_composite peri_muxes[] = {
> +	MUX_MIXED(CLK_PERI_UART0_SEL, uart_ck_sel_parents, 0x40C, 0, 1),
> +	MUX_MIXED(CLK_PERI_UART1_SEL, uart_ck_sel_parents, 0x40C, 1, 1),
> +	MUX_MIXED(CLK_PERI_UART2_SEL, uart_ck_sel_parents, 0x40C, 2, 1),
> +	MUX_MIXED(CLK_PERI_UART3_SEL, uart_ck_sel_parents, 0x40C, 3, 1),
> +};
> +
>  static const struct mtk_gate_regs peri0_cg_regs = {
>  	.set_ofs = 0x8,
>  	.clr_ofs = 0x10,
> @@ -980,6 +1048,7 @@ static int mt7623_topckgen_probe(struct udevice *dev)
>  static const struct mtk_clk_tree mt7623_clk_gate_tree = {
>  	/* Each CLK ID for gates clock starts at index 1 */
>  	.gates_offs = 1,
> +	.xtal_rate = 26 * MHZ,
>  };
>
>  static int mt7623_infracfg_probe(struct udevice *dev)
> @@ -988,10 +1057,18 @@ static int mt7623_infracfg_probe(struct udevice *dev)
>  					infra_cgs);
>  }
>
> +static const struct mtk_clk_tree mt7623_clk_peri_tree = {
> +	.id_offs_map = peri_id_offs_map,
> +	.muxes_offs = peri_id_offs_map[CLK_PERI_UART0_SEL],
> +	.gates_offs = peri_id_offs_map[CLK_PERI_NFI],
> +	.muxes = peri_muxes,
> +	.gates = peri_cgs,
> +	.xtal_rate = 26 * MHZ,
> +};
> +
>  static int mt7623_pericfg_probe(struct udevice *dev)
>  {
> -	return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree,
> -					peri_cgs);
> +	return mtk_common_clk_infrasys_init(dev, &mt7623_clk_peri_tree);
>  }
>
>  static int mt7623_hifsys_probe(struct udevice *dev)
> @@ -1098,7 +1175,7 @@ U_BOOT_DRIVER(mtk_clk_pericfg) = {
>  	.of_match = mt7623_pericfg_compat,
>  	.probe = mt7623_pericfg_probe,
>  	.priv_auto	= sizeof(struct mtk_cg_priv),
> -	.ops = &mtk_clk_gate_ops,
> +	.ops = &mtk_clk_infrasys_ops,
>  	.flags = DM_FLAG_PRE_RELOC,
>  };
>
> --
> 2.45.2
>
>

Re: [PATCH 0/5] clk: mediatek: mt7623: clk migration for OF_UPSTREAM

[Tom Rini]

On Fri, 02 Aug 2024 15:45:00 +0200, Christian Marangi wrote:

> These are all the required patches to migrate clk and correctly support
> OF_UPSTREAM. This will align the clk index to upstream to support the same
> clk implementation with downstream and upstream DTS.
> 
> Christian Marangi (5):
>   clk: mediatek: mt7623: fix broken peri_cgs clk with XTAL parents
>   clk: mediatek: mt7623: split clk tree to dedicated topckgen and
>     apmixed
>   clk: mediatek: mt7623: define id_offs_map and import clk ID from
>     upstream
>   clk: mediatek: mt7623: remap apmixedsys clock ID
>   clk: mediatek: mt7623: remap peri clock ID and add MUX
> 
> [...]

Applied to u-boot/next, thanks!

-- 
Tom