[PATCH 11/14] clk: mediatek: mt7981: replace infracfg ID with upstream linux

[Christian Marangi <ansuelsmth@gmail.com>]

Replace infracfg clk ID with upstream linux version.

Add some missing clk for PWM3 and for PCIe. The same format is used here
with the factor first, then mux and then gates.

To correctly reference the gates in clk_gate function, define the
gates_offs value in clk_tree now that they are at an offset from mux and
factor.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/clk/mediatek/clk-mt7981.c      |   1 +
 include/dt-bindings/clock/mt7981-clk.h | 136 ++++++++++++-------------
 2 files changed, 66 insertions(+), 71 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c
index aaaebd46791..4435430dcde 100644
--- a/drivers/clk/mediatek/clk-mt7981.c
+++ b/drivers/clk/mediatek/clk-mt7981.c
@@ -523,6 +523,7 @@ static const struct mtk_clk_tree mt7981_topckgen_clk_tree = {
 static const struct mtk_clk_tree mt7981_infracfg_clk_tree = {
 	.fdivs_offs = CK_INFRA_66M_MCK,
 	.muxes_offs = CK_INFRA_UART0_SEL,
+	.gates_offs = CK_INFRA_GPT_STA,
 	.fdivs = infra_fixed_divs,
 	.muxes = infra_muxes,
 	.flags = CLK_INFRASYS,
diff --git a/include/dt-bindings/clock/mt7981-clk.h b/include/dt-bindings/clock/mt7981-clk.h
index 8a6f5cb319e..05019c95ebe 100644
--- a/include/dt-bindings/clock/mt7981-clk.h
+++ b/include/dt-bindings/clock/mt7981-clk.h
@@ -8,11 +8,6 @@
 #ifndef _DT_BINDINGS_CLK_MT7981_H
 #define _DT_BINDINGS_CLK_MT7981_H
 
-/* INFRACFG */
-
-#define CK_INFRA_66M_MCK		0
-#define CLK_INFRA_NR_CLK		1
-
 /* TOPCKGEN */
 
 #define CK_TOP_CB_CKSQ_40M		0
@@ -124,74 +119,73 @@
 #define CK_TOP_U2U3_SYS_SEL		106
 #define CK_TOP_U2U3_XHCI_SEL		107
 #define CK_TOP_USB_FRMCNT_SEL		108
-#define CLK_TOP_NR_CLK			109
+#define CK_TOP_AUD_I2S_M		109
+#define CLK_TOP_NR_CLK			110
 
-/*
- * INFRACFG_AO
- * clock muxes need to be append to infracfg domain, and clock gates
- * need to be keep in infracgh_ao domain
- */
-#define INFRACFG_AO_OFFSET		10
+/* INFRACFG */
 
-#define CK_INFRA_UART0_SEL		(0 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_UART1_SEL		(1 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_UART2_SEL		(2 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_SPI0_SEL		(3 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_SPI1_SEL		(4 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_SPI2_SEL		(5 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_PWM1_SEL		(6 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_PWM2_SEL		(7 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_PWM_BSEL		(8 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_PCIE_SEL		(9 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_GPT_STA		(10 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_PWM_HCK		(11 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_PWM_STA		(12 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_PWM1_CK		(13 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_PWM2_CK		(14 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_CQ_DMA_CK		(15 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_AUD_BUS_CK		(16 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_AUD_26M_CK		(17 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_AUD_L_CK		(18 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_AUD_AUD_CK		(19 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_AUD_EG2_CK		(20 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_DRAMC_26M_CK		(21 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_DBG_CK			(22 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_AP_DMA_CK		(23 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SEJ_CK			(24 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SEJ_13M_CK		(25 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_THERM_CK		(26 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_I2C0_CK		(27 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_UART0_CK		(28 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_UART1_CK		(29 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_UART2_CK		(30 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SPI2_CK		(31 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SPI2_HCK_CK		(32 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_NFI1_CK		(33 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SPINFI1_CK		(34 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_NFI_HCK_CK		(35 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SPI0_CK		(36 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SPI1_CK		(37 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SPI0_HCK_CK		(38 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SPI1_HCK_CK		(39 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_FRTC_CK		(40 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_MSDC_CK		(41 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_MSDC_HCK_CK		(42 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_MSDC_133M_CK		(43 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_MSDC_66M_CK		(44 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_ADC_26M_CK		(45 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_ADC_FRC_CK		(46 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_FBIST2FPC_CK		(47 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_I2C_MCK_CK		(48 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_I2C_PCK_CK		(49 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_IUSB_133_CK		(50 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_IUSB_66M_CK		(51 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_IUSB_SYS_CK		(52 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_IUSB_CK		(53 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_IPCIE_CK		(54 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_IPCIER_CK		(55 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_IPCIEB_CK		(56 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_IPCIE_PIPE_CK		(57 - INFRACFG_AO_OFFSET)
-#define CLK_INFRA_AO_NR_CLK		(58 - INFRACFG_AO_OFFSET)
+#define CK_INFRA_66M_MCK		0
+#define CK_INFRA_UART0_SEL		1
+#define CK_INFRA_UART1_SEL		2
+#define CK_INFRA_UART2_SEL		3
+#define CK_INFRA_SPI0_SEL		4
+#define CK_INFRA_SPI1_SEL		5
+#define CK_INFRA_SPI2_SEL		6
+#define CK_INFRA_PWM1_SEL		7
+#define CK_INFRA_PWM2_SEL		8
+#define CK_INFRA_PWM3_SEL		9
+#define CK_INFRA_PWM_BSEL		10
+#define CK_INFRA_PCIE_SEL		11
+#define CK_INFRA_GPT_STA		12
+#define CK_INFRA_PWM_HCK		13
+#define CK_INFRA_PWM_STA		14
+#define CK_INFRA_PWM1_CK		15
+#define CK_INFRA_PWM2_CK		16
+#define CK_INFRA_PWM3_CK		17
+#define CK_INFRA_CQ_DMA_CK		18
+#define CK_INFRA_AUD_BUS_CK		19
+#define CK_INFRA_AUD_26M_CK		20
+#define CK_INFRA_AUD_L_CK		21
+#define CK_INFRA_AUD_AUD_CK		22
+#define CK_INFRA_AUD_EG2_CK		23
+#define CK_INFRA_DRAMC_26M_CK		24
+#define CK_INFRA_DBG_CK		        25
+#define CK_INFRA_AP_DMA_CK		26
+#define CK_INFRA_SEJ_CK		        27
+#define CK_INFRA_SEJ_13M_CK		28
+#define CK_INFRA_THERM_CK		29
+#define CK_INFRA_I2C0_CK		30
+#define CK_INFRA_UART0_CK		31
+#define CK_INFRA_UART1_CK		32
+#define CK_INFRA_UART2_CK		33
+#define CK_INFRA_SPI2_CK		34
+#define CK_INFRA_SPI2_HCK_CK		35
+#define CK_INFRA_NFI1_CK		36
+#define CK_INFRA_SPINFI1_CK		37
+#define CK_INFRA_NFI_HCK_CK		38
+#define CK_INFRA_SPI0_CK		39
+#define CK_INFRA_SPI1_CK		40
+#define CK_INFRA_SPI0_HCK_CK		41
+#define CK_INFRA_SPI1_HCK_CK		42
+#define CK_INFRA_FRTC_CK		43
+#define CK_INFRA_MSDC_CK		44
+#define CK_INFRA_MSDC_HCK_CK		45
+#define CK_INFRA_MSDC_133M_CK		46
+#define CK_INFRA_MSDC_66M_CK		47
+#define CK_INFRA_ADC_26M_CK		48
+#define CK_INFRA_ADC_FRC_CK		49
+#define CK_INFRA_FBIST2FPC_CK		50
+#define CK_INFRA_I2C_MCK_CK		51
+#define CK_INFRA_I2C_PCK_CK		52
+#define CK_INFRA_IUSB_133_CK		53
+#define CK_INFRA_IUSB_66M_CK		54
+#define CK_INFRA_IUSB_SYS_CK		55
+#define CK_INFRA_IUSB_CK		56
+#define CK_INFRA_IPCIE_CK		57
+#define CK_INFRA_IPCIE_PIPE_CK		58
+#define CK_INFRA_IPCIER_CK		59
+#define CK_INFRA_IPCIEB_CK		60
+#define CLK_INFRA_NR_CLK		61
 
 /* APMIXEDSYS */
 
-- 
2.45.2