* [PATCH] sunxi: mmc: Improve reset procedure
@ 2025-03-09 6:12 Jernej Skrabec
2025-03-25 1:16 ` Andre Przywara
0 siblings, 1 reply; 5+ messages in thread
From: Jernej Skrabec @ 2025-03-09 6:12 UTC (permalink / raw)
To: eng.fan, jh80.chung, trini
Cc: andre.przywara, u-boot, linux-sunxi, Jernej Skrabec
Cards should always be reset and threshold set. This fixes eMMC on H616.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---
drivers/mmc/sunxi_mmc.c | 28 ++++++++++++++++++++++------
drivers/mmc/sunxi_mmc.h | 15 +++++++++++++--
2 files changed, 35 insertions(+), 8 deletions(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 0b56d1405bee..335def4b9738 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -442,6 +442,26 @@ out:
return error;
}
+static void sunxi_mmc_reset(struct sunxi_mmc *regs)
+{
+ /* Reset controller */
+ writel(SUNXI_MMC_GCTRL_RESET, ®s->gctrl);
+ udelay(1000);
+
+ if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) {
+ /* Reset card */
+ writel(SUNXI_MMC_HWRST_ASSERT, ®s->hwrst);
+ udelay(10);
+ writel(SUNXI_MMC_HWRST_DEASSERT, ®s->hwrst);
+ udelay(300);
+
+ /* Setup FIFO R/W threshold. Needed on H616. */
+ writel(SUNXI_MMC_THLDC_READ_THLD(512) |
+ SUNXI_MMC_THLDC_WRITE_EN |
+ SUNXI_MMC_THLDC_READ_EN, ®s->thldc);
+ }
+}
+
/* non-DM code here is used by the (ARM) SPL only */
#if !CONFIG_IS_ENABLED(DM_MMC)
@@ -489,9 +509,7 @@ static int sunxi_mmc_core_init(struct mmc *mmc)
{
struct sunxi_mmc_priv *priv = mmc->priv;
- /* Reset controller */
- writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
- udelay(1000);
+ sunxi_mmc_reset(priv->reg);
return 0;
}
@@ -684,9 +702,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
upriv->mmc = &plat->mmc;
- /* Reset controller */
- writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
- udelay(1000);
+ sunxi_mmc_reset(priv->reg);
return 0;
}
diff --git a/drivers/mmc/sunxi_mmc.h b/drivers/mmc/sunxi_mmc.h
index f4ae5a790c87..9d55904c213c 100644
--- a/drivers/mmc/sunxi_mmc.h
+++ b/drivers/mmc/sunxi_mmc.h
@@ -37,7 +37,9 @@ struct sunxi_mmc {
u32 res0; /* 0x54 reserved */
u32 a12a; /* 0x58 Auto command 12 argument */
u32 ntsr; /* 0x5c New timing set register */
- u32 res1[8];
+ u32 res1[6];
+ u32 hwrst; /* 0x78 Hardware Reset */
+ u32 res5;
u32 dmac; /* 0x80 internal DMA control */
u32 dlba; /* 0x84 internal DMA descr list base address */
u32 idst; /* 0x88 internal DMA status */
@@ -46,7 +48,8 @@ struct sunxi_mmc {
u32 cbda; /* 0x94 */
u32 res2[26];
#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
- u32 res3[17];
+ u32 thldc; /* 0x100 Threshold control */
+ u32 res3[16];
u32 samp_dl;
u32 res4[46];
#endif
@@ -123,6 +126,9 @@ struct sunxi_mmc {
#define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31)
+#define SUNXI_MMC_HWRST_ASSERT (0x0 << 0)
+#define SUNXI_MMC_HWRST_DEASSERT (0x1 << 0)
+
#define SUNXI_MMC_IDMAC_RESET (0x1 << 0)
#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1)
#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7)
@@ -133,6 +139,11 @@ struct sunxi_mmc {
#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)
#define SUNXI_MMC_COMMON_RESET (1 << 18)
+#define SUNXI_MMC_THLDC_READ_EN (0x1 << 0)
+#define SUNXI_MMC_THLDC_BSY_CLR_INT_EN (0x1 << 1)
+#define SUNXI_MMC_THLDC_WRITE_EN (0x1 << 2)
+#define SUNXI_MMC_THLDC_READ_THLD(x) (((x) & 0xfff) << 16)
+
#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7)
#endif /* _SUNXI_MMC_H */
--
2.48.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] sunxi: mmc: Improve reset procedure
2025-03-09 6:12 [PATCH] sunxi: mmc: Improve reset procedure Jernej Skrabec
@ 2025-03-25 1:16 ` Andre Przywara
2025-03-25 13:39 ` Andre Przywara
0 siblings, 1 reply; 5+ messages in thread
From: Andre Przywara @ 2025-03-25 1:16 UTC (permalink / raw)
To: Jernej Skrabec; +Cc: eng.fan, jh80.chung, trini, u-boot, linux-sunxi
On Sun, 9 Mar 2025 07:12:41 +0100
Jernej Skrabec <jernej.skrabec@gmail.com> wrote:
Hi Jernej,
many thanks for your investigation and this fix here! Not having
working eMMC access was a major annoyance for those TV boxes, and this
indeed seems to be fixed now, judging by my experiments. Also checked
boot partition access, works fine (though data partitions seem to take
precedence on most devices).
> Cards should always be reset and threshold set. This fixes eMMC on H616.
>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
> ---
> drivers/mmc/sunxi_mmc.c | 28 ++++++++++++++++++++++------
> drivers/mmc/sunxi_mmc.h | 15 +++++++++++++--
> 2 files changed, 35 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
> index 0b56d1405bee..335def4b9738 100644
> --- a/drivers/mmc/sunxi_mmc.c
> +++ b/drivers/mmc/sunxi_mmc.c
> @@ -442,6 +442,26 @@ out:
> return error;
> }
>
> +static void sunxi_mmc_reset(struct sunxi_mmc *regs)
> +{
> + /* Reset controller */
> + writel(SUNXI_MMC_GCTRL_RESET, ®s->gctrl);
> + udelay(1000);
> +
> + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) {
> + /* Reset card */
> + writel(SUNXI_MMC_HWRST_ASSERT, ®s->hwrst);
> + udelay(10);
> + writel(SUNXI_MMC_HWRST_DEASSERT, ®s->hwrst);
> + udelay(300);
> +
> + /* Setup FIFO R/W threshold. Needed on H616. */
> + writel(SUNXI_MMC_THLDC_READ_THLD(512) |
> + SUNXI_MMC_THLDC_WRITE_EN |
> + SUNXI_MMC_THLDC_READ_EN, ®s->thldc);
> + }
> +}
> +
> /* non-DM code here is used by the (ARM) SPL only */
>
> #if !CONFIG_IS_ENABLED(DM_MMC)
> @@ -489,9 +509,7 @@ static int sunxi_mmc_core_init(struct mmc *mmc)
> {
> struct sunxi_mmc_priv *priv = mmc->priv;
>
> - /* Reset controller */
> - writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
> - udelay(1000);
> + sunxi_mmc_reset(priv->reg);
>
> return 0;
> }
> @@ -684,9 +702,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
>
> upriv->mmc = &plat->mmc;
>
> - /* Reset controller */
> - writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
> - udelay(1000);
> + sunxi_mmc_reset(priv->reg);
>
> return 0;
> }
> diff --git a/drivers/mmc/sunxi_mmc.h b/drivers/mmc/sunxi_mmc.h
> index f4ae5a790c87..9d55904c213c 100644
> --- a/drivers/mmc/sunxi_mmc.h
> +++ b/drivers/mmc/sunxi_mmc.h
> @@ -37,7 +37,9 @@ struct sunxi_mmc {
> u32 res0; /* 0x54 reserved */
> u32 a12a; /* 0x58 Auto command 12 argument */
> u32 ntsr; /* 0x5c New timing set register */
> - u32 res1[8];
> + u32 res1[6];
> + u32 hwrst; /* 0x78 Hardware Reset */
> + u32 res5;
> u32 dmac; /* 0x80 internal DMA control */
> u32 dlba; /* 0x84 internal DMA descr list base address */
> u32 idst; /* 0x88 internal DMA status */
> @@ -46,7 +48,8 @@ struct sunxi_mmc {
> u32 cbda; /* 0x94 */
> u32 res2[26];
> #if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
> - u32 res3[17];
> + u32 thldc; /* 0x100 Threshold control */
> + u32 res3[16];
> u32 samp_dl;
> u32 res4[46];
> #endif
> @@ -123,6 +126,9 @@ struct sunxi_mmc {
>
> #define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31)
>
> +#define SUNXI_MMC_HWRST_ASSERT (0x0 << 0)
> +#define SUNXI_MMC_HWRST_DEASSERT (0x1 << 0)
> +
> #define SUNXI_MMC_IDMAC_RESET (0x1 << 0)
> #define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1)
> #define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7)
> @@ -133,6 +139,11 @@ struct sunxi_mmc {
> #define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)
> #define SUNXI_MMC_COMMON_RESET (1 << 18)
>
> +#define SUNXI_MMC_THLDC_READ_EN (0x1 << 0)
> +#define SUNXI_MMC_THLDC_BSY_CLR_INT_EN (0x1 << 1)
> +#define SUNXI_MMC_THLDC_WRITE_EN (0x1 << 2)
> +#define SUNXI_MMC_THLDC_READ_THLD(x) (((x) & 0xfff) << 16)
> +
> #define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7)
>
> #endif /* _SUNXI_MMC_H */
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] sunxi: mmc: Improve reset procedure
2025-03-25 1:16 ` Andre Przywara
@ 2025-03-25 13:39 ` Andre Przywara
2025-03-25 14:27 ` FIXUP! " Andre Przywara
0 siblings, 1 reply; 5+ messages in thread
From: Andre Przywara @ 2025-03-25 13:39 UTC (permalink / raw)
To: Jernej Skrabec; +Cc: eng.fan, jh80.chung, trini, u-boot, linux-sunxi
On Tue, 25 Mar 2025 01:16:41 +0000
Andre Przywara <andre.przywara@arm.com> wrote:
Hi,
the U-Boot CI just told me off:
....
> On Sun, 9 Mar 2025 07:12:41 +0100
> Jernej Skrabec <jernej.skrabec@gmail.com> wrote:
>
> Hi Jernej,
>
> many thanks for your investigation and this fix here! Not having
> working eMMC access was a major annoyance for those TV boxes, and this
> indeed seems to be fixed now, judging by my experiments. Also checked
> boot partition access, works fine (though data partitions seem to take
> precedence on most devices).
>
> > Cards should always be reset and threshold set. This fixes eMMC on H616.
> >
> > Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
>
> Acked-by: Andre Przywara <andre.przywara@arm.com>
>
> Cheers,
> Andre
>
> > ---
> > drivers/mmc/sunxi_mmc.c | 28 ++++++++++++++++++++++------
> > drivers/mmc/sunxi_mmc.h | 15 +++++++++++++--
> > 2 files changed, 35 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
> > index 0b56d1405bee..335def4b9738 100644
> > --- a/drivers/mmc/sunxi_mmc.c
> > +++ b/drivers/mmc/sunxi_mmc.c
> > @@ -442,6 +442,26 @@ out:
> > return error;
> > }
> >
> > +static void sunxi_mmc_reset(struct sunxi_mmc *regs)
> > +{
> > + /* Reset controller */
> > + writel(SUNXI_MMC_GCTRL_RESET, ®s->gctrl);
> > + udelay(1000);
> > +
> > + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) {
> > + /* Reset card */
> > + writel(SUNXI_MMC_HWRST_ASSERT, ®s->hwrst);
> > + udelay(10);
> > + writel(SUNXI_MMC_HWRST_DEASSERT, ®s->hwrst);
> > + udelay(300);
> > +
> > + /* Setup FIFO R/W threshold. Needed on H616. */
> > + writel(SUNXI_MMC_THLDC_READ_THLD(512) |
> > + SUNXI_MMC_THLDC_WRITE_EN |
> > + SUNXI_MMC_THLDC_READ_EN, ®s->thldc);
> > + }
> > +}
> > +
> > /* non-DM code here is used by the (ARM) SPL only */
> >
> > #if !CONFIG_IS_ENABLED(DM_MMC)
> > @@ -489,9 +509,7 @@ static int sunxi_mmc_core_init(struct mmc *mmc)
> > {
> > struct sunxi_mmc_priv *priv = mmc->priv;
> >
> > - /* Reset controller */
> > - writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
> > - udelay(1000);
> > + sunxi_mmc_reset(priv->reg);
> >
> > return 0;
> > }
> > @@ -684,9 +702,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
> >
> > upriv->mmc = &plat->mmc;
> >
> > - /* Reset controller */
> > - writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
> > - udelay(1000);
> > + sunxi_mmc_reset(priv->reg);
> >
> > return 0;
> > }
> > diff --git a/drivers/mmc/sunxi_mmc.h b/drivers/mmc/sunxi_mmc.h
> > index f4ae5a790c87..9d55904c213c 100644
> > --- a/drivers/mmc/sunxi_mmc.h
> > +++ b/drivers/mmc/sunxi_mmc.h
> > @@ -37,7 +37,9 @@ struct sunxi_mmc {
> > u32 res0; /* 0x54 reserved */
> > u32 a12a; /* 0x58 Auto command 12 argument */
> > u32 ntsr; /* 0x5c New timing set register */
> > - u32 res1[8];
> > + u32 res1[6];
> > + u32 hwrst; /* 0x78 Hardware Reset */
> > + u32 res5;
> > u32 dmac; /* 0x80 internal DMA control */
> > u32 dlba; /* 0x84 internal DMA descr list base address */
> > u32 idst; /* 0x88 internal DMA status */
> > @@ -46,7 +48,8 @@ struct sunxi_mmc {
> > u32 cbda; /* 0x94 */
> > u32 res2[26];
> > #if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
> > - u32 res3[17];
> > + u32 thldc; /* 0x100 Threshold control */
That being in an #ifdef triggers a build failure for older SoCs (A10), as
reported by the CI. You did the right thing by using IS_ENABLED() above,
but this means the thldc member name is still visible to the compiler in
the .c file. Another reason for not describing register frames in a struct
;-)
There are like 18 registers used, so rewriting that is a bit of churn. Not
sure we want to do that now, or just #define SUNXI_MMC_THLDC_OFFSET and use
that in the .c file, as an interim measure? Because I would really like to
take this patch rather sooner than later.
Cheers,
Andre
> > + u32 res3[16];
> > u32 samp_dl;
> > u32 res4[46];
> > #endif
> > @@ -123,6 +126,9 @@ struct sunxi_mmc {
> >
> > #define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31)
> >
> > +#define SUNXI_MMC_HWRST_ASSERT (0x0 << 0)
> > +#define SUNXI_MMC_HWRST_DEASSERT (0x1 << 0)
> > +
> > #define SUNXI_MMC_IDMAC_RESET (0x1 << 0)
> > #define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1)
> > #define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7)
> > @@ -133,6 +139,11 @@ struct sunxi_mmc {
> > #define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)
> > #define SUNXI_MMC_COMMON_RESET (1 << 18)
> >
> > +#define SUNXI_MMC_THLDC_READ_EN (0x1 << 0)
> > +#define SUNXI_MMC_THLDC_BSY_CLR_INT_EN (0x1 << 1)
> > +#define SUNXI_MMC_THLDC_WRITE_EN (0x1 << 2)
> > +#define SUNXI_MMC_THLDC_READ_THLD(x) (((x) & 0xfff) << 16)
> > +
> > #define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7)
> >
> > #endif /* _SUNXI_MMC_H */
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread* FIXUP! sunxi: mmc: Improve reset procedure
2025-03-25 13:39 ` Andre Przywara
@ 2025-03-25 14:27 ` Andre Przywara
2025-03-25 16:13 ` Jernej Škrabec
0 siblings, 1 reply; 5+ messages in thread
From: Andre Przywara @ 2025-03-25 14:27 UTC (permalink / raw)
To: Peng Fan, Jaehoon Chung, Tom Rini; +Cc: u-boot, linux-sunxi
Hi Jernej,
what do you think about this solution the A10 compilation problem?
That looks like a simple change, somewhat half of the way to the proper
solution.
If you agree, I'd squash that into your patch, then push it for U-Boot
next.
Cheers,
Andre
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/mmc/sunxi_mmc.c | 10 +++++-----
drivers/mmc/sunxi_mmc.h | 4 ++++
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 31dbfb10c59..951e6acd34d 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -449,23 +449,23 @@ out:
return error;
}
-static void sunxi_mmc_reset(struct sunxi_mmc *regs)
+static void sunxi_mmc_reset(void *regs)
{
/* Reset controller */
- writel(SUNXI_MMC_GCTRL_RESET, ®s->gctrl);
+ writel(SUNXI_MMC_GCTRL_RESET, regs + SUNXI_MMC_GCTRL);
udelay(1000);
if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) {
/* Reset card */
- writel(SUNXI_MMC_HWRST_ASSERT, ®s->hwrst);
+ writel(SUNXI_MMC_HWRST_ASSERT, regs + SUNXI_MMC_HWRST);
udelay(10);
- writel(SUNXI_MMC_HWRST_DEASSERT, ®s->hwrst);
+ writel(SUNXI_MMC_HWRST_DEASSERT, regs + SUNXI_MMC_HWRST);
udelay(300);
/* Setup FIFO R/W threshold. Needed on H616. */
writel(SUNXI_MMC_THLDC_READ_THLD(512) |
SUNXI_MMC_THLDC_WRITE_EN |
- SUNXI_MMC_THLDC_READ_EN, ®s->thldc);
+ SUNXI_MMC_THLDC_READ_EN, regs + SUNXI_MMC_THLDC);
}
}
diff --git a/drivers/mmc/sunxi_mmc.h b/drivers/mmc/sunxi_mmc.h
index 9d55904c213..bc313dcabe0 100644
--- a/drivers/mmc/sunxi_mmc.h
+++ b/drivers/mmc/sunxi_mmc.h
@@ -12,6 +12,10 @@
#include <linux/types.h>
+#define SUNXI_MMC_GCTRL 0x000
+#define SUNXI_MMC_HWRST 0x078
+#define SUNXI_MMC_THLDC 0x100
+
struct sunxi_mmc {
u32 gctrl; /* 0x00 global control */
u32 clkcr; /* 0x04 clock control */
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: FIXUP! sunxi: mmc: Improve reset procedure
2025-03-25 14:27 ` FIXUP! " Andre Przywara
@ 2025-03-25 16:13 ` Jernej Škrabec
0 siblings, 0 replies; 5+ messages in thread
From: Jernej Škrabec @ 2025-03-25 16:13 UTC (permalink / raw)
To: Peng Fan, Jaehoon Chung, Tom Rini, Andre Przywara; +Cc: u-boot, linux-sunxi
Dne torek, 25. marec 2025 ob 15:27:37 Srednjeevropski standardni čas je Andre Przywara napisal(a):
> Hi Jernej,
>
> what do you think about this solution the A10 compilation problem?
> That looks like a simple change, somewhat half of the way to the proper
> solution.
> If you agree, I'd squash that into your patch, then push it for U-Boot
> next.
Sure, I'm all for it. Sorry for missing this, it seems so obvious now.
Best regards,
Jernej
>
> Cheers,
> Andre
>
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> drivers/mmc/sunxi_mmc.c | 10 +++++-----
> drivers/mmc/sunxi_mmc.h | 4 ++++
> 2 files changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
> index 31dbfb10c59..951e6acd34d 100644
> --- a/drivers/mmc/sunxi_mmc.c
> +++ b/drivers/mmc/sunxi_mmc.c
> @@ -449,23 +449,23 @@ out:
> return error;
> }
>
> -static void sunxi_mmc_reset(struct sunxi_mmc *regs)
> +static void sunxi_mmc_reset(void *regs)
> {
> /* Reset controller */
> - writel(SUNXI_MMC_GCTRL_RESET, ®s->gctrl);
> + writel(SUNXI_MMC_GCTRL_RESET, regs + SUNXI_MMC_GCTRL);
> udelay(1000);
>
> if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) {
> /* Reset card */
> - writel(SUNXI_MMC_HWRST_ASSERT, ®s->hwrst);
> + writel(SUNXI_MMC_HWRST_ASSERT, regs + SUNXI_MMC_HWRST);
> udelay(10);
> - writel(SUNXI_MMC_HWRST_DEASSERT, ®s->hwrst);
> + writel(SUNXI_MMC_HWRST_DEASSERT, regs + SUNXI_MMC_HWRST);
> udelay(300);
>
> /* Setup FIFO R/W threshold. Needed on H616. */
> writel(SUNXI_MMC_THLDC_READ_THLD(512) |
> SUNXI_MMC_THLDC_WRITE_EN |
> - SUNXI_MMC_THLDC_READ_EN, ®s->thldc);
> + SUNXI_MMC_THLDC_READ_EN, regs + SUNXI_MMC_THLDC);
> }
> }
>
> diff --git a/drivers/mmc/sunxi_mmc.h b/drivers/mmc/sunxi_mmc.h
> index 9d55904c213..bc313dcabe0 100644
> --- a/drivers/mmc/sunxi_mmc.h
> +++ b/drivers/mmc/sunxi_mmc.h
> @@ -12,6 +12,10 @@
>
> #include <linux/types.h>
>
> +#define SUNXI_MMC_GCTRL 0x000
> +#define SUNXI_MMC_HWRST 0x078
> +#define SUNXI_MMC_THLDC 0x100
> +
> struct sunxi_mmc {
> u32 gctrl; /* 0x00 global control */
> u32 clkcr; /* 0x04 clock control */
>
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2025-03-09 6:12 [PATCH] sunxi: mmc: Improve reset procedure Jernej Skrabec
2025-03-25 1:16 ` Andre Przywara
2025-03-25 13:39 ` Andre Przywara
2025-03-25 14:27 ` FIXUP! " Andre Przywara
2025-03-25 16:13 ` Jernej Škrabec
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